Computing system compatible PIM-DRAM

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to a PIM-DRAM compatible with a computing system, and the PIM-DRAM comprises a PIM-Channel address configurator which is used for processing address mapping conversion between a memory channel and a DIMM level according to an address mapping function; the PIM-Rank address configurator is used for processing address mapping conversion of a Rank level and a Bank level according to an address mapping function; the PIM-Local address configurator is used for isolating data of a PIM task and a main system task in the DRAM Bank according to address mapping conversion; wherein the address mapping function is a reversible function of a mapping relation between the system original address and the PIM task address. According to the invention, the compatibility of the computing system and the PIM-DRAM is realized under the condition that the memory interleaving is not closed.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a PIM-DRAM compatible with a computing system. Background Art

[0002] Existing computer systems adopt Memory Interleaving technology to disperse data to different physical levels (memory channels, DIMMs, ranks, chips, banks) to improve bandwidth. However, PIM (Processing-in-Memory)-DRAM requires associated data to be centrally stored in the same physical area for efficient computing. This contradiction makes it impossible to directly deploy PIM-DRAM in existing systems, and turning off memory interleaving will significantly reduce system performance.

[0003] That is to say, DRMA-PIM requires associated data to be placed in the same physical area as much as possible, while the memory interleaving of computer systems will disperse associated data to different memory channels, DIMMs, ranks, chips, and different banks, resulting in a contradiction and incompatibility between the data storage mode required by PIM-DRAM and the data storage mode of the computing system, making it impossible to deploy PIM-DRAM on the computing system.

[0004] The existing solution is to turn off the memory interleaving in the computing system. Although it meets the memory access requirements of PIM-DRAM, it will greatly reduce the memory access performance of the computing system. Summary of the Invention

[0005] Aiming at the technical problem of the incompatibility between the memory interleaving adopted by the computing system and PIM-DRAM, the purpose of the present invention is to provide a PIM-DRAM compatible with the computing system.

[0006] To solve the foregoing technical problem, the present invention provides a PIM-DRAM compatible with a computing system, and the PIM-DRAM compatible with the computing system includes:

[0007] A PIM-Channel address configurator, which is respectively connected to the CPU and the memory management unit, and is used for processing the address mapping conversion between the memory channel and the DIMM level according to the address mapping function;

[0008] A PIM-Rank address configurator, which is connected to the PIM-Channel address configurator, and is used for processing the address mapping conversion between the Rank level and the Bank level according to the address mapping function;

[0009] PIM-Local address configurator, the PIM-Local address configurator is respectively connected to the PIM-Rank address configurator and the DRAM controller, and is used to isolate the data of PIM tasks and main system tasks within the DRAM Bank according to address mapping conversion;

[0010] Wherein, the address mapping function is an invertible function of the mapping relationship between the system original address and the PIM task address.

[0011] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM-Channel address configurator and the PIM-Rank address configurator both include:

[0012] Original address reverse reading module, which is used to retain and read back the hardware address information after the memory interleaving of the computing system to obtain the original address mapping table of the current memory interleaving strategy of the system;

[0013] PIM address feature extraction module, which is used to generate a theoretical address mapping that meets the requirements of centralized data storage according to the PIM calculation requirements;

[0014] Page table function fitting module, which is used to fit the original address mapping table and the theoretical address mapping to generate an invertible function, that is, an address mapping function, to achieve address conversion.

[0015] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM address feature extraction module monitors the memory access requests of PIM tasks, statistically analyzes the data distribution characteristics of PIM tasks, and generates a theoretical address mapping that meets the requirements of centralized data storage.

[0016] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM-Channel address configurator is located on the motherboard side, and the PIM address feature extraction module in the PIM-Channel address configurator serves as the motherboard-side PIM address feature extraction module. The motherboard-side PIM address feature extraction module is used to generate a theoretical address mapping that meets the requirements of centralized data storage according to the access characteristics at the memory channel or DIMM level.

[0017] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM-Rank address configurator is located on the memory side, and the PIM address feature extraction module of the PIM-Rank address configurator serves as the memory-side PIM address feature extraction module. The memory-side PIM address feature extraction module is used to generate a theoretical address mapping that meets the requirements of centralized data storage according to the access characteristics at the Rank level or Bank level.

[0018] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM-DRAM includes a 3D stacked DRAM storage layer and a logic computing layer, and both the PIM-Local address configurator and the DRAM controller are located in the logic computing layer.

[0019] Optionally, in the PIM-DRAM of the compatible computing system as described above, the PIM-Local address configurator differentiates PIM task data from main system data according to address mapping conversion, stores the PIM task data centrally in the same DRAM Bank or DRAM Chip to avoid memory interleaving interference, and triggers the PIM arithmetic unit to perform calculations.

[0020] Optionally, in the PIM-DRAM of the compatible computing system as described above, when differentiating PIM task data from main system data, the PIM-Local address configurator marks the PIM task data with tags or metadata to distinguish the PIM task data from the main system data.

[0021] The positive and progressive effects of the present invention are as follows:

[0022] 1. By adding a multi-level memory controller group composed of a PIM-Channel address configurator, a PIM-Rank address configurator, and a PIM-Local address configurator, the present invention realizes the compatibility of the computing system and the PIM-DRAM without turning off memory interleaving.

[0023] 2. The present invention can adjust the address mapping function in real time according to the computing requirements of PIM tasks to balance PIM performance and the overall throughput of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Referring to the accompanying drawings, the disclosure of the present invention will become more apparent. It should be understood that these drawings are only for the purpose of illustration and are not intended to limit the scope of protection of the present invention. In the figures:

[0025] Figure 1 is a schematic diagram of a connection relationship of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0026] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0028] In the description of the present invention, it should be noted that for the orientation terms, such as the terms "outer side", "middle section", "inner", "outer", etc., which indicate the orientation and position relationship are based on the orientation or position relationship shown in the drawings. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be construed as limiting the specific protection scope of the present invention.

[0029] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, the meanings of "several" and "a number of" are two or more, unless otherwise specifically defined.

[0030] An embodiment of the present invention provides a PIM-DRAM compatible with a computing system. The PIM-DRAM compatible with the computing system includes a multi-level memory controller group, and through this multi-level memory controller group, the compatibility between the computing system and the PIM-DRAM is achieved without shutting down memory interleaving.

[0031] Refer to Figure 1 , the multi-level memory controller group includes a PIM-Channel address configurator (MAPA-C), a PIM-Rank address configurator (MAPA-R), and a PIM-Local address configurator (MAPA-B).

[0032] The PIM-Channel address configurator is respectively connected to a CPU (Central Processing Unit) and a Memory Management Unit (MMU). The PIM-Channel address configurator is used to process the address mapping conversion between the memory channel and the DIMM level according to the address mapping function. That is to say, the address information collected and converted by the PIM-Channel address configurator is the level above Rank (memory channel, DIMM level).

[0033] The PIM-Rank address configurator is respectively connected to the PIM-Channel address configurator and the PIM-Local address configurator. The PIM-Rank address configurator is used to process the address mapping conversion between the Rank level and the Bank level according to the address mapping function. That is to say, the address information collected and converted by the PIM-Rank address configurator is the Rank level and the Bank level.

[0034] The above address mapping function is an invertible function of the mapping relationship between the system original address and the PIM task address.

[0035] The PIM-Local address configurator is respectively connected to the PIM-Rank address configurator and the DRAM controller (MC). The PIM-Local address configurator is used to isolate the data of the PIM task and the main system task within the DRAM Bank according to the address mapping conversion. Among them, the DRAM controller is a conventional controller for controlling DRAM in the prior art.

[0036] The present invention can retain the hardware address information after the interleaving of the computing system memory through a multi-level memory controller group. This hardware address information is provided by the MMU. The MMU converts the virtual address created by the CPU into a physical address in the computer memory, and this physical address is the hardware address information, also known as the system original address. According to this hardware address information and the address mapping function, the mapping relationship between it and the PIM task address is obtained, and the PIM task data and the main system task data are effectively isolated according to this mapping relationship to avoid the problem of memory interleaving interference, and finally achieve the purpose of being compatible with the computing system and PIM-DRAM.

[0037] In some embodiments, both the PIM-Channel address configurator and the PIM-Rank address configurator include an original address reverse reading module for obtaining the system original address mapping, a PIM address feature extraction module for extracting the PIM task data access address arrangement characteristics, and a page table function fitting module for fitting the page table function. The dynamic address conversion purpose is achieved through these three modules.

[0038] The original address reverse reading module is used to retain and read back the hardware address information after the interleaving of the computing system memory to obtain the original address mapping table (PT1) of the current memory interleaving strategy of the system.

[0039] The PIM address feature extraction module is used to generate a theoretical address mapping (PT2) that meets the requirements of centralized data storage according to the PIM calculation requirements.

[0040] The page table function fitting module is used to fit the original address mapping table and the theoretical address mapping to generate an invertible function, that is, an address mapping function, to achieve address conversion.

[0041] Specifically, by performing linear / nonlinear fitting on PT1 and PT2, the mapping function F1 = PT2 = f1(PT1) and the inverse function F2 = PT1 = f2(PT2) are generated. These mapping function and inverse function are the address mapping functions.

[0042] In some embodiments, the PIM address feature extraction module monitors the memory access requests of the PIM task, statistically analyzes the PIM task data distribution characteristics, and generates a theoretical address mapping that meets the requirements of centralized data storage.

[0043] Specifically, the PIM task data distribution characteristics include characteristics such as continuity and locality. By analyzing the access patterns of PIM tasks, a theoretical address distribution table is generated to obtain the theoretical address mapping. This process can be implemented using existing technologies such as time series analysis based on a sliding window.

[0044] After the above design, the address mapping function can be adjusted in real time according to the computing requirements of PIM tasks to balance PIM performance and the overall system throughput.

[0045] In some embodiments, the PIM-Channel address configurator is located on the motherboard side, that is, the PIM-Channel address configurator is deployed on the motherboard. The PIM address feature extraction module in the PIM-Channel address configurator serves as the motherboard-side PIM address feature extraction module, and the motherboard-side PIM address feature extraction module is used to generate a theoretical address mapping that meets the requirements of centralized data storage according to the access characteristics at the memory channel or DIMM level.

[0046] In some embodiments, the PIM-Rank address configurator is located on the memory side, that is, the PIM-Rank address configurator is deployed on the DIMM. The PIM address feature extraction module in the PIM-Rank address configurator serves as the memory-side PIM address feature extraction module, and the memory-side PIM address feature extraction module is used to generate a theoretical address mapping that meets the requirements of centralized data storage according to the access characteristics at the Rank level or Bank level.

[0047] In some embodiments, the PIM-DRAM includes a 3D stacked DRAM storage layer and a logic computing layer, and both the PIM-Local address configurator and the DRAM controller are located on the logic computing layer. That is, the PIM-Local address configurator and the DRAM controller are deployed on the logic computing layer of the PIM-DRAM 3D chip.

[0048] As Figure 1 shown, there can be several processor cores NPU on the logic computing layer, and several DRAM layers of RAM are stacked on the DRAM storage layer. Each RAM has a corresponding MC to achieve control, and each MC is connected to its corresponding NPU, MAPA-B, and MMU.

[0049] In some embodiments, the PIM-Local address configurator distinguishes PIM task data from main system data according to the address mapping conversion, and centrally stores the PIM task data in a specific row (Row) of the same DRAM Bank or within a DRAM Chip (chip) to avoid memory interleaving interference and trigger the PIM arithmetic unit to perform calculations. The main system data and other task data maintain the original interleaving strategy.

[0050] The PIM-Local address configurator of this embodiment realizes functions of data differentiation, rearrangement, and local computing scheduling.

[0051] In some embodiments, when differentiating PIM task data from main system data, the PIM-Local address configurator marks the PIM task data with tags or metadata to distinguish the PIM task data from the main system data.

[0052] The present invention has been described in detail with reference to the embodiments accompanied by drawings. Those of ordinary skill in the art can make various variations of the present invention according to the above description. Therefore, certain details in the embodiments should not constitute a limitation to the present invention, and the present invention will take the scope defined by the appended claims as the protection scope.

Claims

1. A PIM-DRAM compatible with a computing system, characterized in that, The PIM-DRAM compatible with the computing system includes: A PIM-Channel address configurator, which is respectively connected to the CPU and the memory management unit, and is used to process the address mapping conversion between the memory channel and the DIMM level according to the address mapping function; A PIM-Rank address configurator, which is connected to the PIM-Channel address configurator, and is used to process the address mapping conversion between the Rank level and the Bank level according to the address mapping function; A PIM-Local address configurator, which is respectively connected to the PIM-Rank address configurator and the DRAM controller, and is used to isolate the data of the PIM task and the main system task within the DRAM Bank according to the address mapping conversion; Among them, the address mapping function is an invertible function of the mapping relationship between the system original address and the PIM task address.

2. The PIM-DRAM for a compatible computing system according to claim 1, wherein Both the PIM-Channel address configurator and the PIM-Rank address configurator include: An original address reverse reading module, which is used to retain and read back the hardware address information after the interleaving of the computing system memory to obtain the original address mapping table of the current memory interleaving strategy of the system; A PIM address feature extraction module, which is used to generate a theoretical address mapping that meets the requirements of centralized data storage according to the PIM computing requirements; A page table function fitting module, which is used to fit the original address mapping table and the theoretical address mapping to generate an invertible function, that is, an address mapping function, to realize address conversion.

3. The PIM-DRAM of the compatible computing system according to claim 2, wherein, The PIM address feature extraction module monitors the memory access requests of the PIM task, statistically analyzes the data distribution characteristics of the PIM task, and generates a theoretical address mapping that meets the requirements of centralized data storage.

4. The PIM-DRAM for a compatible computing system according to claim 3, wherein, The PIM-Channel address configurator is located on the motherboard side. The PIM address feature extraction module in the PIM-Channel address configurator serves as the PIM address feature extraction module on the motherboard side. The PIM address feature extraction module on the motherboard side is used to generate a theoretical address mapping that meets the requirements of centralized data storage according to the access characteristics of the memory channel or the DIMM level.

5. The PIM-DRAM for a compatible computing system according to claim 3, wherein, The PIM-Rank address configurator is located on the memory side. The PIM address feature extraction module in the PIM-Rank address configurator serves as the PIM address feature extraction module on the memory side. The PIM address feature extraction module on the memory side is used to generate a theoretical address mapping that meets the requirements of centralized data storage according to the access characteristics of the Rank level or the Bank level.

6. The PIM-DRAM of the compatible computing system according to claim 1, wherein The PIM-DRAM includes a 3D stacked DRAM storage layer and a logic computing layer. Both the PIM-Local address configurator and the DRAM controller are located in the logic computing layer.

7. The PIM-DRAM for a compatible computing system according to claim 1, wherein, The PIM-Local address configurator differentiates PIM task data from main system data according to address mapping conversion, centrally stores the PIM task data in the same DRAM Bank or DRAM Chip to avoid memory interleaving interference, and triggers the PIM arithmetic unit to perform calculations.

8. The PIM-DRAM for a compatible computing system according to claim 7, wherein When differentiating PIM task data from main system data, the PIM-Local address configurator marks the PIM task data with tags or metadata to distinguish the PIM task data from the main system data.

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