Serdes alignment scheme based on xilinx fpga

Abstract

The invention relates to a serdes alignment scheme based on xilinx fpga, two FPGAs are connected through serdes and are in butt joint with RX through TXs, and the conversation process between the two FPGAs comprises the steps that the two FPGAs are globally reset after being powered on, the TX parts on the two sides sequentially send a certain number of K codes and I codes to the opposite RX, waiting is carried out for a certain time after the I codes are sent every time, whether the RX ends of the FPGAs feed back correctness of all channel I codes or not is checked, if yes, the RX ends of the FPGAs are not correct, and if not, the RX ends of the FPGAs are not correct, the RX ends of the FPGAs are not correct, and if not, the RX ends of the FPGAs are not correct, the and if the RX end feeds back that all channel I codes are correct, the RX end sends an F code to the opposite side, and the opposite side prepares to receive effective data after receiving the F code. According to a xilinx ip handshake and calibration mechanism, it is ensured that a sender can determine that a receiver is prepared for receiving at the moment, data are stably received for a long time in the communication process, and the correctness of the data is ensured.

Description

Technical Field

[0001] The present invention relates to the field of data transmission, and in particular to a SerDes alignment scheme based on Xilinx FPGA. Background Art

[0002] SerDes is short for serializer / deserializer. It can convert parallel data into serial data for transmission and convert it back to parallel data at the receiving end. This transmission method can save chip pin resources and greatly improve the data transmission rate.

[0003] In Xilinx FPGA, the IP used to implement the SerDes function is as Figure 1 shown. By using the Transceivers IP and setting parameters such as the baud rate of each lane (a single data serial channel in SerDes, and each channel transmits a serial data stream), the use of PLL (phase-locked loop, used for frequency multiplication and division of clock signals), the reference clock frequency, the encoding method, and the use of physical resources, SerDes can be generated. In Xilinx FPGA, usually there are four pairs of transceiver lanes and two pairs of reference clocks in each bank, and the clocks can be shared between adjacent banks (the name of the area divided in the FPGA). When generating the IP, it is necessary to select the bank sequence and pins corresponding to the current IP, as Figure 2 shown.

[0004] Since there is no clock along with the SerDes transmission, generally at least one encoding method needs to be set to ensure the balance of the number of 0s and 1s during transmission. Because when there are multiple consecutive unchanged logical 1s or 0s in the high-speed serial stream, the signal conversion will cause transmission errors due to the voltage level relationship. In this case, the most commonly used 8B / 10B encoding is adopted. It can encode 8-bit data into 10-bit data for transmission and restore it to 8-bit data at the receiving end. This encoding method needs to be implemented through the setting of the common code, and its setting page is as Figure 3 shown. If it is directly used after the IP is generated, sometimes the data received at the receiving end will be incorrect due to the lack of lock word alignment inside the SerDes, but the sending party cannot know the status of the receiving party. Therefore, a mechanism is needed to ensure that the data received by the receiving party is correct. Summary of the Invention

[0005] To solve the existing technical problems of ensuring the correctness of the received data and the long-term continuous state alignment of the data between the sending and receiving parties of the FPGA, the present invention provides a SerDes alignment scheme based on Xilinx FPGA.

[0006] The specific content of the present invention is as follows: A SerDes alignment solution based on Xilinx FPGA. Two FPGAs are connected through SerDes and the TX of one is docked with the RX of the other. The communication process between the two FPGAs includes: After the two FPGAs are powered on, they are globally reset. The TX parts on both sides sequentially send at least 1000 K codes (alignment codes) and I codes (monitoring codes) to the RX on the opposite side. After sending each I code, wait for a certain time to check whether all channels' I codes are correctly fed back at its own RX end. If all channels' I codes are correctly fed back at its own RX end, then send an F code (feedback code) to the opposite side. After receiving the F code, the opposite side is ready to receive valid data.

[0007] Further, the receiving party checks whether the correct number of I codes is received and confirms alignment through a status signal. If alignment is confirmed, the receiving end replies with an F code. The correct number of I codes is agreed upon by the sending party and the receiving party.

[0008] Further, after the two FPGAs power on and reset SerDes, they both wait for a certain delay time before sending K codes and I codes, and the delay time is not less than 2 ms.

[0009] Further, before sending K codes and I codes, it is necessary to determine whether the SerDes status is normal. If the SerDes status is abnormal, then reset SerDes again and wait for a certain delay time.

[0010] Further, the sending party waits for 2 ms after starting to send I codes and then checks whether all channels' I codes are correctly fed back at its own RX end.

[0011] Further, if the sending end does not wait for the F code within the specified time, then reset SerDes again and repeat sending K codes and I codes.

[0012] The format of the valid data in each lane switches back and forth between K codes, I codes, and data.

[0013] The present invention aims at the handshake and calibration mechanisms of Xilinx IP, ensuring that the sending party can determine that the receiving party is ready to receive at this time and stably receive data during the communication process for a long time, guaranteeing the correctness of the data. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The following further clarifies the specific implementation manners of the present invention with reference to the accompanying drawings.

[0015] Figure 1 It is a schematic diagram of parameter settings for Transceivers ip; Figure 2 It is a schematic diagram of physical resource settings for Transceivers ip; Figure 3Schematic diagram of the encoding settings for Transceivers ip Figure 4 Waveform diagram of the sender's data Figure 5 Waveform diagram when serdes is still unstable just after power-on Figure 6 Waveform diagram of the received data when serdes is unstable Figure 7 Received control signal in the data manual Figure 8 Explanation of the alignment status bit in the data manual Figure 9 Status bit when serdes is not yet stable Figure 10 Status bit after serdes is stable Figure 11 Schematic diagram of the switching between K code and I code when serdes is stable Figure 12 Block diagram of the serdes docking between FPGAs Figure 13 Schematic diagram of the data transmission format in each lane Figure 14 Schematic diagram of the design of the transmit and receive state machines Figure 15 Communication handshake for all transmissions and receptions between two FPGAs Specific implementation manner

[0016] Combined with Figure 3 - Figure 15 The present invention provides a serdes alignment scheme based on xilinx fpga. In view of the characteristics of xilinx ip, a handshake and calibration mechanism is designed to ensure that the sender can determine that the receiver is ready to receive at this time and can stably receive data for a long time during the communication process.

[0017] Figure 4 The waveform diagram of the sender's data is shown. The waveform in the red box in the figure is the 32-bit transmitted data. At this time, the transmission is an alternation between the K code and the IDLE code (hereinafter referred to as the I code). The K code is the alignment code in serdes, which is determined by the 8b10b encoding method of serdes, and the I code is the monitoring code. Among them, BCBCBCBC is the specified K28.5 code pattern for calibrating data alignment. B5B595BC is the set I code for detecting whether the current data is aligned and whether the received data will be missed. The transmission of the K code and the I code is distinguished by the txctrl signal (shown in the pink box). When the receiver can correctly receive the I code, it is determined that the data has been latched at this time.

[0018] Figure 5 The waveform shows the waveform of the SerDes when it is just powered on and the data is not aligned yet. Figure 6 Magnified Figure 5 data part ( Figure 6 red box). From the received data, it is obvious that the received data is not the I code (B5B595BC).

[0019] According to the data manual of the IP, when the rxctrl1 signal is high, it indicates that a disparity error occurs in the received data. This is because the 0s and 1s in the received data link are not balanced at this time, resulting in the data not being aligned successfully. rxctrl3 indicates that the received data is valid at this time, and each bit corresponds to 8-bit data. For specific explanations, refer to Figure 7 .

[0020] In the data manual, the status bits of the received data are explained. When the alignment is successful, the status bit RXBYTEISALIGNED is pulled high and maintained. However, during the transmission process, once the K code is lost and the alignment fails, the module will automatically realign to the nearest boundary and pull high the realignment signal RXBYTEREALIGNED.

[0021] Figure 9 These are the status bits when the SerDes is not stable. The several signals in the red box in the figure represent the power supply good signal, the receive buf status signal, the receive byte aligned signal, and the receive byte realignment signal in sequence. It can be seen from the waveform that the receive byte is already aligned at this time (RXBYTEISALIGNED = FF), but at this time it is in the state of losing lock again after power-on. Therefore, the realignment signal (RXBYTEREALIGN) is continuously driven high, indicating that not all lanes are in the aligned state at this time, and the received I code at this moment also indicates that it is not locked.

[0022] After several resets, the waveforms of each status bit after the SerDes is stable are as Figure 10 shown. When transmitting stably, RXBYTEISALIGNED = FF and RXBYTEREALIGN == 00.

[0023] As Figure 11 is the waveform of the switching between the K code and the I code in the stable state. It can be seen that even in the stable state, when switching, a short disparity error will occur in rxctrl1, and realignment is required at this time. When RXBYTEREALIGN returns to 00, data can be transmitted normally.

[0024] According to the waveform results described above, K-code alignment is required in SerDes transmission, and I-code is used to confirm the data alignment result. Data can only be transmitted after the alignment is correct. Since long-term data transmission may cause misalignment of the data, a certain number of K-codes need to be transmitted again after each valid data transmission to align. The data transmission format in each lane is as Figure 13 shown, with K-code, I-code, and valid data switching back and forth.

[0025] Figure 14 shows the corresponding status bits of transmission / reception after the chip is powered on. After power-on, both parties reset the SerDes and wait for a certain delay, usually about 2 ms. Then, the valid status of the SerDes is judged. If the current SerDes is working properly (signals such as powergood, active, etc.), the next step is entered. If the SerDes is not working properly, the SerDes is reset again and waits for a certain delay until the SerDes works properly. At this time, the sender will first send a certain number of K-codes, such as 1024, and then immediately send 1024 I-codes, while the receiver waits and checks whether the received data is I-code. If a continuous number of I-codes equivalent to the sender's can be received, and RXBYTEISALIGNED = FF and RXBYTEREALIGN is stable at 00, it means that the received data is aligned at this time. At this time, the receiver will reply with a feedback code (F-code). After the sender receives the F-code, it starts to send valid data and repeats the transmission according to the Figure 13 format shown until all data is sent.

[0026] According to Figure 12 the structure and the above description, between two FPGAs, TX is connected to RX mutually, and each bank has 4 transmission lanes and 4 reception lanes respectively. Each lane is a differential signal. In addition to the transmission / reception handshake of the opposite lanes, there also needs to be communication between the transmission and reception within the same FPGA. mainly, the reception part needs to inform the transmission part of the correct information of the received I-code, as Figure 15 shown.

[0027] The SerDes alignment scheme based on Xilinx FPGA of the present invention has the following handshake process: S1. The two FPGAs are powered on and globally reset. The TX parts on both sides sequentially send a certain number of K-codes and I-codes after the SerDes is valid.

[0028] S2. After starting to send the I code, wait for a certain period of time and check whether all channels' I codes are correctly fed back at the RX end of itself. The serdes reset is a reset of all channels, and it is necessary to confirm that the I codes of all channels are correct here. If the receiving party continuously receives multiple I codes, it will feed back that the I codes are correct; otherwise, it will receive again and judge the I codes. The number of I codes that need to be continuously received is in accordance with the agreement between the sending party and the receiving party. For example, if the sending party sends 1000 Icodes, as long as the receiving party receives more than 500, it will confirm that the circuit is stable at this time and feed back that the I codes are correct (that is, send the F code). Wait for several ms after sending the I code. Preferably, in this embodiment, the waiting time is 2 ms.

[0029] S3. If the correct feedback of all channels' I codes is not received within the specified time, then reset the serdes again and repeat sending the K code and the I code. After the receiving end receives them, confirm that multiple consecutive I codes are received correctly and send the F code to the opposite side (the sending end). When the sending end receives the F code, the receiving end can be ready to receive the valid data.

[0030] S4. Subsequent communications follow the format of the K code, the I code, and the F code, and the three are alternately sent in a certain proportion. The proportional relationship between the K code, the I code, and the F code can be based on the agreed empirical values. For example, if 1000 K codes are sent, as long as the opposite side continuously receives 10, it can be determined to be aligned, but no feedback is required at this time. Then the sending party will send 1000 consecutive I codes. At this time, the receiving party will also count a certain number of I codes. For example, if 500 are received, it is considered that the link is stable. The F code is used as an acknowledgment signal. As long as the receiving party receives this data, it means that the link is completely stable and valid data can be sent.

[0031] This patent provides a handshaking method for the alignment problem of the serdes dedicated IP of xilinx fpga after power-on to ensure the correctness of the received data after power-on. This method performs handshaking through different data codes agreed upon by both receiving parties at the beginning of power-on without adding additional hardware overhead; and after both parties confirm the alignment of the received data, they start to send the valid data, ensuring that the sending of the valid data will not be lost due to the misalignment of the serdes serial-to-parallel conversion, and ensuring the stability of the data during the long-term continuous communication process.

[0032] Numerous specific details are set forth in the above description to facilitate a full understanding of the present invention. However, the above description is only a preferred embodiment of the present invention, and the present invention can be implemented in many other ways different from those described herein. Therefore, the present invention is not limited by the specific embodiments disclosed above. At the same time, any person skilled in the art can make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent embodiment with equivalent changes, without departing from the scope of the technical solution of the present invention. All simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A SerDes alignment scheme based on Xilinx FPGA, characterized in that: Two FPGAs are connected through SerDes and their TXs are docked with each other's RXs. The call process between the two FPGAs includes: after the two FPGAs are powered on, they are globally reset. The TX parts on both sides sequentially send at least 1000 K codes and I codes to the RX on the opposite side. After waiting for a certain time, check whether all channels' I codes are correctly fed back at its own RX end. If all channels' I codes are correctly fed back at its own RX end, then send an F code to the opposite side. After receiving the F code, the opposite side is ready to receive valid data.

2. The serdes alignment scheme based on xilinx fpga according to claim 1, wherein: The receiving party checks whether the correct number of I codes is received and confirms alignment through the status signal. If the alignment is confirmed, the receiving end replies with an F code. The correct number of I codes is agreed upon by the sending party and the receiving party.

3. The serdes alignment scheme based on xilinx fpga according to claim 1, characterized in that: After the two FPGAs are powered on and reset the SerDes, they both wait for a certain delay time before sending the K codes and I codes. The delay time is not less than 2 ms.

4. The serdes alignment scheme based on xilinx fpga according to claim 3, wherein: Before sending the K codes and I codes, it is necessary to judge whether the SerDes status is normal. If the SerDes status is abnormal, then reset the SerDes again and wait for a certain delay time.

5. The serdes alignment scheme based on xilinx fpga according to claim 1, characterized in that: After the sending party starts sending the I codes, it waits for 2 ms and then checks whether all channels' I codes are correctly fed back at its own RX end.

6. The serdes alignment scheme based on xilinx fpga according to claim 3, characterized in that: If the sending end does not wait for the F code within the specified time, then reset the SerDes again and repeat sending the K codes and I codes.

7. The serdes alignment scheme based on xilinx fpga according to claim 1, wherein: The format of the data sent in each lane switches back and forth between K codes, I codes, and valid data.

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