Memory access mode recognition device and method based on hardware implementation

Abstract

The invention provides a memory access mode recognition device and method based on hardware implementation, and the device comprises a plurality of parallel memory access mode recognition units, each memory access mode recognition unit is implemented through independent state machine logic, and is configured to dynamically adjust a confidence value according to a memory access trace of an application program, and recognize a memory access mode of a specific type; the plurality of data storage units are connected with the plurality of memory access mode identification units, and part of the memory access mode identification units share the same data storage unit; the confidence counters are used for recording confidence values of the memory access modes by using the program counters as indexes; the control unit is used for coordinating the working time sequence of the memory access mode recognition unit, the data storage unit and the confidence counter; the memory access mode recognition unit, the data storage unit, the confidence counter and the control unit are all realized through the hardware RTL, the memory access mode recognition efficiency is remarkably improved, and hardware resource occupation is reduced.

Description

Technical Field

[0001] The present invention relates to the field of computer architecture and hardware design, and particularly to a memory access pattern recognition device and method implemented based on hardware. Background Art

[0002] The cache is a key component in modern computer storage systems, and its performance directly affects the overall efficiency of the central processing unit (CPU). Whether the data prefetcher in the cache can accurately prefetch the data blocks that the CPU will need soon is an important factor determining the system performance. Memory access pattern analysis provides important support for the design and testing of cache data prefetcher: by analyzing the memory access behavior of application programs, specific memory access patterns can be identified, and hardware prefetcher can be designed for these patterns. During the design process, selecting applications with a relatively high proportion of target memory access patterns as the test set can effectively verify the performance of the prefetcher.

[0003] However, existing memory access pattern analysis tools are mainly implemented based on software, and have problems such as low running efficiency and large storage overhead, and it is difficult to meet the requirements of real-time performance and resource efficiency. To address this problem, the present invention considers proposing a memory access pattern hardware circuit implemented based on hardware to improve the memory access pattern analysis speed and reduce the storage overhead, providing efficient support for the design and optimization of cache prefetcher. Summary of the Invention

[0004] Aiming at the deficiencies of the prior art, the present invention proposes a memory access pattern recognition device and method implemented based on hardware. For the recognition requirements of different memory access patterns, based on hardware RTL implementation, a dedicated storage structure and read / write control logic are designed, including a block shared storage unit and a parallel recognition unit. By optimizing the data storage and access process, the efficiency of memory access pattern recognition is significantly improved, and at the same time, the hardware resource occupancy is reduced, realizing high resource utilization efficiency.

[0005] On the one hand, the present invention provides a memory access pattern recognition device implemented based on hardware, including:

[0006] Multiple parallel memory access pattern recognition units, each memory access pattern recognition unit is implemented through an independent state machine logic and is configured to dynamically adjust the confidence value recorded by the confidence counter according to the memory access trace of the application program to recognize specific types of memory access patterns;

[0007] Multiple data storage units adopting a block storage structure, connected to the multiple memory access pattern recognition units, and some of the memory access pattern recognition units share the same data storage unit, for storing the memory access trace and the intermediate data output by each of the memory access pattern recognition units;

[0008] Multiple confidence counters, each confidence counter is correspondingly connected to one of the memory access pattern recognition units, and is used to record the confidence values of each memory access pattern with the program counter as an index;

[0009] A control unit, connected to multiple memory access pattern recognition units, multiple data storage units, and multiple confidence counters, and is used to coordinate the working timings of the memory access pattern recognition units, data storage units, and confidence counters;

[0010] Among them, the memory access pattern recognition unit, data storage unit, confidence counter, and control unit are all implemented by hardware RTL.

[0011] In an embodiment of the present invention, the memory access pattern recognition unit includes a first recognition unit for recognizing static memory access patterns, configured as:

[0012] Compare the consistency between the current memory access address in the memory access trace and the historical memory access address of the same instruction. If they are consistent, increase the confidence value; otherwise, decrease the confidence value;

[0013] When the confidence value is greater than or equal to the first threshold, it is recognized as a static memory access pattern.

[0014] In an embodiment of the present invention, the memory access pattern recognition unit includes a second recognition unit for recognizing strided memory access patterns, configured as:

[0015] Calculate the difference between the memory access addresses of the same instruction with a given stride in the memory access trace, and verify whether the differences are continuously consistent;

[0016] If the differences are continuously consistent, increase the confidence value; otherwise, decrease the confidence value;

[0017] When the confidence value is greater than or equal to the second threshold, it is recognized as a strided memory access pattern.

[0018] In an embodiment of the present invention, the memory access pattern recognition unit includes:

[0019] A third recognition unit for recognizing pointer array memory access patterns, configured as: perform a matching detection on the current memory access address in the memory access trace and the historical memory access read / write values in a preset number of strided memory access patterns. If a successful match is detected, increase the confidence value; if a match fails and the confidence value is less than the third threshold, decrease the confidence value; when the confidence value is greater than or equal to the third threshold, it is recognized as a pointer array memory access pattern; and / or,

[0020] The fourth recognition unit for identifying the general pointer memory access pattern is configured to: perform a matching detection on the current memory access address in the memory access trace with a preset number of historical memory access read / write values; if a successful match is detected, increase the confidence value; if a match fails and the confidence value is less than the fourth threshold, decrease the confidence value; when the confidence value is greater than or equal to the fourth threshold, identify it as the general pointer memory access pattern;

[0021] The fifth recognition unit for identifying the structure pointer memory access pattern is configured to: calculate the absolute difference between the current memory access address in the memory access trace and a preset number of historical memory access read / write values as the first difference, and compare this first difference with a preset difference threshold. If it is greater than or equal to the preset difference threshold, increase the confidence value; otherwise, decrease the confidence value; when the confidence value is greater than or equal to the fifth threshold, identify it as the structure pointer memory access pattern;

[0022] The sixth recognition unit for identifying the pointer chasing memory access pattern is configured to: calculate the difference between the memory access address and the memory access read / write value for each memory access of the same instruction in the memory access trace as the second difference, and compare whether the current calculated second difference is the same as the previous one. If the second difference remains consistent, increase the confidence value; if the second difference is inconsistent and the confidence value is less than the sixth threshold, decrease the confidence value; when the confidence value is greater than or equal to the sixth threshold, identify it as the pointer chasing memory access pattern.

[0023] In an embodiment of the present invention, the memory access pattern recognition unit includes a seventh recognition unit for identifying the indirect memory access pattern, configured to:

[0024] Calculate the difference between the current memory access address in the memory access trace and the historical memory access address of the same instruction as the third difference;

[0025] Calculate the stride difference of the historical memory access read / write values in a preset number of stride memory access patterns as the fourth difference;

[0026] If the proportional relationship between the third difference and the fourth difference conforms to a preset proportional factor, increase the confidence value; if it does not conform to the preset proportional factor and the confidence value is less than the seventh threshold, decrease the confidence value; when the confidence value is greater than or equal to the seventh threshold, identify it as the indirect memory access pattern.

[0027] In an embodiment of the present invention, the memory access pattern recognition unit includes an eighth recognition unit for identifying the heap memory access pattern, configured to: calculate whether the proportional difference between the memory access addresses of the same instruction at a given stride interval in the memory access trace satisfies the characteristics of a heap. If it satisfies, increase the confidence value; if it does not satisfy, decrease the confidence value; when the confidence value is greater than or equal to the eighth threshold, identify it as the heap memory access pattern.

[0028] In one embodiment of the present invention, the multiple data storage units include:

[0029] A first data storage unit, connected to the first identification unit and the seventh identification unit, and the first identification unit and the seventh identification unit share the first data storage unit;

[0030] A second data storage unit, connected to the second identification unit and the eighth identification unit, and the second identification unit and the eighth identification unit share the second data storage unit;

[0031] A third data storage unit, connected to the fourth identification unit and the fifth identification unit, and the fourth identification unit and the fifth identification unit share the third data storage unit;

[0032] A fourth data storage unit, connected to the sixth identification unit;

[0033] A fifth data storage unit, connected to the third identification unit and the seventh identification unit, and the third identification unit and the seventh identification unit share the fifth data storage unit.

[0034] In one embodiment of the present invention, it further includes:

[0035] An input / output interface unit, connected to the multiple data storage units and the multiple confidence counters, supports user-defined protocols, is used to receive externally input memory access trace data, and output the finally identified memory access patterns and the confidence values of each memory access pattern to an external storage medium or a computer.

[0036] According to the above memory access pattern recognition device implemented based on hardware, on the other hand, the present invention also provides a memory access pattern recognition method implemented based on hardware, including:

[0037] Receiving the memory access trace data of the application program and storing it in each data storage unit;

[0038] The control unit triggers each memory access pattern recognition unit and each confidence counter, and calls the memory access trace to determine the confidence values recorded by each confidence counter according to a preset pattern recognition strategy, and recognizes various types of memory access patterns.

[0039] In one embodiment of the present invention, the stride-type memory access pattern is preferentially triggered, and then the pointer array-type memory access pattern and / or the indirect-type memory access pattern are triggered.

[0040] In one embodiment of the present invention, the preset pattern recognition strategy includes:

[0041] The first recognition strategy is used to recognize the static memory access pattern. The first recognition strategy is configured to: compare the consistency between the current memory access address in the memory access trace and the historical memory access addresses of the same instruction. If they are consistent, increase the confidence value; otherwise, decrease the confidence value. When the confidence value is greater than or equal to the first threshold, it is recognized as the static memory access pattern; and / or,

[0042] The second recognition strategy is used to recognize the strided memory access pattern. The second recognition strategy is configured to: calculate the difference between the memory access addresses of the same instruction with a given stride in the memory access trace, and verify whether the differences are continuously consistent. If the differences are continuously consistent, increase the confidence value; otherwise, decrease the confidence value. When the confidence value is greater than or equal to the second threshold, it is recognized as the strided memory access pattern;

[0043] The third recognition strategy is used to recognize the pointer array memory access pattern. The third recognition strategy is configured to: perform a matching detection on the current memory access address in the memory access trace and the historical memory access read / write values in a preset number of strided memory access patterns. If a successful match is detected, increase the confidence value; if a match fails and the confidence value is less than the third threshold, decrease the confidence value. When the confidence value is greater than or equal to the third threshold, it is recognized as the pointer array memory access pattern;

[0044] The fourth recognition strategy is used to recognize the general pointer memory access pattern. The fourth recognition strategy is configured to: perform a matching detection on the current memory access address in the memory access trace and the historical memory access read / write values in a preset number. If a successful match is detected, increase the confidence value; if a match fails and the confidence value is less than the fourth threshold, decrease the confidence value. When the confidence value is greater than or equal to the fourth threshold, it is recognized as the general pointer memory access pattern;

[0045] The fifth recognition strategy is used to recognize the structure pointer memory access pattern. The fifth recognition strategy is configured to: calculate the absolute difference between the current memory access address in the memory access trace and the historical memory access read / write values in a preset number as the first difference, and compare the first difference with a preset difference threshold. If it is greater than or equal to the preset difference threshold, increase the confidence value; otherwise, decrease the confidence value. When the confidence value is greater than or equal to the fifth threshold, it is recognized as the structure pointer memory access pattern;

[0046] The sixth recognition strategy is used to recognize the pointer-chasing memory access pattern, and the sixth recognition strategy is configured as follows: calculate the difference between the memory access address and the memory access read / write value of each memory access of the same instruction in the memory access trace as the second difference, and compare whether the current second difference is the same as the previous calculated second difference. If the second difference remains consistent, increase the confidence value; if the second difference is inconsistent and the confidence value is less than the sixth threshold, decrease the confidence value; when the confidence value is greater than or equal to the sixth threshold, recognize it as a pointer-chasing memory access pattern;

[0047] The seventh recognition strategy is used to recognize the indirect memory access pattern, and the seventh recognition strategy is configured as follows: calculate the difference between the current memory access address and the historical memory access address of the same instruction in the memory access trace as the third difference; calculate the step difference of the historical memory access read / write values in a preset number of stride memory access patterns as the fourth difference; if the proportional relationship between the third difference and the fourth difference meets the preset proportional factor, increase the confidence value; if it does not meet the preset proportional factor and the confidence value is less than the seventh threshold, decrease the confidence value; when the confidence value is greater than or equal to the seventh threshold, recognize it as an indirect memory access pattern;

[0048] The eighth recognition strategy is used to recognize the heap memory access pattern, and is configured as follows: calculate whether the proportional difference between the memory access addresses of the same instruction at a given step interval in the memory access trace meets the characteristics of the heap. If it meets, increase the confidence value; if it does not meet, decrease the confidence value; when the confidence value is greater than or equal to the eighth threshold, recognize it as a heap memory access pattern.

[0049] As can be seen from the above solutions, the advantages of the present invention are as follows:

[0050] The memory access pattern recognition device based on hardware implementation provided by the present invention is implemented based on hardware RTL, and a dedicated storage structure and read / write control logic are designed, including a block-sharing storage unit and a parallel recognition unit. Among them, there are multiple parallel memory access pattern recognition units, and each memory access pattern recognition unit is implemented through an independent state machine logic and is configured to dynamically adjust the confidence value according to the memory access trace of the application program to recognize a specific type of memory access pattern; some memory access pattern recognition units share the same data storage unit; multiple confidence counters are used to record the confidence values of each memory access pattern with the program counter as the index; a control unit is used to coordinate the working timings of the memory access pattern recognition unit, the data storage unit, and the confidence counter. The memory access pattern recognition unit, the data storage unit, the confidence counter, and the control unit of the present invention are all implemented through hardware RTL. By optimizing the data storage and access processes, the efficiency of memory access pattern recognition is significantly improved, and at the same time, the hardware resource occupancy is reduced, realizing high-efficient resource utilization. At the same time, the present invention supports adding new recognition units, and this scalable design enables the system to flexibly adapt to new recognition requirements. Brief Description of the Drawings

[0051] Figure 1 Fig. shows a schematic diagram of the overall structure of a memory access pattern recognition device implemented based on hardware according to Embodiment 1 of the present invention;

[0052] Figure 2 Fig. shows a schematic diagram of the detailed structure of a memory access pattern recognition device implemented based on hardware according to Embodiment 2 of the present invention;

[0053] Figure 3 Fig. shows a schematic diagram of the overall flow of a memory access pattern recognition method implemented based on hardware according to Embodiment 3 of the present invention.

[0054] Among them, the reference numerals are as follows:

[0055] 10: Memory access pattern recognition device;

[0056] 110: Memory access pattern recognition unit;

[0057] 1101: First recognition unit;

[0058] 1102: Second recognition unit;

[0059] 1103: Third recognition unit;

[0060] 1104: Fourth recognition unit;

[0061] 1105: Fifth recognition unit;

[0062] 1106: Sixth recognition unit;

[0063] 1107: Seventh recognition unit;

[0064] 1108: Eighth recognition unit;

[0065] 120: Data storage unit;

[0066] 1201: First data storage unit;

[0067] 1202: Second data storage unit;

[0068] 1203: Third data storage unit;

[0069] 1204: Fourth data storage unit;

[0070] 1205: Fifth data storage unit;

[0071] 130, 1301~1308: Confidence counter;

[0072] 140: Control unit;

[0073] 1501: Input interface unit;

[0074] 1502: Output interface unit;

[0075] 160: Storage medium. Detailed implementation manners

[0076] It should be noted that in this application, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device.

[0077] Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of another identical element in the process, method, article or device including the said element.

[0078] Embodiment 1:

[0079] Figure 1 The overall structural diagram of a memory access pattern recognition device implemented based on hardware provided by an embodiment of the present invention is shown. The memory access pattern recognition device 10 includes a plurality of memory access pattern recognition units 110, a plurality of data storage units 120, a plurality of confidence counters 130, a control unit 140, and an input / output interface unit. Among them, the plurality of memory access pattern recognition units 110 adopt a parallel processing architecture to accelerate the memory access pattern recognition process. Each memory access pattern recognition unit is implemented through an independent state machine logic and is configured to dynamically adjust the confidence value recorded by the confidence counter according to the memory access trace of the application program to recognize a specific type of memory access pattern.

[0080] The plurality of data storage units 120 are connected to the plurality of memory access pattern recognition units 110, and the plurality of data storage units 120 are used to store the memory access trace and the intermediate data output by each of the memory access pattern recognition units 110. The plurality of data storage units 120 adopt a block storage structure to reduce the storage overhead and improve the data access efficiency. In one embodiment, some of the memory access pattern recognition units 110 share the same data storage unit 120, and some of the same data storage units 120 are configured to support shared access by at least two memory access pattern recognition units 110, and efficient data sharing is achieved through a time-division multiplexing or parallel access mechanism.

[0081] Each confidence counter 130 is correspondingly connected to the memory access pattern recognition unit 110 to record the confidence values of each memory access pattern with the program counter (PC) as the index, so that each memory access pattern recognition unit can identify the corresponding memory access pattern by using the corresponding confidence value.

[0082] It should be noted that in this embodiment, each memory access pattern corresponds to a memory access pattern recognition unit 110, and each memory access pattern recognition unit 110 corresponds to a confidence counter 130. This confidence counter only records the confidence value of the corresponding memory access pattern, rather than the confidence values of other memory access pattern recognition units. The confidence counters 130 of each memory access pattern recognition unit 110 are independent of each other. The confidence values of each memory access pattern are only collectively referred to as the parameter of the confidence value. In fact, the calculation methods of the confidence values of different memory access patterns are different, that is, different memory access patterns correspond to different confidence values.

[0083] The control unit 140 is connected to multiple memory access pattern recognition units 110, multiple data storage units 120, and multiple confidence counters 130, and is used to coordinate the working timings of the memory access pattern recognition unit 110, the data storage unit 120, and the confidence counter 130. For example, sending read / write signals to the data storage unit to schedule the access of memory access trace data and intermediate data; sending enable signals to the memory access pattern recognition unit to trigger its state machine to start the analysis process to identify the memory access pattern; and receiving the update results of the confidence counter, determining whether the confidence values recorded by each confidence counter exceed the thresholds corresponding to each memory access pattern, and outputting the corresponding memory access pattern identifier.

[0084] The input / output interface unit is connected to multiple data storage units 120, multiple confidence counters 130, and an external storage medium 160, supports user-defined protocols, and supports FIFO buffering and bus protocols. Among them, the input / output interface unit includes an input interface unit 1501 and an output interface unit 1502. The input interface unit 1501 is used to transfer the memory access trace data stored in the external storage medium 160 to the data storage unit 120 for temporary storage, and then the memory access pattern recognition unit 110 performs memory access pattern recognition. Intermediate data generated during the recognition process is stored in the data storage unit 120. The output interface unit 1502 outputs the finally recognized memory access pattern and confidence value to be stored in the external storage medium 160 or the computer.

[0085] Among them, the memory access pattern recognition unit 110, the data storage unit 120, the confidence counter 130, the control unit 140, and the input / output interface unit are all implemented by hardware RTL.

[0086] In this embodiment, for the recognition requirements of different memory access patterns, multiple memory access pattern recognition units are configured to run in parallel. Each memory access pattern recognition unit independently processes one memory access pattern, and the timing is coordinated by the control unit. At the same time, the data storage unit adopts a block and shared design to reduce resource contention. The memory access pattern recognition unit relies on a state machine to implement the operation process, and the update of the confidence counter and the pattern determination are completed synchronously in the state machine to ensure the correctness of the timing. By optimizing the data storage and access processes, the efficiency of memory access pattern recognition is significantly improved, while the hardware resource occupancy is reduced, achieving high resource utilization efficiency.

[0087] Embodiment 2:

[0088] Figure 2 FIG. shows a detailed structural schematic diagram of a memory access pattern recognition device implemented based on hardware provided by another embodiment of the present invention. The memory access pattern recognition device 10 includes multiple memory access pattern recognition units 110, multiple data storage units 120, multiple confidence counters 130, a control unit 140, and an input / output interface unit. The memory access pattern recognition unit 110, the data storage unit 120, the confidence counter 130, the control unit 140, and the input / output interface unit are all implemented by hardware RTL.

[0089] Among them, for the recognition requirements of different memory access patterns, specifically, eight memory access patterns need to be recognized in this embodiment, namely static memory access pattern, strided memory access pattern, pointer array memory access pattern, ordinary pointer memory access pattern, structure pointer memory access pattern, pointer chasing memory access pattern, indirect memory access pattern, and heap memory access pattern. For the recognition of these eight memory access patterns, the multiple memory access pattern recognition units 110 in this embodiment specifically include a first recognition unit 1101 for recognizing the static memory access pattern, a second recognition unit 1102 for the strided memory access pattern, a third recognition unit 1103 for recognizing the pointer array memory access pattern, a fourth recognition unit 1104 for recognizing the ordinary pointer memory access pattern, a fifth recognition unit 1105 for the structure pointer memory access pattern, a sixth recognition unit 1106 for recognizing the pointer chasing memory access pattern, a seventh recognition unit 1107 for the indirect memory access pattern, and an eighth recognition unit 1108 for recognizing the heap memory access pattern. Among them, the first recognition unit 1101, the second recognition unit 1102, the third recognition unit 1103, the fourth recognition unit 1104, the fifth recognition unit 1105, the sixth recognition unit 1106, the seventh recognition unit 1107, and the eighth recognition unit 1108 adopt a parallel processing architecture to accelerate the recognition process of the memory access pattern. Each memory access pattern recognition unit is implemented by an independent state machine logic and is configured to dynamically adjust the confidence value recorded by the confidence counter according to the memory access trace of the application program to recognize a specific type of memory access pattern.

[0090] A plurality of data storage units 120 are connected to the plurality of memory access pattern recognition units 110. The plurality of data storage units 120 are used to store the memory access traces and the intermediate data output by each of the memory access pattern recognition units 110. The plurality of data storage units 120 adopt a block storage structure to reduce storage overhead and improve data access efficiency. In one embodiment, some of the memory access pattern recognition units 110 share the same data storage unit 120. Specifically, the plurality of data storage units 120 include: a first data storage unit 1201, a second data storage unit 1202, a third data storage unit 1203, a fourth data storage unit 1204, and a fifth data storage unit 1205. Among them, the first data storage unit 1201 is connected to the first recognition unit 1101 and the seventh recognition unit 1107. The first recognition unit 1101 and the seventh recognition unit 1107 share the first data storage unit 1201, that is, the intermediate data output by the first recognition unit 1101 and the seventh recognition unit 1107 can be stored in the first data storage unit 1201. The second data storage unit 1202 is connected to the second recognition unit 1102 and the eighth recognition unit 1108. The second recognition unit 1102 and the eighth recognition unit 1108 share the second data storage unit 1202, and the intermediate data output by the second recognition unit 1102 and the eighth recognition unit 1108 is stored in the second data storage unit 1202. The third data storage unit 1203 is connected to the fourth recognition unit 1104 and the fifth recognition unit 1105. The fourth recognition unit 1104 and the fifth recognition unit 1105 share the third data storage unit 1203, that is, the intermediate data output by the fourth recognition unit 1104 and the fifth recognition unit 1105 is stored in the third data storage unit 1203. The fourth data storage unit 1204 is connected to the sixth recognition unit 1106, and the intermediate data output by the sixth recognition unit 1106 is stored in the fourth data storage unit 1204. The fifth data storage unit 1205 is connected to the third recognition unit 1103 and the seventh recognition unit 1107. The third recognition unit 1103 and the seventh recognition unit 1107 share the fifth data storage unit 1205, and the intermediate data output by the third recognition unit 1103 and the seventh recognition unit 1107 can be stored in the fifth data storage unit 1205. In this embodiment, some of the same data storage units 120 are configured to support shared access by at least two memory access pattern recognition units 110, and efficient sharing of data is achieved through a time-division multiplexing or parallel access mechanism.

[0091] Each confidence counter 130 is correspondingly connected to the memory access pattern recognition unit 110 to record the confidence values of each memory access pattern using the program counter (PC) as an index, so that each memory access pattern recognition unit can recognize the corresponding memory access pattern using the corresponding confidence value. In this embodiment, each memory access pattern corresponds to a memory access pattern recognition unit 110, and each memory access pattern recognition unit 110 corresponds to a confidence counter 130. Specifically, as Figure 2 shown in Figure 2 , the first recognition unit 1101, the second recognition unit 1102, the third recognition unit 1103, the fourth recognition unit 1104, the fifth recognition unit 1105, the sixth recognition unit 1106, the seventh recognition unit 1107, and the eighth recognition unit 1108 respectively correspond to the confidence counters 1301 to 1308. The confidence counters 1301 to 1307 are independent of each other. Each confidence counter only records the confidence value of the corresponding memory access pattern, rather than the confidence values of other memory access pattern recognition units.

[0092] The control unit 140 is connected to multiple memory access pattern recognition units 110, multiple data storage units 120, and multiple confidence counters 130 to coordinate the working timings of the memory access pattern recognition unit 110, the data storage unit 120, and the confidence counter 130. The input / output interface unit is connected to multiple data storage units 120, multiple confidence counters 130, and an external storage medium 160, supports user-defined protocols, and supports FIFO buffering and bus protocols. Among them, the input interface unit 1501 is used to retrieve the memory access trace data stored in the external storage medium 160 to the data storage unit 120 for temporary storage, and then the memory access pattern recognition unit 110 performs memory access pattern recognition. Intermediate data generated during the recognition process is stored in the data storage unit 120. The output interface unit 1502 outputs the finally recognized memory access pattern and confidence value to be stored in the external storage medium 160 or the computer.

[0093] In one embodiment, the first recognition unit 1101 is used to recognize the static memory access pattern. The first recognition unit 1101 is configured to: compare the consistency between the current memory access address in the memory access trace and the historical memory access address of the same instruction. If they are consistent, increase the confidence value; otherwise, decrease the confidence value. When the confidence value is greater than or equal to the first threshold, it is recognized as a static memory access pattern. Specifically, the input signals of the first recognition unit 1101 include: the current memory access address, the historical memory access address of the same instruction, the clock signal, the enable signal, and the current confidence value of the instruction. The output signals include: the updated confidence value, and the flag bit of the confidence counter 1301. The first recognition unit 1101 analyzes at the granularity of instructions. The data required for each analysis is the current memory access address and the historical memory access address of the same instruction in the memory access trace. The logic of the first recognition unit 1101 is implemented by a state machine, which includes three main states: the idle state, the confidence counter modification state, and the end state. Among them: In the idle state, it waits for the enable signal to trigger. If the enable signal is true, first check the flag bit of the first confidence counter 1301 connected to the first recognition unit 1101. If the flag bit indicates that the current pattern has been confirmed, directly jump to the end state; if the flag bit is 0, enter the confidence counter modification state to update the confidence value. In the confidence counter modification state, in this state, determine whether the current memory access address is the same as the historical memory access address of the same instruction (such as the previous access address), that is, compare the consistency between the current memory access address in the memory access trace and the historical memory access address of the same instruction. If they are the same, increase the confidence value. For example, increase it in a linear increase, non-linear increase, or conditional increase manner, such as incrementing the confidence counter by one; if they are different, decrease the confidence value. For example, decrease it in a linear decrease, non-linear decrease, or proportional decay manner, such as dividing the confidence counter by 2. When the confidence value is greater than or equal to the first threshold, it is recognized as a static memory access pattern. At this time, enter the end state, send an end signal, and complete the recognition process of the static memory access pattern. In this embodiment, the way of increasing or decreasing the confidence value is not limited to the above method, and the first threshold can be set as a static threshold or an adaptive dynamic threshold according to the static memory access pattern to balance the recognition accuracy and speed. For example, the static threshold can be set in combination with hardware resources, such as memory consumption or counter bit width. For example, based on the historical pattern frequency (if a certain instruction frequently triggers the static memory access pattern, the threshold can be dynamically increased to reduce misjudgment), or set the self-adaptive dynamic threshold according to the rules of increasing or decreasing the confidence value, etc. The present invention is not limited thereto.

[0094] In addition, in this embodiment, data such as the current memory access address and the historical memory access address of the same instruction (for example, the memory access address accessed last time for each instruction), the updated confidence value output, and the flag bit of the confidence counter in the memory access trace required for each analysis by the first recognition unit 1101 can be stored in the first data storage unit 1201, supporting parallel access of multiple instructions.

[0095] In one embodiment, the second recognition unit 1102 is used to recognize the stride memory access pattern and is configured to: calculate the difference between the memory access addresses with a given stride within the same instruction interval in the memory access trace, and verify whether the differences are continuously consistent; if the differences are continuously consistent, increase the confidence value, otherwise decrease the confidence value; when the confidence value is greater than or equal to the second threshold, it is recognized as the stride memory access pattern. Specifically, the input signals of the second recognition unit 1102 include: the current memory access address, the historical memory access addresses of the same instruction, the clock signal, the enable signal, the current confidence value of this instruction, and the stride length recorded in the historical memory access address record; the output signals include: the calculated stride length, the updated confidence value, and the flag bit of the confidence counter 1302. The second recognition unit 1102 analyzes at the instruction granularity, and the required data are the current memory access address and the historical memory access addresses of the same instruction. To support a wider range of stride memory access patterns, taking a given stride of 2 times as an example, the stride length is determined by calculating the difference between the current memory access address and the penultimate memory access address. The second recognition unit 1102 is implemented by a state machine and includes three main states: the idle state, the confidence counter modification state, and the end state, where: In the idle state, it waits for the enable signal to trigger. If the enable signal is true, first check the flag bit of the confidence counter 1302 connected to the second recognition unit 1102. If the flag bit indicates that the current stride memory access pattern has been confirmed, directly jump to the end state; if the flag bit is 0, enter the confidence counter modification state. In the confidence counter modification state, in this state, determine whether the difference between the current memory access address and the penultimate access address is equal to the stride length recorded last time. If they are equal, indicating that the differences are continuously consistent, increase the confidence value, for example, increase it in a linear increase, non-linear increase, or conditional increase manner, such as incrementing the confidence counter by one; if they are different, decrease the confidence value, for example, decrease it in a linear decrease, non-linear decrease, or proportional decay manner, such as dividing the confidence counter by 2. When the confidence value is greater than or equal to the second threshold, it is recognized as the stride memory access pattern. At this time, enter the end state, send an end signal, and complete the recognition process of the stride memory access pattern. In this embodiment, the way of increasing or decreasing the confidence value is not limited to the above method, and the second threshold can be set as a static threshold or an adaptive dynamic threshold according to the stride memory access pattern to balance the recognition accuracy and speed. For example, a static threshold can be set in combination with hardware resources, such as memory consumption or counter bit width, etc. For example, based on the historical pattern frequency (if a certain instruction frequently triggers the stride memory access pattern, the threshold can be dynamically increased to reduce misjudgment), or an adaptive dynamic threshold can be set according to the rules of increasing or decreasing the confidence value, etc. The present invention is not limited thereto.

[0096] In addition, in this embodiment, data such as the current memory access address and the historical memory access address of the same instruction (for example, the last memory access address of each instruction), the updated confidence value output, the calculated stride length, and the flag bit of the confidence counter in the memory access trace required for each analysis by the second recognition unit 1102 can be stored in the second data storage unit 1202.

[0097] In one embodiment, the third recognition unit 1103 is used to recognize the pointer array memory access pattern and is configured to: perform a matching detection on the current memory access address in the memory access trace with the historical memory access read / write values in a preset number of stride memory access patterns. If a successful match is detected, the confidence value is increased; if a match fails and the confidence value is less than the third threshold, the confidence value is decreased; when the confidence value is greater than or equal to the third threshold, it is recognized as the pointer array memory access pattern. The input signals of the third recognition unit 1103 include: the current memory access address, the historical memory access read / write values in a preset number of stride memory access patterns, a clock signal, an enable signal, and the current confidence value of this instruction. The output signals include: the updated confidence value and the flag bit of the confidence counter 1303. The determination condition of the third recognition unit 1103 is based on the historical memory access read / write values of the input stride memory access pattern, and it determines whether the characteristics of the pointer array memory access pattern are satisfied by directly analyzing these values. In one embodiment, 8 historical memory access read / write values of the stride memory access pattern are selected, split, and stored in registers, and at the same time, the current memory access address is respectively matched with these 8 historical memory access read / write values of the stride memory access pattern. If a match is successful, the match result is recorded in a 1-bit register. In the sequential circuit part, the third recognition unit 1103 is implemented by a state machine, and a total of four states are set: an idle state, a confidence counter increase state, a confidence counter decrease state, and an end state. Among them, in the idle state, it waits for the enable signal to trigger. In the confidence counter increase state, if the match register is true, it enters this state and increases the confidence value, for example, by increasing it in a linear, non-linear, or conditional increasing manner, such as incrementing the confidence counter by one. In the confidence counter decrease state, if the match register is false and the confidence value is less than the third threshold, it enters this state and decreases the confidence value, for example, by decreasing it in a linear, non-linear, or proportional decay manner, such as dividing the confidence counter by 2. When the confidence value is greater than or equal to the third threshold, it is recognized as the pointer array memory access pattern. At this time, it enters the end state and sends an end signal to complete the recognition process of the pointer array memory access pattern. In this embodiment, the way of increasing or decreasing the confidence value is not limited to the above way, and the third threshold can be set as a static threshold or an adaptive dynamic threshold according to the pointer array memory access pattern to balance the recognition accuracy and speed. For example, a static threshold can be set in combination with hardware resources, such as memory consumption or counter bit width, etc. For example, based on the historical mode frequency (if a certain instruction frequently triggers the pointer array memory access pattern, the threshold can be dynamically increased to reduce misjudgment), or an adaptive dynamic threshold can be set according to the rules of increasing or decreasing the confidence value, etc. The present invention is not limited thereto.

[0098] In addition, in this embodiment, the current memory access address in the memory access trace required for each analysis by the third identification unit 1103 is stored in the first data storage unit 1201, and the historical memory access read / write values in the preset number of stride memory access patterns are from the fifth data storage unit 1205. The fifth data storage unit 1205 is specifically configured to store the historical memory access read / write values obtained by determination in the stride memory access pattern. Data such as the updated confidence value and the flag bit of the confidence counter 1303 output can be stored in the fifth data storage unit 1205 to support multi-instruction parallel access.

[0099] In one embodiment, the fourth recognition unit 1104 is used to recognize the general pointer type memory access mode, configured as: performing a matching detection on the current memory access address in the memory access trace with a preset number of historical memory access read / write values; if the detection is successful, increasing the confidence value; if the detection fails and the confidence value is less than the fourth threshold, decreasing the confidence value; when the confidence value is greater than or equal to the fourth threshold, recognizing it as the general pointer type memory access mode. Specifically, the input signals of the fourth recognition unit 1104 include: the current memory access address, a preset number of historical memory access read / write values, a clock signal, an enable signal, and the current confidence value of the instruction. The output signals include: the updated confidence value and the flag bit of the confidence counter 1304. In the determination of the general pointer type memory access mode, the current memory access address in the memory access trace may be related to the historical memory access read / write values, so the above signals are required as inputs. To improve the analysis efficiency, it is possible to select to input the historical memory access read / write values of the most recent 32 instructions at one time for analysis, significantly improving the processing rate. Among them, the number of 32 historical memory access read / write values is an adjustable parameter and can be configured according to actual needs. The logic of the fourth recognition unit 1104 is implemented by a state machine, and a flag bit for successful matching is set. This flag bit compares the current memory access address with a preset number of historical memory access read / write values through combinational logic. If the matching is successful, the flag bit is set to high level. The state machine includes four main states: an idle state, a confidence counter increasing state, a confidence counter decreasing state, and an end state. Among them, in the idle state, it waits for the enable signal to trigger. In the confidence counter increasing state, if the current memory access address matches successfully with a preset number of historical memory access read / write values, it enters this state and increases the confidence value, for example, increasing it in a linear increasing, non-linear increasing, or conditional increasing manner, such as incrementing the confidence counter by one. In the confidence counter decreasing state, if there is no match and the confidence value is less than the fourth threshold, the confidence value is decreased, for example, decreasing it in a linear decreasing, non-linear decreasing, or proportional decay manner, such as dividing the confidence counter by 2. When the confidence value is greater than or equal to the fourth threshold, it is recognized as the general pointer type memory access mode. At this time, it enters the end state, sends an end signal, and completes the recognition process of the general pointer type memory access mode. In this embodiment, the way of increasing or decreasing the confidence value is not limited to the above ways, and the fourth threshold can be set as a static threshold or an adaptive dynamic threshold according to the general pointer type memory access mode to balance the recognition accuracy and speed. For example, a static threshold can be set in combination with hardware resources, such as memory consumption or counter bit width, etc. For example, based on the historical mode frequency (if a certain instruction frequently triggers the general pointer type memory access mode, the threshold can be dynamically increased to reduce misjudgment), or an adaptive dynamic threshold can be set according to the rules of increasing or decreasing the confidence value, etc. The present invention is not limited thereto.

[0100] In addition, in this embodiment, data such as the current memory access address, the preset number of historical memory access read / write values, the updated confidence value output, and the flag bit of the confidence counter 1304 in the memory access trace required for each analysis by the fourth recognition unit 1104 can be stored in the third data storage unit 1203 to support multi-instruction parallel access.

[0101] In one embodiment, the fifth recognition unit 1105 is used to recognize the memory access pattern of the structure pointer type, and is configured to: calculate the absolute difference between the current memory access address in the memory access trace and a preset number of historical memory access read / write values as the first difference, and compare the first difference with a preset difference threshold. If it is greater than or equal to the preset difference threshold, the confidence value is increased; otherwise, the confidence value is decreased. When the confidence value is greater than or equal to the fifth threshold, it is recognized as the memory access pattern of the structure pointer type. The input signals of the fifth recognition unit 1105 include: the current memory access address, a preset number of historical memory access read / write values, a clock signal, an enable signal, and the current confidence value of the instruction. The output signals include: the updated confidence value and the flag bit of the confidence counter 1305. The determination of the memory access pattern of the structure pointer type is similar to that of the ordinary pointer type. To improve the analysis efficiency, the historical memory access read / write values of the most recent 32 instructions can be selected for analysis at one time, which significantly improves the processing rate. Among them, the number of 32 historical memory access read / write values is an adjustable parameter and can be configured according to actual needs. The logic of the fifth recognition unit 1105 is similar to that of the fourth recognition unit 1104, and both are implemented by a state machine. The core difference lies in the different conditions for jumping from the idle state to the state of increasing or decreasing the confidence counter. For the fifth recognition unit 1105, it calculates the absolute difference between the current memory access address in the memory access trace and a preset number of historical memory access read / write values as the first difference, and compares the first difference with a preset difference threshold. If the first difference is greater than or equal to the preset difference threshold, the confidence value is increased, for example, increased in a linear increasing, non-linear increasing, or conditional increasing manner, such as incrementing the confidence counter by one. If the first difference is less than the preset difference threshold, the confidence value is decreased, for example, decreased in a linear decreasing, non-linear decreasing, or proportional decay manner, such as dividing the confidence counter by 2. When the confidence value is greater than or equal to the fifth threshold, it is recognized as the memory access pattern of the structure pointer type. At this time, it enters the end state and sends an end signal to complete the recognition process of the memory access pattern of the structure pointer type. In this embodiment, the manner of increasing or decreasing the confidence value is not limited to the above manner, and the fifth threshold can be set as a static threshold or an adaptive dynamic threshold according to the memory access pattern of the structure pointer type to balance the recognition accuracy and speed. For example, a static threshold can be set in combination with hardware resources, such as memory consumption or counter bit width. For example, an adaptive dynamic threshold can be set based on the historical mode frequency (if a certain instruction frequently triggers the memory access pattern of the structure pointer type, the threshold can be dynamically increased to reduce misjudgment), or according to the rules of increasing or decreasing the confidence value. The present invention is not limited thereto.

[0102] In addition, in this embodiment, the fifth recognition unit 1105 shares the third data storage unit 1203 with the fourth recognition unit 1104. Data such as the current memory access address, a preset number of historical memory access read / write values, the updated confidence value output, and the flag bit of the confidence counter 1305 in the memory access trace required for each analysis can be stored in the third data storage unit 1203 to support multi-instruction parallel access.

[0103] In one embodiment, the sixth recognition unit 1106 is used to recognize the pointer-chasing memory access pattern, configured as follows: calculating the difference between the memory access address and the memory access read / write value of each time of the same instruction in the memory access trace as the second difference, comparing whether the second difference of the current time is the same as that of the previous time. If they are the same, the confidence value is increased; if they are different and the confidence value is less than the sixth threshold, the confidence value is decreased; when the confidence value is greater than or equal to the sixth threshold, it is recognized as the pointer-chasing memory access pattern. Specifically, the input signals of the sixth recognition unit 1106 include: the current memory access address, the memory access read / write value of the same instruction, the clock signal, the enable signal, and the current confidence value of the instruction; the output signals include: the updated confidence value and the flag bit of the confidence counter 1306. In the sequential circuit part, the sixth recognition unit 1106 is implemented by a state machine, and a total of four states are set: the idle state, the confidence counter increasing state, the confidence counter decreasing state, and the end state. Among them, in the idle state, it waits for the enable signal to trigger. In the confidence counter increasing state, the difference between the memory access address and the memory access read / write value of each time of the same instruction in the memory access trace is calculated as the second difference, and each time it is compared whether this second difference is the same, that is, if the second difference of the current time is the same as that of the previous time, the confidence value is increased. For example, it is increased in a linear increasing, non-linear increasing, or conditional increasing manner, such as incrementing the confidence counter by one. In the confidence counter decreasing state, if the second difference of the current time is different from that of the previous time and the confidence value is less than the sixth threshold, the confidence value is decreased. For example, it is decreased in a linear decreasing, non-linear decreasing, or proportional decay manner, such as dividing the confidence counter by 2. When the confidence value is greater than or equal to the sixth threshold, it is recognized as the pointer-chasing memory access pattern. At this time, it enters the end state and sends an end signal to complete the recognition process of the pointer-chasing memory access pattern. In this embodiment, the increasing or decreasing manner of the confidence value is not limited to the above manner, and the sixth threshold can be set as a static threshold or an adaptive dynamic threshold according to the pointer-chasing memory access pattern to balance the recognition accuracy and speed. For example, the static threshold can be set in combination with hardware resources, such as memory consumption or counter bit width. For example, based on the historical pattern frequency (if a certain instruction frequently triggers the pointer-chasing memory access pattern, the threshold can be dynamically increased to reduce misjudgment), or the threshold can be set as an adaptive dynamic threshold according to the rules of increasing or decreasing the confidence value. The present invention is not limited thereto.

[0104] In addition, in this embodiment, data such as the memory access address and memory access read / write value of each occurrence of the same instruction in the memory access trace required for each analysis by the sixth identification unit 1106, the updated confidence value output, and the flag bit of the confidence counter 1306 can be stored in the fourth data storage unit 1204.

[0105] In one embodiment, the seventh recognition unit 1107 is used to recognize the indirect memory access mode, configured as follows: calculate the difference between the current memory access address and the historical memory access address of the same instruction in the memory access trace as the third difference; calculate the stride difference of the historical memory access read / write values in a preset number of stride memory access modes as the fourth difference; if the proportional relationship between the third difference and the fourth difference meets a preset proportional factor, increase the confidence value; if it does not meet the preset proportional factor and the confidence value is less than the seventh threshold, decrease the confidence value; when the confidence value is greater than or equal to the seventh threshold, it is recognized as the indirect memory access mode. Specifically, the input signals of the seventh recognition unit 1107 include: the current memory access address, the historical memory access address of the same instruction, the historical memory access read / write values in a preset number of stride memory access modes, the clock signal, the enable signal, and the current confidence value of this instruction; the output signals include: the updated confidence value and the flag bit of the confidence counter 1307. The seventh recognition unit 1107 splits and stores the historical memory access read / write values in a preset number (such as 8) of stride memory access modes into registers through combinational logic. Calculate the difference between the current memory access address and the historical memory access address of the same instruction in the memory access trace (i.e., A[x] - A[y] in high-level language) as the third difference, calculate the stride difference of the historical memory access read / write values in a preset number of stride memory access modes (i.e., B[i] - B[j] in high-level language) as the fourth difference, and record the matching status of the proportional relationship between the third difference and the fourth difference and the preset proportional factor in a 1-bit matching register. If the proportional relationship between the third difference and the fourth difference meets the preset proportional factor (such as {1, 2, 4, 8}), increase the confidence value; if it does not meet the preset proportional factor and the confidence value is less than the seventh threshold, decrease the confidence value. In the sequential circuit part, the seventh recognition unit 1107 is implemented by a state machine, and a total of four states are set: the idle state, the confidence counter increase state, the confidence counter decrease state, and the end state. Among them, the idle state: wait for the enable signal to trigger. When the enable signal is at a low level, the state machine remains in the idle state. The confidence counter increase state, if the matching register is at a high level, enter this state and increase the confidence value, for example, increase it in a linear increasing, non-linear increasing, or conditional increasing manner, such as incrementing the confidence counter by one. The confidence counter decrease state, if the matching register is at a low level and the confidence value is less than the seventh threshold, enter this state and decrease the confidence value, for example, decrease it in a linear decreasing, non-linear decreasing, or proportional decay manner, such as dividing the confidence counter by 2. When the confidence value is greater than or equal to the seventh threshold, it is recognized as the indirect memory access mode. At this time, enter the end state and send an end signal to complete the recognition process of the indirect memory access mode. In this embodiment, the way of increasing or decreasing the confidence value is not limited to the above way, and the seventh threshold can be set as a static threshold or an adaptive dynamic threshold according to the indirect memory access mode to balance the recognition accuracy and speed.For example, static thresholds can be set in combination with hardware resources, such as memory consumption or counter bit width. For example, based on the historical pattern frequency (if a certain instruction frequently triggers an indirect memory access pattern, the threshold can be dynamically increased to reduce misjudgment), or the self-adaptive dynamic threshold can be set according to the rule of increasing or decreasing the confidence level. The present invention is not limited thereto.

[0106] In addition, in this embodiment, for each analysis by the seventh recognition unit 1107, the current memory access address in the memory access trace and the address of the previous access of the same instruction are stored in the first data storage unit 1201. The historical memory access read / write values in a preset number of stride memory access patterns are from the fifth data storage unit 1205, which is dedicated to storing the historical memory access read / write values in the stride memory access pattern. The output updated confidence value, the flag bit of the confidence counter 1307 and other data can be stored in the first data storage unit 1201 or the fifth data storage unit 1205, supporting multi-instruction parallel access.

[0107] In one embodiment, the eighth recognition unit 1108 is used to recognize the heap memory access pattern and is configured to: calculate the proportional difference between the memory access addresses at a given step length within the same instruction interval in the memory access trace to determine whether it meets the characteristics of a heap. If it meets, increase the confidence value; if not, decrease the confidence value; when the confidence value is greater than or equal to the eighth threshold, it is recognized as the heap memory access pattern. Specifically, the input signals of the eighth recognition unit 1108 include: the long memory access address, the clock signal, the enable signal, and the current confidence value of the instruction; the output signals include: the updated confidence value and the flag bit of the confidence counter 1308. The eighth recognition unit 1108 records the matching status in a 1-bit matching register by calculating whether the proportional difference between the memory access addresses at a given step length within the same instruction interval in the memory access trace meets the characteristics of a heap. In the sequential circuit part, the eighth recognition unit 1108 is implemented by a state machine, which has a total of four states: the idle state, the confidence counter increasing state, the confidence counter decreasing state, and the end state. Among them, in the idle state: wait for the enable signal to trigger. When the enable signal is at a low level, the state machine remains in the idle state. In the confidence counter increasing state, if the matching register is at a high level, enter this state and increase the confidence value, for example, increase it in a linear increasing, non-linear increasing, or conditional increasing manner, such as incrementing the confidence counter by one. In the confidence counter decreasing state, if the matching register is at a low level and the confidence value is less than the eighth threshold, enter this state and decrease the confidence value, for example, decrease it in a linear decreasing, non-linear decreasing, or proportional decay manner, such as dividing the confidence counter by 2. When the confidence value is greater than or equal to the eighth threshold, it is recognized as the heap memory access pattern. At this time, enter the end state, send an end signal, and complete the recognition process of the heap memory access pattern. In this embodiment, the way of increasing or decreasing the confidence value is not limited to the above method, and the eighth threshold can be set as a static threshold or an adaptive dynamic threshold according to the heap memory access pattern to balance the recognition accuracy and speed. For example, a static threshold can be set in combination with hardware resources, such as memory consumption or counter bit width. For example, based on the historical pattern frequency (if a certain instruction frequently triggers the heap memory access pattern, the threshold can be dynamically increased to reduce misjudgment), or an adaptive dynamic threshold can be set according to the rules of increasing or decreasing the confidence value, etc. The present invention is not limited thereto.

[0108] In addition, in this embodiment, the current memory access address and the historical memory access address of the same instruction in the memory access trace required for each analysis by the eighth recognition unit 1108 are stored in the second data storage unit 1202, and the output data such as the updated confidence value and the flag bit of the confidence counter 1308 can be stored in the second data storage unit 1202 to support multi-instruction parallel access.

[0109] In addition, in one embodiment, the confidence counter 130 is further configured with a hash collision handling unit for detecting conflicting data with the same program counter (PC) index in the hash table and evicting old data to write a new confidence counter. When a read request signal is triggered, the read signal of the internal hash table is pulled high, and the result is output after stabilizing the read signal through two-stage flip-flops. When a write request signal is triggered, the write signal of the internal hash table is pulled high, and the write operation is completed after stabilizing the write signal through two-stage flip-flops. Meanwhile, a write end signal is output. If there is already data corresponding to other PCs at the written hash position, the data is evicted and output.

[0110] In one embodiment, the logic of the control unit 140 is implemented by a state machine. When a reset signal is triggered, the control unit 140 resets the current state to the reset state and sends a reset signal to the confidence counter 130. Subsequently, the state machine jumps to the second stage of reset, in which the read signal of the confidence counter 130 is pulled high. When the read end signal from the confidence counter 130 is received, the state machine jumps to the reset state of the memory access pattern recognition unit 110, resets the state machines of the respective memory access pattern recognition units 110, and pulls high the read data signal of each memory access pattern recognition unit 110 to read data from the data storage unit 120.

[0111] When the data reading of all the memory access pattern recognition units 110 is completed, the state machine enters the next state, pulls high the enable signal of each memory access pattern recognition unit 110 to enable it to recognize each memory access pattern. When the processing end signal of a certain memory access pattern recognition unit 110 is received, the control unit 140 pulls high the corresponding write data signal to write the updated data into the corresponding data storage unit 120. When the write operations of all the memory access pattern recognition units 110 are completed, the state machine enters the next state, and writes the updated confidence values of each memory access pattern into the corresponding confidence counters 130 respectively. Thus, the processing flow of a memory access trace is completed.

[0112] It should be noted that the fifth data unit 1105 shared by the third recognition unit 1103 and the seventh recognition unit 1107 needs to rely on the result of the stride type recognition of the second recognition unit 1102. Therefore, the enable signal of the fifth data unit 1105 is pulled high only after the second recognition unit 1102 finishes recognition.

[0113] In one embodiment, the input / output interface unit is connected to multiple data storage units 120, multiple confidence counters 130, and an external storage medium 160, supports user-defined protocols, and supports FIFO buffering and bus protocols. Among them, the input interface unit 1501 is used to retrieve the memory access trace data stored in the external storage medium 160 to the data storage unit 120 for temporary storage, and then the memory access mode recognition unit 110 performs memory access mode recognition. During the recognition process, intermediate data is generated and stored in the data storage unit 120. The output interface unit 1502 outputs the finally recognized memory access mode and confidence value to be stored in the external storage medium 160 or a computer, and can be visually processed using data analysis tools. Specifically, the output interface unit 1502 outputs each memory access mode information and the corresponding confidence value as structured data. Through the visualization tool, the user can intuitively view the distribution of each memory access mode, the hot spot area, and the change trend of its confidence, so as to provide data support for program optimization, hardware design debugging, and performance analysis.

[0114] In summary, the memory access mode recognition device based on hardware implementation provided by the present invention defines the memory access mode as: static memory access mode, striding memory access mode, ordinary pointer memory access mode, structure pointer memory access mode, pointer chasing memory access mode, indirect memory access mode, pointer array memory access mode, and heap memory access mode according to the recognition requirements of different memory access modes. Based on hardware RTL implementation, a dedicated storage structure and read / write control logic are designed, including a block-sharing storage unit and a parallel recognition unit. By optimizing the data storage and access process, the efficiency of memory access mode recognition is significantly improved, and at the same time, the hardware resource occupancy is reduced, realizing high resource utilization.

[0115] Embodiment 3:

[0116] The following is a method embodiment corresponding to the above device embodiment. As Figure 3 shown, Figure 3 shows a schematic flowchart of a hardware-implemented memory access mode recognition method provided by an embodiment of the present invention. The implementation manner of this method can be implemented in cooperation with the above device implementation manner. The relevant technical details mentioned in the above device implementation manner are still valid in the implementation manner of this method. To avoid repetition, they will not be elaborated here.

[0117] A hardware-implemented memory access mode recognition method specifically includes the following steps:

[0118] Step S1: Receive the memory access trace data of the application program and store it in each data storage unit.

[0119] Step S2: The control unit triggers each memory access mode recognition unit and each confidence counter, and calls the memory access trace to determine the confidence values recorded by each confidence counter according to a preset mode recognition strategy, and recognizes various types of memory access modes.

[0120] In one embodiment, the recognition of the indirect memory access mode and the recognition of the pointer array memory access mode depend on the recognition result of the strided memory access mode. Therefore, the recognition of the strided memory access mode is triggered first, and then the recognition of the pointer array memory access mode or the indirect memory access mode is triggered. For example, the static, strided, ordinary pointer, pointer chasing, structure pointer memory access modes, and heap memory access mode can be recognized in parallel. After the recognition of these six memory access modes is completed, the confidence values corresponding to these six modes are updated first, and then the parallel recognition of the indirect and pointer array memory access modes is performed. Finally, the confidence values corresponding to these two modes are updated, and whether it belongs to the corresponding mode is output according to whether the confidence values corresponding to each mode reach the thresholds of each mode.

[0121] In one embodiment, the preset mode recognition strategy includes:

[0122] The first recognition strategy is used to recognize the static memory access mode. The first recognition strategy is configured to: compare the consistency between the current memory access address and the historical memory access address of the same instruction in the memory access trace. If they are consistent, increase the confidence value; otherwise, decrease the confidence value; when the confidence value is greater than or equal to the first threshold, it is recognized as the static memory access mode.

[0123] The second recognition strategy is used to recognize the strided memory access mode. The second recognition strategy is configured to: calculate the difference between the memory access addresses of the same instruction with a given stride in the memory access trace, and verify whether the difference is continuously consistent; if the difference is continuously consistent, increase the confidence value; otherwise, decrease the confidence value; when the confidence value is greater than or equal to the second threshold, it is recognized as the strided memory access mode.

[0124] The third recognition strategy is used to recognize the pointer array memory access mode. The third recognition strategy is configured to: perform a matching detection on the current memory access address in the memory access trace and the historical memory access read / write values in a preset number of strided memory access modes. If a successful match is detected, increase the confidence value; if a match fails and the confidence value is less than the third threshold, decrease the confidence value; when the confidence value is greater than or equal to the third threshold, it is recognized as the pointer array memory access mode.

[0125] The fourth recognition strategy is used to recognize the general pointer - type memory access pattern, and the fourth recognition strategy is configured as follows: perform a matching detection on the current memory access address in the memory access trace with a preset number of historical memory access read - write values; if a successful match is detected, increase the confidence value; if a match fails and the confidence value is less than the fourth threshold, then decrease the confidence value; when the confidence value is greater than or equal to the fourth threshold, recognize it as the general pointer - type memory access pattern.

[0126] The fifth recognition strategy is used to recognize the structure pointer - type memory access pattern, and the fifth recognition strategy is configured as follows: calculate the absolute difference between the current memory access address in the memory access trace and a preset number of historical memory access read - write values as the first difference, and compare this first difference with a preset difference threshold. If it is greater than or equal to the preset difference threshold, increase the confidence value; otherwise, decrease the confidence value; when the confidence value is greater than or equal to the fifth threshold, recognize it as the structure pointer - type memory access pattern.

[0127] The sixth recognition strategy is used to recognize the pointer chasing - type memory access pattern, and the sixth recognition strategy is configured as follows: calculate the difference between the memory access address and the memory access read - write value of the same instruction in the memory access trace as the second difference, and compare whether the second difference of the current time is the same as that of the previous time. If the second difference is consistent, increase the confidence value; if the second difference is inconsistent and the confidence value is less than the sixth threshold, then decrease the confidence value; when the confidence value is greater than or equal to the sixth threshold, recognize it as the pointer chasing - type memory access pattern.

[0128] The seventh recognition strategy is used to recognize the indirect - type memory access pattern, and the seventh recognition strategy is configured as follows: calculate the difference between the current memory access address in the memory access trace and the historical memory access address of the same instruction as the third difference; calculate the step - difference of the historical memory access read - write values in a preset number of stride - type memory access patterns as the fourth difference; if the proportional relationship between the third difference and the fourth difference conforms to a preset proportional factor, increase the confidence value; if it does not conform to the preset proportional factor and the confidence value is less than the seventh threshold, then decrease the confidence value; when the confidence value is greater than or equal to the seventh threshold, recognize it as the indirect - type memory access pattern.

[0129] The eighth recognition strategy is used to recognize the heap memory access pattern, and is configured as follows: calculate whether the proportional difference between the memory access addresses of the same instruction at a given step interval in the memory access trace satisfies the characteristics of the heap. If it is satisfied, increase the confidence value; if it is not satisfied, then decrease the confidence value; when the confidence value is greater than or equal to the eighth threshold, recognize it as the heap memory access pattern.

[0130] The relevant technical details of the recognition of each memory access pattern mentioned in the second embodiment above are still valid in each recognition strategy of this method. To avoid repetition, they will not be elaborated here.

[0131] It should also be understood that in various embodiments of the present invention, the magnitudes of the serial numbers of the above processes do not imply the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0132] In addition, it should be understood that the storage medium in the device embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0133] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and the embodiments. It can be fully applied to various fields suitable for the present invention. For those skilled in the art, additional modifications can be easily made. Therefore, without departing from the general concept defined by the claims and the equivalent scope, the present invention is not limited to the specific details and the illustrated and described examples here.

Claims

1. A memory access pattern recognition device implemented based on hardware, characterized in that Including: Multiple parallel memory access pattern recognition units, each memory access pattern recognition unit is implemented through independent state machine logic, and is configured to dynamically adjust the confidence value recorded by the confidence counter according to the memory access trace of the application program, and recognize specific types of memory access patterns; Multiple data storage units adopting a block storage structure, connected to the multiple memory access pattern recognition units, and the same data storage unit is shared among some of the memory access pattern recognition units, for storing the memory access trace and the intermediate data output by each memory access pattern recognition unit; Multiple confidence counters, each confidence counter is correspondingly connected to one of the memory access pattern recognition units, and is used to record the confidence value of each memory access pattern with the program counter as an index; A control unit, connected to the multiple memory access pattern recognition units, the multiple data storage units, and the multiple confidence counters, for coordinating the working timings of the memory access pattern recognition units, the data storage units, and the confidence counters; Wherein, the memory access pattern recognition unit, the data storage unit, the confidence counter, and the control unit are all implemented by hardware RTL.

2. The device according to claim 1, characterized in that The memory access pattern recognition unit includes a first recognition unit for recognizing a static memory access pattern, configured as: Comparing the consistency between the current memory access address in the memory access trace and the historical memory access address of the same instruction, if they are consistent, increasing the confidence value, otherwise decreasing the confidence value; When the confidence value is greater than or equal to the first threshold, it is recognized as a static memory access pattern.

3. The device according to claim 2, characterized in that, The memory access pattern recognition unit includes a second recognition unit for recognizing a striding memory access pattern, configured as: Calculating the difference between the memory access addresses of the same instruction with a given step length interval in the memory access trace, and verifying whether the difference is continuously consistent; If the difference is continuously consistent, increasing the confidence value, otherwise decreasing the confidence value; When the confidence value is greater than or equal to the second threshold, it is recognized as a striding memory access pattern.

4. The device according to claim 3, characterized in that, The memory access pattern recognition unit includes: A third recognition unit for recognizing a pointer array type memory access pattern, configured as: performing a matching detection on the current memory access address in the memory access trace and the historical memory access read / write values in a preset number of striding memory access patterns, if a successful match is detected, increasing the confidence value; if a match fails and the confidence value is less than the third threshold, decreasing the confidence value; when the confidence value is greater than or equal to the third threshold, it is recognized as a pointer array type memory access pattern; and / or, A fourth recognition unit for recognizing a general pointer type memory access pattern, configured as: performing a matching detection on the current memory access address in the memory access trace and the historical memory access read / write values in a preset number; if a successful match is detected, increasing the confidence value; if a match fails and the confidence value is less than the fourth threshold, decreasing the confidence value; When the confidence value is greater than or equal to the fourth threshold, it is recognized as a general pointer type memory access pattern; The fifth recognition unit for identifying the memory access pattern of a structure pointer type is configured to: calculate the absolute difference between the current memory access address in the memory access trace and the historical memory access read / write values of a preset number as the first difference, and compare the first difference with a preset difference threshold. If it is greater than or equal to the preset difference threshold, increase the confidence value; otherwise, decrease the confidence value; When the confidence value is greater than or equal to the fifth threshold, it is recognized as a structure pointer type memory access pattern; The sixth recognition unit for identifying the pointer chasing type memory access pattern is configured to: calculate the difference between the memory access address and the memory access read / write value for each time of the same instruction in the memory access trace as the second difference, and compare whether the second difference calculated in the current time is the same as that in the previous time. If the second difference remains consistent, increase the confidence value; If the second difference is inconsistent and the confidence value is less than the sixth threshold, decrease the confidence value; When the confidence value is greater than or equal to the sixth threshold, it is recognized as a pointer chasing type memory access pattern.

5. The device according to claim 4, characterized in that The memory access pattern recognition unit includes: The seventh recognition unit for identifying the indirect type memory access pattern is configured to: Calculate the difference between the current memory access address in the memory access trace and the historical memory access address of the same instruction as the third difference; Calculate the stride difference of the historical memory access read / write values in a preset number of stride type memory access patterns as the fourth difference; If the proportional relationship between the third difference and the fourth difference conforms to a preset proportional factor, increase the confidence value; If it does not conform to the preset proportional factor and the confidence value is less than the seventh threshold, decrease the confidence value; When the confidence value is greater than or equal to the seventh threshold, it is recognized as an indirect type memory access pattern; and / or, The eighth recognition unit for identifying the heap memory access pattern is configured to: calculate whether the proportional difference between the memory access addresses of the same instruction at a given stride interval in the memory access trace meets the characteristics of the heap. If it meets, increase the confidence value; if it does not meet, decrease the confidence value; when the confidence value is greater than or equal to the eighth threshold, it is recognized as a heap memory access pattern.

6. The device according to claim 5, wherein The multiple data storage units include: The first data storage unit is connected to the first recognition unit and the seventh recognition unit, and the first recognition unit and the seventh recognition unit share the first data storage unit; The second data storage unit is connected to the second recognition unit and the eighth recognition unit, and the second recognition unit and the eighth recognition unit share the second data storage unit; The third data storage unit is connected to the fourth recognition unit and the fifth recognition unit, and the fourth recognition unit and the fifth recognition unit share the third data storage unit; The fourth data storage unit is connected to the sixth recognition unit; The fifth data storage unit is connected to the third recognition unit and the seventh recognition unit, and the third recognition unit and the seventh recognition unit share the fifth data storage unit.

7. The device according to claim 1, characterized in that It further includes: The input / output interface unit is connected to multiple said data storage units and multiple said confidence counters, supports user-defined protocols, and is used to receive the memory access trace data input externally and output the finally recognized memory access patterns and the confidence values of each memory access pattern to an external storage medium or a computer.

8. A method for recognizing memory access patterns implemented based on hardware, characterized in that, It includes: Receiving the memory access trace data of the application program and storing it in each data storage unit; The control unit triggers each memory access pattern recognition unit and each confidence counter, and calls the said memory access trace to determine the confidence values recorded by each confidence counter according to the preset pattern recognition strategy, and recognizes various types of memory access patterns.

9. The method according to claim 8, wherein It preferentially triggers the recognition of the strided memory access pattern, and then triggers the recognition of the pointer array memory access pattern and / or the indirect memory access pattern.

10. The method according to claim 9, wherein The preset pattern recognition strategy includes: The first recognition strategy is used to recognize the static memory access pattern, and the first recognition strategy is configured as: comparing the consistency between the current memory access address in the said memory access trace and the historical memory access address of the same instruction. If they are consistent, the confidence value is increased; otherwise, the confidence value is decreased; when the confidence value is greater than or equal to the first threshold, it is recognized as the static memory access pattern; and / or, The second recognition strategy is used to recognize the strided memory access pattern, and the second recognition strategy is configured as: calculating the difference between the memory access addresses of the same instruction with a given step size interval in the said memory access trace, and verifying whether the differences are continuously consistent; if the differences are continuously consistent, the confidence value is increased; otherwise, the confidence value is decreased; When the confidence value is greater than or equal to the second threshold, it is recognized as the strided memory access pattern; The third recognition strategy is used to recognize the pointer array memory access pattern, and the third recognition strategy is configured as: performing a matching detection on the current memory access address in the said memory access trace and the historical memory access read / write values in a preset number of strided memory access patterns. If a successful match is detected, the confidence value is increased; if a failed match is detected and the confidence value is less than the third threshold, the confidence value is decreased; When the confidence value is greater than or equal to the third threshold, it is recognized as the pointer array memory access pattern; The fourth recognition strategy is used to recognize the ordinary pointer memory access pattern, and the fourth recognition strategy is configured as: performing a matching detection on the current memory access address in the said memory access trace and a preset number of historical memory access read / write values; if a successful match is detected, the confidence value is increased; if a failed match is detected and the confidence value is less than the fourth threshold, the confidence value is decreased; When the confidence value is greater than or equal to the fourth threshold, it is recognized as the ordinary pointer memory access pattern; The fifth recognition strategy is used to recognize the structure pointer memory access pattern, and the fifth recognition strategy is configured as: calculating the absolute difference between the current memory access address in the said memory access trace and a preset number of historical memory access read / write values as the first difference, and comparing the first difference with a preset difference threshold. If it is greater than or equal to the preset difference threshold, the confidence value is increased; otherwise, the confidence value is decreased; When the confidence value is greater than or equal to the fifth threshold, it is recognized as the structure pointer memory access pattern; The sixth recognition strategy is used to recognize the pointer chasing memory access pattern. The sixth recognition strategy is configured to: calculate the difference between the memory access address and the memory access read / write value for each time of the same instruction in the memory access trace as the second difference, and compare whether the current calculated second difference is the same as the previously calculated second difference. If the second difference remains consistent, increase the confidence value; If the second difference is inconsistent and the confidence value is less than the sixth threshold, decrease the confidence value; When the confidence value is greater than or equal to the sixth threshold, it is recognized as a pointer chasing memory access pattern; The seventh recognition strategy is used to recognize the indirect memory access pattern. The seventh recognition strategy is configured to: calculate the difference between the current memory access address and the historical memory access address of the same instruction in the memory access trace as the third difference; Calculate the stride difference of the historical memory access read / write values in a preset number of stride memory access patterns as the fourth difference; If the proportional relationship between the third difference and the fourth difference meets the preset proportional factor, increase the confidence value; If it does not meet the preset proportional factor and the confidence value is less than the seventh threshold, decrease the confidence value; When the confidence value is greater than or equal to the seventh threshold, it is recognized as an indirect memory access pattern; The eighth recognition strategy is used to recognize the heap memory access pattern, and is configured to: calculate whether the proportional difference between the memory access addresses of the same instruction at a given stride interval in the memory access trace meets the characteristics of the heap. If it meets, increase the confidence value; if it does not meet, decrease the confidence value; when the confidence value is greater than or equal to the eighth threshold, it is recognized as a heap memory access pattern.

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