Processing system and related method

Abstract

The invention relates to a processing system and a related method. A processing system includes: a memory controller subsystem connected to a communication channel, the communication channel configured to connect to an external memory, where the communication channel includes a data signal; and a host circuit configured to send write and read requests to the memory subsystem. In response to receiving a write request, each memory controller generates a respective first communication or a second communication for storing a respective data to a respective memory address by generating a respective first data signal or a second data signal for transmitting the respective memory address and the respective data. In response to receiving a read request, each memory controller generates a respective first communication or second communication for receiving data associated with a respective memory address by generating a respective first data signal or second data signal that transmits the respective memory address and receives the respective data.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of Italian Patent Application No. 102024000000057, filed on January 4, 2024, which is incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to methods and processing systems including a memory controller for an external memory (such as an OctalSPI memory interface). Background Art

[0004] Figure 1 A typical electronic system (such as an electronic system of a vehicle) is shown, which includes a plurality of processing systems 10 (such as embedded systems or integrated circuits, for example, field programmable gate arrays (FPGAs), digital signal processors (DSPs), or microcontrollers (for example, dedicated to the automotive market)).

[0005] For example, Figure 1 Three processing systems 101, 102, and 103 connected by a suitable communication system 20 are shown. For example, the communication system may include a vehicle control bus (such as a controller area network (CAN) bus) and a possible multimedia bus (such as a media oriented system transport (MOST) bus) connected to the vehicle control bus via a gateway. Typically, the processing systems 10 are located at different positions in the vehicle and may include, for example, an engine control unit, a transmission control unit (TCU), an anti-lock braking system (ABS), a body control module (BCM), and / or a navigation and / or multimedia audio system. Thus, one or more processing systems 10 may also implement real-time control and regulation functions. These processing systems are typically identified as electronic control units.

[0006] Figure 2 A block diagram of an exemplary digital processing system 10 (such as a microcontroller) is shown, which can be used as Figure 1 any processing system 10.

[0007] In the example considered, the processing system 10 includes a microprocessor 102 (usually a central processing unit (CPU)) programmed by software instructions. Generally, the software executed by the microprocessor 102 is stored in a non-volatile program memory 104 (such as flash memory or EEPROM). Thus, the memory 104 is configured to store the firmware of the processing unit 102, where the firmware includes software instructions to be executed by the microprocessor 102. Generally, the non-volatile memory 104 can also be used to store other data (such as configuration data (e.g., calibration data)).

[0008] The microprocessor 102 typically also has an associated volatile memory 104b (such as a random access memory (RAM)). For example, the memory 104b can be used to store temporary data.

[0009] As Figure 2 shown, communication with the memories 104 and / or 104b is typically performed via one or more memory controllers 100. The memory controller(s) 100 can be integrated in the microprocessor 102 or connected to the microprocessor 102 via a communication channel (such as the system bus of the processing system 10, etc.). The memories 104 and / or 104b can be integrated with the microprocessor 102 in a single integrated circuit, or the memories 104 and / or 104b can be in the form of separate integrated circuits and connected to the microprocessor 102, for example, via traces of a printed circuit board.

[0010] In the example considered, the microprocessor 102 can have one or more (hardware) resources / peripherals 106 selected from the following groups:

[0011] - One or more communication interfaces IF, for example, for exchanging data via the communication system 20, such as a universal asynchronous receiver / transmitter (UART), a serial peripheral interface bus (SPI), an internal integrated circuit (I 2 C), a controller area network (CAN) bus, and / or an Ethernet interface, and / or a debug interface; and / or

[0012] - One or more analog-to-digital converters AD and / or digital-to-analog converters DA; and / or

[0013] - One or more dedicated digital components DC (such as hardware timers and / or counters) or a cryptographic coprocessor; and / or

[0014] - One or more analog components AC, such as comparators, sensors (such as temperature sensors), etc.; and / or

[0015] - One or more mixed-signal components MCS, such as a PWM (pulse width modulation) driver.

[0016] Generally, the dedicated digital component DC can also correspond to an FPGA integrated in the processing system 10. For example, in this case, the memory 104 can also include program data for such an FPGA.

[0017] Thus, the digital processing system 10 can support different functionalities. For example, the behavior of the microprocessor 102 is determined by the firmware stored in the memory 104, such as software instructions to be executed by the microprocessor 102 of the microcontroller 10. Thus, by installing different firmware, the same hardware (microcontroller) can be used for different applications.

[0018] In this regard, future generations of such a processing system 10 (e.g., a microcontroller suitable for use in automotive applications) are expected to exhibit an increase in complexity, mainly due to the increase in the number of requested functionalities (new protocols, new features, etc.) and the strict constraints on execution conditions (e.g., lower power consumption, increased computing power and speed, etc.). In parallel with the growth in complexity, a high degree of flexibility is also requested for the microcontroller configuration in order to adapt to individual product applications that were previously allocated to separate processing systems 10.

[0019] For example, more complex multi-core processing systems 10 have recently been proposed. For example, such multi-core processing systems can be used to (parallel) execute Figure 1 a number of processing systems 10 as shown (such as a number of ECUs of a vehicle).

[0020] Figure 3 Another example of a processing system 10 is shown, such as a multi-core processing system 10. Specifically, in the example considered, the processing system 10 includes a plurality of n processing cores 1021…102 connected to a (on-chip) communication system 114 n . For example, in the context of a real-time control system, the processing cores 1021…102 n can be ARM cores. Generally, the communication system 114 can include one or more bus systems, such as a bus system based on the Advanced eXtensible Interface (AXI) bus architecture and / or a Network-on-Chip (NoC).

[0021] For example, as shown in the example of processing core 1021, each processing core 102 can include a microprocessor 1020 and a communication interface 1022, which is configured to manage the communication between the microprocessor 1020 and the communication system 114. Generally, the interface 1022 is a host interface, which is configured to forward a given (read or write) request from the microprocessor 1020 to the communication system 114 and forward an optional response from the communication system 114 to the microprocessor 1020. However, the communication interface 1022 can also include a slave interface. For example, in this way, the first microprocessor 1020 can send a request to the second microprocessor 1020 (via the communication interface 1022 of the first microprocessor, the communication system 114, and the communication interface 1022 of the second microprocessor). Generally, each processing core 1021…102 n can also include other local resources, such as one or more local memories 1026, which are typically identified as tightly coupled memories (TCM).

[0022] As previously mentioned, typically, the processing cores 1021…102 nconfigured to exchange data with one or more non-volatile memories 104 and / or one or more volatile memories 104b. In the multi-core processing system 10, these memories are typically system memories, i.e., shared for the processing cores 1021…102 n However, as mentioned previously, each processing core 1021…102 n may include one or more additional local memories 1026. For example, as Figure 3 shown, the processing system 10 may include one or more memory controllers 100 configured to couple at least one non-volatile memory 104 and at least one volatile memory 104b to the communication system 114.

[0023] As mentioned previously, the processing system 10 may include one or more resources 106, such as one or more communication interfaces or coprocessors (e.g., cryptographic coprocessors). The resources 106 are typically coupled to the communication system 114 via respective communication interfaces 1062 (such as peripheral bridges). For example, for this purpose, the communication system 114 may actually include an Advanced Microcontroller Bus Architecture (AMBA) High Performance Bus (AHB) and an Advanced Peripheral Bus (APB) for coupling the resources / peripherals 106 to the AMBA AHB bus. Generally, the communication interface 1062 includes at least a slave interface. For example, in this way, the processing core 102 may send requests to the resources 106 and the resources return given data. Generally, one or more communication interfaces 1062 may also include respective host interfaces. For example, in a case where a resource has to initiate communication to exchange data with another circuit (such as a resource 106 or a processing core 102) coupled to the communication system 114 via (read and / or write) requests, such a host interface (commonly identified as an integrated direct memory access (DMA) controller) may be useful.

[0024] Typically, such a processing system 10 also includes one or more general-purpose DMA controllers 110. For example, as Figure 3 shown, the DMA controller 110 may be used to directly exchange data with a memory (e.g., memory 104b) based on requests received from the resources 106. For example, in this way, the communication interface may directly read data from the memory 104b (via the DMA controller 110) and transmit this data without having to exchange other data with the processing unit 102. Typically, the DMA controller 110 may communicate with one or more memories via the communication system 114 or via one or more dedicated communication channels.

[0025] As mentioned previously, one or more of the memories 104 and / or 104b may be externally connected integrated circuits to the processing system 10. For example, the processing system 10 may include:

[0026] - A first memory 104 and / or 104a, integrated in the integrated circuit of the processing system 10 and connected to the communication system 114 via a first memory controller 100, and

[0027] - A second memory 104 and / or 104a, external to the integrated circuit of the processing system 10 and connected to the communication system 114 via a second memory controller 100.

[0028] In the context of automotive applications, such a processing system 10 and corresponding subsystems may have to meet a given Automotive Safety Integrity Level (ASIL) defined by ISO 26262. Similarly, safety levels can also be defined for other applications. For example, possible solutions for implementing the security protection of a memory subsystem are disclosed in US Patent Application Publication Nos. US2020 / 0310683 A1, US2022 / 0243437 A1, US2022 / 0180959 A1, and US2019 / 0220346 A1, as well as US Patent No. US11,392,455 B1 (incorporated herein by reference for this purpose). SUMMARY OF THE INVENTION

[0029] In view of the foregoing, an object of various embodiments of the present disclosure is to provide an improved solution for interfacing one or more external memories with a processing system, such as a microcontroller.

[0030] According to one or more embodiments, one or more of the above objects are achieved by a processing system having the features specifically recited in the following claims. Moreover, embodiments relate to a related integrated circuit, device, and method.

[0031] The claims are an integral part of the technical teachings of the present disclosure provided herein.

[0032] As previously mentioned, various embodiments of the present disclosure relate to a processing system integrated in an integrated circuit. In various embodiments, the processing system includes a communication system, a memory subsystem configured to interface a memory external to the integrated circuit, and a host circuit configured to send write requests and read requests to the memory subsystem via the communication system to store data in the memory and read data from the memory. For example, the host circuit can be a microprocessor or a DMA controller. Specifically, in various embodiments, the memory controller subsystem is connected to the communication system and a communication channel, and the communication channel is connected to a terminal of the integrated circuit, and the terminal is configured to be connected to the memory. Specifically, the communication channel includes at least data signals. For example, the communication channel can be a Serial Peripheral Interface (SPI) or an OctalSPI bus.

[0033] In various embodiments, a memory controller subsystem includes a first memory controller and a second memory controller. Each of the first memory controller and the second memory controller is configured to receive a write request or a read request, the write or read request including data indicating a memory address and, in the case of a write request, including corresponding data to be stored. In response to receiving a write request, the memory controller extracts the corresponding memory address and the corresponding data to be stored from the write request and generates a corresponding first communication or second communication for storing the extracted corresponding data to the extracted corresponding memory address by generating a corresponding first data signal or second data signal for transmitting the extracted corresponding memory address and the extracted corresponding data. Conversely, in response to receiving a read request, the memory controller extracts the corresponding memory address from the read request and generates a corresponding first communication or second communication for receiving data associated with the extracted memory address by generating a corresponding first data signal or second data signal, so as to transmit the extracted corresponding memory address and receive the corresponding data associated with the extracted memory address. Further, in response to having received the corresponding data, the memory controller generates a corresponding first response or second response including the received corresponding data.

[0034] In various embodiments, in a first operation mode, the first communication of the first memory controller is connected to a communication channel, whereby the first data signal corresponds to a data signal.

[0035] In various embodiments, in a first operation mode, in response to receiving a write request from a communication system, the memory controller subsystem is configured to forward the received write request to the first memory controller and the second memory controller, whereby the first memory controller generates a corresponding first data signal for transmitting the extracted corresponding memory address and the extracted corresponding data, and the second memory controller generates a corresponding second data signal for transmitting the extracted corresponding memory address and the extracted corresponding data. Further, the memory controller subsystem is configured to compare the first data signal with the second data signal and, in response to determining that the first data signal does not correspond to the second data signal, assert a first error signal.

[0036] In various embodiments, in a first operation mode, in response to receiving a read request from a communication system, a memory controller subsystem is configured to forward the received read request to a first memory controller and a second memory controller, whereby the first memory controller generates a corresponding first data signal for transmitting an extracted corresponding memory address and receiving corresponding data associated with the extracted corresponding memory address, and the second memory controller generates a corresponding second data signal for transmitting an extracted corresponding memory address and receiving corresponding data associated with the extracted corresponding memory address. Moreover, the first memory controller generates a corresponding response including the received corresponding data, and the second memory controller generates a corresponding response including the received corresponding data. Further, in response to determining that the first memory controller transmits the extracted memory data via the first data signal, the memory controller subsystem is configured to compare the first data signal with the second data signal, and in response to determining that the first data signal does not correspond to the second data signal, assert a second error signal. Conversely, in response to determining that the first memory controller receives the corresponding data via the first data signal, the memory controller subsystem is configured to connect the first data signal to the second data signal, compare a first response generated by the first memory controller with a second response generated by the second memory controller, and in response to determining that the first response does not correspond to the second response, assert a third error signal.

[0037] In various embodiments, in a second operation mode, a first communication of the first memory controller and a second communication of the second memory controller are connected to a communication channel, whereby the first data signal and the second data signal correspond to data signals. Specifically, in this case, the communication channel is a shared communication channel.

[0038] In various embodiments, in a second operation mode, in response to receiving a write request from a communication system, the memory controller subsystem is configured to select one of the first memory controller and the second memory controller and forward the received write request to the one memory controller, whereby the one memory controller generates a corresponding first data signal for transmitting an extracted corresponding memory address and extracted corresponding data. Next, the memory controller subsystem selects the other one of the first memory controller and the second memory controller and forwards the received write request to the other memory controller, whereby the other memory controller generates a corresponding first data signal for transmitting an extracted corresponding memory address and extracted corresponding data.

[0039] In various embodiments, in a second operation mode, in response to receiving a read request from a communication system, a memory controller subsystem is configured to select one of a first memory controller and a second memory controller and forward the received read request to the one memory controller, whereby the one memory controller generates a corresponding data signal for transmitting an extracted corresponding memory address and receiving corresponding data associated with the extracted corresponding memory address, and the one memory controller generates a corresponding response including the received corresponding data. Next, the memory controller subsystem selects the other of the first memory controller and the second memory controller and forwards the received read request to the other memory controller, whereby the other memory controller generates a corresponding data signal for transmitting an extracted corresponding memory address and receiving corresponding data associated with the extracted corresponding memory address, and the other memory controller generates a corresponding response including the received corresponding data. Next, the memory controller subsystem compares a first response generated by the first memory controller with a second response generated by the second memory controller and, in response to determining that the first response does not correspond to the second response, asserts a fourth error signal.

[0040] In various embodiments, in a first operation mode and / or a second operation mode, the first response and the second response include corresponding first response control signals and second response control signals. In such a case, the memory controller subsystem may be configured to compare the first response control signal generated by the first memory controller with the second response control signal generated by the second memory controller and, in response to determining that the first response control signal does not correspond to the second response control signal, assert a fifth error signal.

[0041] In various embodiments, in a third operation mode, a first communication of a first memory controller and a second communication of a second memory controller are connected to a communication channel, whereby a first data signal and a second data signal correspond to data signals. Specifically, in such a case, the communication channel is a shared communication channel.

[0042] In various embodiments, in a third operation mode, in response to receiving a write request from a communication system, the memory controller subsystem is configured to determine whether the write request includes data indicating a memory address associated with a first memory controller or data indicating a memory address associated with a second memory controller. In response to determining that the write request includes data indicating a memory address associated with the first memory controller, the memory controller subsystem is configured to forward the received write request to the first memory controller, whereby the first memory controller generates a corresponding first data signal for transmitting the retrieved corresponding memory address and the retrieved corresponding data. Conversely, in response to determining that the write request includes data indicating a memory address associated with the second memory controller, the memory controller subsystem is configured to forward the received write request to the second memory controller, whereby the second memory controller generates a corresponding second data signal for transmitting the retrieved corresponding memory address and the retrieved corresponding data.

[0043] In various embodiments, in a third operation mode, in response to receiving a read request from a communication system, the memory controller subsystem is configured to determine whether the read request includes data indicating a memory address associated with a first memory controller or data indicating a memory address associated with a second memory controller. In response to determining that the read request includes data indicating a memory address associated with the first memory controller, the memory controller subsystem is configured to forward the received read request to the first memory controller, whereby the first memory controller generates a corresponding data signal for transmitting the retrieved corresponding memory address and receiving the corresponding data associated with the retrieved corresponding memory address, and the first memory controller generates a corresponding response including the received corresponding data. Conversely, in response to determining that the read request includes data indicating a memory address associated with the second memory controller, the memory controller subsystem is configured to forward the received read request to the second memory controller, whereby the second memory controller generates a corresponding data signal for transmitting the retrieved corresponding memory address and receiving the corresponding data associated with the retrieved corresponding memory address, and the second memory controller generates a corresponding response including the received corresponding data.

[0044] In various embodiments, such as in a second operation mode and a third operation mode, the shared communication channel includes a first chip enable signal applicable to enable a first memory and a second chip enable signal applicable to enable a second memory. In this case, the first memory controller may be configured to assert a first chip select signal when transmitting or receiving data via the first data signal, and the second memory controller is configured to assert a second chip select signal when transmitting or receiving data via the second data signal.

[0045] In various embodiments, a memory controller subsystem includes a first error correction code (ECC) circuit associated with a first memory controller and a second ECC circuit associated with a second memory controller. In such a case, in response to receiving a write request, each memory controller may be configured to calculate ECC bits via a respective first ECC circuit or second ECC circuit, and transmit the respective memory address retrieved, the respective data retrieved, and the respective ECC bits calculated. Conversely, in response to receiving a read request, each memory controller may be configured to transmit the respective memory address retrieved and receive the respective data and respective ECC bits, calculate additional ECC bits via the respective first ECC circuit and second ECC circuit, and compare the additional ECC bits with the received ECC bits, and assert an ECC error signal in response to determining that the additional ECC bits do not correspond to the received ECC bits. In various embodiments, the ECC circuit may be an error detection and correction circuit configured to generate correction data, where the first response or the second response includes the respective corrected data. In various embodiments, the ECC circuit may be configured to calculate the respective ECC bits based on the respective data retrieved or the data received and the respective memory address.

[0046] In various embodiments, the memory controller subsystem may support multiple modes, and the memory controller subsystem may include control circuitry configured to receive configuration data and select one of a first operating mode, a second operating mode, or a third operating mode based on the configuration data. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Embodiments of the present disclosure will now be described with reference to the drawings, which are provided by way of non-limiting example only, and in which:

[0048] Figure 1 An example of an electronic system including a plurality of processing systems is shown;

[0049] Figure 2 An example of a processing system, such as a microcontroller, is shown;

[0050] Figure 3 An example of a multi-core processing system is shown;

[0051] Figure 4 An embodiment of a processing system according to the present disclosure is shown;

[0052] Figure 5 and Figure 6 shows Figure 4 an embodiment of a memory controller subsystem of a processing system;

[0053] Figure 7 shows in Figure 5 orFigure 6 An embodiment of implementing a write request in a first operation mode of a memory controller subsystem;

[0054] Figure 8 Illustrates an embodiment of implementing a read request in a first operation mode of a memory controller subsystem in Figure 5 or Figure 6 ;

[0055] Figure 9 Illustrates an embodiment of implementing a write request in a second operation mode of a memory controller subsystem in Figure 5 or Figure 6 ;

[0056] Figure 10 Illustrates an embodiment of implementing a read request in a second operation mode of a memory controller subsystem in Figure 5 or Figure 6 ;

[0057] Figure 11 Illustrates an embodiment of implementing a write request in a third operation mode of a memory controller subsystem in Figure 5 or Figure 6 ; and

[0058] Figure 12 Illustrates an embodiment of implementing a read request in a third operation mode of a memory controller subsystem in Figure 5 or Figure 6 ; DETAILED DESCRIPTION

[0059] In the following description, numerous specific details are given to provide a thorough understanding of the embodiments. The embodiments may be practiced without one or more of the specific details or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring various aspects of the embodiments.

[0060] References to "one embodiment" or "an embodiment" throughout this specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" throughout this specification are not necessarily all referring to the same embodiment. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0061] The reference numerals provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0062] In the following Figures 4 to 12 has been referenced Figures 1 to 3Parts, elements, or components described previously are represented by the same reference numerals as used previously in such figures; to avoid overburdening this detailed description, the description of such previously described elements will not be repeated hereinafter.

[0063] As previously mentioned, various embodiments of the present disclosure provide improved solutions for interfacing one or more external memories with a processing system, such as a microcontroller.

[0064] Figure 4 An embodiment of a processing system 10a according to the present disclosure is shown. Specifically, in the embodiment considered, the processing system 10a includes a host circuit 54 connected to a memory controller 50 via a communication system 52.

[0065] Specifically, the host circuit 54 can be any digital processing circuit configured to send (read and write) requests to the memory controller 50 via the communication system 52. For example, according to Figure 2 and Figure 3 the description, the host circuit 54 can be a processing core 102 including a microprocessor 1020, or an integrated or general-purpose DMA controller, such as the DMA controller 110. Thus, the communication system 52 can include a system bus or a system NoC 114 and / or a dedicated DMA communication channel.

[0066] Specifically, the memory controller 50 is configured to interface an external memory 42, i.e., a memory 42 that is external to the integrated circuit 40 including the host circuit 54, the communication system 52, and the memory controller 50. Generally, the external memory 42 can be a non-volatile memory or a volatile memory. Thus, with respect to Figure 2 and Figure 3 , in various embodiments, the memory controller 50 can be used as a memory controller 100 that is configured to interface a non-volatile memory 104 or a volatile memory 104b with the communication system 114 of the processing system 10a.

[0067] In various embodiments, as Figure 4 shown, the host circuit 54 is configured to send read and write requests to the memory controller 50, where these requests are transmitted via the communication system 52. Thus, the memory controller 50 is configured to exchange various signals COM with the communication system 52 for transferring requests and possible responses.

[0068] For example, for this purpose, each request may include address data ADR that indicates an address within the physical address range of the communication system 52, where a given address range within the physical address range of the communication system 52 is associated with the memory controller 50, i.e., the communication system 52 is configured to forward requests addressed to the given physical address range to the memory controller 50. In this regard, the memory controller 50 may be configured to map the address ADR of the physical address range associated with the memory controller 50 to the corresponding address of the memory 42. Generally speaking, such an address mapping operation is only optional because the physical address of the communication system 52 may also directly correspond to the memory address, for example, in the case of a dedicated DMA channel.

[0069] For example, in the case where the communication system 52 is a system bus or a NoC, the processing system 10a may include one or more other slave interfaces connected to the communication system 52, where a corresponding physical address range is associated with each slave interface. For example, such a slave interface may be used to interface the communication system 52 with one or more resources / peripherals 106 (or corresponding peripheral bridges) and / or other memory controllers 100. Thus, the processing system 10a may be a microcontroller, such as a multi-core microcontroller, as described with respect to Figure 2 and Figure 3 described.

[0070] In various embodiments, the host circuit 54 is configured to signal a request via one or more request control signals CREQ, such as indicating that the request should be transmitted and the type of the request. For example, the signal CREQ may include a signal REQ that is asserted (e.g., set high) to indicate the request, and a signal W_R that is set to a first logic level (e.g., low) to indicate a read request and is set to a second logic level (e.g., high) to indicate a write request.

[0071] In various embodiments, in response to a request, the memory controller 50 may transmit a response to the host circuit 54, where the response is again transmitted via the communication system 52.

[0072] For example, in the case of a write request, the write request further includes data to be transmitted to the memory controller 50. In response to having received the write request, the memory controller 50 may then write the received data to the memory 42, where the corresponding memory address is indicated via the address data ADR (e.g., by mapping the address ADR to the corresponding memory address). Thus, in this case, the memory controller 50 may transmit a response to the host circuit 54, which response includes one or more response control signals CRES that indicate whether the write request has been received and / or whether the write operation was successful. Generally speaking, in the case of a write request, such a response is only optional.

[0073] Conversely, in response to having received a read request, the memory controller 50 may read data from the memory 42, wherein the corresponding memory address is indicated via the address data ADR (e.g., by mapping the address ADR to the corresponding memory address). Thus, in such a case, the memory controller 50 may transmit a response to the host circuit 54, wherein the response includes the data that has been read from the memory 42. In various embodiments, the response may also include other response control data CRES associated with, for example, an error correction operation.

[0074] Generally, the communication system 52 (and thus also the host circuit 54 and the memory controller 50) may be configured to exchange the data (write) transmitted by the host circuit 54 and the data (read) transmitted by the memory controller 50 via a shared bidirectional data signal DATA (as Figure 4 shown) or via two separate data signals (e.g., DATA_IN and DATA_OUT). Typically, the data signal DATA has (or the data signals DATA_IN and DATA_OUT have) a given number of bits, such as 8 bits, 16 bits, or 32 bits.

[0075] Thus, in various embodiments, the memory controller 50 is configured to receive a communication COM from the communication system 52, wherein the communication COM includes a read request or a write request, and to execute the request by communicating with the external memory 42 using other signals EXT.

[0076] Generally, various types of memory controllers 50 are known in the art. For example, the memory controller 50 may be an SPI or an OctalSPI memory controller. For example, in the case of an SPI interface, the memory controller 50 communicates with the memory 42 via four signals: a data input signal SIN, a data output signal SOUT, a clock signal SCK, and a chip select signal SCS. Conversely, also as Figure 4 shown, in the case of OctalSPI (commonly also identified as OctoSPI), the memory controller 50 communicates with the memory 42 via a clock signal CLK, a chip select signal SCS, and eight bidirectional data signals IO[7:0], and thus these eight bidirectional data signals may be used to transmit eight bits in parallel in response to the clock signal CLK. Thus, in such a case, for each of these signals, the integrated circuit 40 includes a corresponding pad of the die of the integrated circuit 40 or a pin of the packaged integrated circuit 40.

[0077] For example, in various embodiments, the communication system 52 is configured to use an address ADR having 32 bits and data DATA having 32 bits. Thus, in this case, the OctalSPI interface of the memory controller 50 can be configured to use four cycles to transmit the address ADR and four cycles to exchange (i.e., send or receive) the corresponding data DATA. Also, typically one or more cycles are used to transmit a command / instruction indicating a write or read operation. Generally, the sampling of the value of the signal IO can occur in response to the rising edge and / or falling edge of the clock signal CLK.

[0078] OctalSPI interfaces and their variants (such as Hexadeca - SPI) are well - known in the art, for example, in the context of STM32 - based microcontrollers. For example, the Application Note AN5050 "Getting started with Octo - SPI and Hexadeca - SPI Interface on STM32 microcontrollers" from March 2023 can be cited, which is hereby incorporated by reference for this purpose.

[0079] Generally, the memory controller 50 and the memory 42 can also use another communication protocol instead of using OctalSPI. Specifically, in various embodiments, the communication protocol is a serial or at least sequential communication protocol, i.e., a communication protocol that uses one or more data signals IO, where the number of data signals is preferably less than the number of bits of the data DATA exchanged via the communication system 52. Specifically, in various embodiments, the communication protocol is a synchronous communication protocol, i.e., the memory controller 50 is configured to generate the clock signal CLK. As mentioned previously, in various embodiments, the signal IO is used to exchange a command indicating a read operation or a write operation, the corresponding memory address, and the corresponding data (read from the memory or to be written to the memory, respectively).

[0080] In various embodiments, the memory controller 50 and the memory 42 are configured to use a communication protocol having a chip select signal CS, such as SPI or OctalSPI. In fact, in such a case, multiple memories 42 can be connected in parallel to the same clock and data signals (e.g., signals CLK and IO), where each memory 42 receives a corresponding chip select signal. Thus, in such a case, the memory interface 50 (or another circuit of the processing system 10a, such as the processing core 102) can enable one of the memories 42 in the memory 42 by asserting the corresponding chip select signal. For example, in the case of OctalSPI, the memory 42 is enabled when the corresponding chip select signal is set low.

[0081] Thus, in various embodiments, the memory controller 50 can be connected to the communication system 52 like any other memory controller of the processing system 10a, whereby the host device 54 of the communication system 52 can communicate with the memory controller 50 (like any other memory controller 100) by sending a memory transaction request COM to the memory controller 50. In contrast, the communication EXT with the external memory 42 can use a communication system with less wiring.

[0082] Figure 5 An embodiment of a memory controller subsystem 50a according to the present disclosure is shown. Specifically, the memory controller subsystem 50a can be used as Figure 4 the memory controller 50.

[0083] In the considered embodiment, the memory controller subsystem 50a includes at least a first memory controller 500a and a second memory controller 500b.

[0084] Specifically, in various embodiments, the memory controller 500a is configured to receive read and write requests via the signal COMa. In response to having received a request via the signal COMa, the memory controller 500a generates signals EXTa for communicating with the external memory. Specifically, in response to a read request received via the signal COMa, the memory controller 500a generates the signal EXTa to read data from the memory address indicated by the read request, and then the memory controller 500a generates a response passed via the signal COMa. In contrast, in response to a write request received via the signal COMa, the memory controller 500a generates the signal EXTa to write the data received together with the write request to the memory address indicated by the write request.

[0085] Similarly, in various embodiments, the memory controller 500b is configured to receive read and write requests via the signal COMb. In response to having received a request via the signal COMb, the memory controller 500a generates signals EXTb for communicating with an external memory. Specifically, in response to a read request received via the signal COMb, the memory controller 500b generates the signal EXTb to read data from the memory address indicated by the read request, and then generates a response passed via the signal COMb. Conversely, in response to a write request received via the signal COMb, the memory controller 500a generates the signal EXTb to write the data received together with the write request to the memory address indicated by the write request.

[0086] For example, similar to that described with respect to Figure 4 each of the memory controllers 500a and 500b can be configured to receive read and write requests by using the previously described signals ADR, DATA (or DATA_IN and DATA_OUT), CREQ, and CRES. Thus, each of the signals COMa and COMb can include such signals, such as DATA_INa and DATA_OUTa (or DATAa), ADRa, CREQa, and CRESa for passing COMa, and DATA_INb and DATA_OUTb (or DATAb), ADRb, CREQb, and CRESb for passing COMb. Moreover, to communicate with the memory, each of the memory controllers 500a and 500b can be configured to generate a clock signal CLK, one or more data signals IO, and preferably a chip select signal CS. Thus, each of the signals EXTa and EXTb can include such signals, such as CLKa, IOa, and CSa for passing EXTa, and CLKb, IOb, and CSb for passing EXTb.

[0087] In various embodiments, the memory controller subsystem 50a further includes a comparison circuit 504 configured to compare one or more signals and generate one or more error signals ERR based on the comparison. For example, one or more error signals ERR can be provided to the fault collection and error management circuit of the processing system 10a. For example, such a fault collection and error management circuit can be configured to generate an interrupt or a reset of the processing system 10a based on one or more error signals ERR.

[0088] In various embodiments, the memory controller subsystem 50a may further include a first error detection and optional correction circuit 502a associated with the memory controller 500a and a second error detection and optional correction circuit 502b associated with the memory controller 500b. For example, as is well known in the art, an error detection circuit may use an error correction code (ECC). For example, in such a case, the error detection circuit receives a plurality of bits and corresponding ECC bits, and calculates additional ECC bits for the plurality of bits. In this regard, based on the ECC scheme used, the error detection circuit may detect and optionally correct an error in the plurality of bits by comparing the calculated ECC bits with the received ECC bits.

[0089] In various embodiments, the memory controller subsystem 50a includes a first switch circuit 506 configured to interface the memory controller subsystem 50a with a communication system 52, which is schematically shown via a signal COM. For example, as mentioned previously, the signal COM may also include corresponding signals ADR, DATA_IN, and DATA_OUT (or DATA), CREQ, and CRES.

[0090] Specifically, in various embodiments, the first switch circuit 506 is configured to selectively connect the signal COM to the first memory controller 500a (via the signal COMa), the second memory controller 500b (via the signal COMb), and the comparison circuit 504.

[0091] In various embodiments, the memory controller subsystem 50a further includes a second switch circuit 508 configured to interface the memory controller subsystem 50a with a first external memory 42a (schematically shown via a signal EXT1) and optionally with a second external memory 42b (schematically shown via a signal EXT2). For example, each of the signals EXT1 and EXT2 may also include corresponding signals CLK, IO, and optionally CS, such as signals CLK1, IO1, and CS1 for transmitting EXT1, and signals CLK2, IO2, and CS2 for transmitting EXT2. As mentioned previously, the clock signals CLK1 and CLK2 and the data signals IO1 and IO2 may also be shared signals, i.e., the clock signals CLK1 and CLK2 may correspond to the clock signal CLK, and the data signals IO1 and IO2 may correspond to the data signal IO.

[0092] For example, this is also as Figure 6As shown, the switch circuit 508 provides a clock signal CLK, one or more data signals IO, a first chip select signal CS1, and a second chip select signal CS2. Thus, in this case, the signals EXT1 for interfacing with the memory 42a may include the signals CLK, IO, and CS1, and the signals EXT2 for interfacing with the memory 42b may include the signals CLK, IO, and CS2. Thus, in this case, the integrated circuit 40 may include only pads / pins for the signals CLK, IO, CS1, and CS2, since the signals CLK and IO are shared for both memories 42a and 42b, and the chip select signals CS1 and CS2 may be used to enable one of the memories 42a or 42b.

[0093] Those skilled in the art will appreciate that shared signals can be implemented by connecting the corresponding lines to the supply voltage via pull-up resistors, and each circuit arranged to transmit data includes an open-drain driver. In fact, in this case, when no circuit drives the line (open-drain configuration), the line is connected to the supply voltage via the pull-up resistor, and the logic level of the line is high. Conversely, when one of the circuits connects the line to ground via a driver circuit, the logic level of the line is low. Generally, such pull-up resistors may be integrated in the integrated circuit 40 and / or may be externally connected to the corresponding pads / pins of the integrated circuit 40. For example, in various embodiments, each of the memory controllers 500a and 500b may include an open-drain driver for the clock signal CLK and each signal IO. Typically, each of the memory controllers 500a and 500b may drive the corresponding chip select signals CSa and CSb via an open-drain driver or via a push-pull configuration.

[0094] Specifically, in various embodiments, the second switch circuit 508 is configured to selectively connect the signals EXT1 and EXT2 to the first memory controller 500a (via the signal EXTa), the second memory controller 500b (via the signal EXTb), and the comparison circuit 504.

[0095] In various embodiments, the memory controller subsystem 50a thus further includes a control circuit 510 configured to drive the first switch circuit 506 and the second switch circuit 508 according to the configuration data CD.

[0096] For example, in various embodiments, the processing system 10a is configured to read configuration data CD from a non-volatile memory of the processing system 10a. Generally, the non-volatile memory can be any non-volatile memory integrated in the integrated circuit 40 or external to the integrated circuit 42. For example, the configuration data CD can be stored in the non-volatile program memory 104 of the processing system 10a or in a one-time programmable (OTP) memory implemented with fuses, for example. Alternatively, the non-volatile memory can be an external memory, such as the first external memory 42a. For example, in various embodiments, the processing system 10a can be configured to read the configuration data CD from such a non-volatile memory during the initialization phase of the processing system 10a. For example, European Patent Application Publication No. EP 3 413 194 A1 discloses possible solutions for obtaining the configuration data of the processing system 10a from a non-volatile memory, the content of which is incorporated herein by reference.

[0097] Alternatively, the configuration data CD can be set via one or more pads or pins of the integrated circuit 40, for example by selectively connecting the corresponding pins to a power supply voltage or ground. Generally, the configuration data CD can also be hardwired within the processing system 10a.

[0098] Alternatively, the configuration data CD can be stored in a register, preferably a register programmable via a write request (sent via the communication system 52), such as a register programmable by the microprocessor 1020 of the processing system 10a.

[0099] Thus, in various embodiments, the control circuit 510 is configured to manage different operation modes of the memory controller subsystem 50a according to the configuration data CD.

[0100] As mentioned previously, the memory controller subsystem 50a is configured to support multiple operation modes according to the configuration data CD. Specifically, in various embodiments, the memory controller subsystem 50a can support at least one operation mode, preferably at least two operation modes, among the following operation modes:

[0101] - A first operation mode, for example when the configuration data CD is set to "00";

[0102] - A second operation mode, preferably ASIL B or C compliant, for example when the configuration data CD is set to "01"; and

[0103] - A third operation mode, preferably ASIL D compliant, for example when the configuration data CD is set to "10".

[0104] As indicated previously, even with reference to the first, second, or third operating modes, the memory controller subsystem 50a may support only one of the operating modes or any combination of the operating modes, such as the first and second operating modes, the first and third operating modes, the second and third operating modes, or all three operating modes.

[0105] Figure 7 and Figure 8 illustrates an embodiment of the first operating mode. Specifically, Figure 7 illustrates a scenario when the memory controller subsystem 50a receives a write request, and Figure 8 illustrates a scenario when the memory controller subsystem 50a receives a read request.

[0106] Specifically, in the first operating mode, each of the memory controllers 500a and 500b is configured to interface with the respective memories 42a and 42b. For example, in the embodiment under consideration, the second switch circuit 508 is configured such that communication EXT1 corresponds to communication EXTa of the first memory controller 500a, and communication EXT2 corresponds to communication EXTb of the second memory controller 500b.

[0107] Thus, in this case, the memory controller subsystem 50a has two associated address sub-ranges within the physical address range of the communication system 52, where requests having addresses within the first sub-range are used to interface to the first memory 42a via the first memory controller 500a, and requests having addresses within the second sub-range are used to interface to the second memory 42b via the second memory controller 500b.

[0108] Generally, the corresponding address mapping operations may be implemented in each of the memory controllers 500a and 500b, or within the switch circuit 506. Specifically, in the former case, each of the communications COMa and COMb corresponds to the communication COM exchanged with the communication system 52. In contrast, in the latter case, the switch circuit 506 receives requests from the communication system 52 via the signal COM, and forwards the request to one of the memory controllers 500a and 500b via the signal COMa or COMb based on the address data ADR included in the request, with the address mapping operation possibly also being implemented.

[0109] For example, in Figure 7 and Figure 8 it is schematically shown that each of the memory controllers 500a and 500b is configured to receive a request that includes:

[0110] - The corresponding address ADRa or ADRb, which may directly correspond to a memory address, such as a memory address obtained via an address mapping operation;

[0111] - The corresponding request control signal CREQa or CREQb, indicating the type of request, i.e., a write request or a read request.

[0112] Moreover, as Figure 7 shown, in the case of a write request, each memory controller 500a and 500b is configured to receive the corresponding data DATA_INa or DATA_INb to be stored in the corresponding memory. Conversely, as Figure 8 shown, in the case of a read request, each memory controller 500a and 500b is configured to provide the corresponding data DATA_OUTa or DATA_OUTb, including the data read from the corresponding memory. As described in the foregoing, these data can also be transmitted via the bidirectional data signal DATA.

[0113] Moreover, each memory controller 500a and 500b can generate one or more response control signals CRESa or CRESb, which signal, for example, indicates that the request has been received and / or processed, e.g., to indicate that the data DATA_OUTa or DATA_OUTb read from the corresponding memory is available.

[0114] Thus, when a write request including an address ADR associated with the memory controller 500a is received, the memory controller 500a uses the signal EXTa, e.g., by asserting the chip select signal CSa, generating the clock signal CLKa, and transmitting the memory address ADRa and the data DATA_Ina via the signal IOa, so as to write the corresponding data DATA_INa (corresponding to the data received from the communication system 52 via the communication COM) into the memory 42a. As mentioned previously, in order to interface with the memory 42a, the second switch circuit 508 can connect the signal EXTa to the signal EXT1, e.g., the signals CSa, CLKa, and IOa can respectively correspond to the signals CS1, CLK, and IO.

[0115] Conversely, when a read request including an address ADR associated with the memory controller 500a is received, the memory controller 500a uses the signal EXTa. For example, by asserting the chip select signal CSa, generating the clock signal CLKa, transmitting the memory address ADRa via the signal IO, and receiving the data DATA_OUTa via the signal IO, in order to read the corresponding data DATA_OUTa from the memory 42a. Also in this case, in order to interface with the memory 42a, the second switch circuit 508 can connect the signal EXTa to the signal EXT1. For example, the signals CSa, CLKa, and IOa can respectively correspond to the signals CS1, CLK, and IO. Next, the memory controller 500a transmits a response signaled via, for example, the signal CRESa, including the data DATA_OUTa (corresponding to the data received from the memory 42a).

[0116] As mentioned previously, when using OctalSPI, the memory address ADRa and the data DATA_INa can be sequentially exchanged via the same bidirectional line IO.

[0117] Similarly, when a write request including an address ADR associated with the memory controller 500b is received, the memory controller 500a uses the signal EXTb. For example, by asserting the chip select signal CSb, generating the clock signal CLKb, and transmitting the memory address ADRb and the data DATA_INb via the signal IOb, in order to write the corresponding data DATA_INb (corresponding to the data received from the communication system 52 via the communication COM) to the memory 42b. As mentioned previously, in order to interface with the memory 42b, the second switch circuit 508 can connect the signal EXTb to the signal EXT2. For example, the signals CSb, CLKb, and IOb can respectively correspond to the signals CS2, CLK, and IO.

[0118] Conversely, when a read request including an address ADR associated with the memory controller 500b is received, the memory controller 500a uses the signal EXTb. For example, by asserting the chip select signal CSb, generating the clock signal CLK, transmitting the memory address ADRb via the signal IO, and receiving the data DATA_OUTb via the signal IO, in order to read the corresponding data DATA_OUTb from the memory 42b. Also in this case, in order to interface with the memory 42b, the second switch circuit 508 can connect the signal EXTb to the signal EXT2. For example, the signals CSb, CLKb, and IOb can respectively correspond to the signals CS2, CLK, and IO. Next, the memory controller 500b transmits a response signaled via, for example, the signal CRESb, including the data DATA_OUTb (corresponding to the data received from the memory 42b).

[0119] Thus, in the embodiments considered, the first operating mode can be used to independently interface two external memories 42a and 42b via two memory controllers 500a and 500b, where each of the memory controllers 500a and 500b has a corresponding sub-range within the address range of the communication system 52. In general, the number of memory controllers 500 (and the corresponding memories 42) can also be greater than two.

[0120] Thus, in various embodiments, the host circuit 54 can write to and read the entire memory space of memories 42a and 42b in the first operating mode.

[0121] Figure 9 and Figure 10 An embodiment of the second operating mode is shown. Specifically, Figure 9 a scenario is shown when the memory controller subsystem 50a receives a write request, and Figure 10 a scenario is shown when the memory controller subsystem 50a receives a read request.

[0122] Specifically, in the embodiments considered, the first memory controller 500a is configured to interface the external memory 42a, while the second memory controller 500a and the comparison circuit 504 are configured to verify the operation of the first memory controller 500a.

[0123] In various embodiments, the memory subsystem 50a can also use the first ECC circuit 502a and optionally use the second ECC circuit 502b. Specifically, in various embodiments, when a write request is received, the first ECC circuit 502a and the first memory controller 500a are configured to store additional ECC bits into the memory 42a. Moreover, when a read request is received, the ECC circuit 502a and the memory controller 500a are configured to verify the ECC bits read from the memory 42a. In this case, the second ECC circuit 502b and the comparison circuit 504 can be configured to verify the operation of the first ECC circuit 502a.

[0124] Specifically, in Figure 9 the embodiment shown, in response to receiving a write request, the first switch circuit 506 is configured to forward the communication COM to the first memory controller 500a, such that the first memory controller 500a receives the address ADRa (e.g., obtained via the address mapping of the address ADR of the communication COM), the corresponding data DATA_INa of the write request, and the corresponding request control signal CREQa (received via the communication COM).

[0125] In various embodiments, the first ECC circuit 502a may be configured to calculate ECC bits based only on the received data DATA_INa or based on the received data DATA_INa and the memory address ADRa.

[0126] Thus, in various embodiments, when a write request including an address ADR associated with the memory controller 500a is received via the communication COM, the memory controller 500a uses the signal EXTa, for example, by asserting the chip select signal CSa, generating the clock signal CLKa, and transmitting the memory address ADRa, the data DATA_INa, and optional ECC bits via the signal IOa, so as to write the corresponding data DATA_INa (corresponding to the data received from the communication system 52 via the communication COM) and the optional ECC bits generated by the ECC circuit 502a into the memory 42a. As mentioned before, for interfacing with the memory 42a, the second switch circuit 508 may connect the signal EXTa to the signal EXT1, for example, the signals CSa, CLKa, and IOa may respectively correspond to the signals CS1, CLK, and IO.

[0127] In various embodiments, the first switch circuit 506 is configured to provide the signals ADRa, DATA_INa, and CREQa as the corresponding signals ADRb, DATA_INb, and CREQb to the second memory controller 500b. In this regard, when the first ECC circuit 502a is used, the second ECC circuit 502b may be configured to calculate second ECC bits based on the received data DATA_INb (i.e., DATA_INa) and optionally the address ADRb (i.e., ADRa).

[0128] Thus, in various embodiments, when a write request is received, the memory controller 500b also generates the signal EXTb, for example, by asserting the chip select signal CSb, generating the clock signal CLKb, and transmitting the memory address ADRb, the data DATA_INb, and optionally the second ECC bits via the signal IOb, so as to write the corresponding data DATA_INb (i.e., DATA_INa) and the optional ECC bits generated by the second ECC circuit 502b into the external memory 42b (which actually does not exist or is at least not used).

[0129] Thus, in the considered embodiments, in order to verify the operation of the memory controller 500a and optionally the ECC circuit 502a, the comparison circuit 504 may include a comparison circuit 5040, which is configured to sequentially compare the bits applied by the memory controller 500a to the (multiple) signals IOa with the bits applied by the memory controller 500b to the (multiple) signals IOb, and assert the error signal A1 in response to determining that one or more bits do not correspond. Although Figure 9Although not shown, the comparison circuit 5040 can also be configured to compare the clock signals CLKa and CLKb and / or the chip select signals CSa and CSb.

[0130] As mentioned previously, in various embodiments, the memory controllers 500a and 500b can also generate one or more corresponding response control signals CRESa and CRESb, for example to indicate that a write request has been received and / or a write request has been executed. Thus, in this case, the comparison circuit 504 can include a comparison circuit 5042, which is configured to compare the signals CRESa and CRESb and assert an error signal A2 in response to determining that the signals CRESa and CRESb do not correspond.

[0131] In various embodiments, the comparison circuit 504 can include combinational logic circuitry 5044, such as an OR gate, which is configured to generate a combinational error signal ERR1, where the combinational logic circuitry 5044 is configured to assert the combinational error signal ERR1 in response to determining that at least one of the error signals A1 and A2 is asserted. In various embodiments, one or more of the error signals A1, A2, and / or ERR1 are provided to the fault collection and error management circuitry of the processing system 10a.

[0132] Conversely, in Figure 10 the illustrated embodiment, in response to receiving a read request, the first switch circuit 506 is again configured to forward the communication COM to the first memory controller 500a, such that the first memory controller 500a receives the address ADRa (e.g., obtained via the address mapping of the address ADR of the communication COM) and a request control signal CREQa indicating the read request.

[0133] Specifically, in the considered embodiment, the first memory controller 500a is again configured to interface with the external memory 42a, while the second memory controller 500a and the comparison circuit 504 are again configured to verify the operation of the first memory controller 500a.

[0134] Thus, in various embodiments, when a read request including an address ADR associated with the memory controller 500a is received, the memory controller 500a uses the signal EXTa, for example by asserting the chip select signal CSa, generating the clock signal CLKa, and transmitting the memory address ADRa via the signal IOa, in order to read the corresponding data DATA_OUTa from the memory 42a. As mentioned previously, in order to interface with the memory 42a, the second switch circuit 508 can connect the signal EXTa to the signal EXT1, e.g., the signals CSa, CLKa, and IOa can correspond to the signals CS1, CLK, and IO, respectively.

[0135] In various embodiments, when ECC bits have been written to the memory in response to a write request, the memory controller 500a also receives the ECC bits via signal IOa (i.e., line IO) accordingly. Thus, in this case, the memory controller 500a can provide the received ECC bits, data DATA_OUTa, and optionally address ADRa to the first ECC circuit 502a, so that the first ECC circuit 502a can calculate other ECC bits based on the data DATA_OUTa and optionally address ADRa (based on the same ECC rules used during the write operation), and assert an error signal E1 when the received ECC bits do not correspond to the calculated ECC bits.

[0136] In various embodiments, the first ECC circuit 502a can also be configured to generate corrected data DATA_OUTa by comparing the received ECC bits with the calculated ECC bits. Specifically, in this case, the ECC circuit 502a can:

[0137] - Assert error signal E1 when an uncorrectable error is detected (e.g., a double-bit error in the case of a single-error correction and double-error detection (SECDED) ECC code);

[0138] - Assert error signal E2 when a correctable error is detected (e.g., a single-bit error with a SECDED code).

[0139] In various embodiments, signals ADRa and CREQa are also provided to the second memory controller 500b as corresponding signals ADRb and CREQb. Thus, in various embodiments, when a read request is received, the memory controller 500b also generates signal EXTb, for example, by asserting chip select signal CSb, generating clock signal CLKb, and transmitting memory address ADRa via signal IOb and then sequentially sampling signal IOb to read corresponding data DATA_OUTb from an external memory 42b (which does not actually exist or is at least not used).

[0140] Thus, when the memory controller 500b also transmits a read command including the same address and the memory controller 500b processes the received data in the same way as the memory controller 500a, the communication between the memory controller 500a and the memory 42a works correctly.

[0141] Thus, in various embodiments, the comparison circuit 504 includes a comparison circuit 5046 (which may correspond to the comparison circuit 5040) configured to verify whether the memory controllers 500a and 500b generate the same signals IOa and IOb in order to transmit a read command including the address ADRa. For example, as previously mentioned, when using OctalSPI, the memory controllers 500a and 500b may be configured to transmit a read command and a memory address via a fixed number of cycles (such as 5 cycles in the case of a 32-bit address). Thus, the comparison circuit 5046 may be configured to determine whether the signals IOa and IOb correspond to each of the fixed number of cycles, and assert an error signal A3 in response to determining that one or more bits do not correspond. Although Figure 10 not shown in Figure 10 , the comparison circuit 5046 may also be configured to compare the clock signals CLKa and CLKb and / or the chip select signals CSa and CSb.

[0142] In various embodiments, the data DATA_OUTa received via the signal IO is also provided to the memory controller 500b. For example, when using OctalSPI, once a read command has been transmitted via a fixed number of cycles, the memory 42a applies the corresponding data to the line IO. For example, in various embodiments, the second switch circuit 508 may include a switch 5080 configured to provide the signal IOb to the comparison circuit 5046 during a fixed number of cycles and connect the signal IOb to the line IO to receive the data DATA_OUTa. For example, in response to determining that the fixed number of cycles has been reached, the switch 5080 may be driven by the switch circuit 508, the first memory controller 500a, or the control circuit 510.

[0143] Thus, the memory controller 500b receives the data DATA_OUTb, which should correspond to the data DATA_OUTa read from the memory 42a. In this regard, when ECC bits have been written to the memory 42a in response to a write request, the memory controller 500b also receives the ECC bits via the signal IOb (i.e., the line IO). Thus, in this case, the memory controller 500b may provide the received ECC bits, the received data DATA_OUTb (which should correspond to the data DATA_OUTa), and optionally the address ADRa to the second ECC circuit 502b, so that the second ECC circuit 502b can calculate additional ECC bits based on the data DATA_OUTb and optionally the address ADRa (depending on the ECC scheme used), and assert an error signal E3 when the received ECC bits do not correspond to the calculated ECC bits.

[0144] Similar to the first ECC circuit 502a, in various embodiments, the second ECC circuit 502b may also be configured to generate correction data DATA_OUTb by comparing the received ECC bits with the calculated ECC bits. Specifically, in such a case, the ECC circuit 502b may:

[0145] - Assert the error signal E3 when an uncorrectable error is detected (e.g., a double-bit error in the case of a SECDED ECC code);

[0146] - Assert the error signal E4 when a correctable error is detected (e.g., a single-bit error with a SECDED code).

[0147] Once the data DATA_OUTa has been received and optionally corrected via the ECC circuit 502a, the memory controller 500a generates a response for transmitting the data DATA_OUTa via the signal COMa, for example, by asserting one or more response control signals CRESa. Similarly, once the data DATA_OUTb has been received and optionally corrected via the ECC circuit 502b, the memory controller 500b generates a response for transmitting the data DATA_OUTb via the signal COMb, for example, by asserting one or more response control signals CRESb. Generally, each of the response control signals CRESa and CRESb may also include signals for indicating the status of the ECC verification, such as the signals E1 and / or E2 and E3 and / or E4, respectively.

[0148] Thus, in various embodiments, the comparison circuit 504 may include a comparison circuit 5048 (possibly corresponding to the comparison circuit 5042), which is configured to compare the signals CRESa and CRESb and assert the error signal A4 in response to determining that the signals CRESa and CRESb do not correspond. Similarly, in various embodiments, the comparison circuit 504 may include a comparison circuit 5050, which is configured to compare the signals DATA_OUTa and DATA_OUTb (provided by the memory controllers 500a and 500b) and assert the error signal A5 in response to determining that the signals DATA_OUTa and DATA_OUTb do not correspond.

[0149] In various embodiments, the comparison circuit 504 may thus include combinational logic circuit 5052, such as an OR gate, configured to generate a combined error signal ERR2 indicative of uncorrectable errors, where the combinational logic circuit 5052 is configured to assert the combined error signal ERR2 in response to determining that at least one of the error signals A3, A4, A5, E1, and E3 (in use) is asserted. In various embodiments, one or more of the error signals A3, A4, A5, E1, E3, and / or ERR2 are provided to the fault collection and error management circuitry of the processing system 10a.

[0150] In various embodiments, the comparison circuit 504 may also include combinational logic circuit 5054, such as an OR gate, configured to generate a combined error signal ERR3 indicative of correctable errors, where the combinational logic circuit 5054 is configured to assert the combined error signal ERR3 in response to determining that at least one of the error signals E2 and E4 is asserted. In various embodiments, one or more of the error signals E2, E4, and / or ERR3 are provided to the fault collection and error management circuitry of the processing system 10a.

[0151] Thus, in the embodiments considered, the second operating mode allows an ASIL-B / C configuration to be implemented with a single memory 42a. Specifically, by using the ECC codes calculated for data and memory addresses, the entire path from the communication COM received from the communication system 52 to the device interface EXT1 to the external memory 42a can be protected. Then, when data is read from the external memory 42a, the ECC codes are verified.

[0152] For example, in Figure 9 the embodiment shown, the address, data, and request control signals received from the communication system 52 are sent to both memory controllers 500a and 500b. Comparator 5040 verifies the signals EXTa and EXTb generated by memory controllers 500a and 500b. Another comparator 5048 verifies the responses generated by memory controllers 500a and 500b. In contrast, in Figure 10 the embodiment shown, the address and request control signals received from the communication system 52 are sent to both memory controllers 500a and 500b. Comparator 5046 verifies the signals EXTa and EXTb generated by memory controllers 500a and 500b. Moreover, two comparators 5048 and 5050 verify the data and responses generated by memory controllers 500a and 500b.

[0153] However, this scheme does not protect all possible faults within the memory 42a, such as internal stuck signals, whereby a memory location not corresponding to the requested memory address specified via signal ADRa is written to or read from.

[0154] Figure 11 and Figure 12 illustrates an embodiment of a third operation mode. Specifically, Figure 11 illustrates a scenario when the memory controller subsystem 50a receives a write request, and Figure 12 illustrates a scenario when the memory controller subsystem 50a receives a read request.

[0155] Specifically, in the embodiment under consideration, the first memory controller 500a is configured to interface with the first external memory 42a, and the second memory controller 500b is configured to interface with the second external memory 42b. Moreover, the first memory controller 500a and the second memory controller 500b are configured to store the same data into the first memory 42a and the second memory 42b, thereby substantially copying the content of the memory 42a to the memory 42b. In fact, in this way, the comparison circuit 504 can be configured to verify whether the data read from the first memory 42a via the first memory controller 500a corresponds to the data read from the second memory 42b via the second memory controller 500b, thereby also verifying the operation of the memory 42a.

[0156] In various embodiments, the memory subsystem 50a may also use the first ECC circuit 502a and the second ECC circuit 502b. Specifically, in various embodiments, when a write request is received, the first ECC circuit 502a and the first memory controller 500a are configured to store additional ECC bits into the memory 42a. Similarly, the second ECC circuit 502b and the second memory controller 500b are configured to store additional ECC bits into the memory 42b. Moreover, when a read request is received, the ECC circuit 502a and the memory controller 500a are configured to verify the ECC bits read from the memory 42a. Similarly, the ECC circuit 502b and the memory controller 500b are configured to verify the ECC bits read from the memory 42b. In this case, the comparison circuit 504 can be configured to also verify the operation of the first ECC circuit 502a.

[0157] Specifically, in Figure 11 the illustrated embodiment, in response to receiving a write request, the first switch circuit 506 is configured to forward the communication COM to the first memory controller 500a, so that the first memory controller 500a receives the address ADRa (e.g., obtained through the address mapping of the address ADR of the communication COM), the corresponding data DATA_INa of the write request, and the corresponding request control signal CREQa (received via the communication COM).

[0158] In various embodiments, the first ECC circuit 502a may be configured to calculate ECC bits based on the received data DATA_INa and optionally the address ADRa.

[0159] Thus, in various embodiments, when a write request including an address ADR associated with the memory controller 500a is received via the communication COM, the memory controller 500a uses the signal EXTa, for example by asserting the chip select signal CSa, generating the clock signal CLKa and transmitting the memory address ADRa, the data DATA_INa and optionally the ECC bits via the signal IOa, so as to write the corresponding data DATA_INa (corresponding to the data received from the communication system 52 via the communication COM) and the optional ECC bits generated by the ECC circuit 502a into the memory 42a. As mentioned before, in order to interface with the memory 42a, the second switch circuit 508 may connect the signal EXTa to the signal EXT1, for example the signals CSa, CLKa and IOa may correspond to the signals CS1, CLK and IO respectively.

[0160] In various embodiments, the first switch circuit 506 is configured to provide the signals ADRa, DATA_INa and CREQa as the corresponding signals ADRb, DATA_INb and CREQb to the second memory controller 500b. In this regard, when the first ECC circuit 502a is used, the second ECC circuit 502b may be configured to calculate second ECC bits based on the received data DATA_INb (i.e., DATA_INa) and optionally the address ADRb (i.e., ADRa).

[0161] Thus, in various embodiments, when a write request is received, the memory controller 500b also generates the signal EXTb, for example by asserting the chip select signal CSb, generating the clock signal CLKb and transmitting the memory address ADRb, the data DATA_INb and optionally the ECC bits via the signal IOb, so as to write the corresponding data DATA_INb (i.e., DATA_INa) and the optional ECC bits generated by the second ECC circuit 502b into the external memory 42b. As mentioned before, in order to interface with the memory 42b, the second switch circuit 508 may connect the signal EXTb to the signal EXT2, for example the signals CSb, CLKb and IOb may correspond to the signals CS2, CLK and IO respectively.

[0162] Specifically, when using the shared signals CLK and IO, actually during a given cycle, only one of the memory controllers 500a and 500b can transmit data. Thus, in this case, the memory subsystem 50a may include a selection circuit 5082 configured to indicate one of the memory controllers 500a and 500b that is allowed to access the shared signals CLK and IO. For example, the selection circuit 5082 may be implemented with an arbiter. Thus, once a write request is received via the signal COM, the selection circuit 5082 can select one of the memory controllers 500a and 500b (e.g., memory controller 500a), such that this memory controller can write the received data to the corresponding external memory (e.g., memory 42a). Next, the selection circuit 5082 can select the other memory controller 500a or 500b (e.g., memory controller 500b), such that this memory controller can write the received data to the corresponding external memory (e.g., memory 42b).

[0163] In various embodiments, the comparison circuit 504 may be configured to verify one or more signals generated by the memory controller 500a or 500b. For example, in the considered embodiment, the comparison circuit 504 includes a comparison circuit 5056 configured to assert an error signal ERR4 when the response control signals CRESa and CRESb generated by the memory controller 500a or 500b do not correspond after two write operations are completed. For example, the comparison circuit 5056 may correspond to Figure 9 the comparison circuit 5042 shown and / or Figure 10 the comparison circuit 5048 shown, which are used for the second operation mode.

[0164] Conversely, in Figure 12 the embodiment shown, in response to receiving a read request, the first switch circuit 506 is again configured to forward the communication COM to the first memory controller 500a, such that the first memory controller 500a receives the address ADRa (e.g., obtained by address mapping of the address ADR of the communication COM) and a request control signal CREQa indicating the read request.

[0165] Specifically, in the considered embodiment, the first memory controller 500a and the second memory controller 500b are again configured to interface with the corresponding external memories 42a and 42b, while the comparison circuit 504 is configured to compare one or more signals generated by the memory controllers 500a and 500b and / or by the ECC circuits 502a and 502b.

[0166] Thus, in various embodiments, when a read request including an address ADR associated with the memory controller 500a is received, the memory controller 500a uses the signal EXTa, e.g., by asserting the chip select signal CSa, generating the clock signal CLKa, and transmitting the memory address ADRa via the signal IOa, so as to read the corresponding data DATA_OUTa from the memory 42a. As mentioned previously, for interfacing with the memory 42a, the second switch circuit 508 may connect the signal EXTa to the signal EXT1, e.g., the signals CSa, CLKa, and IOa may correspond to the signals CS1, CLK, and IO, respectively.

[0167] In various embodiments, when writing ECC bits to the memory in response to a write request, the memory controller 500a also receives the ECC bits via the signal IOa (i.e., the line IO) accordingly. Thus, in this case, the memory controller 500a may provide the received ECC bits, the received data DATA_OUTa, and optionally the address ADRa to the first ECC circuit 502a, so that the first ECC circuit 502a may calculate other ECC bits based on the data DATA_OUTa and optionally the address ADRa (depending on the ECC scheme used), and assert the error signal E1 when the received ECC bits do not correspond to the calculated ECC bits.

[0168] As described in the foregoing, in various embodiments, the first ECC circuit 502a may also be configured to generate the corrected data DATA_OUTa by comparing the received ECC bits with the calculated ECC bits. Specifically, in this case, the ECC circuit 502a may:

[0169] - Assert the error signal E1 when an uncorrectable error is detected (e.g., a double-bit error in the case of a SECDED ECC code);

[0170] - Assert the error signal E2 when a correctable error is detected (e.g., a single-bit error with a SECDED code).

[0171] In various embodiments, signals ADRa and CREQa are also provided as corresponding signals ADRb and CREQb to the second memory controller 500b. Thus, in various embodiments, when a read request is received, memory controller 500b also uses signal EXTb, e.g., by asserting chip select signal CSb, to generate clock signal CLKb and transmit memory address ADRb (corresponding to memory address ADRa) via signal IOb to read corresponding data DATA_OUTb from memory 42b. As previously mentioned, to interface with memory 42b, second switch circuit 508 may connect signal EXTb to signal EXT2, e.g., signals CSb, CLKb, and IOb may correspond to signals CS2, CLK, and IO, respectively.

[0172] In various embodiments, when ECC bits have been written to the memory in response to a write request, memory controller 500b also receives the ECC bits via signal IOb (i.e., line IO) accordingly. Thus, in this case, memory controller 500b may provide the received ECC bits, the received data DATA_OUTb, and optionally address ADRb (i.e., ADRa) to the second ECC circuit 502b, so that the second ECC circuit 502b may calculate additional ECC bits based on the received data DATA_OUTb and optionally address ADRb, and assert error signal E3 when the received ECC bits do not correspond to the calculated ECC bits.

[0173] In various embodiments, similar to ECC circuit 502a, the second ECC circuit 502b may also be configured to generate corrected data DATA_OUTb by comparing the received ECC bits with the calculated ECC bits. Specifically, in this case, ECC circuit 502b may:

[0174] - Assert error signal E3 when an uncorrectable error is detected (e.g., a double-bit error in the case of a SECDED ECC code); and

[0175] - Assert error signal E4 when a correctable error is detected (e.g., a single-bit error with a SECDED code).

[0176] Moreover, in this case, when using the shared signals CLK and IO, actually during a given cycle, only one of the memory controllers 500a and 500b can exchange data. Thus, in this case, the selection circuit 5082 can be configured to indicate one of the memory controllers 500a and 500b that is allowed to access the shared signals CLK and IO. Therefore, once a write request is received via the signal COM, the selection circuit 5082 can select one of the memory controllers 500a and 500b (e.g., memory controller 500a), so that this memory controller can communicate with the corresponding external memory (e.g., memory 42a). Next, the selection circuit 5082 can select the other memory of either memory controller 500a or 500b (e.g., memory controller 500b), so that this memory controller can communicate with the corresponding external memory (e.g., memory 42b).

[0177] In various embodiments, the comparison circuit 504 can be configured to verify one or more signals generated by the memory controller 500a or 500b.

[0178] For example, in the considered embodiment, the comparison circuit 504 includes a comparison circuit 5058, which is configured to: in response to determining that the response control signals CRESa and CRESb generated by the memory controller 500a or 500b do not correspond after two write operations are completed, assert an error signal A6. For example, the comparison circuit 5058 can correspond to Figure 11 the comparison circuit 5056 shown.

[0179] Additionally or alternatively, the comparison circuit 504 can include a comparison circuit 5060, which is configured to compare the signals DATA_OUTa and DATA_OUTb (the correction data provided by the memory controllers 500a and 500b or by the ECC circuits 502a and 502b), and assert an error signal A7 in response to determining that the signals DATA_OUTa and DATA_OUTb do not correspond. For example, the comparison circuit 5060 can correspond to Figure 10 the comparison circuit 5050 shown.

[0180] In various embodiments, the comparison circuit 504 may thus include combinational logic circuit 5062, such as an OR gate, configured to generate a combined error signal ERR2 indicative of uncorrectable errors, where the combinational logic circuit 5062 is configured to assert the combined error signal ERR5 in response to determining that at least one of the error signals A6, A7, E1, and E3 (in use) is asserted. In various embodiments, one or more of the error signals A6, A7, E1, E3, and / or ERR5 are provided to the fault collection and error management circuit of the processing system 10a.

[0181] In various embodiments, the comparison circuit 504 may also include combinational logic circuit 5064, such as an OR gate, configured to generate a combined error signal ERR6 indicative of correctable errors, where the combinational logic circuit 5064 is configured to assert the combined error signal ERR6 in response to determining that at least one of the error signals E2 and E4 is asserted. In various embodiments, one or more of the error signals E2, E4, and / or ERR6 are provided to the fault collection and error management circuit of the processing system 10a. For example, the combinational logic circuit 5064 may correspond to Figure 10 the combinational logic circuit 5054 shown.

[0182] Thus, in Figure 11 and Figure 12 the embodiment shown, the first memory 42a (via the switch circuit 508) is connected to the memory controller 500a, and the second (preferably identical) memory 42b is connected to the second memory controller 500b. The two memories 42a and 42b and the memory controllers 500a and 500b are used substantially in a replicated mode.

[0183] Figure 11 and Figure 12 The third operating mode shown in and allows for obtaining an ASIL-D configuration since the entire path from the communication system 52 to the device interfaces EXT1 and EXT2 to the external memories 42a and 42b is protected. Additionally, an ECC code may be calculated from the data DATA_INa and the memory address ADRa and appended to the data DATA_INa written in the external memories 42a and 42b, and then it may be verified for each read operation. Possible faults within the external memories 42a and 42b are covered by replication.

[0184] Thus, in various embodiments, the memory subsystem 50a supports multiple operating modes, where one of the operating modes is selected based on (e.g., static) configuration data CD. For example, the configuration may be selected based on the type and quantity of data to be stored in the external memory 42a or memories 42a and 42b and the required protection.

[0185] Basically, the first operating mode allows the use of the full memory space of the two external memories 42a and 42b. Although Figure 7 and Figure 8 not explicitly shown in, in this operating mode, the ECC circuits 502a and 502b (similar to Figure 11 and Figure 12 shown) can also be used to store additional ECC bits into the memories 42a and 42b.

[0186] Conversely, the second and third operating modes use the second memory controller 500b and the comparison circuit 508 to verify the operation of the first memory controller 500a. In this regard, when the first ECC circuit 502a is used, the second ECC circuit 502b and the comparison circuit 508 are configured to verify the operation of the first ECC circuit 502a. Specifically, in both operating modes, the comparison circuit 508 is configured to compare the signals COMa and COMb generated by the memory controllers 500a and 500b. For example, the comparison circuits 5042, 5048, 5056, and 5058 (possibly corresponding to the same comparison circuit) are configured to compare the response control signals CRESa and CRESb, and the comparison circuits 5050 and 5060 (possibly corresponding to the same comparison circuit) are configured to compare the response data DATA_OUTa and DATA_OUTb.

[0187] In the third operating mode, this comparison is sufficient because the memory controllers 500a and 500b individually interface the two memories 42a and 42b with the data replication interface. Conversely, in the second operating mode, the memory controllers 500a and 500b interface a single memory 42a, but the additional comparison circuits 5040 and 5046 (possibly corresponding to the same comparison circuit) are configured to compare at least a portion of the signals EXTa and EXTb generated by the memory controllers 500a and 500b. Specifically, in various embodiments, the comparison circuits 5040 and 5046 (possibly corresponding to the same comparison circuit) are configured to compare the signals IOa and IOb at least during the periods when the memory controllers 500a and 500b apply data to these signals to, for example, issue a write request and the corresponding data or a read request. As previously mentioned, the comparison circuit 508 can also be configured to compare the clock signals CLKa and CLKb and / or the chip select signals CSa and CSb.

[0188] Of course, without prejudice to the principles of the present invention, the details of the construction and embodiments can vary widely with respect to what is only described and illustrated herein by way of example, without thereby departing from the scope of the present invention as defined by the subsequent claims.

Claims

1. A processing system integrated in an integrated circuit, the processing system comprising: A communication system; A memory controller subsystem configured to interface with a memory external to the integrated circuit; A host circuit configured to send write requests and read requests to the memory controller subsystem via the communication system to store data in and read data from the memory; Wherein the memory controller subsystem is connected to the communication system and a communication channel, the communication channel is connected to a terminal of the integrated circuit, the terminal is configured to be connected to the memory, and wherein the communication channel includes data signals; Wherein the memory controller subsystem includes a first memory controller and a second memory controller, and wherein each of the first memory controller and the second memory controller is configured to: Receive a write request or a read request including data indicating a memory address, and for the write request, receive the corresponding data to be stored; In response to receiving the write request: Extract the corresponding memory address and the corresponding data to be stored from the write request, and Generate a corresponding first communication or second communication for storing the extracted corresponding data at the extracted corresponding memory address by generating a corresponding first data signal or second data signal for transmitting the extracted corresponding memory address and the extracted corresponding data; In response to receiving a read request: Extract the corresponding memory address from the read request, Generate the corresponding first communication or second communication for receiving data associated with the extracted memory address by generating the corresponding first data signal or second data signal to transmit the extracted corresponding memory address and receive the corresponding data associated with the extracted memory address, and Generate a corresponding first response or second response including the received corresponding data; Wherein, in a first operating mode, the first communication of the first memory controller is connected to the communication channel, wherein the first data signal corresponds to the data signal, and the memory controller subsystem is configured to: In response to receiving the write request from the communication system: Forward the received write request to the first memory controller and the second memory controller, wherein the first memory controller generates the corresponding first data signal for transmitting the extracted corresponding memory address and the extracted corresponding data, and the second memory controller generates the corresponding second data signal for transmitting the extracted corresponding memory address and the extracted corresponding data, and Compare the first data signal with the second data signal, and assert a first error signal in response to determining that the first data signal does not correspond to the second data signal; In response to receiving the read request from the communication system: Forward the received read request to the first memory controller and the second memory controller, wherein the first memory controller generates the corresponding first data signal, the corresponding first data signal is used to transmit the extracted corresponding memory address and receive the corresponding data associated with the extracted corresponding memory address, and the second memory controller generates the corresponding second data signal, the corresponding second data signal is used to transmit the extracted corresponding memory address and receive the corresponding data associated with the extracted corresponding memory address, and the first memory controller generates the corresponding response including the received corresponding data, and the second memory controller generates the corresponding response including the received corresponding data; In response to determining that the first memory controller transmits the extracted memory data via the first data signal, compare the first data signal with the second data signal, and in response to determining that the first data signal does not correspond to the second data signal, assert a second error signal; and In response to determining that the first memory controller receives the corresponding data via the first data signal, connect the first data signal to the second data signal, compare the first response generated by the first memory controller with the second response generated by the second memory controller, and in response to determining that the first response does not correspond to the second response, assert a third error signal.

2. The processing system according to claim 1, wherein the communication channel is a shared communication channel, and wherein, In the second operation mode, the first communication of the first memory controller and the second communication of the second memory controller are connected to the communication channel, wherein the first data signal and the second data signal correspond to the data signal, and the memory controller subsystem is configured to: In response to receiving a write request from the communication system: Select one memory controller from the first memory controller and the second memory controller, Forward the received write request to the one memory controller, wherein the one memory controller generates the corresponding first data signal for transmitting the extracted corresponding memory address and the extracted corresponding data, Select the other memory controller from the first memory controller and the second memory controller, and Forward the received write request to the other memory controller, wherein the other memory controller generates the corresponding first data signal for transmitting the extracted corresponding memory address and the extracted corresponding data; And In response to receiving a read request from the communication system: Select one memory controller from the first memory controller and the second memory controller, Forward the received read request to the one memory controller, where the one memory controller generates the corresponding data signal, the corresponding data signal is used to transmit the extracted corresponding memory address and receive the corresponding data associated with the extracted corresponding memory address, and the one memory controller generates the corresponding response including the received corresponding data. Select the other memory controller among the first memory controller and the second memory controller. Forward the received read request to the other memory controller, where the other memory controller generates the corresponding data signal, the corresponding data signal is used to transmit the extracted corresponding memory address and receive the corresponding data associated with the extracted corresponding memory address, and the other memory controller generates the corresponding response including the received corresponding data, and Compare the first response generated by the first memory controller with the second response generated by the second memory controller, and in response to determining that the first response does not correspond to the second response, assert a fourth error signal.

3. The processing system according to claim 2, wherein the first response and the second response include corresponding first response control signals and second response control signals, and wherein, In the first operation mode and / or the second operation mode, the memory controller subsystem is configured to compare the first response control signal generated by the first memory controller with the second response control signal generated by the second memory controller, and in response to determining that the first response control signal does not correspond to the second response control signal, assert a fifth error signal.

4. The processing system according to claim 2, wherein the communication channel is a shared communication channel, and wherein, In a third operation mode, the first communication of the first memory controller and the second communication of the second memory controller are connected to the communication channel, where the first data signal and the second data signal correspond to the data signal, and the memory controller subsystem is configured to: In response to receiving a write request from the communication system: Determine whether the write request includes data indicating a memory address associated with the first memory controller or data indicating a memory address associated with the second memory controller. In response to determining that the write request includes data indicating a memory address associated with the first memory controller, forward the received write request to the first memory controller, where the first memory controller generates the corresponding first data signal for transmitting the extracted corresponding memory address and the extracted corresponding data, and In response to determining that the write request includes data indicating a memory address associated with the second memory controller, forward the received write request to the second memory controller, where the second memory controller generates the corresponding second data signal for transmitting the extracted corresponding memory address and the extracted corresponding data; And In response to receiving a read request from the communication system: Determine whether the read request includes data indicating a memory address associated with the first memory controller or data indicating a memory address associated with the second memory controller, In response to determining that the read request includes data indicating a memory address associated with the first memory controller, forward the received read request to the first memory controller, wherein the first memory controller generates the corresponding data signal, the corresponding data signal is used to transmit the extracted corresponding memory address and receive the corresponding data associated with the extracted corresponding memory address, and the first memory controller generates the corresponding response including the received corresponding data, and In response to determining that the read request includes data indicating a memory address associated with the second memory controller, forward the received read request to the second memory controller, wherein the second memory controller generates the corresponding data signal, the corresponding data signal is used to transmit the extracted corresponding memory address and receive the corresponding data associated with the extracted corresponding memory address, and the second memory controller generates the corresponding response including the received corresponding data.

5. The processing system according to claim 4, wherein the shared communication channel includes a first chip enable signal applicable to enable the first memory and a second chip enable signal applicable to enable the second memory, and wherein the first memory controller is configured to assert the first chip enable signal when transmitting or receiving data via the first data signal, and the second memory controller is configured to assert the second chip enable signal when transmitting or receiving data via the second data signal.

6. The processing system according to claim 5, wherein the shared communication channel is a Serial Peripheral Interface bus or OctalSPI.

7. The processing system according to claim 1, wherein the memory controller subsystem includes a first Error Correction Code (ECC) circuit associated with the first memory controller and a second ECC circuit associated with the second memory controller, wherein each of the first memory controller and the second memory controller is configured to: In response to receiving a write request: Calculate ECC bits via the corresponding first ECC circuit or the second ECC circuit, and Transmit the extracted corresponding memory address, the extracted corresponding data, and the calculated corresponding ECC bits; and In response to receiving a read request: Transmit the extracted corresponding memory address and receive the corresponding data and corresponding ECC bits; Calculate other ECC bits via the corresponding first ECC circuit or the second ECC circuit, and Compare the other ECC bits with the received ECC bits, and in response to determining that the other ECC bits do not correspond to the received ECC bits, assert an ECC error signal.

8. The processing system according to claim 7, wherein the first ECC circuit and the second ECC circuit are error detection and correction circuits configured to generate correction data, and wherein the first response or the second response includes the corresponding corrected data.

9. The processing system according to claim 7, wherein the first ECC circuit and the second ECC circuit are configured to calculate the corresponding ECC bits based on the corresponding data extracted or the received data and the corresponding memory address.

10. The processing system according to claim 4, wherein the memory controller subsystem includes control circuitry configured to receive configuration data and select one of the first operation mode, the second operation mode, or the third operation mode based on the configuration data.

11. A method of operating a processing system integrated in an integrated circuit, the processing system including a communication system, a memory controller subsystem, and a host circuit, the memory controller subsystem including a first memory controller and a second memory controller, and the memory controller subsystem being connected to a communication channel including data signals and to terminals of the integrated circuit, the terminals being connected to a memory external to the integrated circuit, the method including, in a first operation mode: sending, by the host circuit, write and read requests to the memory controller subsystem via the communication system to store data in the memory and read data from the memory; connecting the first memory controller to the communication channel, a first data signal corresponding to the data signal; in response to receiving a write request from the communication system: forwarding the received write request to the first memory controller and the second memory controller, wherein the first memory controller generates the corresponding first data signal for transmitting the corresponding memory address and the corresponding data extracted, and the second memory controller generates a corresponding second data signal for transmitting the corresponding memory address and the corresponding data extracted; and comparing the first data signal with the second data signal, and asserting a first error signal in response to determining that the first data signal does not correspond to the second data signal; in response to receiving a read request from the communication system: Forward the received read request to the first memory controller and the second memory controller, where the first memory controller generates the corresponding first data signal for transmitting the extracted corresponding memory address and receiving the corresponding data associated with the extracted corresponding memory address, and the second memory controller generates the corresponding second data signal for transmitting the extracted corresponding memory address and receiving the corresponding data associated with the extracted corresponding memory address, and the first memory controller generates the corresponding response including the received corresponding data, and the second memory controller generates the corresponding response including the received corresponding data; In response to determining that the first memory controller transmits the extracted memory data via the first data signal, compare the first data signal with the second data signal, and in response to determining that the first data signal does not correspond to the second data signal, assert a second error signal; And In response to determining that the first memory controller receives the corresponding data via the first data signal, connect the first data signal to the second data signal, compare the first response generated by the first memory controller with the second response generated by the second memory controller, and in response to determining that the first response does not correspond to the second response, assert a third error signal.

12. The method according to claim 11, wherein the communication channel is a shared communication channel, and wherein, In a second operating mode, the first communication of the first memory controller and the second communication of the second memory controller are connected to the communication channel, where the first data signal and the second data signal correspond to the data signal, and the method includes: In response to receiving a write request from the communication system: Select one of the first memory controller and the second memory controller; Forward the received write request to the one memory controller, where the one memory controller generates the corresponding first data signal for transmitting the extracted corresponding memory address and the extracted corresponding data; Select the other one of the first memory controller and the second memory controller, and Forward the received write request to the other memory controller, where the other memory controller generates the corresponding first data signal for transmitting the extracted corresponding memory address and the extracted corresponding data; and In response to receiving a read request from the communication system: Select one of the first memory controller and the second memory controller, Forward the received read request to the one memory controller, where the one memory controller generates the corresponding data signal for transmitting the extracted corresponding memory address and receiving the corresponding data associated with the extracted corresponding memory address, and the one memory controller generates the corresponding response including the received corresponding data. Select the other memory controller of the first memory controller and the second memory controller. Forward the received read request to the other memory controller, where the other memory controller generates the corresponding data signal for transmitting the extracted corresponding memory address and receiving the corresponding data associated with the extracted corresponding memory address, and the other memory controller generates the corresponding response including the received corresponding data, and Compare the first response generated by the first memory controller with the second response generated by the second memory controller, and assert a fourth error signal in response to determining that the first response does not correspond to the second response.

13. The method according to claim 12, wherein the first response and the second response include corresponding first response control signals and second response control signals, and wherein, In the first operation mode and / or the second operation mode, the method includes: comparing the first response control signal generated by the first memory controller with the second response control signal generated by the second memory controller, and asserting a fifth error signal in response to determining that the first response control signal does not correspond to the second response control signal.

14. The method according to claim 12, wherein the communication channel is a shared communication channel, and wherein, In a third operation mode, the first communication of the first memory controller and the second communication of the second memory controller are connected to the communication channel, where the first data signal and the second data signal correspond to the data signal, and the method includes: In response to receiving a write request from the communication system: Determine whether the write request includes data indicating a memory address associated with the first memory controller or data indicating a memory address associated with the second memory controller. In response to determining that the write request includes data indicating a memory address associated with the first memory controller, forward the received write request to the first memory controller, where the first memory controller generates the corresponding first data signal for transmitting the extracted corresponding memory address and the extracted corresponding data, and In response to determining that the write request includes data indicating a memory address associated with the second memory controller, forward the received write request to the second memory controller, where the second memory controller generates the corresponding second data signal for transmitting the extracted corresponding memory address and the extracted corresponding data; and In response to receiving a read request from the communication system: Determine whether the read request includes data indicating a memory address associated with the first memory controller or data indicating a memory address associated with the second memory controller, In response to determining that the read request includes data indicating a memory address associated with the first memory controller, forward the received read request to the first memory controller, wherein the first memory controller generates the corresponding data signal, the corresponding data signal is used to transmit the extracted corresponding memory address and receive the corresponding data associated with the extracted corresponding memory address, and the first memory controller generates the corresponding response including the received corresponding data, and In response to determining that the read request includes data indicating a memory address associated with the second memory controller, forward the received read request to the second memory controller, wherein the second memory controller generates the corresponding data signal, the corresponding data signal is used to transmit the extracted corresponding memory address and receive the corresponding data associated with the extracted corresponding memory address, and the second memory controller generates the corresponding response including the received corresponding data.

15. The method according to claim 14, wherein the shared communication channel includes a first chip enable signal adapted to enable a first memory and a second chip enable signal adapted to enable a second memory, and wherein the method includes: Assert the first chip enable signal when transmitting or receiving data via the first data signal, and the second memory controller asserts the second chip enable signal when transmitting or receiving data via the second data signal.

16. The method according to claim 15, wherein the shared communication channel is a Serial Peripheral Interface bus or OctalSPI.

17. The method according to claim 11, wherein the memory controller subsystem includes a first Error Correction Code (ECC) circuit associated with the first memory controller and a second ECC circuit associated with the second memory controller, and the method includes, for each of the first memory controller and the second memory controller: In response to receiving a write request: Calculate ECC bits via the corresponding first ECC circuit or the second ECC circuit, and Transmit the extracted corresponding memory address, the extracted corresponding data, and the calculated corresponding ECC bits; and In response to receiving a read request: Transmit the extracted corresponding memory address and receive the corresponding data and corresponding ECC bits; Calculate other ECC bits via the corresponding first ECC circuit or the second ECC circuit, and Compare the other ECC bits with the received ECC bits, and in response to determining that the other ECC bits do not correspond to the received ECC bits, assert an ECC error signal.

18. The method according to claim 17, wherein the first ECC circuit and the second ECC circuit are error detection and correction circuits, and the method includes generating corrected data, and wherein the first response or the second response includes the corrected corresponding data.

19. The method according to claim 17, further comprising: The corresponding ECC bits are calculated by the first ECC circuit and the second ECC circuit according to the extracted corresponding data or the received data and the corresponding memory address.

20. The method according to claim 14, wherein the memory controller subsystem includes control circuitry, and the method includes: Configuration data is received by the control circuit, and one of the first operation mode, the second operation mode, or the third operation mode is selected according to the configuration data.

Images