Frequency spectrum segmentation FFT method and device based on FPGA

Abstract

The invention provides a frequency spectrum segmentation FFT (Fast Fourier Transform) method and device based on an FPGA (Field Programmable Gate Array). The method comprises the following steps: step 1, acquiring original data of a time domain of a real-time vector signal through acquisition equipment; 2, parameters of a frequency spectrum segmentation FFT model are set, the parameters are set through an input configuration signal FFTconfig, the bit width of the signal FFTconfig is 8 bits, low 4 bits are the set point number L of each path of signal, and the calculation method is the power of a decimal number corresponding to the low 4 bits of 2; the high 4 bits are the channel number M; step 3, inputting the obtained original data of the time domain of the vector signal into a frequency spectrum segmentation FFT model; and step 4, outputting frequency domain data of the vector signal. The method supports a wide range of FFT points, can process FFT points of non-second power, and can effectively reduce the time for processing large-point FFT through multi-channel FFT parallel processing.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and particularly to a spectrum segmentation FFT method and device based on FPGA. Background Art

[0002] Fast Fourier Transform (FFT) is a core algorithm widely used in the fields of signal processing, communication, radar, medical imaging, etc. Traditional FFT usually performs calculations based on the radix-2 or higher-order radix-r algorithms, and most hardware acceleration schemes face problems of computational complexity and storage bottlenecks when processing FFT with a large number of points. In addition, existing FFT architectures often only support powers of 2 number of points (such as 512, 1024, 2048, etc.), and for non-power-of-2 number of points (such as 1000, 3000, etc.), the computational efficiency is low, and additional interpolation or zero-padding operations are even required, resulting in resource waste and increased computational time.

[0003] On the other hand, traditional parallel FFT architectures usually perform parallel calculations based on even channels such as 2, 4, 8, etc., and have poor support for odd channels (such as 3-channel, 5-channel). This limitation reduces the utilization rate of FFT computational resources in some specific applications (such as multi-input multi-output (MIMO) communication systems, unequally spaced sampling signal processing, sampling rate being an odd multiple of the clock frequency, etc.), and it is difficult to achieve flexible parallel processing. Summary of the Invention

[0004] Object of the Invention: The technical problem to be solved by the present invention is to provide a spectrum segmentation FFT method and device based on FPGA aiming at the deficiencies of the prior art, which can support 2, 3, 5, 8 channels, and the number of points is of FFT, where , , and can significantly improve the spectral calculation efficiency of the signal processing system for large number of points and the flexibility of the number of points.

[0005] The method includes the following steps: Step 1, obtaining the original data in the time domain of the real-time vector signal through an acquisition device; Step 2, setting the parameters of the spectrum segmentation FFT model: setting the parameters through the input configuration signal FFTconfig. The bit width of the signal FFTconfig is 8 bits, where the lower 4 bits are the number of points L of each path of the signal set, and the calculation method is the power of 2 corresponding to the decimal number of the lower 4 bits; the upper 4 bits are the number of channels M; Step 3: Input the original data in the time domain of the acquired vector signal into the spectrum segmentation FFT model. The spectrum segmentation FFT model is designed based on the two-dimensional decomposition of FFT and the conversion of the discrete Fourier transform (DFT) into a cyclic convolution algorithm. First, perform the first horizontal spectrum transformation on multiple paths of time-domain data simultaneously, then multiply the data by the corresponding correction factor, and then perform the spectrum transformation of the number of points in the longitudinal channel again. Decompose the DFT transformation matrix of channel number M into the multiplication of 3 matrices: , where the matrix 、 only contains 0, 1, -1 elements, is a diagonal matrix; due to the characteristics of such decomposition 、 only contains addition and subtraction, which can greatly reduce the resources of the multiplier; Step 4: Output the frequency-domain data of the vector signal.

[0006] In Step 3, the spectrum segmentation FFT model decomposes the FFT of positive integer N points into the product of two positive integers R and C, converts one-dimensional data into two-dimensional data, and the formula is: , where 、 are the abscissa and ordinate in the frequency domain of the two-dimensional data respectively, 、 are the abscissa and ordinate in the time domain of the two-dimensional data respectively, , , , ; is the correction factor, is the rotation factor for the horizontal frequency-domain transformation, is the rotation factor for the vertical frequency-domain transformation, is the continuous and non-overlapping complete frequency-domain signal finally segmented by the frequency domain.

[0007] In Step 3, the spectrum segmentation FFT model includes a data splitting module, a multi-channel FFT module, a correction angle storage module, a vector rotation module, and a matrix transformation module; The data splitting module is connected to the multi-channel FFT module, the multi-channel FFT module and the correction angle storage module are connected to the vector rotation module, and the vector rotation module is connected to the matrix transformation module; The data splitting module adopts an improved splitting method for the acquired vector time-domain data, inputs the sampled time-domain vector signal into a first-in-first-out (FIFO) data buffer with a depth of M, performs grouped processing by asymmetric input and output, and evenly divides the acquired vector signal into M paths; The multi-channel FFT module calculates the intermediate frequency-domain signals from the multi-channel data signals; The correction angle storage module stores the rotation angle of the correction factor in a Block Random Access Memory. The multi-channel FFT module outputs the valid frequency-domain signals and feeds them back to the correction angle storage module as its start signal, and outputs the multi-channel frequency-domain signals after delay and the correction angle simultaneously; The vector rotation module uses the Coordinate Rotation Digital Computer method to rotate the multi-channel vector data simultaneously, achieving the effect of complex multiplication. This method effectively saves multiplier resources and memory resources when the calculation speed is not much different. The storage of the correction factor can be reduced by 50%, and the more calculation points there are, the more storage resources can be saved; The matrix transformation module performs a spectral transformation on the multi-channel data that has been multiplied by the correction factor longitudinally again, and performs a matrix transformation on the multi-channel independent signal results to obtain a complete multi-channel frequency-domain signal with frequency-domain segmentation but continuous and non-overlapping. This process uses the method of circular convolution to convert the DFT with excessive resource consumption and inflexibility into multiple matrix multiplications that can effectively reduce complex multipliers.

[0008] In step 3, the multi-channel FFT module assigns an independent FFT calculation unit to each channel of data. Through parallel processing, two or more rows of FFT can be calculated simultaneously, and the data after all parallel calculations are completed is directly output in a pipeline.

[0009] In step 3, the correction angle storage module calculates the rotation angle of the correction factor in advance on the host computer and stores it in the block random access memory. The exponent of the correction factor is the calculation formula of the rotation angle, and the calculation formula of the correction factor is , multiplying by the correction factor is an intermediate step to convert the multi-channel segmented independent FFT into a complete continuous spectrum, where and are the ordinate of the frequency domain and the abscissa of the time domain of the two-dimensional data respectively, N is the total number of points calculated by the FFT, e represents the natural constant, and j is the imaginary unit.

[0010] In step 3, the vector rotation module aligns according to the calculation completion signal when the data is first put into the multi-channel FFT module and outputs it simultaneously with the data of the correction angle storage module, and then uses the Coordinate Rotation Digital Computer method to perform vector data rotation correction.

[0011] In step 3, the matrix transformation module performs spectral transformation longitudinally on the multiplexed data that has been multiplied by the correction factor, and performs matrix transformation on the multiplexed independent signal results to obtain a complete frequency-domain signal, supporting channel numbers M = 2, 3, 5, 8, and the total number of points supported by FFT , where ; takes values from 3 to 14; ; , , , respectively represent the parameters indicating whether the 2, 3, 5, and 8 channel numbers are selected. If it is 2-channel data, then = 1, otherwise a is 0. If it is 3-channel data, then b = 1, otherwise b is 0. If it is 5-channel data, then c = 1, otherwise c is 0. If it is 8-channel data, then d = 1, otherwise d is 0; is the exponent of the second power of the first spectral transformation; since it is necessary to ensure data continuity and simultaneity, delay units need to be added to the data of each channel to meet simultaneity. The delay of the complex multiplier in the matrix transformation is 4 clock cycles, and the delay of the complex adder is 1 clock cycle. From this, the delays of 2, 3, 5, and 8 channels are calculated to be 3, 9, 9, and 8 clock cycles respectively; the two-channel data is a standard butterfly operation, and the matrix transformations of three-channel data, five-channel data, and eight-channel data are successively , , : , , .

[0012] In step 3, a multiplexed hybrid data structure with resource reuse design is formed in the matrix transformation modules of 2, 3, 5, and 8 channels. First, the data after vector rotation is input into the multiplexed hybrid data structure. When the parallelism of the data is less than 8, the input data needs to be set to 0 for the ports without data, and then the data is rearranged. After passing through more than two one-of-two data selectors to obtain the correct data paths for different channels, and the elements in the diagonal matrix are used to configure one end input of the multiplier. Finally, the output data is rearranged again to achieve the longitudinal frequency-domain transformation of different channel numbers.

[0013] The present invention also provides an FPGA-based spectral splitting FFT device implemented according to the above method, including a data demultiplexing module, a multiplexed FFT module, a correction angle storage module, a vector rotation module, and a matrix transformation module; The data demultiplexing module is connected to the multiplexed FFT module, the multiplexed FFT module and the correction angle storage module are connected to the vector rotation module, and the vector rotation module is connected to the matrix transformation module.

[0014] The data splitting module processes the acquired vector time-domain data by grouping, evenly dividing the acquired vector signals into M paths, where M represents the number of channels; The multi-channel FFT module calculates the intermediate frequency-domain signals from the multi-channel data signals.

[0015] The correction angle storage module stores the rotation angle of the correction factor in the BRAM.

[0016] The vector rotation module rotates the multi-channel vector data simultaneously.

[0017] The matrix transformation module performs matrix transformation on the multi-channel independent signal results to obtain a complete frequency-domain signal.

[0018] The present invention also provides an electronic device, including a processor and a memory. The memory stores program codes. When the program codes are executed by the processor, the processor executes the steps of the above method.

[0019] Beneficial effects: By converting the data from one path to multiple paths (allowing an odd number of channels), segmenting the signals and sending them into the processing units of the multi-channel FFT, then using CORDIC to perform vector rotation on the independent frequency-domain signals, and finally performing multiple decomposition matrix transformations on the data to obtain a complete, continuous and non-overlapping multi-segment frequency-domain signal. This method supports a wide range of FFT point numbers and can handle non-power-of-two FFT point numbers. The multi-channel FFT parallel processing can effectively reduce the time for processing large-point FFTs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a flowchart of the method of the present invention.

[0021] Figure 2 It is a schematic diagram of the segmented FFT model architecture in an embodiment of the present invention.

[0022] Figure 3 It is a data flow diagram of the data splitting module in an embodiment of the present invention.

[0023] Figure 4 It is a flowchart of the 3-path data structure in an embodiment of the present invention.

[0024] Figure 5 It is a flowchart of the 5-path data structure in an embodiment of the present invention.

[0025] Figure 6 It is a flowchart of the 8-path data structure in an embodiment of the present invention.

[0026] Figure 7 It is a flowchart of the multi-channel mixed data structure in an embodiment of the present invention.

[0027] Figure 8 It is a comparison chart of the FFT amplitude spectrum between the FFT function of MATLAB and the FPGA simulation in the embodiments of the present invention.

[0028] Figure 9 It is an error chart of the FFT amplitude spectrum between the FFT function of MATLAB and the FPGA simulation in the embodiments of the present invention.

[0029] Figure 10 It is a graph of five continuous non - overlapping amplitude spectra obtained by splitting the spectrum in the embodiments of the present invention. Specific implementation manner

[0030] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners, and the above - mentioned and / or other advantages of the present invention will become clearer.

[0031] As Figure 1 shown, an FPGA - based spectrum - splitting FFT method is proposed in an embodiment of the present invention, including: Step 1: Obtain the original data in the time domain of the real - time vector signal through an acquisition device.

[0032] Step 2: Set the parameters of the spectrum - splitting FFT model.

[0033] The parameters of the splitting FFT model are specifically as follows: the number of channels M (in this embodiment, M supports 2, 3, 5, 8), the data bit - width is depth bits, the upper depth / 2 bits are the imaginary part of the acquired signal, and the lower depth / 2 bits are the real part of the acquired signal. The number of points for each channel is L, and the total number of sampling points N = M * L. The parameter setting is performed by the input configuration signal FFTconfig, and the bit - width of this signal is 8 bits. Among them, the lower 4 bits are the number of points L set for each path of the signal, and the calculation method is the power of 2 to the decimal number corresponding to the lower 4 bits. The upper 4 bits of the configuration signal are the number of channels M.

[0034] Step 3: Input the acquired vector time - domain data into the spectrum - splitting FFT model.

[0035] The spectrum - splitting FFT model decomposes the N - point FFT of positive integers into the product of two positive integers R and C, converts one - dimensional data into two - dimensional data and is designed based on the following formula: , This formula is obtained by , substituting into the DFT formula to get, where , and , are the horizontal and vertical coordinates of the frequency domain and time domain of the two - dimensional data respectively, , , , . is the correction factor, is the rotation factor for the horizontal frequency-domain transformation, is the rotation factor for the vertical frequency-domain transformation, is the continuous and non-overlapping complete frequency-domain signal obtained by finally splitting the frequency domain.

[0036] The implementation steps of this formula all correspond to the various modules of the split FFT model.

[0037] As Figure 2 shown, in this example, the split FFT model includes a data demultiplexing module, a multi-channel FFT module, a correction angle storage module, a vector rotation module, and a matrix transformation module.

[0038] Data demultiplexing module; used to achieve efficient conversion from single-channel data to multi-channel data in the FPGA. The traditional method usually adopts the way of outputting all at once after sampling, that is, parallel output after collecting a complete set of data, while the present invention adopts an improved demultiplexing method. Just input the sampled time-domain vector signal into the FIFO with a depth of M. The specific data flow diagram is as Figure 3 shown, where d represents the input data, d0 represents the 0th data, and d4M-1 represents the (4M - 1)th data. Set the asymmetric input and output of the FIFO. For example, if the input bit width is 32 bits, the output bit width is 32*M. Wait until every Mth data is input and then immediately output M-channel data simultaneously (M is the number of channels), rather than waiting until the end of the entire sampling period to demultiplex the data. This can ensure that the data delay is only 1 clk, improve the real-time response ability of the system, and at the same time reduce the demand for the internal storage space of the FPGA.

[0039] Multi-channel FFT module; this module uses M-channel parallelism, and each channel adopts a pipeline architecture. First, the input data is bit-reversed by the preprocessing unit to meet the input requirements of the FFT algorithm. Next, the data enters each stage of the pipeline structure, and each stage performs a butterfly operation and multiplies by the corresponding rotation factor. After each butterfly operation stage, the data is multiplied by a programmable scaling factor to control the amplitude of the data and prevent overflow. The entire processing process uses a streaming I / O interface to ensure that each sampled point enters the pipeline processing immediately after being collected. Finally, after processing all stages, the output data needs to be bit-reversed and rearranged to obtain the frequency-domain result in natural order. The number of points supported by each channel of FFT is , and p takes values from 3 to 14.

[0040] Vector rotation module; In traditional FFT calculations, the storage and calculation of rotation factors usually adopt two methods: one is to store pre-calculated rotation factors through a lookup table; the other is to use the Coordinate Rotation Digital Computer (CORDIC) to dynamically calculate rotation factors and then perform complex multiplication with the previous data. The optimized method is to combine the storage of rotation factors with complex multiplication. The essence of the complex multiplication of data and rotation factors is to rotate vector signals. Therefore, CORDIC can very well combine this feature for calculation. Since the stored data of rotation factors is complex, with a real part and an imaginary part, and by using CORDIC instead of a complex multiplier, only the rotation angle needs to be stored. Therefore, compared with the rotation factors stored and calculated through LUT, the optimized solution can save 50% of the internal storage resources. Especially for large-point FFTs, the resources consumed by storing rotation factors are proportional to the number of points calculated by the FFT. Generally speaking, there will be a certain hardware resource overhead and calculation delay when calculating rotation factors in real time through the CORDIC algorithm. Assume that the delay of calculating rotation factors by CORDIC is , and the delay of complex multiplication is , then the total delay of this method is , while the delay of using CORDIC instead of complex multiplication is only . Especially for the resource consumption of complex multipliers in the traditional two schemes, compared with the optimized scheme, a lot of DSP resources are saved, especially when the number of channels M is large. Specifically, let , when the number of channels is M, the data of M channels are respectively , and the vector rotation module is to use vector rotation to replace the complex multiplier and multiply these M rows of data with .

[0041] Correction angle storage module; The correction angle storage module calculates and stores the rotation angle of the correction factor in advance on the host computer and stores it in the BRAM. The calculation formula of the correction factor is , N is the total number of points calculated by the FFT. This process needs to add the angle greater than and less than by to satisfy that the rotation angle is between and .

[0042] Matrix transformation module; For conventional two-dimensional decomposition algorithms, the following steps are generally required: First, decompose the N-point data into matrix data of natural numbers R multiplied by C; Second, perform FFT of C points on each of the R rows of the matrix data; Then multiply by the matrix factor; Then transpose the multiplied data; Finally, perform FFT of R points on each of the C rows of the transposed data. It can be seen from the general method that this method requires transposing the pre-data when performing the second FFT. However, transposing a large number of parallel data in the FPGA is a very time-consuming and resource-consuming operation, and after the second spectral transformation of the transposed data, a second transpose is required to obtain multiple segments of continuous and non-overlapping spectra. Therefore, the present invention decomposes the DFT transformation matrix of the number of channels M into the product of these 3 matrices, where , contains only elements 0, 1, -1, is a diagonal matrix. Due to the characteristics of such decomposition , contains only addition and subtraction, which can greatly reduce the use of multipliers and save resources. Compared with the traditional algorithm, this example allows FFT of odd channels. In theory, any number of channels can be combined with the mixed-radix algorithm to achieve. Supports M = 2, 3, 5, 8 channels. Therefore, the total number of sampling points , p takes values from 3 to 14, . The relationship between the input and output of this module is , when M = 2 . The 2-channel data structure is the same as the ordinary butterfly operation unit.

[0043] When M = 3, .

[0044] When M = 5, ; When M = 8, .

[0045] As Figure 4 , Figure 5 and Figure 6 shown, they are the flowcharts of the specific 3-channel, 5-channel, and 8-channel data structures, where represents the vertical data of the input matrix, represents the 0th data in the vertical direction of the matrix, represents the 5th data in the vertical direction of the matrix. Similarly, The 0th frequency point of the vertical data represented as output, where j is the imaginary unit. Compared with the parallel-structure DFT, it reduces the number of complex multipliers by 2, 11, 28 respectively and the number of complex adders by 0, 3, 30 respectively. Using this decomposed matrix transformation to process the pre-data not only avoids the way of data transposition, greatly shortening the latency, but also saves many multipliers and adders for the FFT of the number of channels and points.

[0046] To further save the resources of complex multipliers and complex adders, it is necessary to reuse the resources in the matrix transformation modules of 2, 3, 5, and 8 channels. As Figure 7 shown, it is the flow graph of the multi-channel hybrid data structure. To ensure the correct matrix transformation operation for different numbers of channels and the frequency-domain data output in the natural sequence, it needs to be jointly controlled by the data rearrangement unit, data selector, and multiplication factor.

[0047] Figure 7 The butterfly unit in it has 2 inputs and 2 outputs. The upper output is the sum of the upper input and the lower output, and the lower output is the difference between the upper input and the lower input. Din0 to Din7 are 8 input ports for receiving the data after CORDIC vector rotation, and Dout0 to Dout7 are 8 output ports for outputting the finally segmented spectrum data. First, the data after vector rotation is sent to Din0 to Din7. When the parallelism of the data is less than 8, the input data of the ports without data needs to be set to 0, and then the data is rearranged, passed through the butterfly unit, multiplier, and data selector to obtain to out-of-order data, and finally the data is rearranged again to output Dout0 to Dout7 to ensure the correct frequency-domain order. The correspondence between setting the data of different numbers of channels to 0 and the positions of the input data is shown in Table 1.

[0048] Table 1

[0049] The correspondence between the positions of the out-of-order data in the middle for different numbers of channels is shown in Table 2, where X is in the high-impedance state, indicating that no data is output.

[0050] Table 2

[0051] MUX is the data selector, represents the data selection switch of the first MUX. When is set to 1, it selects the upper output. On the contrary, when set to 0, it selects the lower output. There are a total of 6 data selectors in this multi-channel hybrid data structure to control the data flow of different numbers of channels, as shown in Table 3.

[0052] Table 3

[0053] To achieve multiplier multiplexing, when selecting different paths, it is also necessary to configure the multiplication factors at the input end of the multiplier. There are a total of 5 multiplication factors in this flow graph, which are respectively , , , , . Since the multiplication factors required for the diagonal matrix in the decomposition matrix are different when performing matrix transformation on data with different numbers of channels, the multipliers not used in different numbers of channels are set to 0. When M = 2, all multipliers are set to 0; when M = 3, , , ; when M = 5, , , , , , ; when M = 8, , , , .

[0054] For the vector signal passing through the spectrum splitting FFT model, the total delay is , where is the total delay. The first term in the formula is the delay of the vector signal passing through the splitting module, the second term is the delay of the vector signal passing through the multi-channel FFT module, the third term is the delay of the signal in the CORDIC complex multiplication, and the last term is the delay of the signal in the matrix transformation. Since it is necessary to ensure the continuity of the multi-channel signals, delay units also need to be added to the flowcharts of each channel's data structure to ensure data continuity and simultaneity. The delay of the complex multiplier is 4 clk, and the delay of the complex adder is 1 clk. From this, the delays of 2, 3, 5, and 8 channels are calculated to be 3, 9, 9, and 8 clk respectively.

[0055] Step 4: Output the frequency domain of the vector signal.

[0056] The present invention divides the output frequency domain data into M channels, and the corresponding frequency domain range for each channel is , , is the corresponding number of channels.

[0057] Simulate the content of this example. Generate a signal function through MATLAB: , where the sampling frequency = 64Mhz, the signal frequency = 21.37Mhz, the number of channels M = 5, and the total number of sampling points = 40960. As Figure 8 shown, save 5-channel data in the field-programmable gate array (FPGA) and compare it with the amplitude spectrum of the fast Fourier transform (FFT) of the system function of the mathematical calculation software MATLAB. As Figure 9 shown, it is the error graph of the FFT function of MATLAB and the FPGA-simulated FFT amplitude spectrum. The reason for the difference is caused by quantization and is within the allowable error range. As Figure 10 shown, it is the 5-channel continuous non-overlapping amplitude spectrum diagram obtained by the FPGA-simulated FFT dividing the frequency spectrum. The frequency ranges of channels 1 to 5 are 0 to 12.8 MHz, 12.8 to 25.6 MHz, 25.6 to 38.4 MHz, 38.4 to 51.2 MHz, and 51.2 to 64.0 MHz respectively. The system model delay is clk. Since the model calculates the FFT with a non-power-of-two number of points, another set of data M = 8 and the total number of sampling points n = 65536 are tested. The system model delay tested is clk. Comparing with the FFT IP core in Vivado, the delay of the signal passing through the IP core is 65741 clk. The acceleration ratio of the time for the present invention to execute FFT compared with the traditional FFT IP core is 7.817, which meets the requirement of being able to process large-point FFTs more efficiently and quickly.

[0058] The present invention also provides a spectrum-splitting FFT device based on FPGA, including: a data demultiplexing module, a multi-channel FFT module, a correction angle storage module, a vector rotation module, and a matrix transformation module.

[0059] The data demultiplexing module is connected to the multi-channel FFT module. The multi-channel FFT module and the correction angle storage module are connected to the vector rotation module, and the vector rotation module is connected to the matrix transformation module.

[0060] The data demultiplexing module performs grouping processing on the acquired vector time-domain data, and evenly divides the acquired vector signal into M channels, where M represents the number of channels; The multi-channel FFT module calculates the intermediate frequency-domain signal from the multi-channel data signals.

[0061] The correction angle storage module stores the rotation angle of the correction factor in the BRAM.

[0062] The vector rotation module rotates the multi-channel vector data simultaneously.

[0063] The matrix transformation module performs matrix transformation on the multi-channel independent signal results to obtain a complete frequency-domain signal.

[0064] The present invention provides a spectrum splitting FFT method and apparatus based on FPGA. There are many methods and ways to specifically implement this technical solution. The above description is only the preferred embodiment of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention. Each component not clearly defined in this embodiment can be implemented by using the prior art.

Claims

1. A spectrum splitting FFT method based on FPGA, characterized in that, It includes the following steps: Step 1: Obtain the original data in the time domain of the real-time vector signal through a collection device; Step 2: Set the parameters of the spectrum splitting FFT model: Set the parameters through the input configuration signal FFTconfig. The bit width of the signal FFTconfig is 8 bits. Among them, the lower 4 bits are the number of points L of each path of the signal set, and the calculation method is the power of 2 corresponding to the decimal number of the lower 4 bits; the higher 4 bits are the number of channels M; Step 3, input the original data in the time domain of the acquired vector signal into the spectrum splitting FFT model. The spectrum splitting FFT model is designed based on the two-dimensional decomposition of FFT and the conversion of the discrete Fourier transform DFT into a circular convolution algorithm. First, perform the first horizontal spectrum transformation on multiple channels of time-domain data simultaneously, then multiply the data by the corresponding correction factor, and then perform the spectrum transformation of the number of points in the longitudinal channels again. Decompose the DFT transformation matrix of the number of channels M into the multiplication of 3 matrices: , where the matrix , only contains elements 0, 1, -1, is a diagonal matrix; Step 4: Output the frequency domain data of the vector signal.

2. The method according to claim 1, characterized in that, In Step 3, the spectrum splitting FFT model decomposes the FFT of N positive integer points into the product of two positive integers R and C, and converts one-dimensional data into two-dimensional data. The formula is: ， wherein and are the abscissa and ordinate of the frequency domain of the two-dimensional data respectively, and are the abscissa and ordinate of the time domain of the two-dimensional data respectively, , , , ; is the correction factor, is the rotation factor for the horizontal frequency domain transformation, is the rotation factor for the vertical frequency domain transformation, is the continuous and non-overlapping complete frequency domain signal obtained by dividing the final frequency domain.

3. The method according to claim 2, wherein In Step 3, the spectrum splitting FFT model includes a data demultiplexing module, a multi-channel FFT module, a correction angle storage module, a vector rotation module, and a matrix transformation module; The data demultiplexing module is connected to the multi-channel FFT module. The multi-channel FFT module and the correction angle storage module are connected to the vector rotation module, and the vector rotation module is connected to the matrix transformation module; The data demultiplexing module adopts an improved demultiplexing method for the obtained vector time-domain data, inputs the sampled time-domain vector signal into a first-in-first-out data buffer with a depth of M, and performs grouping processing by asymmetric input and output, and evenly divides the obtained vector signal into M paths; The multi-channel FFT module calculates the intermediate frequency domain signal from the multi-channel data signals; The correction angle storage module stores the rotation angle of the correction factor in the block random access memory. The multi-channel FFT module outputs a valid frequency domain signal and feeds it back to the correction angle storage module as a start signal, and outputs the multi-channel frequency domain signals after delay and the correction angle at the same time; The vector rotation module uses the coordinate rotation digital calculation method to rotate the multi-channel vector data simultaneously to achieve the effect of complex multiplication; The matrix transformation module performs a spectrum transformation on the multi-channel data that has been multiplied by the correction factor longitudinally again, and performs a matrix transformation on the multi-channel independent signal results to obtain a complete multi-channel frequency domain signal with frequency domain segmentation but continuous and non-overlapping; 4. The method according to claim 3, wherein In Step 3, the multi-channel FFT module assigns an independent FFT calculation unit to each path of data. Through parallel processing, two or more rows of FFTs can be calculated simultaneously, and the data after all parallel calculations are directly output in a pipeline; 5. The method according to claim 4, wherein In step 3, the correction angle storage module calculates in advance the rotation angle of the correction factor on the host computer and stores it in the block random access memory. The exponent of the correction factor is the calculation formula of the rotation angle, and the calculation formula of the correction factor is , where and are respectively the ordinate of the frequency domain and the abscissa of the time domain of the two-dimensional data, N is the total number of points for FFT calculation, e represents the natural constant, and j is the imaginary unit.

6. The method according to claim 5, characterized in that In Step 3, the vector rotation module aligns according to the calculation completion signal of the first time the data is put into the multi-channel FFT module and outputs it at the same time as the data of the correction angle storage module, and then uses the coordinate rotation digital calculation method to perform vector data rotation correction; 7. The method according to claim 6, wherein In step 3, the matrix transformation module performs a spectral transformation on the vertically multiplexed data that has been multiplied by the correction factor, and performs a matrix transformation on the multiplexed independent signal results to obtain a complete frequency-domain signal, supporting the number of channels M = 2, 3, 5, 8, and the total number of points supported by the FFT , where ; takes values from 3 to 14; , , , respectively represent the parameters indicating whether the 2, 3, 5, and 8 channels are selected. If it is 2-channel data, then = 1, otherwise a is 0. If it is 3-channel data, then b = 1, otherwise b is 0. If it is 5-channel data, then c = 1, otherwise c is 0. If it is 8-channel data, then d = 1, otherwise d is 0; is the exponent of the second power of the first spectral transformation; The data of each channel needs to be added with a delay unit to meet simultaneity. In matrix transformation, the delay of the complex multiplier is 4 clock cycles, and the delay of the complex adder is 1 clock cycle. Thus, the delays of 2, 3, 5, and 8 channels are calculated to be 3, 9, 9, and 8 clock cycles respectively; the two-channel data is butterfly operation, and the matrix transformations of three-channel data, five-channel data, and eight-channel data are successively 、 、 : ， ， 。 8. The method according to claim 7, wherein In step 3, a multi-channel hybrid data structure with resource reuse design is formed in the matrix transformation modules of channels 2, 3, 5, and 8. First, the data after vector rotation is input into the multi-channel hybrid data structure. When the parallelism of the data is less than 8, the ports without data need to set the input data to 0, and then the data is rearranged. After passing through more than two one-of-two data selections, the correct data paths for different channels are obtained, and one end input of the multiplier is configured by the elements in the diagonal matrix. Finally, the output data is rearranged again to achieve the longitudinal frequency domain transformation of different numbers of channels.

9. An FPGA-based spectrum splitting FFT device implemented according to the method described in any one of claims 1 to 8, characterized in that, It includes a data demultiplexing module, a multi-channel FFT module, a correction angle storage module, a vector rotation module, and a matrix transformation module; The data demultiplexing module is connected to the multi-channel FFT module. The multi-channel FFT module and the correction angle storage module are connected to the vector rotation module, and the vector rotation module is connected to the matrix transformation module; The data demultiplexing module performs grouping processing on the obtained vector time-domain data, and evenly divides the obtained vector signal into M paths, where M represents the number of channels; The multi-channel FFT module calculates the intermediate frequency domain signals from multi-channel data signals; The correction angle storage module stores the rotation angle of the correction factor in the BRAM; The vector rotation module rotates multi-channel vector data simultaneously; The matrix transformation module performs matrix transformation on the multi-channel independent signal results to obtain a complete frequency domain signal.

10. An electronic device, characterized in that, It includes a processor and a memory, and the memory stores program codes. When the program codes are executed by the processor, the processor is caused to execute the steps of the method according to any one of claims 1 to 8.

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