A spectrum segmentation FFT method and device based on FPGA

Abstract

The present invention provides an FPGA-based spectrum segmentation FFT method and device. The method comprises: step 1, acquiring the time-domain raw data of a real-time vector signal through an acquisition device; step 2, setting parameters of the spectrum segmentation FFT model: the parameters are set by inputting a configuration signal FFTconfig, the signal FFTconfig bit width being 8 bits, wherein the lower 4 bits represent the number of points L set for each signal channel, calculated as the power of 2 corresponding to the decimal number corresponding to the lower 4 bits; the upper 4 bits represent the number of channels M; step 3, inputting the acquired time-domain raw data of the vector signal into the spectrum segmentation FFT model; and step 4, outputting the frequency-domain data of the vector signal. This method supports a wide range of FFT point numbers and can process FFT point numbers that are not powers of 2. Parallel processing of multi-channel FFTs can effectively reduce the processing time of large-point FFTs.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to a spectrum segmentation FFT method and device based on FPGA. Background Art

[0002] The Fast Fourier Transform (FFT) is a core algorithm widely used in fields such as signal processing, communications, radar, and medical imaging. Traditional FFTs are typically calculated using radix-2 or higher-order radix-r algorithms, and most hardware acceleration solutions face computational complexity and storage bottlenecks when processing FFTs with larger number of points. Furthermore, existing FFT architectures often only support power-of-two points (such as 512, 1024, and 2048). For non-power-of-two points (such as 1000 and 3000), computational efficiency is low and may even require additional interpolation or zero-padding operations, resulting in wasted resources and increased computation time.

[0003] On the other hand, traditional parallel FFT architectures typically perform parallel computations on even-numbered channels, such as 2, 4, or 8, but offer limited support for odd-numbered channels (such as 3 or 5). This limitation reduces FFT computational resource utilization and hinders flexible parallel processing in certain applications, such as multiple-input, multiple-output (MIMO) communication systems, signal processing with unevenly spaced sampling, and sampling rates that are odd multiples of the clock frequency. Summary of the Invention

[0004] Purpose of the invention: The technical problem to be solved by the present invention is to provide a spectrum segmentation FFT method and device based on FPGA, which can support 2, 3, 5, 8 channels and the number of points is The FFT of , , and can significantly improve the signal processing system's efficiency in spectrum calculation for large numbers of points and the flexibility of the points.

[0005] The method comprises the following steps:

[0006] Step 1: Obtain the time domain raw data of the real-time vector signal through an acquisition device;

[0007] Step 2: Set the parameters of the spectrum segmentation FFT model: Set the parameters through the input configuration signal FFTconfig. The signal FFTconfig bit width is 8 bits, of which the lower 4 bits are the number of points L for each signal, calculated by the power of the decimal number corresponding to the lower 4 bits of 2; the upper 4 bits are the number of channels M;

[0008] Step 3: Input the acquired time domain raw data of the vector signal into the spectrum partitioning FFT model. The spectrum partitioning FFT model is designed based on the two-dimensional decomposition FFT and the discrete Fourier transform (DFT) converted into a circular convolution algorithm. First, the multi-channel time domain data is simultaneously subjected to the first horizontal spectrum transformation, and then the data is multiplied by the corresponding correction factor. Then, the spectrum transformation of the number of channel points is performed again in the vertical direction, and the DFT transformation matrix of the channel number M is decomposed into three matrix multiplications: , where the matrix 、 It only contains 0, 1, -1 elements. is a diagonal matrix; due to the characteristics of this decomposition 、 Only including addition and subtraction can greatly reduce the resources of multiplier;

[0009] Step 4: Output the frequency domain data of the vector signal.

[0010] In step 3, the spectrum segmentation FFT model decomposes the FFT of the positive integer N points into the product of two positive integers R and C, converting the one-dimensional data into two-dimensional data. The formula is:

[0011] ,

[0012] in 、 are the horizontal and vertical coordinates of the frequency domain of the two-dimensional data, 、 are the horizontal and vertical coordinates of the time domain of the two-dimensional data, , , , ; is the correction factor, is the rotation factor of the transverse frequency domain transform, is the rotation factor of the longitudinal frequency domain transform, The final frequency domain is divided into continuous and non-overlapping complete frequency domain signals.

[0013] In step 3, the spectrum segmentation FFT model includes a data branching module, a multi-channel FFT module, a correction angle storage module, a vector rotation module and a matrix transformation module;

[0014] The data branching module is connected to the multi-channel FFT module, the multi-channel FFT module and the correction angle storage module are connected to the vector rotation module, and the vector rotation module is connected to the matrix transformation module;

[0015] The data splitting module uses an improved splitting method to input the sampled time domain vector signal into a first-in-first-out (FIFO) data buffer with a depth of M, performs group processing by asymmetric input and output, and divides the acquired vector signal into M paths;

[0016] The multi-channel FFT module calculates the multi-channel data signals to obtain the intermediate frequency domain signals;

[0017] The correction angle storage module stores the rotation angle of the correction factor in a block random access memory (BRAM). The multi-channel FFT module outputs a valid frequency domain signal and feeds it back to the correction angle storage module as its start signal. The multi-channel frequency domain signal is output simultaneously with the correction angle after delay.

[0018] The vector rotation module uses a coordinate rotation digital calculation method to simultaneously rotate multiple channels of vector data to achieve the effect of complex multiplication. This method effectively saves multiplier and memory resources while maintaining a similar calculation speed. The storage of correction factors can be reduced by 50%. The more calculation points there are, the more storage resources saved.

[0019] The matrix transformation module performs a longitudinal spectrum transformation on the multiple data that have been multiplied by the correction factor, and matrix transforms the multiple independent signal results to obtain a complete multi-channel frequency domain signal that is frequency-domain segmented but continuous and non-overlapping. This process uses the circular convolution method to convert the resource-intensive and inflexible DFT into multiple matrix multiplications that can effectively reduce the number of complex multipliers.

[0020] In step 3, the multi-channel FFT module allocates an independent FFT calculation unit to each channel of data. Through parallel processing, FFTs of more than two rows can be calculated simultaneously, and all data after parallel calculation are directly pipelined and output.

[0021] In step 3, the correction angle storage module calculates the rotation angle of the correction factor in advance on the host computer and stores it in the block random access memory. The exponent of the correction factor is the calculation formula of the rotation angle. The calculation formula of the correction factor is , multiplying by the correction factor is an intermediate step in converting the multi-channel segmented independent FFT into a complete continuous spectrum, where and are the ordinate of the frequency domain and the abscissa of the time domain of the two-dimensional data, N is the total number of points calculated by FFT, e represents a natural constant, and j is an imaginary unit.

[0022] In step 3, the vector rotation module outputs the data into the multi-channel FFT module according to the calculation completion signal and aligns it with the data of the correction angle storage module, and then uses the coordinate rotation digital computer method to perform rotation correction of the vector data.

[0023] In step 3, the matrix transformation module performs spectrum transformation on the multi-channel data that have been multiplied by the correction factor, and performs matrix transformation on the multi-channel independent signal results to obtain a complete frequency domain signal. The supported channel number M=2, 3, 5, 8, and the total number of points supported by FFT are ,in ; The value ranges from 3 to 14; ; , , , Parameters indicating whether 2, 3, 5, or 8 channels are selected. If 2 channels are selected, =1, otherwise a is 0, if it is 3-way data, b=1, otherwise b is 0, if it is 5-way data, c=1, otherwise c is 0, if it is 8-way data, d=1, otherwise d is 0; is the exponent of the first spectrum transformation to the power of 2; because of the need to ensure data continuity and simultaneity, each channel data needs to add a delay unit to meet simultaneity. The delay of the complex multiplier in the matrix transformation is 4 clock cycles, and the delay of the complex adder is 1 clock cycle. Therefore, the delays of 2, 3, 5, and 8 channels are calculated to be 3, 9, 9, and 8 clock cycles respectively; the two-channel data is a standard butterfly operation, and the matrix transformations of the three-channel data, five-channel data, and eight-channel data are as follows: 、 、 :

[0024] , , .

[0025] In step 3, a multi-channel mixed data structure with resource reuse design is formed in the matrix transformation modules of 2, 3, 5, and 8. First, the data after vector rotation is input into the multi-channel mixed data structure. When the parallelism of the data is less than 8, the port without data needs to set the input data to 0. Then the data is rearranged. After two or more data selections, the correct data paths of different channels are obtained, and the data is obtained by The elements in the diagonal matrix are used to configure one end of the input of the multiplier, and finally the output data is rearranged again to realize the longitudinal frequency domain transformation of different channel numbers.

[0026] The present invention also provides an FPGA-based spectrum segmentation FFT device implemented according to the method, comprising a data branching module, a multi-channel FFT module, a correction angle storage module, a vector rotation module and a matrix transformation module;

[0027] The data branching module is connected to the multi-channel FFT module, the multi-channel FFT module and the correction angle storage module are connected to the vector rotation module, and the vector rotation module is connected to the matrix transformation module.

[0028] The data splitting module performs group processing on the acquired vector time domain data and divides the acquired vector signal into M paths, where M represents the number of channels;

[0029] The multi-channel FFT module calculates the multi-channel data signals to obtain the intermediate frequency domain signals.

[0030] The correction angle storage module stores the rotation angle of the correction factor in the BRAM.

[0031] The vector rotation module rotates multiple channels of vector data simultaneously.

[0032] The matrix transformation module transforms the results of multiple independent signals into a complete frequency domain signal.

[0033] The present invention also provides an electronic device, comprising a processor and a memory, wherein the memory stores program code, and when the program code is executed by the processor, the processor executes the steps of the method.

[0034] Beneficial Effects: This method converts data from one channel into multiple channels (an odd number of channels is permitted), segments the processed signals into a multi-channel FFT processing unit, then uses CORDIC to perform vector rotation on the independent frequency domain signals. Afterwards, the data undergoes multiple decomposition matrix transformations to produce complete, continuous, and non-overlapping frequency domain signals. This method supports a wide range of FFT point counts and can handle FFT point counts that are not powers of two. Parallel processing of multiple channels' FFTs can effectively reduce the processing time for large-point FFTs. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Flowchart of the method of the present invention.

[0036] Figure 2 Schematic diagram of the split FFT model architecture in an example of the present invention.

[0037] Figure 3 This is a data flow diagram of the data splitting module in an example of the present invention.

[0038] Figure 4 This is a flow chart of a three-way data structure in an example of the present invention.

[0039] Figure 5 This is a flow chart of a 5-way data structure in an example of the present invention.

[0040] Figure 6 This is a flow chart of the 8-way data structure in an example of the present invention.

[0041] Figure 7 This is a flow chart of the multi-channel mixed data structure in an example of the present invention.

[0042] Figure 8 This is a comparison chart of the FFT function of MATLAB and the FFT amplitude spectrum simulated by FPGA in the example of the present invention.

[0043] Figure 9 This is a diagram of the FFT function of MATLAB and the FFT amplitude spectrum error of FPGA simulation in an example of the present invention.

[0044] Figure 10 This is a 5-way continuous non-overlapping amplitude spectrum diagram obtained by dividing the spectrum in an example of the present invention. DETAILED DESCRIPTION

[0045] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more apparent.

[0046] like Figure 1 As shown, an embodiment of the present invention proposes a spectrum segmentation FFT method based on FPGA, including:

[0047] Step 1: Obtain the time domain raw data of the real-time vector signal through the acquisition device.

[0048] Step 2: Set the parameters of the spectrum segmentation FFT model.

[0049] The parameters for the split FFT model are as follows: the number of channels, M (in this example, M supports 2, 3, 5, and 8), a data width of depth bits, with the upper depth / 2 bits representing the imaginary part of the acquired signal and the lower depth / 2 bits representing the real part, the number of points per channel, L, and the total number of sampling points, N = M * L. These parameters are set by the input configuration signal, FFTconfig. This signal is 8 bits wide, with the lower 4 bits representing the number of points per channel, L, calculated as the power of the decimal number corresponding to the lower 4 bits of 2. The upper 4 bits of the configuration signal represent the number of channels, M.

[0050] Step 3: Input the acquired vector time domain data into the spectrum segmentation FFT model.

[0051] The spectrum segmentation FFT model decomposes the FFT of a positive integer N points into the product of two positive integers R and C, converts one-dimensional data into two-dimensional data, and is designed based on the following formula:

[0052] ,

[0053] The formula is , Substitute into the DFT formula Get, among them , and , are the horizontal and vertical coordinates of the frequency domain and time domain of the two-dimensional data, , , , . is the correction factor, is the rotation factor of the transverse frequency domain transform, is the rotation factor of the longitudinal frequency domain transform, The final frequency domain is divided into continuous and non-overlapping complete frequency domain signals.

[0054] The implementation steps of this formula correspond to the various modules of the segmented FFT model.

[0055] like Figure 2 As shown, in this example, the split FFT model includes a data branching module, a multi-channel FFT module, a correction angle storage module, a vector rotation module, and a matrix transformation module.

[0056] The data splitting module is used to realize the efficient conversion of single-channel data to multi-channel data in FPGA. The traditional method usually adopts a one-time output method after sampling is completed, that is, parallel output is performed after a set of data is completely collected. However, the present invention adopts an improved splitting method, which inputs the sampled time domain vector signal into a FIFO with a depth of M. The specific flow diagram of the data is as follows: Figure 3 As shown in the figure, d represents the input data, d0 represents the 0th data point, and d4M-1 represents the 4M-1th data point. Setting the FIFO to asymmetric input and output. For example, if the input bit width is 32 bits, the output bit width is 32*M. After each Mth data point is input, M channels of data are simultaneously output (M is the number of channels), rather than waiting for the entire sampling cycle to complete before data demultiplexing. This ensures data latency of only 1 clk, improving the system's real-time responsiveness while reducing the need for internal FPGA storage space.

[0057] Multi-channel FFT module; this module adopts M-channel parallelism, and each channel adopts pipeline architecture. First, the input data is bit-reversed and arranged through the pre-processing unit to meet the input requirements of the FFT algorithm. Next, the data enters the pipeline structure at each level, and each stage performs butterfly operation and multiplies by the corresponding rotation factor. After each butterfly operation stage, the data is multiplied by a programmable scaling factor to control the amplitude of the data and prevent overflow. The entire processing process uses a streaming I / O interface to ensure that each sampling point enters the pipeline processing immediately after acquisition. Finally, after all stages of processing, the output data must be bit-reversed to obtain a natural order of frequency domain results. The number of points supported by each FFT is , p ranges from 3 to 14.

[0058] Vector rotation module; In traditional FFT calculations, the storage and calculation of rotation factors usually adopt two methods: one is to store the pre-calculated rotation factors through a lookup table; the other is to use the coordinate rotation digital calculation method (CORDIC) to dynamically calculate the rotation factors, and then perform complex multiplication with the previous data. The optimized method combines the storage and complex multiplication of the rotation factors. The essence of complex multiplication of data and rotation factors is to rotate the vector signal. Therefore, CORDIC can combine this feature very well for calculation. Because the storage data of the rotation factor is complex, with real and imaginary parts, using CORDIC instead of the complex multiplier only requires storing the rotation angle. Therefore, compared with the rotation factors calculated by LUT storage, the optimized solution can save 50% of the internal storage resources, especially for FFTs with large points. The resources consumed by storing the rotation factors are proportional to the number of points calculated by the FFT. Generally speaking, there will be a certain hardware resource overhead and computational delay when the rotation factors are calculated in real time by the CORDIC algorithm. Assume that the delay of CORDIC calculating the rotation factor is , the delay of complex multiplication is , then the total delay of this method is , and the delay of using CORDIC instead of complex multiplication is only Especially for the traditional two solutions and the resource consumption of the complex multiplier, the optimized solution saves a lot of DSP resources, especially when the number of channels M is large. Specifically, let , when the number of channels is M, the data of M channels are The vector rotation module uses vector rotation to replace the multiplier and Multiply.

[0059] Correction angle storage module; the correction angle storage module calculates the rotation angle of the correction factor in advance on the host computer and stores it in the BRAM. The calculation formula of the correction factor is , N is the total number of points for FFT calculation. This process requires that the rotation angle be greater than and is less than The angle plus To meet the rotation angle in arrive between.

[0060] Matrix transformation module; For conventional two-dimensional decomposition algorithms, the following steps are generally required: first, decompose N-point data into matrix data of natural number R times C; second, perform FFT of C points on each of the R rows of the matrix data; then multiply by the matrix factor; then transpose the multiplied data; and finally, perform FFT of R points on each of the C rows of the transposed data. It can be seen from the general method that this method needs to transpose the preceding data when performing FFT for the second time. However, transposing large-point parallel data in FPGA is a very time-consuming and resource-intensive operation, and after the transposition is completed, the data needs to be transposed for the second time after the second spectrum transformation to obtain multiple continuous non-overlapping spectrums. Therefore, the present invention decomposes the DFT transformation matrix of the channel number M into These three matrices are multiplied together, 、 To contain only 0, 1, -1 elements, is a diagonal matrix. Due to the characteristics of this decomposition 、 Contains only addition and subtraction, which can greatly reduce the use of multipliers and save resources. Compared with traditional algorithms, this example can allow FFT of odd channels. In theory, any number of channels can be combined with mixed basis algorithms to achieve. Supports M = 2, 3, 5, 8 channels. Therefore, the total number of sampling points , p ranges from 3 to 14, The relationship between the input and output of this module is , when M=2 The 2-way data structure is the same as that of a normal butterfly unit.

[0061] When M=3, .

[0062] When M=5,

[0063] ;

[0064] When M=8,

[0065] .

[0066] like Figure 4 、 Figure 5 and Figure 6 As shown in the figure, it is a specific 3, 5, and 8-way data structure flow chart, where Represents the vertical data of the input matrix, Indicates the 0th data in the vertical direction of the matrix, Indicates the fifth data in the vertical direction of the matrix. Similarly, denoted as the 0th frequency point of the output longitudinal data, where j is an imaginary unit. Compared to a parallel DFT, this reduces the number of complex multipliers by 2, 11, and 28, and the number of complex adders by 0, 3, and 30, respectively. Using this decomposed matrix transform to process preprocessed data not only avoids data transposition and significantly reduces latency, but also saves many multipliers and adders for FFTs with a certain number of channels and points.

[0067] In order to further save complex multiplier and complex adder resources, it is necessary to reuse the resources in the 2-, 3-, 5-, and 8-way matrix transformation modules. Figure 7 The following is a flow chart of the multi-channel mixed data structure. To ensure the correct matrix transformation operation of different channel numbers and the natural sequence output of frequency domain data, the data rearrangement unit, data selector, and multiplication factor need to be jointly controlled.

[0068] Figure 7 The butterfly unit in the figure has 2 inputs and 2 outputs. The upper output is the sum of the upper input and the lower output, and the lower output is the difference between the upper input and the lower input. Din0 to Din7 are 8 input ports for receiving data after CORDIC vector rotation. Dout0 to Dout7 are 8 output ports for outputting the final segmented spectrum data. First, the data after vector rotation will be sent to Din0 to Din7. When the parallelism of the data is less than 8, the port without data needs to set its input data to 0. Then the data is rearranged and passed through the butterfly unit, multiplier, and data selector to obtain arrive The out-of-order data is finally rearranged and output as Dout0 to Dout7 to ensure the correct frequency domain order. The corresponding relationship between the data of different channel numbers being set to 0 and the input data position is shown in Table 1.

[0069] Table 1

[0070]

[0071] The corresponding relationship between the positions of disordered data in the middle of different channel numbers is shown in Table 2, where X is a high-impedance state, indicating that no data is output.

[0072] Table 2

[0073]

[0074] MUX is a data selector. Indicates the data selection switch of the first MUX. When set to 1, select the upper output. When set to 0, the lower output is selected. There are 6 data selectors in the multiplexed data structure to control the data flow of different channel numbers, as shown in Table 3.

[0075] Table 3

[0076]

[0077] In order to realize the reuse of multipliers, it is also necessary to configure the multiplication factors at the input of the multiplier when selecting different paths. There are 5 multiplication factors in this flow chart. 、 、 、 、 Since the multiplication factors required for the diagonal matrix in the decomposition matrix are different when the matrix transformation is performed on data with different channel numbers, the multipliers not used in different channel numbers are set to 0. When M=2, all multipliers are set to 0; when M=3, , , ; When M=5, , , , , , ; When M=8, , , , .

[0078] For a vector signal, the total delay after spectrum segmentation FFT model is: ,in = is the total delay, where the first term is the delay of the vector signal passing through the splitter module, the second term is the delay of the vector signal passing through the multi-channel FFT module, the third term is the delay of the signal during the CORDIC complex multiplication, and the last term is the delay of the signal during the matrix transformation. To ensure the continuity of multi-channel signals, delay units are added to the data structure flow chart of each channel to ensure data continuity and simultaneity. The delay of the complex multiplier is 4 clks, and the delay of the complex adder is 1 clk. Therefore, the delays for channels 2, 3, 5, and 8 are calculated to be 3, 9, 9, and 8 clks, respectively.

[0079] Step 4: Output the frequency domain of the vector signal.

[0080] The present invention divides the output frequency domain data into M paths, and the frequency domain range corresponding to each path is , , is the corresponding road number.

[0081] Simulate the content of this example. Generate signal function through MATLAB:

[0082] ,

[0083] The sampling frequency =64Mhz, signal frequency =21.37Mhz, number of channels M=5, total number of sampling points =40960. Figure 8 As shown, the 5-channel data in the programmable gate array FPGA is saved and compared with the amplitude spectrum of the fast Fourier transform (FFT) of the mathematical calculation software MATLAB system function, as shown in Figure 9 As shown in the figure, the error diagram of the FFT function of MATLAB and the FFT amplitude spectrum of FPGA simulation is caused by quantization, which is within the allowable error range. Figure 10 The figure shows the 5-channel continuous non-overlapping amplitude spectrum obtained by FPGA simulation FFT. The frequency ranges of channels 1 to 5 are 0 to 12.8 MHz, 12.8 to 25.6 MHz, 25.6 to 38.4 MHz, 38.4 to 51.2 MHz, and 51.2 to 64.0 MHz, respectively. The system model delay is Since the model calculates non-power-of-two point FFT, another set of data M=8 is tested, with a total number of sampling points n=65536. The system model delay tested is CLKs. Compared to the FFT IP core in Vivado, the signal delay through the IP core is 65,741 CLKs. The FFT execution time of the present invention is accelerated by 7.817 compared to the traditional FFT IP core, meeting the requirement of efficient and faster processing of large-point FFTs.

[0084] The present invention also provides an FPGA-based spectrum segmentation FFT device, comprising: a data branching module, a multi-channel FFT module, a correction angle storage module, a vector rotation module, and a matrix transformation module.

[0085] The data branching module is connected to the multi-channel FFT module, the multi-channel FFT module and the correction angle storage module are connected to the vector rotation module, and the vector rotation module is connected to the matrix transformation module.

[0086] The data splitting module performs group processing on the acquired vector time domain data and divides the acquired vector signal into M paths, where M represents the number of channels;

[0087] The multi-channel FFT module calculates the multi-channel data signals to obtain the intermediate frequency domain signals.

[0088] The correction angle storage module stores the rotation angle of the correction factor in the BRAM.

[0089] The vector rotation module rotates multiple channels of vector data simultaneously.

[0090] The matrix transformation module transforms the results of multiple independent signals into a complete frequency domain signal.

[0091] The present invention provides an FPGA-based spectrum segmentation FFT method and apparatus. There are numerous methods and approaches for implementing this technical solution. The above description is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications are also within the scope of protection of the present invention. Any components not specified in this embodiment may be implemented using existing technologies.

Claims

1. A spectrum segmentation FFT method based on FPGA, characterized in that: The following steps are involved: Step 1: Obtain the time domain raw data of the real-time vector signal through an acquisition device; Step 2: Set the parameters of the spectrum segmentation FFT model: Set the parameters through the input configuration signal FFTconfig. The signal FFTconfig bit width is 8 bits, of which the lower 4 bits are the number of points L for each signal, calculated by the power of the decimal number corresponding to the lower 4 bits of 2; the upper 4 bits are the number of channels M; Step 3: Input the acquired time domain raw data of the vector signal into the spectrum segmentation FFT model. The spectrum segmentation FFT model is designed based on the two-dimensional decomposition FFT and the discrete Fourier transform DFT converted into a circular convolution algorithm. First, the multi-channel time domain data is simultaneously subjected to the first horizontal spectrum transformation, and then the data is multiplied by the corresponding correction factor. Then, the spectrum transformation of the number of channel points is performed again in the vertical direction, and the DFT transformation matrix of the channel number M is decomposed into three matrix multiplications: , where the matrix 、 It only contains 0, 1, -1 elements. is a diagonal matrix; Step 4, output frequency domain data of the vector signal; In step 3, the spectrum segmentation FFT model decomposes the FFT of the positive integer N points into the product of two positive integers R and C, converting the one-dimensional data into two-dimensional data. The formula is: ， in 、 are the horizontal and vertical coordinates of the frequency domain of the two-dimensional data, 、 are the horizontal and vertical coordinates of the time domain of the two-dimensional data, , , , ; is the correction factor, is the rotation factor of the horizontal frequency domain transform, is the rotation factor of the longitudinal frequency domain transform, The final frequency domain is divided into continuous and non-overlapping complete frequency domain signals; In step 3, the spectrum segmentation FFT model includes a data branching module, a multi-channel FFT module, a correction angle storage module, a vector rotation module and a matrix transformation module; The data branching module is connected to the multi-channel FFT module, the multi-channel FFT module and the correction angle storage module are connected to the vector rotation module, and the vector rotation module is connected to the matrix transformation module; The data splitting module uses an improved splitting method to input the sampled time domain vector signal into a first-in-first-out data buffer with a depth of M, performs group processing by asymmetric input and output, and divides the acquired vector signal into M paths; The multi-channel FFT module calculates the multi-channel data signals to obtain the intermediate frequency domain signals; The correction angle storage module stores the rotation angle of the correction factor in a block random access memory, the multi-channel FFT module outputs a valid frequency domain signal which is fed back to the correction angle storage module as a start signal, and the multi-channel frequency domain signal is output simultaneously with the correction angle after delay; The vector rotation module uses a coordinate rotation digital calculation method to simultaneously rotate multiple channels of vector data to achieve the effect of complex multiplication; The matrix transformation module performs spectrum transformation on multiple channels of data that have been multiplied by correction factors in the longitudinal direction again, and performs matrix transformation on multiple independent signal results to obtain a complete multi-channel frequency domain signal that is frequency-domain segmented but continuous and non-overlapping.

2. The method according to claim 1, characterized in that In step 3, the multi-channel FFT module allocates an independent FFT calculation unit to each channel of data. Through parallel processing, FFTs of more than two rows can be calculated simultaneously, and all data after parallel calculation are directly pipelined and output.

3. The method according to claim 2, characterized in that In step 3, the correction angle storage module calculates the rotation angle of the correction factor in advance on the host computer and stores it in the block random access memory. The exponent of the correction factor is the calculation formula of the rotation angle. The calculation formula of the correction factor is ,in and are the ordinate of the frequency domain and the abscissa of the time domain of the two-dimensional data, N is the total number of points calculated by FFT, e represents a natural constant, and j is an imaginary unit.

4. The method according to claim 3, characterized in that In step 3, the vector rotation module puts the data into the calculation completion signal of the multi-channel FFT module for the first time and aligns it with the data of the correction angle storage module at the same time, and then uses the coordinate rotation digital calculation method to perform rotation correction of the vector data.

5. The method according to claim 4, characterized in that In step 3, the matrix transformation module performs spectrum transformation on the multi-channel data that have been multiplied by the correction factor, and performs matrix transformation on the multi-channel independent signal results to obtain a complete frequency domain signal. The supported channel number M=2, 3, 5, 8, and the total number of points supported by FFT are ,in ; The value ranges from 3 to 14; , , , Parameters indicating whether 2, 3, 5, or 8 channels are selected. If 2 channels are selected, =1, otherwise a is 0, if it is 3-way data, b=1, otherwise b is 0, if it is 5-way data, c=1, otherwise c is 0, if it is 8-way data, d=1, otherwise d is 0; is the exponent of the first spectral transformation to the power of 2; Each channel data needs to add a delay unit to meet the simultaneity. The delay of the complex multiplier in the matrix transformation is 4 clock cycles, and the delay of the complex adder is 1 clock cycle. Therefore, the delays of 2, 3, 5, and 8 channels are calculated to be 3, 9, 9, and 8 clock cycles respectively; the two-channel data is butterfly operation, and the matrix transformation of the three-channel data, five-channel data, and eight-channel data is as follows: 、 、 : ， ， 。 6. The method according to claim 5, characterized in that In step 3, a multi-channel mixed data structure with resource reuse design is formed in the matrix transformation modules of 2, 3, 5, and 8. First, the data after vector rotation is input into the multi-channel mixed data structure. When the parallelism of the data is less than 8, the port without data needs to set the input data to 0. Then the data is rearranged. After two or more data selections, the correct data paths of different channels are obtained, and the data is obtained by The elements in the diagonal matrix are used to configure one end of the input of the multiplier, and finally the output data is rearranged again to realize the longitudinal frequency domain transformation of different channel numbers.

7. A spectrum segmentation FFT device based on FPGA implemented according to the method according to any one of claims 1 to 6, characterized in that: It includes data splitting module, multi-channel FFT module, correction angle storage module, vector rotation module and matrix transformation module; The data branching module is connected to the multi-channel FFT module, the multi-channel FFT module and the correction angle storage module are connected to the vector rotation module, and the vector rotation module is connected to the matrix transformation module; The data splitting module performs group processing on the acquired vector time domain data and divides the acquired vector signal into M paths, where M represents the number of channels; The multi-channel FFT module calculates the multi-channel data signals to obtain the intermediate frequency domain signals; The correction angle storage module stores the rotation angle of the correction factor in the BRAM; The vector rotation module rotates multiple channels of vector data simultaneously; The matrix transformation module transforms the results of multiple independent signals into a complete frequency domain signal.

8. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores program codes, and when the program codes are executed by the processor, the processor is caused to perform the steps of the method according to any one of claims 1 to 6.

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