Integrated circuit model verification method and system, computer equipment and storage medium

Abstract

The invention provides an integrated circuit model verification method and system, computer equipment and a storage medium. The method comprises the steps that parameters in a model library are analyzed through a script, and model parameters needed by verification are automatically extracted; a standard configuration file format is obtained, the model parameters are loaded into a standard configuration file, and a simulation configuration file is generated; obtaining netlist file formats required by different simulators, and generating netlist files which comprise output instructions and are adaptive to different simulators in batches according to the simulation configuration file; calling each simulator to execute the corresponding netlist file for simulation, and outputting an intermediate file; analyzing the numerical data in the intermediate file, and generating a standard format file; and comparing the standard format files generated by different simulators to obtain a verification result. According to the scheme, batch parameter configuration, netlist generation, simulation execution and result processing of the integrated circuit model can be realized, so that the model verification efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of simulation model verification, and particularly to an integrated circuit model verification method, system, computer device, and storage medium. Background Art

[0002] In the process of integrated circuit design, model verification is a key link, which involves parameter configuration, netlist generation, simulation operation, and result analysis. Traditional methods rely on manual parameter configuration and manual execution of simulation scripts, and there are the following problems: 1. Low efficiency: The netlist needs to be generated manually and cannot batch process complex models; 2. Fragmented simulation process: Multiple tools need to be switched between netlist generation and simulation execution, and the management of intermediate files is chaotic, which is prone to errors; 3. Complicated result processing: The intermediate files generated by the simulation need to extract data manually, and it is impossible to accurately compare and generate error results through waveform viewing; 4. Poor compatibility: The output formats of different simulators vary greatly and are difficult to uniformly process.

[0003] Therefore, there is an urgent need for a model verification method that can achieve batch parameter configuration, netlist generation, simulation execution, and result processing of integrated circuit models. Summary of the Invention

[0004] The purpose of the present invention is to provide an integrated circuit model verification method, system, computer device, and storage medium, which can achieve batch parameter configuration, netlist generation, simulation execution, and result processing of integrated circuit models, thereby improving the efficiency of model verification.

[0005] The technical solution provided by the present invention is as follows: In the first aspect, the present application provides an integrated circuit model verification method, including the steps of: Parsing the parameters in the model library through a script and automatically extracting the model parameters required for verification; Obtaining the standard configuration file format and loading the model parameters into the standard configuration file to generate a simulation configuration file; Obtaining the netlist file formats required by different simulators and batch generating netlist files adapted to different simulators containing output instructions according to the simulation configuration file; Calling each simulator to execute the corresponding netlist file for simulation and outputting intermediate files; Parsing the numerical data in the intermediate file and generating a standard format file; Comparing the standard format files generated by different simulators to obtain a verification result.

[0006] This solution realizes the extraction of batch model parameters required for integrated circuit model verification, the generation of standard simulation configuration files, the generation of netlist files adapted to different simulators, and the generation and automatic comparison of standard format files of simulation results through scripts, thereby improving the model verification efficiency, realizing the high-efficiency, standardization, and extensibility of the integrated circuit model verification process, significantly enhancing the productivity of semiconductor design and verification links, and being applicable to large-scale device model verification, EDA tool development, and academic research scenarios.

[0007] In some embodiments, after parsing the parameters in the model library and automatically extracting the model parameters required for verification, it further includes: Judging the component type corresponding to the model parameters, and classifying and storing the simulation configuration file and the netlist file according to the component type.

[0008] In some embodiments, after generating the simulation configuration file and before calling each simulator to execute the corresponding netlist file for simulation, it further includes: Identifying the simulation type according to the model parameters corresponding to the simulation configuration file, where the simulation type includes DC simulation mode, AC simulation mode, and noise simulation mode; After calling each simulator to execute the corresponding netlist file for simulation, it further includes: Classifying and storing the intermediate file and the standard format file according to the simulation type.

[0009] In some embodiments, it further includes: Abstracting the simulation logics of different simulation types into standardized function interfaces.

[0010] In some embodiments, parsing the numerical data in the intermediate file and generating a standard format file includes: Parsing the numerical data in the intermediate file and extracting it to a temporary file; Deleting the redundant intermediate files in the temporary file and generating the standard format file according to the standard format.

[0011] In some embodiments, the standard format file includes formatted output of key parameters.

[0012] In some embodiments, before parsing the parameters in the model library, it further includes: Constructing a script, which includes a first script for parsing the parameters in the model library, a second script for automatically generating a simulation configuration file, a third script for batch generating a netlist file according to the simulation configuration file, a fourth script for generating a standard format file, and a fifth script for automatically comparing the standard format files generated by different simulators.

[0013] In a second aspect, the present application provides an integrated circuit model verification system, including: A parameter configuration layer, configured to parse the parameters in the model library through a script, automatically extract the model parameters required for verification, obtain a standard configuration file format, and load the model parameters into the standard configuration file to generate a simulation configuration file; A netlist generation and simulation layer, configured to obtain the netlist file formats required by different simulators, and batch generate netlist files adapted to different simulators containing output instructions according to the simulation configuration file, call each simulator to execute the corresponding netlist file for simulation, and output intermediate files; A data processing layer, configured to parse the numerical data in the intermediate file and generate a standard format file; An output and verification layer, configured to compare the standard format files generated by different simulators to obtain a verification result.

[0014] In a third aspect, the present application provides a computer device, including a memory, a processor, and a computer program stored on the memory, where the processor executes the computer program to implement the steps of the integrated circuit model verification method described in the first aspect.

[0015] In a fourth aspect, the present application provides a computer storage medium, on which a computer program or instruction is stored, and when the computer program or instruction is executed by a processor, the steps of the integrated circuit model verification method described in the first aspect are implemented.

[0016] According to an integrated circuit model verification method, system, computer device, and storage medium provided by the present invention, through a script, batch extraction of model parameters required for integrated circuit model verification, generation of a standard simulation configuration file, generation of netlist files adapted to different simulators, and generation and automatic comparison of a standard format file of simulation results are realized, thereby improving the model verification efficiency, achieving the high-efficiency, standardization, and extensibility of the integrated circuit model verification process, significantly enhancing the productivity of the semiconductor design and verification links, and being applicable to large-scale device model verification, EDA tool development, and academic research scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The following will further illustrate the above characteristics, technical features, advantages, and their implementation manners of the present solution in a clear and understandable manner in combination with the drawings and the preferred embodiments.

[0018] Figure 1 is the overall flow schematic diagram of an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will describe the specific embodiments of the present invention with reference to the accompanying drawings. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings, and other embodiments can also be obtained.

[0020] To make the drawings concise, only the parts related to the present invention are schematically shown in each drawing, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, in some drawings, components with the same structure or function are only schematically shown one of them, or only one of them is marked. In this article, "one" not only means "only this one", but also means "more than one" situation.

[0021] In the process of integrated circuit design, model verification is a key link, involving parameter configuration, netlist generation, simulation operation, and result analysis. Traditional methods rely on manual parameter configuration and manual execution of simulation scripts, and there are the following problems: 1. Low efficiency: The netlist needs to be generated manually and cannot batch process complex models; 2. Disconnected simulation process: Multiple tools need to be switched between netlist generation and simulation execution, and the management of intermediate files is chaotic, which is prone to errors; 3. Complex result processing: The intermediate files generated by the simulation need to extract data manually, and it is impossible to accurately compare and generate error results through waveform viewing; 4. Poor compatibility: The output formats of different simulators vary greatly and are difficult to process uniformly.

[0022] Therefore, there is an urgent need for a model verification method that can realize batch parameter configuration, netlist generation, simulation execution, and result processing of integrated circuit models. This solution realizes the extraction of batch model parameters required for integrated circuit model verification, the generation of standard simulation configuration files, the generation of netlist files adapted to different simulators, and the generation and automatic comparison of standard format files of simulation results through scripts, so as to realize the standardization and generalization of integrated circuit model verification and improve the efficiency of model verification. The following will describe this solution in detail with reference to the accompanying drawings: In one embodiment, referring to the attached Figure 1 of the specification, the present application provides an integrated circuit model verification method, including the steps: S100. Parse the parameters in the model library through a script and automatically extract the model parameters required for verification; the model library is a general simulation library in existing integrated circuit simulations. The model library stores the model parameters commonly used in integrated circuit model verification and supports the addition and modification of parameters. This solution realizes the automatic extraction of some model parameters required for verifying the integrated circuit model to be verified from the model library by designing a script.

[0023] S200. Obtain the standard configuration file format, load the model parameters into the standard configuration file, and generate a simulation configuration file. Since the configuration files corresponding to different simulators are different, in order to standardize, this application sets a standard configuration file. After obtaining the model parameters, each model parameter is loaded into the standard configuration file through a script to generate a standard simulation configuration file.

[0024] S300. Obtain the netlist file formats required by different simulators, and batch generate netlist files adapted to different simulators containing output instructions according to the simulation configuration file. For different simulators, in order to achieve standardization, obtain the netlist file formats required by different simulators respectively, and batch generate netlist files adapted to different simulators containing output instructions through a script according to the simulation configuration file to perform separate simulations for each simulator.

[0025] S400. Call each simulator to execute the corresponding netlist file for simulation and output intermediate files.

[0026] S500. Parse the numerical data in the intermediate file and generate a standard format file. Since the netlist generation and simulation execution require multiple tool switches, resulting in chaotic management and error-prone of the intermediate files, this application parses the numerical data in the intermediate file through a script and generates a standard format file, which is conducive to subsequent comparison and realization of the verification operation.

[0027] S600. Compare the standard format files generated by different simulators to obtain the verification result.

[0028] Specifically, the integrated circuit model verification solution of this application can be summarized as including: batch generation of parameter configuration, netlist generation and simulation execution, simulation result processing and standardization, result comparison and verification. Among them, the batch generation of parameter configuration includes: (1) Input source preparation: The user provides the model library file, file parameter format, and netlist content. (2) Script execution and parameter generation: Parse the model library, extract key parameters, and generate a parameter configuration file. (3) Output directory structure: The generated parameter files are classified and stored according to the model type (such as npn, pnp, etc.).

[0029] The netlist generation and simulation execution include: (1) Netlist generation rule: Generate netlist files adapted to different simulators according to the test specifications in the parameter file. (2) Simulation execution command: Directly call the simulator to execute the netlist file through the system command, and the generated simulation result file is stored in the subdirectory of the corresponding model directory.

[0030] Simulation result processing and standardization include: (1) Data parsing and cleaning: Extract the information required by the user from the simulation result file and store it in a temporary data file, while deleting unnecessary intermediate files; (2) Standardized file generation: Output the data from the temporary data file to a standard format file according to different formatting rules based on the test type (DC, AC, or noise).

[0031] Result comparison and verification include: (1) Automated comparison script: Use a script to compare the standard result files of different simulators; (2) Verification conclusion generation: Classify the files according to the error range defined by the user (pass / fail / compare failed, etc.).

[0032] This solution realizes the extraction of batch model parameters required for integrated circuit model verification, the generation of standard simulation configuration files, the generation of netlist files adapted to different simulators, and the generation and automatic comparison of standard format files of simulation results through scripts, thereby improving the model verification efficiency, realizing the high-efficiency, standardization, and extensibility of the integrated circuit model verification process, significantly enhancing the productivity of the semiconductor design and verification links, and being applicable to large-scale device model verification, EDA tool development, and academic research scenarios.

[0033] This solution realizes the high-efficiency, standardization, and extensibility of the integrated circuit model verification process through automated scripts. Before realizing the batch parameter configuration, netlist generation, simulation execution, and result processing of the integrated circuit model through scripts, it is first necessary to construct scripts. The scripts include a first script for parsing the parameters in the model library, a second script for automatically generating simulation configuration files, a third script for batch generating netlist files according to the simulation configuration files, a fourth script for generating standard format files, and a fifth script for automatically comparing the standard format files generated by different simulators, so as to realize the automation of the integrated circuit model verification. The specific structure of the script is not limited in this application, as long as it can achieve the above operations.

[0034] In one embodiment, on the basis of the foregoing embodiment, after parsing the parameters in the model library and automatically extracting the model parameters required for verification, it further includes: Determine the component type corresponding to the model parameters, and classify and store the simulation configuration files and netlist files according to the component type. For example, classify folders according to the component type (such as triodes, diodes, etc.), store both the simulation configuration files and the subsequent netlist files in the corresponding folders, and maintain the directory structure defined by the user to avoid compatibility problems caused by subsequent path modifications.

[0035] In one embodiment, based on the foregoing embodiment, after generating the simulation configuration file and before calling each simulator to execute the corresponding netlist file for simulation, the following steps are further included: Identify the simulation type according to the model parameters corresponding to the simulation configuration file. The simulation types include DC simulation mode, AC simulation mode, and noise simulation mode. The simulation model parameters corresponding to different simulation types are different and specific. After obtaining the model parameters in the simulation configuration file, the specific type of simulation can be determined according to the characteristics of these model parameters.

[0036] After calling each simulator to execute the corresponding netlist file for simulation, the following steps are further included: Classify and store the intermediate files and standard format files according to the simulation type for subsequent result traceability. After determining the simulation type, the intermediate files and standard format files can also be classified and stored according to the simulation type. That is, this solution can classify and store files in different folders according to two classification methods: component type and test type, and users can select according to their needs. In other embodiments, other classification storage methods can also be selected to make the data in the simulation more clearly organized for subsequent traceability.

[0037] In one embodiment, based on the foregoing embodiment, before simulation verification, the following steps are further included: Abstract the simulation logics of different simulation types into standardized function interfaces to achieve a unified simulation interface. By encapsulating different simulation logics with functions, the call process can be simplified, making the system more convenient to use and more general.

[0038] In one embodiment, based on the foregoing embodiment, parsing the numerical data in the intermediate file and generating a standard format file includes: Parse the numerical data in the intermediate file and extract it to a temporary file; delete the redundant intermediate files in the temporary file and generate a standard format file according to the standard format. The standard format file includes the formatted output of key parameters (such as the horizontal and vertical axis data of the waveform).

[0039] In one embodiment, based on the foregoing embodiment, the integrated circuit model verification method provided by this application includes: 1. Batch generation of model parameter configuration (1) Parameter extraction: Parse the parameters in the model library through a script, automatically extract the required model parameters, and support configuration templates for multiple component types (such as triodes, diodes); (2) Generation of parameter configuration file: Use the library import mode to replace manual configuration. Through the standard configuration file format provided by the user, load the model parameters into the configuration file to ensure parameter consistency.

[0040] 2. Batch Generation of Netlists and Simulation Automation (1)Fixed directory structure: Classify folders by component type (such as transistors, diodes), maintain the existing user-defined directory structure, and avoid compatibility issues caused by path modifications; (2)Netlist generation rules: Research the netlist file formats required by different simulators, batch generate netlist files containing output instructions, and ensure the correct generation of simulation output files; (3)Simulation execution interface: Directly call the simulator to execute the netlist through system commands, and output the results or intermediate files to a file.

[0041] 3. Simulation Result Processing and Standardized File Generation (1)Extraction of intermediate files: Parse the numerical data in the file, extract it to a temporary file, and delete redundant intermediate files; (2)Generation of standard files: Automatically generate standardized report files from the temporary data, including formatted output of key parameters (horizontal and vertical axis data of waveforms).

[0042] 4. Automatic Judgment and Processing of Simulation Modes (1)Identification of simulation types based on parameter configuration files: Automatically distinguish between DC, AC, or noise simulation modes according to parameters; (2)Unified simulation interface: Simplify the call process by encapsulating different simulation logics through functions.

[0043] 5. File Classification and Comparison Rules (1)Classification rules: Classify and store files in different folders according to component type and test type for easy result traceability; (2)Comparison of results of different simulation files: Compare the standard format files generated by different simulators to verify the error of simulation results.

[0044] This application realizes the high efficiency, standardization, and extensibility of the integrated circuit model verification process through automated scripting technology, significantly improves the productivity of semiconductor design and verification, and is applicable to large-scale device model verification, EDA tool development, and academic research scenarios. Specifically, the integrated circuit model verification method of this application has at least the following technical effects: (1)Significantly improve verification efficiency: The netlist generation and simulation cycle are shortened. Call scripts to batch generate netlist files adapted to multiple simulators, ensure the integrity of output files, and reduce tool switching and manual debugging time; (2)Improve result accuracy and consistency: Replace manual data comparison operations with automated scripts to eliminate common problems such as incorrect path input; preset tolerances (such as ±0.1%) and matching rules (such as ignoring spaces and comment lines), and the results are completely objective, supporting scientific notation and precise comparison of floating-point numbers; (3) Enhance process compatibility and expandability: The format is self - adaptive during result comparison, and it is compatible with the outputs of multiple simulators through regular expressions and template matching; it supports adding comparison rules for new test types (such as noise analysis), and only the configuration file needs to be modified.

[0045] In one embodiment, based on the foregoing embodiment, the present application provides an integrated circuit model verification system, including: A parameter configuration layer, which is used to parse the parameters in the model library through scripts, automatically extract the model parameters required for verification, obtain the standard configuration file format, and load the model parameters into the standard configuration file to generate a simulation configuration file; A netlist generation and simulation layer, which is used to obtain the netlist file formats required by different simulators, and batch - generate netlist files adapted to different simulators containing output instructions according to the simulation configuration file, call each simulator to execute the corresponding netlist file for simulation, and output intermediate files; A data processing layer, which is used to parse the numerical data in the intermediate files and generate standard - format files; An output and verification layer, which is used to compare the standard - format files generated by different simulators to obtain verification results.

[0046] This solution realizes the extraction of batch model parameters required for integrated circuit model verification, the generation of step - by - step simulation configuration files, the generation of netlist files adapted to different simulators, and the generation and automatic comparison of standard - format files of simulation results through scripts, thereby improving the model verification efficiency, realizing the high - efficiency, standardization, and expandability of the integrated circuit model verification process, significantly enhancing the productivity of the semiconductor design and verification links, and being applicable to large - scale device model verification, EDA tool development, and academic research scenarios.

[0047] In one embodiment, the present application provides a computer device, including a memory, a processor, and a computer program stored on the memory. The processor executes the computer program to implement the steps of the integrated circuit model verification method in the foregoing embodiment.

[0048] In one embodiment, the present application provides a computer storage medium, on which a computer program or instruction is stored. When the computer program or instruction is executed by a processor, the steps of the integrated circuit model verification method in the foregoing embodiment are implemented.

[0049] In one embodiment, the present application provides a computer program product, including a computer program or instruction. When the computer program or instruction is executed by a processor, the steps of the integrated circuit model verification method in the foregoing embodiment are implemented.

[0050] The integrated circuit model verification method of the present application can be implemented by program codes executable by a computing device. Thus, they can be stored in a storage device for execution by the computing device, or be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them be fabricated into a single integrated circuit module for implementation. In this way, the present invention is not limited to any specific combination of hardware and software.

[0051] It should be noted that the above embodiments can be freely combined as needed. The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can still be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. An integrated circuit model verification method, characterized in that, Including the steps: Parsing the parameters in the model library through a script and automatically extracting the model parameters required for verification; Obtaining the standard configuration file format and loading the model parameters into the standard configuration file to generate a simulation configuration file; Obtaining the netlist file formats required by different simulators and batch generating netlist files adapted to different simulators containing output instructions according to the simulation configuration file; Invoking each simulator to execute the corresponding netlist file for simulation and outputting intermediate files; Parsing the numerical data in the intermediate file and generating a standard format file; Comparing the standard format files generated by different simulators to obtain the verification result.

2. The integrated circuit model verification method according to claim 1, wherein After parsing the parameters in the model library and automatically extracting the model parameters required for verification, it further includes: Judging the component type corresponding to the model parameters and classifying and storing the simulation configuration file and the netlist file according to the component type.

3. The integrated circuit model verification method according to claim 1, characterized in that After generating the simulation configuration file and before invoking each simulator to execute the corresponding netlist file for simulation, it further includes: Identifying the simulation type according to the model parameters corresponding to the simulation configuration file, and the simulation type includes DC simulation mode, AC simulation mode, and noise simulation mode; After invoking each simulator to execute the corresponding netlist file for simulation, it further includes: Classifying and storing the intermediate file and the standard format file according to the simulation type.

4. The integrated circuit model verification method according to claim 3, wherein It further includes: Abstracting the simulation logics of different simulation types into standardized function interfaces.

5. The integrated circuit model verification method according to claim 1, wherein The parsing the numerical data in the intermediate file and generating a standard format file includes: Parsing the numerical data in the intermediate file and extracting it to a temporary file; Deleting the redundant intermediate files in the temporary file and generating the standard format file according to the standard format.

6. The integrated circuit model verification method according to claim 1, wherein The standard format file includes the formatted output of key parameters.

7. The integrated circuit model verification method according to claim 1, characterized in that Before parsing the parameters in the model library, it further includes: Constructing the script, which includes a first script for parsing the parameters in the model library, a second script for automatically generating a simulation configuration file, a third script for batch generating netlist files according to the simulation configuration file, a fourth script for generating a standard format file, and a fifth script for automatically comparing the standard format files generated by different simulators.

8. An integrated circuit model verification system, characterized in that Including: A parameter configuration layer for parsing the parameters in the model library through a script and automatically extracting the model parameters required for verification, obtaining the standard configuration file format, and loading the model parameters into the standard configuration file to generate a simulation configuration file; A netlist generation and simulation layer for obtaining the netlist file formats required by different simulators and batch generating netlist files adapted to different simulators containing output instructions according to the simulation configuration file, invoking each simulator to execute the corresponding netlist file for simulation, and outputting intermediate files; A data processing layer for parsing the numerical data in the intermediate file and generating a standard format file; An output and verification layer for comparing the standard format files generated by different simulators to obtain the verification result.

9. A computer device, comprising a memory, a processor, and a computer program stored on the memory, characterized in that, The processor executes the computer program to implement the steps of the integrated circuit model verification method according to any one of claims 1-7.

10. A computer storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instruction is executed by the processor, the steps of the integrated circuit model verification method according to any one of claims 1-7 are implemented.

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