Integrated circuit process deviation sensitivity analysis method, device, equipment and medium

Abstract

The present application provides a method, device, equipment and medium for analyzing the sensitivity of integrated circuit process deviation, including: N The invention relates to a method for performing random sampling to obtain a sampling matrix of process deviation variables; performing circuit simulation based on the sampling matrix to obtain a corresponding circuit performance vector, and forming a data set with the sampling matrix and the circuit performance vector; constructing a circuit performance parameter model based on the sampling matrix and the circuit performance vector; merging the effects of random process deviation variables belonging to the same device on circuit performance to evaluate the effects of each device on circuit performance and identify the key devices with the greatest impact on circuit performance. The embodiment of the present application can efficiently complete the sensitivity analysis of the high-dimensional process deviation space while ensuring the accuracy of the analysis, and accurately identify the key devices with the greatest impact on circuit performance, thereby facilitating the optimization of circuit design.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an integrated circuit process deviation sensitivity analysis method, device, equipment and medium. Background Art

[0002] In the design and manufacturing of integrated circuits, as process nodes enter the nanometer scale, process deviations have an increasingly greater impact on circuit performance, which directly affects chip reliability and yield. Especially in large-scale integrated circuits, a small cell failure may cause the failure of the entire system. For example, for an SRAM (static random access memory) array containing millions of cells, the failure rate of any single cell must be extremely low (typically 10 -6 ) to ensure the normal operation of the entire array. In this context, it is particularly important to establish an accurate and efficient process variation sensitivity analysis method. It is not only a necessary means to evaluate circuit robustness, but also an important basis for optimizing design margins and improving chip yield.

[0003] The finite difference method, which is currently widely used in process deviation sensitivity analysis, has significant limitations. This method is based on the principle of numerical differentiation. It calculates the sensitivity coefficient by applying a small perturbation to a single process parameter and observing the change in circuit response. It requires 2n simulations to complete the first-order sensitivity analysis of n parameters. Therefore, the computational efficiency of this method will deteriorate sharply in high-dimensional parameter space. For modern large-scale integrated circuit design, the number of simulations required for this method will increase linearly, causing the computational cost to become unaffordable. In addition, this method uses an isolated parameter perturbation strategy and is completely unable to capture the complex coupling effects between process parameters, which makes its analysis results often significantly deviate from the actual situation at nanoscale process nodes. Summary of the Invention

[0004] The purpose of this application is to provide an integrated circuit process deviation sensitivity analysis method, device, equipment and medium, which can efficiently complete the sensitivity analysis of high-dimensional process deviation space while ensuring analysis accuracy, and accurately identify the key components that have the greatest impact on circuit performance, thereby optimizing circuit design.

[0005] In order to solve the above technical problems, the embodiment of the present application provides an integrated circuit process deviation sensitivity analysis method, comprising: performing a process deviation analysis on the process deviation variables corresponding to all devices in the integrated circuit. Nrandom sampling to obtain a sampling matrix of process deviation variables; perform circuit simulation based on the sampling matrix to obtain a corresponding circuit performance vector, and form a data set with the sampling matrix and the circuit performance vector; construct a circuit performance parameter model based on the sampling matrix and the circuit performance vector; combine the effects of process deviation variables belonging to the same device on circuit performance to evaluate the effect of each device on circuit performance and identify the device with the greatest effect on circuit performance; wherein, evaluating the effect of each device on circuit performance includes: calculating the variance of each device on circuit performance based on the coefficients of the circuit performance parameter model to evaluate key devices, wherein the larger the variance value, the greater the effect of the corresponding device on circuit performance.

[0006] In one embodiment, constructing a circuit performance parameter model based on the sampling matrix and the circuit performance vector includes: normalizing the sampling matrix and the circuit performance vector, and constructing a circuit performance parameter model based on the normalized sampling matrix and circuit performance vector.

[0007] In one embodiment, the sampling matrix and the circuit performance vector are normalized, including: for each item in the circuit performance vector Perform normalization to obtain vector :

[0008]

[0009] in and represent the minimum and maximum values ​​of all items in the circuit performance vector, respectively, ;

[0010] At the same time, each column in the sampling matrix is ​​normalized to obtain a matrix under the standard normal distribution:

[0011]

[0012] in, Represents the first m List, Represents the first in the normalized sampling matrix m List, is the mean, is the standard deviation.

[0013] In one embodiment, constructing a circuit performance parameter model based on the sampling matrix and the circuit performance vector includes: using an orthogonal matching pursuit (OMP) algorithm to iteratively select key features and solve linear equations to construct the circuit performance parameter model.

[0014] In one embodiment, N random samples are taken of the process deviation variables corresponding to all devices in the integrated circuit according to a standard normal distribution.

[0015] In one embodiment, the process deviation variables corresponding to all devices in the integrated circuit can be expressed as M-dimensional independent random variables ,in are independent of each other and satisfy the mean , the standard deviation is The normal distribution of .

[0016] The present application also provides an integrated circuit process deviation sensitivity analysis device, comprising:

[0017] Sampling module, which measures the process deviation variables corresponding to all devices in the integrated circuit. N times random sampling to obtain the sampling matrix of process deviation variables;

[0018] a data construction module, performing circuit simulation according to the sampling matrix to obtain a corresponding circuit performance vector, and forming a data set with the sampling matrix and the circuit performance vector;

[0019] A model building module, which builds a circuit performance parameter model based on the sampling matrix and the circuit performance vector;

[0020] The evaluation module combines the effects of process deviation variables belonging to the same device on circuit performance to evaluate the impact of each device on circuit performance.

[0021] Identification module to identify the key components that have the greatest impact on circuit performance;

[0022] The evaluation of the impact of each device on circuit performance includes:

[0023] The variance of each device on the circuit performance is calculated based on the coefficients of the circuit performance parameter model to evaluate key devices, wherein the larger the variance value, the greater the impact of the corresponding device on the circuit performance.

[0024] An embodiment of the present application also provides an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the processor implements the steps of the above-mentioned integrated circuit process deviation sensitivity analysis method when executing the computer program.

[0025] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the above-mentioned integrated circuit process deviation sensitivity analysis method are implemented.

[0026] The embodiment of the present application is based on the principle of sparsity modeling, and uses a finite number of simulation points to quickly construct a circuit performance parameter model between circuit performance and process deviation variables. At the same time, multiple process deviation variables of the same device are merged, which can effectively identify key components that have a significant impact on circuit performance, so that key component parameters can be optimized in a targeted manner, providing a reliable basis for circuit optimization, thereby improving product reliability and overall performance, and is particularly suitable for handling complex integrated circuit sensitivity analysis problems under high-dimensional process deviation conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0028] Figure 1 is a flow chart of a method for analyzing sensitivity of integrated circuit process variations according to one embodiment of the present application;

[0029] Figure 2 is a flow chart of constructing a circuit performance parameter model according to one embodiment of the present application;

[0030] Figure 3 1 is a schematic structural diagram of an integrated circuit process deviation sensitivity analysis device according to one embodiment of the present application;

[0031] Figure 4 It is a structural diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of this application.

[0033] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0034] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0035] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples, however, one skilled in the art will appreciate that the examples can be practiced without these specific details.

[0036] Currently, in the field of integrated circuit design, in order to improve design accuracy and reduce costs, researchers have proposed a variety of new methods to accurately assess the reliability of large-scale integrated circuits, such as applying machine learning to process variation modeling. However, these methods still have significant limitations: they either fail to fully utilize the device-level correlation characteristics between process variables or lack an effective mechanism to identify key influencing factors in the high-dimensional parameter space. In current integrated circuit design practice, how to efficiently complete sensitivity analysis in the high-dimensional process variation space while ensuring analysis accuracy and accurately identify the key components that have the greatest impact on circuit performance remains an important technical challenge that needs to be solved.

[0037] Based on this, the embodiment of the present application proposes a method for analyzing the sensitivity of integrated circuit process deviation, the process of which is as follows: Figure 1 As shown in , the details are as follows:

[0038] In step 101, the process deviation variables corresponding to all devices in the integrated circuit are analyzed. N times random sampling to obtain the sampling matrix of process deviation variables.

[0039] Assume that the integrated circuit contains D Device, d Devices are recorded as . It is also assumed that the device contains process deviation variables. Then the total number of random process deviation variables in the entire integrated circuit is In an optional embodiment, the process deviation variables corresponding to all devices in these integrated circuits can be expressed as M dimensional independent random variables ,in are independent of each other and satisfy the mean , the standard deviation is The normal distribution of In addition, if divided according to the device, x It can also be expressed as , the mean of the corresponding variable can be expressed as , the standard deviation is .

[0040] After adopting the normally distributed independent variable, the sampling standard can be set according to the preset N Specifically, for each variable in the random variable x, , based on the known mean , the standard deviation is The normal distribution N Random sampling is performed to obtain the sampling matrix of process deviation variables .

[0041] By using normally distributed random variables to characterize process deviation variables and performing sampling based on the normal distribution, the relationship between actual process conditions and circuit performance can be accurately reflected in high-dimensional parameter space, making it easier to apply modeling in the design of various integrated circuits.

[0042] In step 102, a circuit simulation is performed based on the sampling matrix to obtain a corresponding circuit performance vector, and the sampling matrix and the circuit performance vector constitute a data set. , the circuit performance vectors of the integrated circuits corresponding to these samples can be obtained through circuit simulation .

[0043] Since the sample data can preliminarily represent a large number of process parameters in integrated circuits, these sample data and circuit performance data can be used to form the sample set (i.e., data set) required for model training.

[0044] In step 103, a circuit performance parameter model is constructed based on the sampling matrix and the circuit performance vector.

[0045] In an optional embodiment, in order to make the training model more accurate, the sampling matrix can be first

[0046] and the circuit performance vector The data is normalized, and the normalization method is as follows:

[0047] For each item in the circuit performance vector y Perform normalization to obtain vector :

[0048] (1)

[0049] in and Respectively represent the minimum and maximum values ​​of all items in vector y, .

[0050] At the same time, normalize each column in the sampling matrix X to obtain the matrix under the standard normal distribution :

[0051] (2)

[0052] in, represents the mth column in matrix X, Representation matrix The m List, , is the mean, is the standard deviation.

[0053] In this embodiment, a method for data normalization is provided. However, other methods can also be used in actual applications and are not limited in the embodiments of this application. By normalizing data, data of different dimensions and orders of magnitude can be converted to the same scale, eliminating the dimensional effects between data features, facilitating comprehensive comparative evaluation, and thus improving model performance and training efficiency.

[0054] After the data is normalized, a circuit performance parameter model can be constructed based on the normalized sampling matrix and the circuit performance vector.

[0055] In an optional embodiment, an orthogonal matching pursuit (OMP) algorithm can be used to construct a circuit performance parameter model by iteratively selecting key features and solving linear equations. With the matrix The circuit performance parameter model is constructed by the orthogonal matching pursuit (OMP) algorithm. The process is referenced Figure 2 , the steps are as follows:

[0056] In step 1031: initialize the model residual vector r = , initialize the collection SIt is empty and is used to store the index of the selected feature. The initial length is M +1 characteristic coefficient vector is a zero vector, where M The first characteristic coefficient corresponds to the process deviation variable, and the last characteristic coefficient corresponds to the constant term in the model. and the maximum number of iterations .

[0057] In step 1032: In the matrix Add a column of unit vectors on the right (corresponding to the last item in the characteristic coefficient vector) to get the expanded matrix .

[0058] In step 1033: calculate the expansion matrix Each column (Right now No. j The inner product of the column) and the current residual r c j :

[0059] (3)

[0060] In step 1034: the absolute value of the inner product The index corresponding to the maximum value Add to the set S. It should be noted that if this step is performed for the first time, the index M +1 added to the collection S In the first iteration, the constant item must be selected; in other cases, the index corresponding to the maximum value of the absolute value of the inner product is added to the set S .

[0061] In step 1035: From the expansion matrix Extract the feature columns corresponding to all indexes in the set S to form a matrix Solve the following linear equation to obtain the corresponding characteristic coefficients :

[0062] (4)

[0063] In step 1036: Update the residual:

[0064] (5)

[0065] In step 1037: determine whether the L2 norm of the residual r is less than a given threshold , or whether the number of iterations is greater than or equal to , if the L2 norm of the residual r is less than the given threshold , or the number of iterations is greater than or equal to , then go to step 1038, otherwise repeat steps 1032-1037.

[0066] In step 1038, the current model coefficients are output .

[0067] according to Reconstructed model coefficients , where the index is in the collection S The values ​​of the items in are given by The corresponding items in are determined, and the values ​​of other items are 0. It can be expressed as , is the normalized model coefficient, c is the coefficient of the constant term. The resulting linear model can be expressed as follows:

[0068] (6)

[0069] is a vector The m item. f(x) is the circuit performance index, which can be obtained after sorting:

[0070] (7)

[0071] in C is a constant term:

[0072] (8)

[0073] Through the above steps, a model with process deviation as input and circuit performance index as output can be constructed. In this embodiment, the construction of the circuit performance parameter model is illustrated by taking the orthogonal matching pursuit algorithm as an example. In other embodiments, the circuit performance parameter model of the present application can also be constructed by other common machine learning algorithms, such as neural networks, positive LASSO algorithms, etc. It should be noted that the process of the learning model constituted by these algorithms and the specific model form formed can be implemented with reference to the existing technology and will not be explained in detail here.

[0074] In step 104 , the effects of process variation variables belonging to the same device on circuit performance are combined to evaluate the effect of each device on circuit performance.

[0075] In the above description, it is assumed that the integrated circuit contains D Device, d Devices are recorded as , assuming the device contains It is not difficult to know that in the circuit performance parameter model, the same device will correspond to multiple process deviation variables. In order to accurately evaluate the impact of each device on the circuit performance, it is necessary to combine the impact of multiple process deviation variables corresponding to the same device on the circuit performance. The method is as follows:

[0076] First, for the variables in formula (7) Grouping based on device, ,get:

[0077] (9)

[0078] in express The corresponding model coefficient. d devices The process deviation affects the circuit performance index f(x) The impact can be expressed as:

[0079] ,yes The sum of independent normally distributed random variables is also a normally distributed random variable with the following variance:

[0080] (10)

[0081] Then, by comparing You can evaluate the device d Impact on circuit performance.

[0082] In summary, the coefficients of the circuit performance parameter model can be , calculate the variance of each device's contribution to the circuit performance , wherein, the larger the variance value is, the greater the impact of the corresponding device on the circuit performance is, so as to evaluate the key devices.

[0083] In step 105, the device that has the greatest impact on circuit performance is identified. The impact of each device on circuit performance can be calculated using formula 10. value, and then all the corresponding Compare the values ​​and select The device with the largest value has the greatest impact on circuit performance.

[0084] Compared with the prior art, the embodiments of the present application are based on the principle of sparse modeling, and use a limited number of simulation points to quickly construct a circuit performance parameter model between circuit performance and process deviation variables. At the same time, multiple process deviation variables of the same device are merged, which can effectively identify key components that have a significant impact on circuit performance, so that key component parameters can be optimized in a targeted manner. It is particularly suitable for processing complex integrated circuit sensitivity analysis problems under high-dimensional process deviation conditions. This method can efficiently and accurately complete circuit process deviation sensitivity analysis, and provide clear guidance for circuit design optimization by extracting key component information that has a significant impact on circuit performance. It also significantly improves calculation efficiency while ensuring analysis accuracy, provides a reliable basis for circuit optimization, and thus improves product reliability and overall performance.

[0085] Based on the same inventive concept, this application also provides an integrated circuit process deviation sensitivity analysis device. It should be noted that the device illustrated below is an example of a device corresponding to the above-mentioned method embodiment, and in other device embodiments, the configuration of unit module functions and the number of modules can be configured accordingly based on the above-mentioned method embodiment.

[0086] like Figure 3 As shown, the integrated circuit process deviation sensitivity analysis device includes:

[0087] Sampling module 1, which measures the process deviation variables corresponding to all devices in the integrated circuit. N times random sampling to obtain the sampling matrix of process deviation variables;

[0088] Data construction module 2, performs circuit simulation based on the sampling matrix to obtain the corresponding circuit performance vector, and forms a data set with the sampling matrix and the circuit performance vector;

[0089] Model building module 3, building a circuit performance parameter model based on the sampling matrix and the circuit performance vector;

[0090] Evaluation module 4 combines the effects of process deviation variables belonging to the same device on circuit performance to evaluate the effect of each device on circuit performance.

[0091] Identification module 5 identifies the key components that have the greatest impact on circuit performance.

[0092] Compared to the prior art, the present embodiment utilizes a finite number of simulation points based on the principle of sparse modeling to rapidly construct a circuit performance parameter model between circuit performance and process deviation variables. The evaluation module 4 then merges multiple process deviation variables for the same device and evaluates the impact of each device on circuit performance. This allows the identification module 5 to effectively identify key devices that significantly impact circuit performance, thereby enabling targeted optimization of key device parameters. This device efficiently and accurately performs circuit process deviation sensitivity analysis, providing clear guidance for circuit design optimization by extracting information about key devices that significantly impact circuit performance.

[0093] like Figure 4 As shown, an embodiment of the present application also provides an electronic device, including a processor 6, a memory 7, and a computer program stored in the memory 7 and capable of running on the processor 6. When the processor 6 executes the computer program, the steps of the above-mentioned integrated circuit process deviation sensitivity analysis method are implemented.

[0094] The electronic device in the embodiment of the present application includes at least one processor 6 and a memory 7 in communication with the at least one processor 6. Figure 4 A processor 6 is used as an example for description.

[0095] The electronic device may further include: an input device 8 and an output device 9 .

[0096] The processor 6, memory 7, input device 8 and output device 9 may be connected via a bus or other means. Figure 4 The bus connection is taken as an example.

[0097] The memory 7 is a non-transitory computer-readable storage medium that can be used to store non-transitory software programs, non-transitory computer executable programs and modules, such as the program instructions / modules corresponding to the integrated circuit process deviation sensitivity analysis method in the embodiment of the present application (for example, the attached Figure 3 The processor 6 executes the non-transitory software programs, instructions, and modules stored in the memory 7 to execute various functional applications and data processing of the server, thereby implementing the integrated circuit process variation sensitivity analysis method in the above method embodiment.

[0098] The memory 7 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created by the use of the processing device according to the list item operation, etc. In addition, the memory 7 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 7 may optionally include a memory remotely located relative to the processor 6, and these remote memories may be connected to the processor 6 for the integrated circuit process deviation sensitivity analysis method via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0099] The input device 8 can receive input digital or character information and generate key signal input related to user settings and function control of the processing device for list item operations. The output device 9 can include a display device such as a display screen.

[0100] In this embodiment, when one or more modules stored in the memory 7 are executed by the one or more processors 6 , the processor 6 executes the integrated circuit process deviation sensitivity analysis method in any of the above method embodiments.

[0101] The above-mentioned product can execute the method provided in the embodiment of this application, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not fully described in this embodiment, please refer to the method provided in the embodiment of this application.

[0102] The electronic devices according to the embodiments of the present invention may be implemented in various forms, including but not limited to:

[0103] (1) Mobile communication devices: These devices are characterized by their mobile communication capabilities and are primarily designed to provide voice and data communications. These terminals include smartphones (e.g., iPhones), multimedia phones, feature phones, and low-end phones.

[0104] (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, have computing and processing capabilities, and generally also have mobile Internet access. These terminals include PDAs, MIDs, and UMPCs, such as the iPad.

[0105] (3) Portable entertainment devices: These devices can display and play multimedia content. These devices include audio and video players (such as iPods), handheld game consoles, e-books, smart toys, and portable car navigation devices.

[0106] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the integrated circuit process deviation sensitivity analysis method described in any embodiment of the present application are implemented.

[0107] It should be noted that the computer storage medium may include, but is not limited to, a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device, or any suitable combination thereof. In a possible embodiment, the present invention may also provide a method of implementing data processing in the form of a program product, which includes program code. When the program product is executed on a terminal device, the program code is used to cause the terminal device to perform several steps of the method described in any of the aforementioned embodiments.

[0108] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A method for analyzing sensitivity of integrated circuit process deviation, characterized in that: include: The process deviation variables corresponding to all devices in the integrated circuit are analyzed. N times random sampling to obtain the sampling matrix of process deviation variables; Perform circuit simulation according to the sampling matrix to obtain a corresponding circuit performance vector, and form a data set with the sampling matrix and the circuit performance vector; Constructing a circuit performance parameter model based on the sampling matrix and the circuit performance vector; Combine the effects of process deviation variables belonging to the same device on circuit performance to evaluate the impact of each device on circuit performance. Identify the components that have the greatest impact on circuit performance; The evaluation of the impact of each device on circuit performance includes: The variance of each device on the circuit performance is calculated based on the coefficients of the circuit performance parameter model to evaluate key devices, wherein the larger the variance value, the greater the impact of the corresponding device on the circuit performance.

2. The integrated circuit process variation sensitivity analysis method according to claim 1, wherein: The constructing of a circuit performance parameter model based on the sampling matrix and the circuit performance vector includes: performing normalization processing on the sampling matrix and the circuit performance vector, A circuit performance parameter model is constructed based on the normalized sampling matrix and circuit performance vector.

3. The integrated circuit process variation sensitivity analysis method according to claim 2, wherein: The normalizing process of the sampling matrix and the circuit performance vector includes: For each term in the circuit performance vector Perform normalization to obtain vector : in, and represent the minimum and maximum values ​​of all items in the circuit performance vector, respectively, ; At the same time, each column in the sampling matrix is ​​normalized to obtain a matrix under the standard normal distribution: in, Represents the first m List, Represents the first in the normalized sampling matrix m List, , is the mean, is the standard deviation.

4. The integrated circuit process variation sensitivity analysis method according to claim 1, wherein: The circuit performance parameter model is constructed based on the sampling matrix and the circuit performance vector, including: using an orthogonal matching pursuit (OMP) algorithm to iteratively select key features and solve linear equations to construct the circuit performance parameter model.

5. The integrated circuit process variation sensitivity analysis method according to claim 1, wherein: According to the standard normal distribution, the process deviation variables corresponding to all devices in the integrated circuit are analyzed. N Random sampling times.

6. The integrated circuit process variation sensitivity analysis method according to claim 1, wherein: The process deviation variables corresponding to all devices in the integrated circuit can be expressed as M dimensional independent random variables ,in are independent of each other and satisfy the mean , the standard deviation is The normal distribution of .

7. An integrated circuit process deviation sensitivity analysis device, characterized in that: include: Sampling module, which measures the process deviation variables corresponding to all devices in the integrated circuit. N times random sampling to obtain the sampling matrix of process deviation variables; a data construction module, performing circuit simulation according to the sampling matrix to obtain a corresponding circuit performance vector, and forming a data set with the sampling matrix and the circuit performance vector; A model building module, which builds a circuit performance parameter model based on the sampling matrix and the circuit performance vector; The evaluation module combines the effects of process deviation variables belonging to the same device on circuit performance to evaluate the impact of each device on circuit performance. Identification module to identify the key components that have the greatest impact on circuit performance; The evaluation of the impact of each device on circuit performance includes: The variance of each device on the circuit performance is calculated based on the coefficients of the circuit performance parameter model to evaluate key devices, wherein the larger the variance value, the greater the impact of the corresponding device on the circuit performance.

8. An electronic device comprising a processor, a memory, and a computer program stored in the memory and capable of running on the processor, characterized in that: When the processor executes the computer program, the steps of the integrated circuit process variation sensitivity analysis method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the integrated circuit process variation sensitivity analysis method according to any one of claims 1 to 6 are implemented.

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