Memristor synapse array supporting online learning of spiking neural networks

Abstract

The application relates to a memristor synapse array supporting online learning of a pulse neural network, comprising n*k*i 2T2R units, the memristor synapse array being composed of k subarrays SubArray, each subarray SubArray comprising n 2T2R unit blocks Block, and each 2T2R unit block Block comprising i 2T2R units; the peripheral circuit of each subarray SubArray and the 2T2R unit blocks Block in the subarray SubArray form i word line signal ends WL, i / 2 bias signal ends SL, 1 pair of reverse inference signal ends INB and inference signal ends INF, n pairs of enable signal ends RWP and enable signal ends RWN, n pairs of weight output ends IBLP and weight output ends IBLN, and n pairs of bit line signal ends ABLP and bit line signal ends ABLN; and the peripheral circuit of the 2T2R unit block Block comprises two pairs of NMOS tubes mpi0 and mni0 and mpa0 and mna0 outside the 2T2R unit block Block. Compared with the prior art, the application has the advantages of reducing related power consumption overheads and the like.

Description

Technical Field

[0001] This invention relates to the technical field of memristor synaptic arrays, and in particular to a memristor synaptic array that supports online learning of spiking neural networks. Background Technology

[0002] Driven by high-performance computing models, traditional silicon-based semiconductors, due to physical limitations, cannot meet the demands for high computational and storage densities. In recent years, with the development of related technologies, the number of parameters required for large-scale model computations has reached hundreds of billions, widening the gap between model iterations and computational power expansion. Even with state-of-the-art hardware, training ultra-large-scale models faces immense computational pressure. Simultaneously, as model size increases, the computing power of a single chip, constrained by the limitations of traditional semiconductor processes, can no longer meet the demands. The industry has had to adopt distributed training and multi-chip interconnect strategies to complete large-scale model computations. This results in significant energy consumption on the hardware side during training, especially for high-performance computing devices such as GPUs and TPUs, which generate high power consumption and carbon emissions. Therefore, to ensure sufficient chip computational capacity while reducing computational load and power consumption, the industry has proposed two approaches: firstly, lower computational overhead network models, such as spiking neural networks that better fit biological behavioral mechanisms and are more hardware-friendly; secondly, the concept of designing dedicated computing chips to alleviate the "memory wall" and "power wall" problems. Among these, some research teams have pioneered a path combining novel multi-valued memristor memories with in-memory computing.

[0003] Integrating spiking neural networks with memristor-based in-memory computing chips might alleviate computational bottlenecks in end-user applications to some extent. However, many problems remain to be solved in practical deployments. In spiking neural networks, memristors typically serve as the carriers of network weights, representing the connection strength between different neurons. However, during on-chip training, the industry generally still uses traditional static random access memory (SRAM), which requires charging and discharging long-line parasitic capacitances, increasing hardware overhead and data transmission power consumption, thus limiting system bandwidth and latency. Summary of the Invention

[0004] The purpose of this invention is to provide a memristor synapse array that supports online learning of spiking neural networks in order to reduce related power consumption overhead.

[0005] The objective of this invention can be achieved through the following technical solutions:

[0006] A memristor synaptic array that supports online learning of spiking neural networks includes n*k*i 2T2R units. The memristor synaptic array is composed of k subarrays, each subarray includes n 2T2R unit blocks, and each 2T2R unit block includes i 2T2R units.

[0007] Each subarray and its 2T2R cell block form i word line signal terminals WL, i / 2 bias signal terminals SL, 1 pair of inverse inference signal terminals INB and inference signal terminals INF, n pairs of enable signal terminals RWP and enable signal terminals RWN, n pairs of weight output terminals IBLP and weight output terminals IBLN, and n pairs of bit line signal terminals ABLP and bit line signal terminals ABLN.

[0008] The peripheral circuit of the 2T2R unit block includes two pairs of NMOS transistors mpi0 and mni0, and mpa0 and mna0 on the outside of the 2T2R unit block.

[0009] Furthermore, in the peripheral circuit of the a-th 2T2R unit block, one end of the NMOS transistor mpi0 is connected to the bit line signal terminal ABLP[a], one end of the NMOS transistor mpa0 and the other end of the NMOS transistor mpi0 are connected to the bit line terminal BL1 of the 2T2R unit, the gate of the NMOS transistor mpi0 is connected to the first CMOS transmission gate tgp0, and the other end of the NMOS transistor mpa0 is connected to the a-th weight output terminal IBLP[a].

[0010] Furthermore, in the peripheral circuit of the a-th 2T2R unit block, one end of the NMOS transistor mni0 is connected to the bit line signal terminal ABLN[a], one end of the NMOS transistor mna0 and the other end of the NMOS transistor mni0 are connected to the bit line terminal BL2 of the 2T2R unit, the gate of the NMOS transistor mni0 is connected to the second CMOS transmission gate tgn0, and the other end of the NMOS transistor mna0 is connected to the a-th weight output terminal IBLN[a].

[0011] Furthermore, in the a-th 2T2R cell block, the gates of NMOS transistor mpa0 and NMOS transistor mna0 are connected and together connected to the inference signal terminal INF.

[0012] Furthermore, the 2T2R unit includes two 2T2R structures, one above the other. The source lines of the two 2T2R structures are interconnected. The bit lines BL1 on the same side of the two 2T2R structures are interconnected, and the bit lines BL2 on the same side of the two 2T2R structures are interconnected. At the same time, the bit lines BL1 on the same side of each 2T2R unit are interconnected, and the bit lines BL2 on the same side of each 2T2R unit are interconnected. The 2T2R structure includes a positive unit memristor and a negative unit memristor.

[0013] Furthermore, in a 2T2R cell block, the word line terminal of one 2T2R cell is connected to the word line signal terminal WL[2b-2], the word line terminal of the other 2T2R cell is connected to the word line signal terminal WL[2b-1], and the source line terminals of the b-th 2T2R cell are connected together to the bias signal terminal SL[b-1], where b = 1, 2, ..., i / 2.

[0014] Furthermore, the first CMOS transmission gate tgp0 of the a-th 2T2R cell block is connected to the a-th enable signal terminal RWP[a-1], the second CMOS transmission gate tgn0 of the a-th 2T2R cell block is connected to the a-th enable signal terminal RWN[a-1], and the first CMOS transmission gate tgp0 and the second CMOS transmission gate tgn0 are connected together to the reverse inference signal terminal INB.

[0015] The present invention also proposes a control method for a memristor synaptic array that supports online learning of spiking neural networks. The method is characterized by employing the aforementioned memristor synaptic array and includes a memristor synaptic array training part and an inference part.

[0016] The reasoning section includes:

[0017] When the network inference current is received, the NMOS transistors mpi0 and mni0 in all subarrays are turned off; the NMOS transistors mpa0 and mna0 are turned on. The current flows from the bias signal terminal SL through each 2T2R unit and is collected at the weight output terminals IBLP and IBLN. The current at the weight output terminals IBLP and IBLN is added or subtracted to complete the reading of the positive and negative weights of the network.

[0018] The training section includes:

[0019] The inference signal terminal INF in the 2T2R cell block that needs to be trained is turned off. For the training of the positive cell memristor of the upper 2T2R structure in the b-th 2T2R cell of the a-th 2T2R cell block that needs to be trained in the SubArray, the training operation of the positive cell memristor is determined by turning on the word line signal terminal WL[2b-2] and the enable signal terminal RWP[a-1] based on the relative potential of the bit line signal terminal ABLP[a] of the a-th 2T2R cell block and the bias signal terminal SL[b-1] of the b-th 2T2R cell of the a-th 2T2R cell block.

[0020] For training the negative cell memristor of the upper 2T2R structure in the bth 2T2R cell of the ath 2T2R cell block in the SubArray, the training operation of the positive cell memristor is determined by turning on the word line signal terminal WL[2b-2] and the enable signal terminal RWN[a-1] based on the relative potential of the bit line signal terminal ABLN[a] of the ath 2T2R cell block and the bias signal terminal SL[b-1] of the bth 2T2R cell of the ath 2T2R cell block.

[0021] For the training of the positive cell memristor of the lower 2T2R structure in the bth 2T2R cell of the ath 2T2R cell block in the SubArray, the training operation of the positive cell memristor is determined by turning on the word line signal terminal WL[2b-1] and the enable signal terminal RWP[a-1], based on the relative potential of the bit line signal terminal ABLP[a] of the ath 2T2R cell block and the bias signal terminal SL[b-1] of the bth 2T2R cell of the ath 2T2R cell block.

[0022] For training the negative cell memristor of the lower 2T2R structure in the bth 2T2R cell of the ath 2T2R cell block in the SubArray, the training operation of the positive cell memristor is determined by turning on the word line signal terminal WL[2b-1] and the enable signal terminal RWN[a-1], based on the relative potential of the bit line signal terminal ABLN[a] of the ath 2T2R cell block and the bias signal terminal SL[b-1] of the bth 2T2R cell of the ath 2T2R cell block.

[0023] Furthermore, the training operation of the memristor is determined based on the relative potential, which includes: performing a set operation when a positive voltage is applied to the top terminal of the memristor (that is, the end of the memristor that is not directly connected to the corresponding 2T2R internal transistor), and writing the device as a low-impedance state; and performing a reset operation when a positive voltage is applied to the bottom terminal of the memristor (that is, the end of the memristor that is directly connected to the corresponding 2T2R internal transistor), and writing the device as a high-impedance state.

[0024] Furthermore, in the inference section, in the resting state before receiving the network inference current, all inference signal terminals INF are enabled, and all bias signals SL also maintain their own inference voltage.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] This invention employs a synaptic array structure with array partitioning and transmission path separation, which meets the low-power online learning requirements of spiking neural networks. It allows access to any unit while reducing the power consumption of weight operations. The word line signal WL and bias signal SL arranged in the row direction ensure parallel computation of the synaptic array. The added computation transistors within each unit block—two pairs of NMOS transistors mpi0 and mni0, and mpa0 and mna0—avoid charging and discharging operations on long-line parasitic capacitances under flexible switching control, reducing related power consumption. This allows for dedicated optimization of peripheral circuits for weight inference and weight updates, while also enabling access and programming of each unit in the column direction, thus providing a complete hardware foundation for online learning of neural networks. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of the present invention;

[0028] Figure 2 This refers to the relevant node voltage waveform of a single memristor representing a negative weight during network operation, specifically during weight reading and weight update states. Detailed Implementation

[0029] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are based on the technical solution of the present invention and provide detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0030] This invention proposes a memristor synaptic array that supports online learning of spiking neural networks, as shown in the structural diagram below. Figure 1 As shown. It includes n*k*i 2T2R units. The memristor synapse array consists of k subarrays. Each subarray includes n 2T2R unit blocks, and each 2T2R unit block includes i 2T2R units.

[0031] Each subarray and its 2T2R cell block form i word line signal terminals WL, i / 2 bias signal terminals SL, 1 pair of inverse inference signal terminals INB and inference signal terminals INF, n pairs of enable signal terminals RWP and enable signal terminals RWN, n pairs of weight output terminals IBLP and weight output terminals IBLN, and n pairs of bit line signal terminals ABLP and bit line signal terminals ABLN.

[0032] The peripheral circuit of the 2T2R unit block includes two pairs of NMOS transistors mpi0 and mni0, and mpa0 and mna0 on the outside of the 2T2R unit block.

[0033] In the peripheral circuit of the a-th 2T2R unit block, one end of NMOS transistor mpi0 is connected to the bit line signal terminal ABLP[a], one end of NMOS transistor mpa0 and the other end of NMOS transistor mpi0 are connected to the bit line terminal BL1 of the 2T2R unit, the gate of NMOS transistor mpi0 is connected to the first CMOS transmission gate tgp0, and the other end of NMOS transistor mpa0 is connected to the a-th weight output terminal IBLP[a].

[0034] In the peripheral circuit of the a-th 2T2R unit block, one end of the NMOS transistor mni0 is connected to the bit line signal terminal ABLN[a], one end of the NMOS transistor mna0 and the other end of the NMOS transistor mni0 are connected to the bit line terminal BL2 of the 2T2R unit, the gate of the NMOS transistor mni0 is connected to the second CMOS transmission gate tgn0, and the other end of the NMOS transistor mna0 is connected to the a-th weight output terminal IBLN[a].

[0035] In the a-th 2T2R cell block, the gates of NMOS transistors mpa0 and mna0 are connected and together connected to the inference signal terminal INF.

[0036] The 2T2R unit includes two 2T2R structures, one above the other. The source lines of the two 2T2R structures are connected to each other. The bit lines BL1 on the same side of the two 2T2R structures are connected to each other, and the bit lines BL2 on the same side of the two 2T2R structures are connected to each other. At the same time, the bit lines BL1 on the same side of each 2T2R unit are connected to each other, and the bit lines BL2 on the same side of each 2T2R unit are connected to each other. The 2T2R structure includes a positive unit memristor and a negative unit memristor.

[0037] In a 2T2R cell block, the word line terminal of one 2T2R cell is connected to the word line signal terminal WL[2b-2], and the word line terminal of the other 2T2R cell is connected to the word line signal terminal WL[2b-1]. The source line terminals of the b-th 2T2R cell are connected together to the bias signal terminal SL[b-1], where b = 1, 2, ..., i / 2.

[0038] The first CMOS transmission gate tgp0 of the a-th 2T2R cell block is connected to the a-th enable signal terminal RWP[a-1], the second CMOS transmission gate tgn0 of the a-th 2T2R cell block is connected to the a-th enable signal terminal RWN[a-1], and the first CMOS transmission gate tgp0 and the second CMOS transmission gate tgn0 are connected together to the reverse inference signal terminal INB.

[0039] This invention also proposes a control method for a memristor synaptic array that supports online learning of spiking neural networks. The method uses the aforementioned memristor synaptic array and includes a memristor synaptic array training part and an inference part.

[0040] The reasoning section includes:

[0041] When the network inference current is received, the NMOS transistors mpi0 and mni0 in all subarrays are turned off; the NMOS transistors mpa0 and mna0 are turned on. The current flows from the bias signal terminal SL through each 2T2R unit and is collected at the weight output terminals IBLP and IBLN. The current at the weight output terminals IBLP and IBLN is added or subtracted to complete the reading of the positive and negative weights of the network.

[0042] The training section includes:

[0043] The inference signal terminal INF in the 2T2R cell block that needs to be trained is turned off. For the training of the positive cell memristor of the upper 2T2R structure in the b-th 2T2R cell of the a-th 2T2R cell block that needs to be trained in the SubArray, the training operation of the positive cell memristor is determined by turning on the word line signal terminal WL[2b-2] and the enable signal terminal RWP[a-1] based on the relative potential of the bit line signal terminal ABLP[a] of the a-th 2T2R cell block and the bias signal terminal SL[b-1] of the b-th 2T2R cell of the a-th 2T2R cell block.

[0044] For training the negative cell memristor of the upper 2T2R structure in the bth 2T2R cell of the ath 2T2R cell block in the SubArray, the training operation of the positive cell memristor is determined by turning on the word line signal terminal WL[2b-2] and the enable signal terminal RWN[a-1] based on the relative potential of the bit line signal terminal ABLN[a] of the ath 2T2R cell block and the bias signal terminal SL[b-1] of the bth 2T2R cell of the ath 2T2R cell block.

[0045] For training the positive cell memristor of the lower 2T2R structure in the bth 2T2R cell of the ath 2T2R cell block in the SubArray, the training operation of the positive cell memristor is determined based on the relative potentials of the bit line signal terminal ABLP[a] of the ath 2T2R cell block and the bias signal terminal SL[b-1] of the bth 2T2R cell of the ath 2T2R cell block by turning on the word line signal terminal WL[2b-1] and the enable signal terminal RWP[a-1].

[0046] For training the negative cell memristor of the lower 2T2R structure in the bth 2T2R cell of the ath 2T2R cell block in the SubArray, the training operation of the positive cell memristor is determined by turning on the word line signal terminal WL[2b-1] and the enable signal terminal RWN[a-1], based on the relative potential of the bit line signal terminal ABLN[a] of the ath 2T2R cell block and the bias signal terminal SL[b-1] of the bth 2T2R cell of the ath 2T2R cell block.

[0047] This invention proposes a multi-valued memristor synaptic array that supports online learning of spiking neural networks. By enabling different gates, the array can perform on-chip spiking neural network inference and training, and can also optimize the transmission paths for network inference and weight update operations. In addition, the introduced macrocell partitioning scheme helps to reduce parasitic parameters in the memristor operation process, thereby reducing the energy consumption of neural network inference.

[0048] The memristor synaptic array consists of n*k*i 2T2R units, with each i rows of 2T2R units forming a subarray. Each subarray contains n columns of 2T2R unit blocks. To reduce the performance overhead of on-chip training and the impact on network inference, each unit block is designed with a set of computing transistors to assist in the on-chip training and inference of the spiking neural network. Finally, each subarray and the peripheral circuit form i WL, i / 2 SL, 1 pair of INB and INF, n pairs of RWP and RWN, n pairs of IBLP and IBLN, and n pairs of ABLP and ABLN interface signals. The read and write operations of the corresponding memristors are controlled by their respective word line signals WL (memristors rp0 and rn0 are enabled by WL[0]; memristors rp1 and rn1 are enabled by WL[1]). The read and write current of the memristor unit is transmitted through two pairs of NMOS transistors on the outside (mpi0 and mni0; mpa0 and mna0).

[0049] During neural network inference, the selectors mpi0 and mni0 in all subarrays are in the off state; the selectors mpa0 and mna0 are in the on state. Current flows from the bias signal SL terminal, through the memristor, and converges at the IBLP and IBLN terminals. Combined with the arithmetic circuit module, the current at the IBLP and IBLN terminals is added or subtracted to complete the reading of the positive and negative weights of the network. During the neural network weight update process, the transistors mpa0 and mna0 in the selected subarray are in the off state, while those in the unselected subarray remain in the on state. The RWP and RWN signals in the column direction, in conjunction with the word line signal WL, can realize the access and write operations of the resistance state of a single device. The multi-value switching of the resistance state is controlled by the bias signal SL, the bit line signals ABLP and ABLN, and the gate voltage WL.

[0050] Control method: Since weight reading operations occupy the majority of the neural network's runtime, in the resting state, all inference signals INF are enabled, and all bias signals SL maintain their own inference voltages. Whenever an input pulse related to network inference arrives, simply enabling the word line signal WL is sufficient to immediately put the synaptic array into weight reading mode.

[0051] During network training, when memristor weights need to be updated, the selectors mpi0 and mni0, mpa0 and mna0 inside the unselected subarray maintain the state during weight reading, and their INF signals are also enabled to reduce power consumption during signal switching. The INF signal inside the selected subarray is turned off, and each memristor cell in the subarray is controlled by the word line signal WL and the read / write enable signals RWP and RWN: when WL[0] and RWP[0] are on, the relative potential of SL[0] and ABLP[0] determines whether a Reset or Set operation is performed on memristor rp0; when WL[0] and RWN[0] are on, the relative potential of SL[0] and ABLN[0] determines whether a Reset or Set operation is performed on memristor rn0. After each write operation is completed, the bias signal SL switches to a lower read voltage, ABLP or ABLN collects the current of the corresponding device, and determines whether to perform a write operation on the same cell again to ensure accurate update of the resistance state.

[0052] The synaptic array structure employing array partitioning and transmission path separation meets the low-power online learning requirements of spiking neural networks. The word line signal WL and bias signal SL arranged in the row direction ensure parallel computation of the synaptic array. The added computation transistors within each unit block, under flexible switching control, avoid charging and discharging operations on long-line parasitic capacitances, reducing related power consumption. This allows for dedicated optimization of peripheral circuits for weight inference and weight updates, while also enabling access and programming of each unit in the column direction, thus providing a complete hardware foundation for online learning of neural networks.

[0053] Because of the increased transmission path, some signals inside the array can remain in a fixed state for a long time after power-on, reducing the energy consumption introduced by parasitic parameters after each input pulse arrives, and effectively improving the network inference energy efficiency.

[0054] Figure 1 The structure diagram of a multi-valued memristor synaptic array based on online learning of a spiking neural network is given; Figure 2 The relevant node voltage waveforms of a single memristor representing a negative weight are presented during the weight reading and weight update states in the network operation.

[0055] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A memristor synaptic array supporting online learning of spiking neural networks, characterized in that, It includes n*k*i 2T2R units. The memristor synapse array is composed of k subarrays. Each subarray includes n 2T2R unit blocks, and each 2T2R unit block includes i 2T2R units. Each subarray and its 2T2R cell block form i word line signal terminals WL, i / 2 bias signal terminals SL, 1 pair of inverse inference signal terminals INB and inference signal terminals INF, n pairs of enable signal terminals RWP and enable signal terminals RWN, n pairs of weight output terminals IBLP and weight output terminals IBLN, and n pairs of bit line signal terminals ABLP and bit line signal terminals ABLN. The peripheral circuit of the 2T2R unit block includes two pairs of NMOS transistors mpi0 and mni0 and mpa0 and mna0 on the outside of the 2T2R unit block. In the peripheral circuit of the a-th 2T2R unit block, one end of NMOS transistor mpi0 is connected to the bit line signal terminal ABLP[a], one end of NMOS transistor mpa0 and the other end of NMOS transistor mpi0 are connected to the bit line terminal BL1 of the 2T2R unit, the gate of NMOS transistor mpi0 is connected to the first CMOS transmission gate tgp0, and the other end of NMOS transistor mpa0 is connected to the a-th weight output terminal IBLP[a]. In the peripheral circuit of the a-th 2T2R unit block, one end of NMOS transistor mni0 is connected to the bit line signal terminal ABLN[a], one end of NMOS transistor mna0 and the other end of NMOS transistor mni0 are connected to the bit line terminal BL2 of the 2T2R unit, the gate of NMOS transistor mni0 is connected to the second CMOS transmission gate tgn0, and the other end of NMOS transistor mna0 is connected to the a-th weight output terminal IBLN[a]. In the a-th 2T2R cell block, the gates of NMOS transistor mpa0 and mna0 are connected and together connected to the inference signal terminal INF; The 2T2R unit includes two 2T2R structures, one above the other. The source lines of the two 2T2R structures are connected to each other. The bit lines BL1 on the same side of the two 2T2R structures are connected to each other, and the bit lines BL2 on the same side of the two 2T2R structures are connected to each other. At the same time, the bit lines BL1 on the same side of each 2T2R unit are connected to each other, and the bit lines BL2 on the same side of each 2T2R unit are connected to each other. The 2T2R structure includes a positive memristor and a negative memristor. In a 2T2R cell block, the word line terminal of one 2T2R cell is connected to the word line signal terminal WL[2b-2], and the word line terminal of the other 2T2R cell is connected to the word line signal terminal WL[2b-1]. The source line terminals of the b-th 2T2R cell are connected together to the bias signal terminal SL[b-1], where b=1, 2, ..., i / 2; The first CMOS transmission gate tgp0 of the a-th 2T2R cell block is connected to the a-th enable signal terminal RWP[a-1], the second CMOS transmission gate tgn0 of the a-th 2T2R cell block is connected to the a-th enable signal terminal RWN[a-1], and the first CMOS transmission gate tgp0 and the second CMOS transmission gate tgn0 are connected together to the reverse inference signal terminal INB.

2. A control method for a memristor synaptic array supporting online learning of spiking neural networks, characterized in that, The method using the memristor synaptic array of claim 1 includes a memristor synaptic array training section and an inference section; The reasoning section includes: When the network inference current is received, the NMOS transistors mpi0 and mni0 in all subarrays are turned off; the NMOS transistors mpa0 and mna0 are turned on. The current flows from the bias signal terminal SL through each 2T2R unit and is collected at the weight output terminals IBLP and IBLN. The current at the weight output terminals IBLP and IBLN is added or subtracted to complete the reading of the positive and negative weights of the network. The training section includes: The inference signal terminal INF in the 2T2R cell block that needs to be trained is turned off. For the training of the positive cell memristor of the upper 2T2R structure in the b-th 2T2R cell of the a-th 2T2R cell block that needs to be trained in the SubArray, the training operation of the positive cell memristor is determined by turning on the word line signal terminal WL[2b-2] and the enable signal terminal RWP[a-1] based on the relative potential of the bit line signal terminal ABLP[a] of the a-th 2T2R cell block and the bias signal terminal SL[b-1] of the b-th 2T2R cell of the a-th 2T2R cell block. For the training of the negative cell memristor of the upper 2T2R structure in the bth 2T2R cell of the ath 2T2R cell block in the SubArray, the training operation of the negative cell memristor is determined by turning on the word line signal terminal WL[2b-2] and the enable signal terminal RWN[a-1] based on the relative potential of the bit line signal terminal ABLN [a] of the ath 2T2R cell block and the bias signal terminal SL[b-1] of the bth 2T2R cell of the ath 2T2R cell block. For the training of the positive cell memristor of the lower 2T2R structure in the bth 2T2R cell of the ath 2T2R cell block in the SubArray, the training operation of the positive cell memristor is determined by turning on the word line signal terminal WL[2b-1] and the enable signal terminal RWP[a-1], based on the relative potential of the bit line signal terminal ABLP[a] of the ath 2T2R cell block and the bias signal terminal SL[b-1] of the bth 2T2R cell of the ath 2T2R cell block. For training the negative cell memristor of the lower 2T2R structure in the bth 2T2R cell of the ath 2T2R cell block in the SubArray, the training operation of the negative cell memristor is determined by turning on the word line signal terminal WL[2b-1] and the enable signal terminal RWN[a-1], based on the relative potential of the bit line signal terminal ABLN [a] of the ath 2T2R cell block and the bias signal terminal SL[b-1] of the bth 2T2R cell of the ath 2T2R cell block.

3. The control method for a memristor synaptic array supporting online learning of a spiking neural network according to claim 2, characterized in that, The training operation for determining the relative potential of a memristor includes: performing a set operation when a positive voltage is applied to the top terminal of the memristor, that is, the terminal of the memristor that is not directly connected to the corresponding 2T2R internal transistor, to write the device as a low-impedance state; and performing a reset operation when a positive voltage is applied to the bottom terminal of the memristor, that is, the terminal of the memristor that is directly connected to the corresponding 2T2R internal transistor, to write the device as a high-impedance state.

4. The control method for a memristor synaptic array supporting online learning of a spiking neural network according to claim 3, characterized in that, In the inference section, in the resting state before receiving the network inference current, all inference signal terminals INF are enabled, and all bias signals SL also maintain their own inference voltage.

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