A packaging and testing method and system for memory chips

Abstract

The present invention provides a method and system for implementing packaging and testing of memory chips, relating to the field of memory chip technology. The method comprises: collecting appearance images of memory chips to be packaged; classifying the appearance images based on differences in texture features and structural features to determine the memory chip category of the memory chips to be packaged; selecting a corresponding packaging type according to the memory chip category to package the memory chips to obtain target memory chips; performing defect identification on the appearance images of the target memory chips to obtain an appearance defect set including different appearance defect categories; performing performance testing on the target memory chips using testing equipment to obtain a performance parameter set including different performance indicators; calculating a quality score of the target memory chips by combining the appearance defect set and the performance parameter set; and marking the target memory chips according to the quality score to complete packaging and testing of the memory chips to be packaged. This method improves the automation capability of packaging and testing and product yield.

Description

Technical Field

[0001] The present invention relates to the technical field of memory chips, and in particular to a packaging and testing method and system for memory chips. Background Art

[0002] Memory chips are integrated circuits used to store digital information (such as program code, data files, and operating status). They are an essential core component of electronic devices. Based on whether they can retain data after a power outage, they are categorized into two main types: non-volatile memory (such as NAND Flash, NOR Flash, EPROM, and MRAM) and volatile memory (such as DRAM and SRAM). They are widely used in various electronic systems, including mobile phones, computers, servers, automotive electronics, and IoT devices.

[0003] Packaging and testing of memory chips is a critical step in ensuring chip reliability, stability, and manufacturability. The packaging process transforms fragile bare chips into devices usable in actual devices, while testing is used to screen out chips with functional anomalies or packaging defects. Packaging testing not only identifies issues such as solder ball defects, package cracks, and performance anomalies, but also enables chip grading management, improves yield rates, prevents defective products from entering the market, and ensures data security and stable operation of end devices. With increasing chip integration and increasingly complex application environments, packaging and testing are becoming increasingly important in modern chip manufacturing.

[0004] However, existing memory chip packaging and testing methods have problems such as low automation and reliance on manual identification and detection, which can easily lead to chip category identification errors and improper packaging process selection, thereby causing packaging failures, performance anomalies and detection misjudgments. This not only affects chip yield and test accuracy, but also increases the probability of rework and manufacturing costs, reduces packaging efficiency and production line continuity, and makes it difficult to meet large-scale automatic packaging and testing needs. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of the embodiments of the present invention is to provide a packaging and testing method for memory chips, which can solve the problems of low automation and reliance on manual identification and detection in the existing memory chip packaging and testing methods in the prior art, which can easily lead to chip category identification errors and improper packaging process selection, thereby causing packaging failures, performance anomalies and detection misjudgments, which not only affect the chip yield and test accuracy, but also increase the probability of rework and manufacturing costs, reduce packaging efficiency and production line continuity, and make it difficult to meet the technical problems of large-scale automatic packaging and testing needs.

[0006] According to a first aspect of an embodiment of the present invention, a method for implementing packaging and testing of a memory chip is provided, comprising:

[0007] S1: Collect the appearance image of the memory chip to be packaged;

[0008] S2: Classify the appearance image based on texture feature differences and structural feature differences to determine the memory chip category of the memory chip to be packaged;

[0009] S3: Selecting a corresponding packaging type according to the memory chip category to package the memory chip to obtain a target memory chip;

[0010] S4: Acquire the appearance image of the target memory chip;

[0011] S5: performing defect recognition on the appearance image of the target memory chip to obtain an appearance defect set including different appearance defect categories;

[0012] S6: Performing performance testing on the target memory chip using a test device to obtain a performance parameter set including different performance indicators;

[0013] S7: Calculate the quality score of the target memory chip by combining the appearance defect set and the performance parameter set;

[0014] S8: Mark the target memory chip according to the quality score, and complete the packaging test of the memory chip to be packaged.

[0015] A second aspect of an embodiment of the present invention provides a packaging and testing system for a memory chip, comprising: a processor and a memory;

[0016] The memory stores programs or instructions that can be run on the processor. When the programs or instructions are executed by the processor, the steps of the packaging and testing method for implementing a memory chip according to the first aspect are implemented.

[0017] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0018] In an embodiment of the present invention, the problem of relying on manual identification in traditional memory chip packaging and testing is effectively solved by automatically classifying memory chips based on differences in texture features and structural features, significantly improving the accuracy and efficiency of classification. This solution avoids misjudgments caused by human factors by extracting the frequency domain texture features and polar coordinate structural features of the image, ensuring the correct matching of the packaging process, thereby reducing the occurrence of packaging failures, performance anomalies and other problems. At the same time, the entire process realizes an automated closed loop from image acquisition, chip category identification, packaging selection, defect detection, performance testing to quality scoring, reducing rework rate and production costs, improving production efficiency, yield rate and test consistency, and meeting the needs of large-scale, efficient packaging and testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are only for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. Throughout the drawings, the same reference symbols represent the same components. Obviously, the drawings described below are only some embodiments of the present invention. It is clear that those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0020] Figure 1 This is a flow chart of a method for implementing packaging and testing of a memory chip provided by an embodiment of the present invention;

[0021] Figure 2 The present invention provides a schematic structural diagram of a system for packaging and testing memory chips. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are part of the embodiments of the present invention, rather than all of the embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work should fall within the scope of protection of the present invention.

[0023] The packaging and testing method for implementing a memory chip provided by an embodiment of the present invention will be described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios.

[0024] Reference Manual Figure 1 , shows a flow chart of a method for implementing packaging and testing of a memory chip provided by an embodiment of the present invention.

[0025] An embodiment of the present invention provides a method for implementing packaging and testing of a memory chip, which may include the following steps:

[0026] S1: Collect appearance images of the memory chip to be packaged.

[0027] Appearance images refer to images of the visible exterior of a memory chip, captured by image acquisition devices such as industrial cameras. These images typically include the chip's packaging structure, surface texture, pin layout, and silkscreen information. These images reflect the chip's physical appearance before packaging and serve as the foundation for subsequent image recognition and classification.

[0028] S2: Classify the appearance image based on texture feature differences and structural feature differences to determine the memory chip category of the memory chip to be packaged.

[0029] Differences in texture features refer to variations in grayscale distribution, texture orientation, and frequency composition within chip surface images. Frequency domain analysis (such as Fourier transforms) can be used to extract microtexture features inherent to different chip types, such as pad edges, silkscreen details, and surface material roughness. Differences in structural features refer to differences in the spatial distribution, symmetry, and arrangement of key elements within chip images (such as pins, solder balls, and device markings). Using methods such as polar coordinate modeling and angular autocorrelation analysis, features reflecting the regularity of package structure can be extracted to differentiate between package formats and types.

[0030] By extracting the differences in texture and structural features in chip appearance images, accurate and automatic identification of chip categories can be achieved, significantly reducing the rate of manual misjudgment and improving the accuracy of packaging process matching and overall packaging efficiency.

[0031] In one possible implementation, the memory chip categories include: NAND flash memory, NOR flash memory, dynamic random access memory, static random access memory, electrically erasable programmable memory, magnetoresistive memory, three-dimensional stacked NAND flash memory, embedded flash memory module, ultraviolet erasable read-only memory, and mask read-only memory. S2 specifically includes:

[0032] S201: Convert the appearance image into a grayscale image.

[0033] S202: Using grayscale-based Figure 2 The first-order derivatives establish the process feature vector that describes the texture characteristics of the appearance image.

[0034] In a possible implementation, S202 specifically includes:

[0035] S2021: Using grayscale-based Figure 2 The adaptive band weight term of the order derivative extracts the texture-weighted spectrum of the appearance image.

[0036] The calculation formula of texture weighted spectrum is as follows:

[0037]

[0038] in, represents the grayscale coordinates, Represents a grayscale image Grayscale Figure 2 derivatives, Grayscale Figure 2 The statistical mean of the derivative, e represents a natural constant, represents pi, represents the two-dimensional Fourier transform basis function, represents the adaptive band weight term, i represents the imaginary unit, represents the frequency coordinate, Represents the texture weighted spectrum.

[0039] Among them, the introduction of the adaptive frequency band weight term makes the high-frequency part (texture edge) more weighted and the low-frequency part (illumination change) is suppressed.

[0040] S2022: Constructing a process feature vector with high-frequency energy concentration and texture-weighted spectrum entropy based on the texture-weighted spectrum.

[0041] The specific formula form of the process characteristic vector is:

[0042]

[0043]

[0044] in, represents the process feature vector, Indicates the frequency threshold used to divide high-frequency and low-frequency frequencies, Indicates the concentration of high-frequency energy, represents the texture weighted spectral entropy, and log represents the logarithmic function.

[0045] It should be noted that those skilled in the art can set the frequency threshold value according to actual needs, and the present invention is not limited here. Optionally, the frequency threshold value can be set to 60% or more of the Nyquist frequency (maximum resolvable frequency) of the appearance image.

[0046] Specifically, step S2021 constructs a texture-weighted spectrum by introducing an adaptive band weight term based on the second-order derivative into the Fourier transform of the grayscale image. This effectively enhances the expressiveness of the high-frequency parts of the image (such as microstructures such as pad edges and silkscreen lines), while suppressing the illumination interference and background clutter caused by the low-frequency parts, thereby improving the accuracy of texture feature extraction. Subsequently, in step S2022, the high-frequency energy concentration and texture spectrum entropy are calculated based on the spectrum to construct a feature vector reflecting the differences in chip process characteristics. This process not only improves the ability to identify differences in chip microprocesses, but also significantly enhances the robustness of the classification model to changes in image quality, helping to achieve stable and high-precision chip category recognition.

[0047] S203: Establishing a structural feature vector for eliminating position sensitivity through a polar coordinate transformation algorithm.

[0048] In a possible implementation, S203 specifically includes:

[0049] S2031: Map the Cartesian coordinates to polar coordinates with the center of the grayscale image as the pole.

[0050] S2032: Perform grayscale integration on the extreme circle to obtain the joint distribution of radial angles:

[0051]

[0052] in, and denote the polar radius and polar angle respectively, Representation with polar coordinates The associated joint distribution of radial angles, represents the rotation angle variable, represents the cosine function, Represents polar coordinates The gray value at .

[0053] It effectively solves the interference caused by slight rotation and displacement of the image, describes the distribution complexity of the marking elements along the radial direction, and resists radial deformation.

[0054] S2033: Calculate the radial distribution entropy of the grayscale image at different polar coordinate radii.

[0055] The calculation formula of radial distribution entropy is as follows:

[0056]

[0057] in, Represents the polar coordinate radius The grayscale response probability at Indicates the grayscale change entropy value at different polar coordinate radii.

[0058] It is understandable that the polar coordinate radius can take finite discrete values ​​according to actual needs.

[0059] S2034: Calculate the angular autocorrelation values ​​of the grayscale image at different discrete polar coordinate angles based on the radial angle joint distribution.

[0060] The calculation formula of the angle autocorrelation value is as follows:

[0061]

[0062] in, Indicates that the polar coordinate angle offset value is The angle autocorrelation value at time , Representation with polar coordinates The associated joint distribution of radial angles, Indicates taking the expected value.

[0063] The expected value is the average of all polar angles and / or polar radii, and the purpose is to obtain the average correlation degree under a certain angle offset in the entire image.

[0064] S2035: Establish a structural feature vector based on the radial distribution entropy and the angular autocorrelation value.

[0065] The calculation formula of the structural characteristic vector is as follows:

[0066]

[0067] in, represents the structural feature vector, Indicates taking the maximum function value .

[0068] Specifically, the entire process constitutes a complete flow for structural feature extraction, aiming to enhance the robust recognition of chip image structural information through polar coordinate modeling. First, in S2031, the chip grayscale image is converted from Cartesian coordinates to a polar coordinate system, with the image center as the pole. This facilitates capturing the structural patterns symmetrically distributed around the chip center and effectively resists interference caused by image rotation and position shifts. In S2032, the radial angle joint distribution function is constructed by integrating the grayscale around the pole circle, characterizing the joint characteristics of grayscale changes in space. In S2033, the grayscale response entropy at different radii is further calculated to reflect the complexity of the structure in the radial direction. In S2034, angular autocorrelation analysis is used to obtain the symmetric distribution of the image in different directions. Finally, in S2035, the radial distribution entropy is combined with the maximum angular autocorrelation value to construct a stable and distinguishable structural feature vector. The entire process achieves a quantitative representation from local structural changes to global distribution patterns, improving the spatial recognition and anti-interference capabilities of memory chip classification, and providing a solid structural information foundation for accurate packaging process matching.

[0069] S204: Obtaining process standard template vectors and structural standard template vectors of different memory chip categories through orthogonal training.

[0070] Orthogonal training involves constructing a set of highly discriminative feature vectors for different memory chip categories during the training phase, ensuring that each category is as orthogonal as possible in the feature space (i.e., dissimilar and with low correlation). This improves the classification model's ability to distinguish between different categories and reduces misjudgments caused by feature overlap. A process standard template vector is a representative process feature vector trained in the texture feature space for each memory chip type, reflecting the typical process image characteristics of that chip type. A structural standard template vector is a standard template trained in the structural feature space for each chip type, used to characterize its typical structural layout characteristics.

[0071] It should be noted that through orthogonal training methods, standard template vectors are established for different memory chip categories in both texture and structure feature spaces, ensuring good separability and discrimination between different chip types in the feature dimension. This process effectively improves the accuracy and robustness of subsequent classification, avoids misjudgments caused by feature confusion, ensures more stable and reliable chip category identification, and facilitates precise matching and automated execution of subsequent packaging processes.

[0072] S205: combining the relative relationship between the process feature vector and the process standard template vector, and the relative relationship between the structure feature vector and the structure standard template vector, classifying the appearance image based on the orthogonal projection principle to obtain the memory chip category of the memory chip to be packaged.

[0073] The classification formula for memory chip categories is as follows:

[0074]

[0075] in, represents the process standard template vector of the k-th type of memory chip, Represents the structural standard template vector of the k-th type of memory chip, represents the fusion weight, Indicates the memory chip category number, It means taking the k with the maximum function value as the output of the memory chip category number C.

[0076] Optionally, the fusion weight can be set to 0.5 or other values.

[0077] Specifically, the system calculates the similarity between the process feature vector of the chip under test and the process standard template vectors for each category, as well as the degree of match between the structural feature vector and the structural standard template vector. Combined with fusion weights, these scores are weighted and the orthogonal projection principle is used to automatically classify the appearance image. This process, by evaluating the degree of match in two independent feature spaces, avoids misclassifications caused by feature coupling, significantly improving classification accuracy and robustness. This ensures scientific and reliable chip category identification and lays the foundation for precise matching in subsequent packaging processes.

[0078] It should be noted that the orthogonal projection classification method, combined with the second-order derivative of the grayscale image and polar coordinate structural features, accurately extracts the texture and structural features of the memory chip. By training standardized templates based on the process and structural characteristics of different memory chip categories, the appearance images of each memory chip type can be accurately classified and the appropriate packaging process selected. This method significantly improves classification accuracy, reduces manual recognition errors, and optimizes the packaging process through automated classification and process matching, improving production efficiency, product yield, and packaging consistency.

[0079] S3: Select a corresponding packaging type according to the memory chip category to package the memory chip to obtain a target memory chip.

[0080] As you can understand, based on the identified memory chip type, the corresponding package type (such as BGA, TSOP, WLCSP, etc.) is automatically matched and the corresponding packaging process is executed to ensure that the chip structure, electrical interface and package form are highly compatible. This process can avoid soldering failures, structural damage or poor electrical performance caused by incorrect package type selection, improve packaging success rate and product consistency, and realize production line automation, reducing human intervention and rework costs.

[0081] In actual application, after the packaging process is determined, packaging can be carried out in a conventional manner, that is, in a preset order. The memory chip subcategory can also be re-identified in a similar manner to the identification method of identifying the memory chip category in step S2, and the packaging process for each step is automatically selected according to the current state of the memory chip. Specifically: First, using the current state of the memory chip as a feature and the corresponding packaging process mark as a category label, the orthogonal training of step S2 is repeated to obtain the process standard template vector and the structure standard template vector corresponding to the subcategories under different memory chip categories, and re-identify the subcategory, that is, the current state of the memory chip, based on the obtained template vector. Then, the packaging process to be selected is automatically determined according to the subcategory, and then packaging is performed according to the selected packaging process, wherein the packaging process includes chip cutting, solder ball mounting, chip bonding, packaging substrate, hot pressing and sealing. Each time a packaging process is performed, it is identified once until the packaging is completed.

[0082] It's important to note that this process achieves a high degree of automation and flexibility by automatically selecting the packaging process for each step based on the memory chip's current state and packaging process subcategory. Each packaging process selection is based on previous state identification, ensuring that packaging quality and process are perfectly matched at every stage. This effectively avoids packaging failures caused by improper process selection in traditional fixed processes, improves packaging accuracy, flexibility, and production efficiency, and reduces rework and manual intervention.

[0083] In a possible implementation, the package types include a TSOP package type, a BGA package type, a WLCSP package type, an eMMC module-level package type, and a UFS module-level package type.

[0084] It is understandable that by accurately matching the memory chip category with the corresponding package type, the most suitable package form can be selected according to the structural characteristics and application requirements of different chips, which helps to improve the compatibility, reliability and production efficiency of the package.

[0085] S4: Collect the appearance image of the target memory chip.

[0086] S5: performing defect recognition on the appearance image of the target memory chip to obtain an appearance defect set including different appearance defect categories.

[0087] It should be noted that by collecting images of the target memory chip after packaging and automatically analyzing them using image recognition algorithms, different types of appearance defects, such as package cracks, missing solder balls, blurred silkscreen, and oxidation spots, are identified and corresponding appearance defect sets are generated. This process avoids the problems of missed detection and misjudgment that often occur with manual inspection, improves the accuracy and stability of defect identification, and facilitates the early detection of packaging quality issues, thereby improving overall product yield and inspection efficiency.

[0088] In one possible implementation, the appearance defect categories include package cracks, missing solder balls, blurred silk screen, and oxidation spots. S5 specifically includes:

[0089] S501: Converting the target memory chip appearance image into a target memory chip appearance image grayscale image.

[0090] S502: Establishing a process feature vector and a structure feature vector of a grayscale image of the target memory chip appearance.

[0091] S503: Obtaining process standard template vectors and structure standard template vectors of different target memory chip appearance images through orthogonal training.

[0092] S504: Classifying the appearance image of the target memory chip based on the orthogonal projection principle to obtain appearance defect categories of the appearance image of the target memory chip, wherein each appearance defect category constitutes an appearance defect set.

[0093] It should be noted that by converting the target memory chip's appearance image into a grayscale image and extracting its process and structural feature vectors, combined with orthogonal training to generate standard defect templates, the orthogonal projection classification method is used to automatically identify and classify typical appearance defects such as package cracks, missing solder balls, blurred silkscreen, and oxidation spots. This process not only achieves accurate detection and classification of appearance defects, but also effectively addresses the blind spot of traditional testing, which focuses solely on electrical parameters, by integrating appearance factors with performance test results. This improves the comprehensiveness, accuracy, and reliability of overall packaging testing and defect screening.

[0094] S6: Performing a performance test on the target memory chip using a test device to obtain a performance parameter set including different performance indicators.

[0095] It should be noted that the electrical performance of the packaged target memory chip is tested by automatic testing equipment to obtain multiple performance indicators including read and write speed, bit error rate, power consumption, bad block rate, etc., to form a performance parameter set to ensure that the chip meets the functional and stability requirements before leaving the factory, thereby improving test consistency and quality control level.

[0096] In a possible implementation, the performance indicators include read and write speed, bit error rate, power consumption, and bad block rate. The performance test of the target memory chip by the test equipment in S6 is specifically as follows:

[0097] Perform performance tests on target memory chips using ATE test equipment.

[0098] ATE (Automatic Test Equipment) refers to automated electronic test equipment used for batch testing of the functionality, electrical properties, timing, and performance of semiconductor chips (such as memory chips). Using ATE testing equipment to perform performance testing on target memory chips efficiently measures key performance indicators such as read / write speed, bit error rate, power consumption, and bad block rate, enabling batch, standardized, and high-precision electrical verification.

[0099] S7: Calculate the quality score of the target memory chip by combining the appearance defect set and the performance parameter set.

[0100] It should be noted that the comprehensive quality score of the target chip is calculated by comprehensively analyzing the set of appearance defects identified in the early stage and the set of performance parameters, assigning influence weights to various defects and performance indicators according to preset quality assessment rules. This process enables the coordinated evaluation of appearance and performance factors, avoiding misclassification or omission caused by single-dimensional judgment, improving the objectivity and accuracy of chip grading, and providing a reliable basis for subsequent factory screening and product traceability.

[0101] In a possible implementation, S7 specifically includes:

[0102] S701: Mark different appearance defect categories and impact scores of different performance indicators according to the memory chip quality rating rules.

[0103] Among them, the memory chip quality rating rules are preset rules set according to the company's own situation. That is, in the chip manufacturing and packaging testing process, it is a standard system for comprehensive quality scoring and grading of single chips. Its core is to set quantifiable impact scores for different defect types and performance deviations, and finally obtain the total score through weighted summation, which is used for good product screening, graded shipment or failure analysis.

[0104] S702: Calculate the quality score of each target memory chip according to the impact score.

[0105] The quality score is calculated as follows:

[0106]

[0107] in, represents the impact score of the jth influencing factor, where the influencing factors include various performance indicators and various appearance defect categories, Indicates the quality score.

[0108] It's understandable that by converting chip appearance defects and performance test results into standardized impact scores and accumulating them to create a quality score, a quantitative assessment of chip quality is achieved. Compared to traditional manual judgment methods, this method is more objective, controllable, and easy to process in batches. It helps accurately screen good products, control shipping quality, and improve automated grading and product consistency management.

[0109] S8: Mark the target memory chip according to the quality score, and complete the packaging test of the memory chip to be packaged.

[0110] In practical applications, this method uses appearance images as a basis to extract texture and structural features for accurate chip classification. It also dynamically matches the packaging process to the chip's state during the packaging process, ensuring process adaptability and flexibility. After packaging, complete quality parameters are acquired through automated visual inspection and electrical testing. This integrated analysis then derives a chip quality score, enabling efficient, accurate, and closed-loop quality control. This overall solution significantly improves packaging success rates, test consistency, and yield rates, reduces rework and manual labor, and is suitable for large-scale, high-reliability chip manufacturing scenarios.

[0111] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0112] In an embodiment of the present invention, the problem of relying on manual identification in traditional memory chip packaging and testing is effectively solved by automatically classifying memory chips based on differences in texture features and structural features, significantly improving the accuracy and efficiency of classification. This solution avoids misjudgments caused by human factors by extracting the frequency domain texture features and polar coordinate structural features of the image, ensuring the correct matching of the packaging process, thereby reducing the occurrence of packaging failures, performance anomalies and other problems. At the same time, the entire process realizes an automated closed loop from image acquisition, chip category identification, packaging selection, defect detection, performance testing to quality scoring, reducing rework rate and production costs, improving production efficiency, yield rate and test consistency, and meeting the needs of large-scale, efficient packaging and testing.

[0113] Reference Manual Figure 2 , shows a structural diagram of a packaging and testing system for memory chips provided by an embodiment of the present invention.

[0114] The embodiment of the present invention provides a packaging and testing system 20 for implementing a memory chip, comprising: a processor 201 and a memory 202;

[0115] The memory 202 stores programs or instructions that can be run on the processor 201. When the programs or instructions are executed by the processor 201, the steps of the above-mentioned packaging and testing method for implementing a memory chip are implemented, and the same technical effect can be achieved. To avoid repetition, the present invention will not go into details.

[0116] It should be understood that the processor 201 in the embodiment of the present invention may be a central processing unit (CPU), or may be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0117] It should also be understood that the memory 202 in the embodiments of the present invention may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0118] The above embodiments can be implemented in whole or in part via software, hardware (e.g., circuits), firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions or computer programs. When loaded or executed on a computer, the processes or functions described in accordance with the embodiments of the present invention are fully or partially performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired means (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server or data center that contains a collection of one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media. The semiconductor media can be a solid-state drive.

[0119] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0120] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0121] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0122] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interface, indirect coupling or communication connection of the device or unit, which can be electrical, mechanical or other forms.

[0123] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0124] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0125] If the functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0126] An embodiment of the present invention provides a readable storage medium including: a program or instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the steps of the above-mentioned packaging and testing method for implementing a memory chip are implemented, and the same technical effect can be achieved. To avoid repetition, the present invention will not be repeated.

[0127] Finally, it should be noted that the above embodiments are merely illustrative of the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and such modifications or replacements do not deviate from the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or replacements that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.

Claims

1. A method for implementing packaging and testing of a memory chip, characterized in that: include: S1: Collect the appearance image of the memory chip to be packaged; S2: classifying the appearance image based on texture feature differences and structural feature differences to determine the memory chip category of the memory chip to be packaged; specifically comprising: S201: converting the appearance image into a grayscale image; S202: establishing a process feature vector describing the texture features of the appearance image based on the second-order derivative of the grayscale image; S203: establishing a structural feature vector for eliminating position sensitivity through a polar coordinate transformation algorithm; S204: obtaining process standard template vectors and structural standard template vectors for different memory chip categories through orthogonal training; S205: combining the relative relationship between the process feature vector and the process standard template vector, and the relative relationship between the structural feature vector and the structural standard template vector, classifying the appearance image based on the orthogonal projection principle to obtain the memory chip category of the memory chip to be packaged; The S202 specifically includes: S2021: extracting a texture weighted spectrum of the appearance image using an adaptive frequency band weight term based on the second-order derivative of the grayscale image; S2022: establishing a process feature vector having high-frequency energy concentration and texture weighted spectrum entropy based on the texture weighted spectrum; The S203 specifically includes: S2031: mapping Cartesian coordinates to polar coordinates with the center of the grayscale image as the pole; S2032: performing grayscale integration on the circumference of the pole to obtain a radial angle joint distribution; S2033: calculating the radial distribution entropy of the grayscale image at different polar coordinate radii; S2034: calculating the angular autocorrelation values ​​of the grayscale image at different discrete polar coordinate angles based on the radial angle joint distribution; S2035: establishing the structural feature vector based on the radial distribution entropy and the angular autocorrelation value; S3: Selecting a corresponding packaging type according to the memory chip category to package the memory chip to obtain a target memory chip; S4: Acquire the appearance image of the target memory chip; S5: performing defect recognition on the appearance image of the target memory chip to obtain an appearance defect set including different appearance defect categories; S6: Performing a performance test on the target memory chip using a test device to obtain a performance parameter set including different performance indicators; S7: Calculating a quality score of the target memory chip based on the appearance defect set and the performance parameter set; S8: Marking the target memory chip according to the quality score, and completing the packaging test of the memory chip to be packaged.

2. The method for implementing packaging and testing of a memory chip according to claim 1, wherein: The memory chip categories include: NAND flash memory, NOR flash memory, dynamic random access memory, static random access memory, electrically erasable programmable memory, magnetoresistive memory, ultraviolet erasable read-only memory and mask read-only memory.

3. The method for implementing packaging and testing of a memory chip according to claim 1, wherein: The package types include TSOP package type, BGA package type, WLCSP package type, eMMC module-level package type and UFS module-level package type.

4. The method for implementing packaging and testing of a memory chip according to claim 1, wherein: The appearance defect categories include package cracks, missing solder balls, blurred silk screen and oxidation spots; S5 specifically includes: S501: Converting the target memory chip appearance image into a target memory chip appearance image grayscale image; S502: Establishing a process feature vector and a structural feature vector of the grayscale image of the target memory chip appearance; S503: Obtaining process standard template vectors and structure standard template vectors of different target memory chip appearance images through orthogonal training; S504: Classifying the appearance image of the target memory chip based on the orthogonal projection principle to obtain appearance defect categories of the appearance image of the target memory chip, wherein each appearance defect category constitutes the appearance defect set.

5. The method for implementing packaging and testing of a memory chip according to claim 1, wherein: The performance indicators include read and write speed, bit error rate, power consumption and bad block rate; the performance test of the target memory chip by the test equipment in S6 is specifically as follows: The target memory chip is subjected to a performance test by using ATE testing equipment.

6. The method for implementing packaging and testing of a memory chip according to claim 1, wherein: The S7 specifically includes: S701: Mark different appearance defect categories and impact scores of different performance indicators according to the memory chip quality rating rules; S702: Calculate the quality score of each target storage chip according to the impact score.

7. A packaging and testing system for memory chips, characterized in that: include: processor and memory; The memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method for implementing packaging and testing of a memory chip according to any one of claims 1 to 6 are implemented.

8. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the method for implementing the packaging and testing of a memory chip as claimed in any one of claims 1 to 6 are implemented.

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