Sensor assembly and electronic device

Abstract

The invention discloses a sensor assembly and electronic equipment, and belongs to the technical field of biological recognition. The sensor assembly comprises a sensor unit, the sensor unit comprises a communication port, and the communication port is used for receiving or sending a communication signal; and the time delay circuit is in communication connection with the communication port, and the time delay circuit is used for adjusting the signal transmission delay duration of the communication signal received or sent by the sensor unit.

Description

Technical Field

[0001] This application belongs to the field of biometric technology, and particularly relates to a sensor component and an electronic device. Background Art

[0002] In the related art, communication between a processor and a fingerprint sensor is generally through a Serial Peripheral Interface (SPI). VDD is a power supply signal. SCLK is a serial clock signal generated by the master device. MOSI is a signal output by the master device and input by the slave device, which is sent by the master device. MISO is a signal input by the master device and output by the slave device, which is sent by the slave device. CS is a chip select signal sent by the master device, and is generally active low. GND is for grounding.

[0003] When a processor (Central Processing Unit, CPU) of an electronic device such as a mobile phone collects signals from a fingerprint sensor, in order to prevent insufficient setup time, a delay mechanism needs to be added, that is, configure delayed signal acquisition. When the delay configuration is improper, it will cause SPI timing mismatch, which may cause problems such as mis-sampling or poor communication.

[0004] CLK is the clock signal of the CPU, and MISO is a signal input by the host and output by the slave, that is, the signal output by the fingerprint sensor to the CPU. Among them, when delay parameters are configured, theoretically signal sampling needs to be performed at the theoretical sampling point. Due to the addition of delay parameters, sampling is performed at the default configured sampling point. The real signal is high level, and the actually sampled signal may be high level or low level. If it is determined to be low level, there will be poor communication.

[0005] To address the above problem of communication failure caused by adding delay parameters, a general solution is to adjust the delay parameters of the CPU sampling time. According to the actual application situation of the fingerprint sensor, turn off the delay or reduce the delay to ensure normal communication between the CPU and the fingerprint sensor.

[0006] When solving the SPI timing mismatch by adjusting the delay of the CPU sampling time, it can only solve the current problem based on the current selection of the CPU and the fingerprint sensor, and cannot be applied to other scenarios. When the fingerprint sensor trace changes, the motherboard trace changes, or other environmental factors change, the SPI signals received by the CPU have different degrees of offset, resulting in the invalidation of the delay parameters, and it is necessary to reconfigure the implementation parameters to ensure normal communication, and the time period is relatively long. Summary of the Invention

[0007] This application aims to provide a sensor component and an electronic device, which can make the SPI timing match the CPU signal sampling time within a relatively short time period.

[0008] In a first aspect, an embodiment of the present application provides a sensor assembly, which includes:

[0009] A sensor unit, which includes a communication port for receiving or sending communication signals;

[0010] A delay circuit, which is communicatively connected to the communication port and is used to adjust the signal transmission delay duration of the communication signals received or sent by the sensor unit.

[0011] In a second aspect, an embodiment of the present application provides an electronic device, which includes:

[0012] A processor;

[0013] The sensor assembly as proposed in the first aspect; the sensor assembly is communicatively connected to the processor.

[0014] In some embodiments of the present application, by setting a delay circuit, the signal transmission delay duration of the communication signals received or sent by the sensor unit is adjusted. Therefore, when there is an out-of-sync situation of the SPI signal between the processor and the sensor unit, the signal transmission delay duration can be directly adjusted through the delay circuit. Therefore, it is not necessary to adjust the CPU delay parameters, and the SPI timing can be matched with the CPU signal sampling time within a relatively short time period. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Shows a schematic structural diagram of a sensor assembly according to some embodiments of the present application;

[0016] Figure 2 Shows a waveform schematic diagram of a clock signal and a sensor sampling output signal according to some embodiments of the present application;

[0017] Figure 3A Shows a schematic circuit diagram of a delay circuit according to some embodiments of the present application;

[0018] Figure 3B Shows a schematic circuit diagram of a delay circuit according to some embodiments of the present application;

[0019] Figure 4 Shows a waveform schematic diagram of a clock signal and a sensor sampling output signal according to some embodiments of the present application;

[0020] Figure 5 Shows a waveform schematic diagram of a clock signal and a sensor sampling output signal according to some embodiments of the present application;

[0021] Figure 6 Shows a schematic diagram of the switch state of a delay circuit according to some embodiments of the present application;

[0022] Figure 7 Schematic diagram of the switching state of the time delay circuit in some embodiments of the present application;

[0023] Figure 8 Schematic diagram of the switching state of the time delay circuit in some embodiments of the present application;

[0024] Figure 9 Schematic diagram of the switching state of the time delay circuit in some embodiments of the present application;

[0025] Figure 10 Schematic diagram of the waveforms of the clock signal and the sensor sampling output signal in some embodiments of the present application;

[0026] Figure 11 Schematic diagram of the waveforms of the clock signal and the sensor sampling output signal in some embodiments of the present application;

[0027] Figure 12 Schematic diagram of the circuit of the time delay circuit in some embodiments of the present application;

[0028] Figure 13 Schematic diagram of the circuit of the time delay circuit in some embodiments of the present application;

[0029] Figure 14 Schematic diagram of the structure of the sensor assembly in some embodiments of the present application.

[0030] Reference numerals:

[0031] 100 - Sensor assembly, 102 - Sensor unit, 1022 - Pixel matrix, 1024 - Analog - to - digital conversion unit, 1026 - Data buffer, 1028 - Digital controller, 104 - Communication port, 106 - Time delay circuit, 108 - Buffer unit, 1082 - Buffer, 1084 - First switching device, 1086 - Second switching device, 110 - Signal transmission cable, 112 - Ninth switching device, 114 - Switching tube, 116 - Tenth switching device;

[0032] Buffer1 - First buffer, Buffer2 - Second buffer, Buffer3 - Third buffer, S1b - Third switching device, S1a - Fourth switching device, S2b - Fifth switching device, S2a - Sixth switching device, S3b - Seventh switching device, S3a - Eighth switching device;

[0033] 200 - Electronic device, 202 - Processor. Detailed implementation manners

[0034] Embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where like or similar reference numerals denote like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary only for explaining the present application and should not be construed as limiting the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0035] The terms "first" and "second" in the description and claims of the present application may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more. In addition, "and / or" in the description and claims means at least one of the connected objects. The character " / " generally indicates an "or" relationship between the associated objects before and after.

[0036] In the description of the present application, it should be understood that the orientation or positional relationships indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.

[0037] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0038] The following will be combined with Figures 1 to 14 Describe the sensor assembly 100 and the electronic device 200 according to the embodiments of the present application.

[0039] In some embodiments of the present application, a sensor assembly 100 is provided. Figure 1 The structural schematic diagram of the sensor assembly 100 in some embodiments of the present application is shown, as Figure 1 shown, the sensor assembly 100 includes:

[0040] The sensor unit 102, and the sensor unit 102 includes a communication port 104, and the communication port 104 is used to receive or send communication signals;

[0041] A time delay circuit 106, the time delay circuit 106 is communicatively connected to the communication port 104, and the time delay circuit 106 is used to adjust the signal transmission delay duration of the communication signals received or sent by the sensor unit 102.

[0042] In some embodiments of the present application, the electronic device 200 includes but is not limited to a mobile phone, a tablet computer, a laptop computer, and a smart watch. The electronic device 200 includes a processor 202. The sensor assembly 100 includes but is not limited to a fingerprint sensor, a pressure sensor, a motion sensor, and a light sensor.

[0043] In the following embodiments, taking the electronic device 200 as a mobile phone and the sensor assembly 100 as a fingerprint sensor assembly 100 as an example, the embodiments of the present application will be illustrated.

[0044] The sensor assembly 100 includes a sensor unit 102 and a time delay circuit 106. Wherein the sensor unit 102 is the fingerprint sensor body. Exemplarily, the sensor unit 102 is an in-screen fingerprint sensor. The sensor unit 102 includes a communication port 104. Exemplarily, the communication port 104 is an SPI communication port 104, that is, the processor 202 communicates with the sensor assembly 100 through SPI communication. Exemplarily, SPI communication includes 4 signal lines, namely SCLK, MOSI, MISO, and CS. Among them, the SCLK signal line is used to transmit a serial clock signal, and this signal is generated by the processor 202. The MOSI signal line is used to transmit the signal output by the processor 202 and input by the sensor assembly 100, and the data transmitted on the MOSI signal line is sent by the processor 202. The MISO signal line is used to transmit the signal output by the sensor assembly 100 and input by the processor 202, and the data transmitted on the MISO signal line is sent by the sensor. The CS signal line is used to transmit a chip select signal, and the chip select signal is sent by the processor 202, and generally it is valid when it is at a low potential.

[0045] The time delay circuit 106 is communicatively connected to the communication port 104 and the processor 202 respectively. Between the sensor unit 102 and the processor 202 of the electronic device 200, the signal transmission of the communication signal is carried out through the time delay circuit 106. During the operation of the electronic device 200 and the sensor assembly 100, the processor 202 continuously outputs a clock signal CLK to the sensor assembly 100.

[0046] Figure 2 Shows a waveform schematic diagram of the clock signal and the sensor sampling output signal in some embodiments of the present application, as Figure 2As shown, between t0 and t1, it is the detection signal transmitted on MISO or MOSI when the user's fingerprint is detected. t2 is the detection time point for the processor 202 to detect the signal. Among them, the time between t0 and t2 is the signal establishment time, and the time between t2 and t1 is the signal holding time.

[0047] When the holding time is too short, it may cause the processor 202 to fail to accurately recognize the user's fingerprint touch, resulting in the failure of SPI communication. By setting a delay circuit to adjust the output delay of the MISO signal, or to adjust the input delays of the MOSI signal and the SCLK signal, it is possible to change the position of the t2 time point relative to the t0 time point and the t1 time point, thereby achieving the adjustment of the establishment time and the holding time, and further avoiding the failure of SPI communication and improving the reliability of SPI communication.

[0048] In this application, by setting the delay circuit 106, the signal transmission delay duration of the communication signal between the sensor unit 102 and the processor 202 is adjusted. Therefore, when there is an out-of-sync situation in the SPI signal between the processor 202 and the sensor unit 102, the signal transmission delay duration can be directly adjusted through the delay circuit 106. Therefore, it is not necessary to adjust the CPU delay parameters, and the SPI timing can be matched with the CPU signal sampling time within a relatively short time period.

[0049] In some embodiments of this application, the sensor unit 102 sends a data level signal through the communication port 104, and the delay circuit 106 is used to adjust the signal transmission delay duration of the data level signal.

[0050] In some embodiments of this application, the sensor unit 102 sends a data level signal to the processor 202 through the communication port 104, specifically the MISO signal line in the SPI communication line. When the data level signal is at a low level, it indicates that the sensor has not detected the user's fingerprint. When the user's fingerprint is detected, the data level signal changes from a low level signal to a high level signal.

[0051] The delay circuit 106 is provided on the MISO signal line, which can adjust the signal transmission delay duration of the data level signal, thereby avoiding the failure of SPI communication and improving the reliability of SPI communication without the need to adjust the CPU delay parameters.

[0052] In some embodiments of this application, the sensor unit 102 receives a clock signal through the communication port 104, and the delay circuit 106 is used to adjust the signal reception delay duration of the clock signal.

[0053] In some embodiments of the present application, the sensor unit 102 receives the clock signal CLK sent by the processor 202 through the communication port 104, specifically the SCLK signal line in the SPI communication line. At the same time, the processor 202 also receives other data signals sent by the processor 202 through the MOSI signal line.

[0054] The delay circuit 106 is arranged on the SCLK signal line and the MOSI signal line, and can adjust the signal reception delay duration of the MOSI signal and the SCLK signal of the sensor component 100, so as to avoid the SPI communication failure and improve the SPI communication reliability without adjusting the CPU delay parameters.

[0055] In some embodiments of the present application, Figure 3A and Figure 3B shows a circuit schematic diagram of the delay circuit 106 in some embodiments of the present application, as Figure 3A shown, the delay circuit 106 includes:

[0056] At least two buffer units 108 connected in series, and the buffer unit 108 includes:

[0057] A buffer 1082;

[0058] A first switching device 1084, and the first switching device 1084 is connected in series with the buffer 1082;

[0059] A second switching device 1086, and the second switching device 1086 is connected in parallel with the buffer 1082;

[0060] Wherein, when the first switching device 1084 is turned on, the second switching device 1086 is turned off; when the first switching device 1084 is turned off, the second switching device 1086 is turned on.

[0061] In some embodiments of the present application, the delay circuit 106 includes at least two buffer units 108 connected in series. Each buffer unit 108 includes a buffer 1082 and two switching devices, specifically a first switching device 1084 and a second switching device 1086. Among them, the first switching device 1084 and the buffer 1082 are connected in series, and the second switching device 1086 is connected in parallel with the buffer 1082.

[0062] When the first switching device 1084 is turned on and the second switching device 1086 is turned off, the current buffer unit 108 is connected in series to the time delay circuit 106. When the first switching device 1084 is turned off and the second switching device 1086 is turned on, the current buffer unit 108 is short-circuited. By adjusting the number of buffer units 108 in the series state and the short-circuited state in the time delay circuit 106, the adjustment of the time delay parameter of the time delay circuit 106 can be achieved.

[0063] It can be understood that the more the number of buffer units 108 connected in series in the time delay circuit 106, the longer the time delay. The more the number of buffer units 108 short-circuited in the time delay circuit 106, the shorter the time delay. When all the buffer units 108 are in the short-circuited state, the time delay of the time delay circuit 106 is 0.

[0064] In some embodiments of the present application, as Figure 3B shown, the time delay circuit 106 includes:

[0065] The first buffer Buffer1;

[0066] The second buffer Buffer2, the input end of the second buffer Buffer2 is electrically connected to the output end of the first buffer Buffer1;

[0067] The third buffer Buffer3, the input end of the third buffer Buffer3 is electrically connected to the output end of the second buffer Buffer2;

[0068] The third switching device S1b, the first end of the third switching device S1b is electrically connected to the input end of the first buffer Buffer1;

[0069] The fourth switching device S1a, the first end of the fourth switching device S1a is electrically connected to the second end of the third switching device S1b, and the second end of the fourth switching device S1a is electrically connected to the output end of the third buffer Buffer3;

[0070] The fifth switching device S2b, the first end of the fifth switching device S2b is electrically connected to the output end of the first buffer Buffer1, and the second end of the fifth switching device S2b is electrically connected to the input end of the second buffer Buffer2;

[0071] The sixth switching device S2a, the first end of the sixth switching device S2a is electrically connected to the first end of the fifth switching device S2b, and the second end of the sixth switching device S2a is electrically connected to the output end of the third buffer Buffer3;

[0072] The seventh switching device S3b, the first end of the seventh switching device S3b is electrically connected to the output end of the second buffer Buffer2, and the second end of the seventh switching device S3b is electrically connected to the input end of the third buffer Buffer3;

[0073] The eighth switching device S3a, the first end of the eighth switching device S3a is electrically connected to the first end of the seventh switching device S3b, and the second end of the eighth switching device S3a is electrically connected to the output end of the third buffer Buffer3.

[0074] In some embodiments of the present application, the delay circuit 106 includes 3 buffers 1082 connected in series, specifically the first buffer Buffer1, the second buffer Buffer2, and the third buffer Buffer3. Among them, the first buffer Buffer1 is connected to the third switching device S1b and the fourth switching device S1a. When the third switching device S1b is turned on and the fourth switching device S1a is turned off, the communication signal between the processor 202 and the sensor unit 102 needs to pass through the first buffer Buffer1. Due to the existence of the first buffer Buffer1, the signal transmission time will increase, thereby increasing the signal transmission delay duration. When the third switching device S1b is turned off and the fourth switching device S1a is turned on, the first buffer Buffer1 is short-circuited, and the communication signal between the processor 202 and the sensor unit 102 does not pass through the first buffer Buffer1, so the signal transmission delay duration will not increase.

[0075] Similarly, when the fifth switching device S2b is turned on and the sixth switching device S2a is turned off, the communication signal between the processor 202 and the sensor unit 102 passes through the second buffer Buffer2. When the fifth switching device S2b is turned off and the sixth switching device S2a is turned on, the communication signal between the processor 202 and the sensor unit 102 does not pass through the second buffer Buffer2. When the seventh switching device S3b is turned on and the eighth switching device S3a is turned off, the communication signal between the processor 202 and the sensor unit 102 passes through the third buffer Buffer3. When the seventh switching device S3b is turned off and the eighth switching device S3a is turned on, the communication signal between the processor 202 and the sensor unit 102 does not pass through the third buffer Buffer3.

[0076] By adjusting the switching states of the third switching device S1b, the fourth switching device S1a, the fifth switching device S2b, the sixth switching device S2a, the seventh switching device S3b, and the eighth switching device S3a, the delay parameters of the delay circuit 106 can be adjusted to adapt to different changes in sensor traces, motherboard traces, or other environmental factor changes, so that the signal transmission delay duration always conforms to the actual situation of the CPU signal sampling time, ensuring the matching of the SPI timing between the processor 202 and the sensor component 100 and improving the reliability of SPI communication.

[0077] In some embodiments of the present application, the delay circuit 106 includes a first delay mode, a second delay mode, a third delay mode, and a fourth delay mode with gradually increasing delays.

[0078] Among them, in the first delay mode, the fourth switching device S1a is turned on, and the third switching device S1b, the fifth switching device S2b, the sixth switching device S2a, the seventh switching device S3b, and the eighth switching device S3a are all turned off.

[0079] In the second delay mode, the third switching device S1b and the sixth switching device S2a are turned on, and the fourth switching device S1a, the fifth switching device S2b, the seventh switching device S3b, and the eighth switching device S3a are all turned off.

[0080] In the third delay mode, the third switching device S1b, the fifth switching device S2b, and the eighth switching device S3a are all turned on, and the fourth switching device S1a, the sixth switching device S2a, and the seventh switching device S3b are all turned off.

[0081] In the fourth delay mode, the third switching device S1b, the fifth switching device S2b, and the seventh switching device S3b are all turned on, and the fourth switching device S1a, the sixth switching device S2a, and the eighth switching device S3a are all turned off.

[0082] In some embodiments of the present application, the delay circuit 106 specifically includes 4 delay modes, specifically the first delay mode, the second delay mode, the third delay mode, and the fourth delay mode. Exemplarily, the delay setting of the first delay mode is recorded as 0, corresponding to an actual delay duration of 0 ns. The delay setting of the second delay mode is 1, corresponding to an actual delay duration of 2 ns. The delay setting of the third delay mode is 2, corresponding to an actual delay duration of 4 ns. The delay setting of the fourth delay mode is 3, corresponding to an actual delay duration of 6 ns.

[0083] Exemplarily, Figure 4 and Figure 5The waveform diagrams of the clock signal and the sensor sampling output signal in some embodiments of the present application are shown. During the prototype debugging, specific delay parameters are determined according to the actual measurement results of the prototype debugging. For example, as Figure 4 shown, during the anode debugging, the waveform as Figure 7 shown is measured, where the setup time is 9 ns and the hold time is 1 ns. At this time, if no measures are taken, due to the differences in chip consistency and temperature environment, the signal hold time of the high-level signal output by the prototype sensor is 1 ns, without sufficient margin, which may cause the fingerprint function of some prototypes to fail.

[0084] At this time, when the time delay is set to 1, 2, or 3, the corresponding hold time can be increased to 3 ns, 5 ns, or 7 ns, and the setup time is correspondingly shortened to 7 ns, 5 ns, or 3 ns, which can effectively increase the hold time, avoid the failure of the fingerprint function caused by insufficient hold time, and improve the stability and reliability of the fingerprint sensor.

[0085] For example, when the time delay is set to 2, that is, the third time delay mode, the waveform at this time is as Figure 5 shown, the hold time is 5 ns, and the signal hold time has sufficient margin. The sufficient hold time can ensure the success rate of SPI communication and reduce the possibility of fingerprint detection failure caused by SPI communication failure.

[0086] Exemplarily, Figure 6 、 Figure 7 、 Figure 8 and Figure 9 show the schematic diagrams of the switching states of the time delay circuit 106 in some embodiments of the present application, where the dotted arrows show the transmission paths of the SPI signals.

[0087] As Figure 6 shown, the time delay circuit 106 is in the first time delay mode, and the time delay is set to 0. At this time, the fourth switching device S1a is turned on, and other switching devices are turned off. At this time, the SPI signal does not pass through any of the buffers 1082, and the signal delay increases by 0 ns.

[0088] As Figure 7 shown, the time delay circuit 106 is in the second time delay mode, and the time delay is set to 1. At this time, the third switching device S1b and the sixth switching device S2a are turned on, and other switching devices are turned off. At this time, the SPI signal passes through 1 buffer 1082, that is, the first buffer Buffer1, and the signal delay increases by 2 ns.

[0089] As Figure 8As shown, the delay circuit 106 is in the third delay mode, and the delay is set to 2. At this time, the third switch device S1b, the fifth switch device S2b, and the eighth switch device S3a are turned on, and other switch devices are turned off. At this time, the SPI signal passes through 2 buffers 1082, that is, the first buffer Buffer1 and the second buffer Buffer2, and the signal delay increases by 4 ns.

[0090] As Figure 9 shown, the delay circuit 106 is in the fourth delay mode, and the delay is set to 3. At this time, the third switch device S1b, the fifth switch device S2b, and the seventh switch device S3b are turned on, and other switch devices are turned off. At this time, the SPI signal passes through all 3 buffers in sequence, and the signal delay increases by 6 ns.

[0091] Exemplarily, Figure 10 shows a waveform schematic diagram of the clock signal and the sensor sampling output signal in some embodiments of the present application. As Figure 10 shown, the CLK signal is fixed, and the theoretical sampling points are as Figure 10 shown. The dashed curves of different colors show the waveform diagrams of the MISO or MOSI signals in different delay modes.

[0092] When in the first delay mode, the delay is set to 0. At this time, the margin of the signal hold time is insufficient. The actual data level signal is high level, but the processor 202 samples a low level, resulting in communication failure.

[0093] When in the second delay mode, the delay is set to 1. At this time, the signal setup time and the signal hold time have sufficient margins. The actual data level signal is high level, and the processor 202 samples a high level, and the communication between the processor 202 and the sensor component 100 is successful.

[0094] When in the third delay mode, the delay is set to 2. At this time, the signal setup time and the signal hold time have sufficient margins. The actual data level signal is high level, and the processor 202 samples a high level, and the communication between the processor 202 and the sensor component 100 is successful.

[0095] When in the fourth delay mode, the delay is set to 3. At this time, the margin of the signal setup time is insufficient. The actual data level signal is high level, and the processor 202 may sample a low level, resulting in communication failure.

[0096] Exemplarily, Figure 11 shows a waveform schematic diagram of the clock signal and the sensor sampling output signal in some embodiments of the present application. As Figure 11As shown, the MOSI signal and the MISO signal are fixed, and the CLK signal is output with a time delay. Different dashed curves show the waveform diagrams of the CLK signal in different time delay modes, corresponding to the sampling points of four colors respectively.

[0097] When in the first time delay mode, the time delay is set to 0. At this time, the margin of the signal setup time is insufficient, and the actual data level signal is high level. The processor 202 may sample a low level, resulting in communication failure.

[0098] When in the second time delay mode, the time delay is set to 1. At this time, the signal setup time and the signal hold time have sufficient margins, the actual data level signal is high level, the processor 202 samples a high level, and the communication between the processor 202 and the sensor component 100 is successful.

[0099] When in the third time delay mode, the time delay is set to 2. At this time, the signal setup time and the signal hold time have sufficient margins, the actual data level signal is high level, the processor 202 samples a high level, and the communication is successful.

[0100] When in the fourth time delay mode, the time delay is set to 3. At this time, the signal setup time and the signal hold time have sufficient margins, the actual data level signal is high level, the processor 202 samples a high level, and the communication is successful.

[0101] In the embodiment of the present application, by adding a time delay circuit 106 to the sensor component 100 and reasonably setting different time delay modes of the time delay circuit 106, the problem of communication failure caused by insufficient setup time or hold time due to environmental factor changes, such as temperature changes and trace length changes, can be effectively solved. This method has low cost and requires few additional devices, ensuring that the signal setup time and the signal hold time have sufficient margins in the case of high-level signals, and improving the SPI transmission rate.

[0102] In some embodiments of the present application, Figure 12 shows a schematic circuit diagram of the time delay circuit 106 of some embodiments of the present application. As Figure 12 shown, the time delay circuit 106 includes at least two signal transmission cables 110 connected in parallel, and a ninth switching device 112 is provided on each signal transmission cable 110; among them, the lengths of at least two signal transmission cables 110 are different, and when the ninth switching device 112 provided on one signal transmission cable a among at least two signal transmission cables 110 is turned on, the ninth switching devices 112 provided on other signal transmission cables among at least two signal transmission cables 110, including the signal transmission cable b and the signal transmission cable c as Figure 12 shown, are all turned off.

[0103] In some embodiments of the present application, the delay circuit 106 includes at least two signal transmission cables 110 that are connected in parallel and have different cable lengths. Exemplarily, these signal transmission wires can be arranged in a coiled manner or in a serpentine arrangement. A ninth switching device 112 is provided on each signal transmission cable 110. At the same time point, among at least two ninth switching devices 112, only 1 ninth switching device 112 is conducting at the same time, and the other ninth switching devices 112 are all in the off state.

[0104] It can be understood that the longer the length of a signal transmission cable 110, the longer the distance the signal needs to travel in the cable and the longer the time it takes. Therefore, by switching signal transmission cables 110 of different lengths, the delay parameter of the delay circuit 106 can be adjusted to adapt to different changes in the sensor wiring, motherboard wiring, or other environmental factors, so that the signal transmission delay duration always conforms to the actual situation of the platform, ensuring the SPI timing match between the processor 202 and the sensor component 100 and improving the reliability of SPI communication.

[0105] In some embodiments of the present application, Figure 13 shows a circuit schematic diagram of the delay circuit 106 according to some embodiments of the present application. As Figure 13 shown, the delay circuit 106 includes:

[0106] At least two switching transistors 114 connected in parallel, each switching transistor 114 is serially connected to a tenth switching device 116; wherein, the switching speeds of at least two switching transistors 114 are different, and when the tenth switching device 116 serially connected to one of the at least two switching transistors 114, such as switching transistor d, is conducting, the tenth switching devices 116 serially connected to the other switching transistors among the at least two switching transistors 114, including those serially connected to switching transistor e and switching transistor f, are turned off.

[0107] In some embodiments of the present application, the delay circuit 106 includes at least two switching transistors 114 connected in parallel, and the switching speeds of these switching transistors 114 are all different. It can be understood that the faster the switching speed of a switching transistor 114, the faster the signal passes through the switching transistor 114. Conversely, the slower the switching speed of a switching transistor 114, the slower the signal transmission speed through the switching transistor 114.

[0108] Each switching transistor 114 is connected in series with a tenth switching device 116. At the same time point, only 1 tenth switching device 116 is conducting. Exemplarily, these signal transmission wires can be arranged in a coiled manner or in a serpentine arrangement. Each signal transmission cable 110 is provided with a ninth switching device 112. At the same time point, among at least two ninth switching devices 112, only 1 switching device is conducting, and the other tenth switching devices 116 are all in the off state.

[0109] By switching the switching transistors 114 with different switching speeds, the delay parameters of the delay circuit 106 can be adjusted to adapt to different changes in sensor traces, motherboard traces, or other environmental factor changes, so that the signal transmission delay duration always conforms to the actual situation of the platform, ensuring that the SPI timing between the processor 202 and the sensor assembly 100 matches, that is, each sampling time point of the processor 202 can fall within the high-level signal establishment time or hold time of the sensor assembly 100, improving the reliability of SPI communication.

[0110] In some embodiments of the present application, the delay circuit 106 is integrally provided in the sensor unit 102; or the delay circuit 106 is communicatively connected to the sensor unit.

[0111] In some embodiments of the present application, the delay circuit 106 can be integrated inside the sensor unit 102, that is, on the basis of the original fingerprint sensor circuit, an additional delay circuit 106 is added. By encapsulating the delay circuit 106 in this way, it is not necessary to change the motherboard structure of the original electronic device 200, and the sensor assembly 100 encapsulated with the delay circuit 106 can be applied to different electronic devices 200 without changing the original design, improving the versatility of the sensor assembly 100. The structure with the delay circuit integrated inside the sensor unit 102 has short traces, which can improve the accuracy of adjusting the signal transmission delay duration.

[0112] Figure 14 The structural schematic diagram of the sensor assembly 100 according to some embodiments of the present application is shown, as Figure 14 shown, the delay circuit 106 can also be independently provided, that is, the delay circuit 106 is separately provided between the fingerprint sensor and the processor 202 of the electronic device 200, which can avoid increasing the size and hardware cost of the fingerprint sensor and can improve the reliability of SPI communication in a low-cost manner.

[0113] In some embodiments of the present application, as Figure 1 and Figure 14 shown, the sensor unit 102 further includes:

[0114] The pixel matrix 1022 is used to convert the collected optical signal into an electrical signal;

[0115] The analog-to-digital conversion unit 1024 is electrically connected to the pixel matrix 1022. The analog-to-digital conversion unit 1024 is used to convert the electrical signal into a digital signal;

[0116] The data buffer 1026 is electrically connected to the analog-to-digital conversion unit 1024 and the communication port 104. The data buffer 1026 is used to cache the digital signal and send the digital signal to the communication port 104;

[0117] The digital controller 1028 is electrically connected to the pixel matrix 1022, the analog-to-digital conversion unit 1024, the data buffer 1026, the communication port 104, and the delay circuit 106. The digital controller 1028 is used to control the working timings of the pixel matrix 1022, the analog-to-digital conversion unit 1024, the data buffer 1026, the communication port 104, and the delay circuit 106.

[0118] In some embodiments of the present application, the sensor unit 102 includes a communication port 104 (SPI), a pixel matrix 1022 (Pixel Array), an analog-to-digital conversion unit 1024 (analog to digital converter, ADC), a data buffer 1026 (First Input First Output, FIFO), and a digital controller 1028 (Digital control).

[0119] Among them, the communication port 104 is used for communication with the processor 202, and data transmission is carried out through the SPI protocol. The pixel matrix 1022 can convert the optical signal collected by exposure into an electrical signal. The analog-to-digital conversion unit 1024 can convert the electrical signal converted by the pixel matrix 1022 into a digital signal to obtain the above data level signal. The data buffer 1026 can cache the digital signal converted by the analog-to-digital conversion unit 1024 and then transmit it to the communication port 104 one by one. The digital controller 1028 mainly controls the working timings of the above-mentioned various module units.

[0120] In some embodiments of the present application, as Figure 1 and Figure 14 shown, an electronic device 200 is provided, including a processor 202 and a sensor component 100 provided in any of the above embodiments. The sensor component 100 is communicatively connected to the processor 202. Therefore, the electronic device 200 can also achieve all the beneficial effects of the sensor component 100 provided in any of the above embodiments. To avoid repetition, it will not be elaborated here.

[0121] In the description of this specification, the descriptions with reference to the terms "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0122] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A sensor component, characterized in that, Comprising: A sensor unit, the sensor unit including a communication port for receiving or transmitting communication signals; A time delay circuit, the time delay circuit being communicatively connected to the communication port, the time delay circuit being configured to adjust the signal transmission delay duration of the communication signals received or transmitted by the sensor unit.

2. The sensor assembly according to claim 1, wherein, The sensor unit transmits a data level signal through the communication port, and the time delay circuit is configured to adjust the signal transmission delay duration of the data level signal.

3. The sensor assembly according to claim 1, wherein, The sensor unit receives a clock signal through the communication port, and the time delay circuit is configured to adjust the signal reception delay duration of the clock signal.

4. The sensor assembly according to claim 1, wherein The time delay circuit includes: At least two buffer units connected in series, the buffer unit including: A buffer; A first switching device, the first switching device being connected in series with the buffer; A second switching device, the second switching device being connected in parallel with the buffer; Wherein, when the first switching device is turned on, the second switching device is turned off; when the first switching device is turned off, the second switching device is turned on.

5. The sensor assembly according to claim 1, characterized in that, The time delay circuit includes: A first buffer; A second buffer, an input end of the second buffer being electrically connected to an output end of the first buffer; A third buffer, an input end of the third buffer being electrically connected to an output end of the second buffer; A third switching device, a first end of the third switching device being electrically connected to an input end of the first buffer; A fourth switching device, a first end of the fourth switching device being electrically connected to a second end of the third switching device, a second end of the fourth switching device being electrically connected to an output end of the third buffer; A fifth switching device, a first end of the fifth switching device being electrically connected to an output end of the first buffer, a second end of the fifth switching device being electrically connected to an input end of the second buffer; A sixth switching device, a first end of the sixth switching device being electrically connected to a first end of the fifth switching device, a second end of the sixth switching device being electrically connected to an output end of the third buffer; A seventh switching device, a first end of the seventh switching device being electrically connected to an output end of the second buffer, a second end of the seventh switching device being electrically connected to an input end of the third buffer; An eighth switching device, a first end of the eighth switching device being electrically connected to a first end of the seventh switching device, a second end of the eighth switching device being electrically connected to an output end of the third buffer.

6. The sensor assembly according to claim 5, wherein The time delay circuit includes a first time delay mode, a second time delay mode, a third time delay mode, and a fourth time delay mode with gradually increasing time delays; Wherein, in the first time delay mode, the fourth switching device is turned on, and the third switching device, the fifth switching device, the sixth switching device, the seventh switching device, and the eighth switching device are all turned off; In the second time delay mode, the third switching device and the sixth switching device are turned on, and the fourth switching device, the fifth switching device, the seventh switching device, and the eighth switching device are all turned off; In the third time delay mode, the third switching device, the fifth switching device, and the eighth switching device are all turned on, and the fourth switching device, the sixth switching device, and the seventh switching device are all turned off; In the fourth time delay mode, the third switching device, the fifth switching device, and the seventh switching device are all turned on, and the fourth switching device, the sixth switching device, and the eighth switching device are all turned off.

7. The sensor assembly according to claim 1, wherein The time delay circuit includes at least two signal transmission cables connected in parallel, and a ninth switching device is provided on each signal transmission cable; Among them, the lengths of at least two of the signal transmission cables are different, and when the ninth switching device provided on one of the at least two signal transmission cables is turned on, the ninth switching devices provided on the other signal transmission cables among the at least two signal transmission cables are all turned off.

8. The sensor assembly according to claim 1, characterized in that, The time delay circuit includes: At least two switching tubes connected in parallel, and each switching tube is connected in series with a tenth switching device; Among them, the switching speeds of at least two of the switching tubes are different, and when the tenth switching device connected in series with one of the at least two switching tubes is turned on, the tenth switching devices connected in series with the other switching tubes among the at least two switching tubes are all turned off.

9. The sensor assembly according to any one of claims 1 to 8, characterized in that The time delay circuit is arranged in the sensor unit; or the time delay circuit is communicatively connected to the sensor unit.

10. The sensor assembly according to any one of claims 1 to 8, characterized in that, The sensor unit further includes: A pixel matrix for converting the collected optical signal into an electrical signal; An analog-to-digital conversion unit electrically connected to the pixel matrix, and the analog-to-digital conversion unit is used to convert the electrical signal into a digital signal; A data buffer electrically connected to the analog-to-digital conversion unit and the communication port, and the data buffer is used to buffer the digital signal and send the digital signal to the communication port; A digital controller electrically connected to the pixel matrix, the analog-to-digital conversion unit, the data buffer, the communication port, and the time delay circuit, and the digital controller is used to control the working timings of the pixel matrix, the analog-to-digital conversion unit, the data buffer, the communication port, and the time delay circuit.

11. An electronic device, characterized in that, Including: A processor, the sensor assembly according to any one of claims 1 to 10; the sensor assembly is communicatively connected to the processor.

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