PWM (Pulse Width Modulation) adjusting circuit, PWM adjusting method, driving chip and display device

Abstract

The invention discloses a PWM adjusting circuit and method, a driving chip and a display device, and the circuit comprises a control signal generation module which is used for generating a plurality of control signals according to inputted gamma data; the signal adjusting module is connected with the control signal generating module and used for prolonging the effective level time of a first driving signal according to the multiple control signals so as to obtain a second driving signal, the gamma data has integer bits and decimal bits, and the integer bits and the decimal bits are different from each other. And the control signal generation module is used for controlling the relative delay between the first driving signal and the second driving signal according to the decimal digit of the gamma data, so that the display deviation caused by the decimal digit of the gamma data can be compensated, and the display brightness of the display device is consistent with the expectation.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a PWM adjustment circuit and method, a driving chip, and a display device. Background Art

[0002] In the display of an LED display screen, a row driving chip and a column driving chip are usually used to light up an LED array. In one case, the anodes of the LED array are connected to the outputs of the row driving chip through row lines, and the cathodes of the LED array are connected to the column driving chip through column lines. The column driving chip is often implemented by a constant current source chip, and the constant current source chip controls the on-time of the constant current source according to the display data, thereby determining the lighting time of the lamp beads on the corresponding column lines. More specifically, the row driving chip controls the lighting of the LEDs in each corresponding row according to the display data, and the column driving chip generates a corresponding PWM signal according to the display data, and within the effective time of the PWM signal, controls the column driving chip to output a constant current to the corresponding column line to light up the LED lamp beads. Among them, the lighting time of the LEDs on the corresponding column lines can be changed by adjusting the effective time of the PWM signal.

[0003] In existing LED display applications, the column driving chip generating a corresponding PWM signal according to the display data includes converting the display data into gamma data with more bits, but non-integer gamma data will be obtained during the conversion process. The general processing method in the prior art is to erase the non-integer part and convert the integer part of the gamma data into a PWM signal, which will cause a deviation between the actual display and the externally input display data. Summary of the Invention

[0004] In view of the above problems, an object of the present invention is to provide a PWM adjustment circuit and method, a driving chip, and a display device, so as to compensate for the display deviation caused by the decimal places of gamma data, and make the display brightness of the display device consistent with the expectation.

[0005] According to an aspect of the present invention, a PWM adjustment circuit is provided, including a control signal generation module for generating a plurality of control signals according to the input gamma data; a signal adjustment module connected to the control signal generation module for extending the effective level time of a first driving signal according to the plurality of control signals to obtain a second driving signal, wherein the gamma data has an integer part and a decimal part, and the control signal generation module is used to control the relative delay between the first driving signal and the second driving signal according to the decimal part of the gamma data.

[0006] Optionally, the signal adjustment module includes a plurality of adjustment units connected in series, each adjustment unit receiving a corresponding control signal, wherein the control signal is used to control the turning on or off of the corresponding adjustment unit, and the adjustment unit is used to extend the valid level time of the input signal by a preset time in the on state.

[0007] Optionally, each adjustment unit includes a plurality of inverters connected in series, each inverter including three input terminals and one output terminal. The first input terminal of the first-stage inverter receives the input signal of the adjustment unit, and the first input terminals of the second to last-stage inverters are connected to the output terminal of the previous-stage inverter; and an OR logic circuit for performing an OR operation on the input signal of the adjustment unit and the output signal of the last-stage inverter to obtain the output signal of the adjustment unit. Among them, for odd-stage inverters, its output terminal is connected to the ground terminal through a load capacitor and to the power supply voltage through a first switch, its second input terminal is connected to the power supply voltage through a current mirror, and its third input terminal is connected to the ground terminal through a second switch; for even-stage inverters, its second input terminal is connected to the power supply voltage and its third input terminal is connected to the ground terminal.

[0008] Optionally, the first switch is implemented by a PMOS transistor, and the second switch is implemented by an NMOS transistor.

[0009] Optionally, the even-stage inverter is implemented by a Schmitt inverter.

[0010] According to a second aspect of the present invention, a PWM adjustment method is provided, including generating a plurality of control signals according to input gamma data; extending the valid level time of the first driving signal according to the plurality of control signals to obtain a second driving signal, wherein the gamma data has an integer part and a fractional part, and the fractional part of the gamma data controls the relative delay between the first driving signal and the second driving signal.

[0011] According to a third aspect of the present invention, a driving chip is provided for driving a display panel, the display panel including a plurality of pixel units arranged in an array, the driving chip including a column driving circuit and a plurality of column lines, each column line connecting a column of pixel units, the column driving circuit being connected to the plurality of pixel units via the column lines, the column driving circuit including a plurality of PWM adjustment circuits as described above, each PWM adjustment circuit being connected to a corresponding column line to adjust the pixel units corresponding to each column line.

[0012] According to a fourth aspect of the present invention, a driving chip is provided for driving a display panel. The display panel includes a plurality of pixel units arranged in an array. The driving chip includes a column driving circuit and a plurality of column lines. Each column line is connected to a column of pixel units. The column driving circuit is connected to the plurality of pixel units via the column lines. The column driving circuit includes a PWM adjustment circuit. The PWM adjustment circuit includes: a control signal generation module for generating a plurality of control signals corresponding to each column line according to the gamma data corresponding to each column line; and a plurality of signal adjustment modules. Each signal adjustment module is connected to a corresponding column line. Each signal adjustment module is configured to extend the effective level time of a first driving signal corresponding to the column line it is connected to according to the plurality of control signals corresponding to the column line it is connected to, so as to obtain a second driving signal corresponding to the column line. Wherein, the gamma data has an integer part and a fractional part, and the control signal generation module is configured to control the relative delay between the first driving signal and the second driving signal according to the fractional part of the gamma data corresponding to each column line.

[0013] Optionally, each signal adjustment module includes a plurality of adjustment units connected in series. Each adjustment unit receives a corresponding control signal. Wherein, the control signal is used to control the turning on or off of the corresponding adjustment unit, and the adjustment unit is configured to extend the effective level time of the input signal by a preset time in the on state.

[0014] According to a fifth aspect of the present invention, a display device is provided, including the driving chip as described above.

[0015] The PWM adjustment circuit, adjustment method, driving chip and display device provided by the present invention include a control signal generation module for generating a plurality of control signals according to the input gamma data; a signal adjustment module connected to the control signal generation module for extending the effective level time of a first driving signal according to the plurality of control signals to obtain a second driving signal. Wherein, the gamma data has an integer part and a fractional part, and the control signal generation module is used to control the relative delay between the first driving signal and the second driving signal according to the fractional part of the gamma data, so as to compensate for the display deviation caused by the fractional part of the gamma data, and make the display brightness of the display device consistent with the expectation. Description of the Drawings

[0016] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features and advantages of the present invention will become clearer. In the drawings:

[0017] Figure 1 A schematic structural diagram of a display device according to an embodiment of the present invention is shown;

[0018] Figure 2 A schematic structural diagram of a PWM adjustment circuit according to an embodiment of the present invention is shown;

[0019] Figure 3 shows a circuit schematic diagram of an adjustment unit according to an embodiment of the present invention;

[0020] Figure 4 shows Figure 3 a circuit schematic diagram of the odd - stage inverters in

[0021] Figures 5a - 5b respectively show two different equivalent circuit diagrams of the adjustment unit according to an embodiment of the present invention;

[0022] Figure 6 shows a timing schematic diagram of the adjustment unit according to an embodiment of the present invention. Detailed implementation manners

[0023] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements or modules are denoted by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0024] It should be understood that in the following description, "circuit" may include a single or a combination of multiple hardware circuits, programmable circuits, state - machine circuits, and / or elements capable of storing instructions executed by a programmable circuit. When an element or circuit is said to be "connected to" another element or when an element or circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there may be intermediate elements, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0025] Meanwhile, in this patent specification and claims, certain terms are used to refer to specific components. Those of ordinary skill in the art should understand that hardware manufacturers may use different nouns to refer to the same component. This patent specification and claims do not use the difference in names as a way to distinguish components, but use the difference in functions of components as the criterion for distinction.

[0026] In this application, the term "semiconductor structure" refers to the structure formed in each step of manufacturing a storage device

[0027] In addition, it should be noted that in this text, relative terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0028] Figure 1 FIG. shows a schematic structural diagram of a display device according to an embodiment of the present invention.

[0029] As Figure 1 shown, the display device 10 includes a display panel 400, a row driving circuit 200, a column driving circuit 100, a timing control circuit 300, a plurality of row lines, and a plurality of column lines. The display panel 400 is composed of a plurality of pixel units arranged in an array. Pixel units in the same row are connected to the same row line, and pixel units in the same column are connected to the same column line. The row driving circuit 200 is connected to the pixel units in the display panel 400 via the row lines to provide a row scanning signal. The column driving circuit 100 is connected to the pixel units in the display panel 400 via the column lines to provide a PWM driving signal corresponding to grayscale data and / or gamma data. The timing control circuit 300 is connected to the row driving circuit 200 and the column driving circuit 100 to provide a clock signal GCLK.

[0030] Among them, the column driving circuit 100 includes a PWM adjustment circuit. The PWM adjustment circuit is used to adjust the driving signal PWM1 related to the integer part of the gamma data according to the decimal part of the gamma data, so as to change the effective level time (i.e., duty cycle) of the driving signal PWM1, thereby compensating for the display deviation caused by the decimal part of the gamma data, and making the display brightness of the display device consistent with the expectation. For the convenience of description, the driving signal before adjustment is hereinafter referred to as the first driving signal PWM1, and the adjusted driving signal is hereinafter referred to as the second driving signal PWM2. In addition, the following takes the effective level of the first driving signal PWM1 as a high level as an example for illustration.

[0031] It can be understood that the embodiments of the present invention do not specifically limit the light-emitting elements in the pixel units. The light-emitting elements in the pixel units can be set according to actual needs, such as LEDs, OLEDs, etc.

[0032] The display panel 400 includes at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electro-wetting display panel, and a small pitch display panel.

[0033] Figure 2 FIG. shows a schematic structural diagram of a PWM adjustment circuit according to an embodiment of the present invention.

[0034] Refer to Figure 2 , the PWM adjustment circuit 110 of the present application includes a control signal generation module 111 and a signal adjustment module 112. The control signal generation module 111 is configured to generate a plurality of control signals ctrl1-ctrln according to the input gamma data, and each control signal ctrl can be regarded as a one-bit binary digit. The signal adjustment module 112 is connected to the control signal generation module 111 and is configured to extend the effective level time of the first driving signal PWM1 according to the plurality of control signals ctrl1-ctrln to obtain a second driving signal PWM2. Among them, the gamma data has an integer part and a fractional part, and the control signal generation module 111 is configured to control the relative delay between the first driving signal PWM1 and the second driving signal PWM2 according to the fractional part of the gamma data. The first driving signal PWM1 is generated according to the integer part of the gamma data, and the second driving signal PWM2 is used to drive the pixel units in the display panel 400.

[0035] The signal adjustment module 112 includes a plurality of adjustment units 112a_1-112a_N connected in series in sequence, and the plurality of adjustment units 112a_1-112a_N correspond to the plurality of control signals ctrl1-ctrln one by one. Among them, each adjustment unit receives the corresponding control signal ctrl, and the control signal ctrl is used to control the on or off of the corresponding adjustment unit. The adjustment unit is configured to extend the effective level time of the input signal by a preset time in the on state and directly output the input signal as the output signal in the off state. In Figure 2 , the input signal of the adjustment unit 112a_1 is the first driving signal PWM1, the output signal of the adjustment unit 112a_N is the second driving signal PWM2, and the output signals of the adjustment units 112a_1-112a_(N-1) are PWM_1-PWM_N-1 in sequence.

[0036] Specifically, when the control signal ctrl corresponding to the adjustment unit is at the first electrical level, the adjustment unit is turned on, and the effective level time of its input signal is extended by a preset time; when the control signal ctrl corresponding to the adjustment unit is at the second electrical level, the adjustment unit is turned off, and its input signal is directly output as the output signal. Among them, when the gamma data is an integer, the value of its fractional part is 0, and at this time, multiple control signals ctrl1-ctrln are all at the second electrical level. The first electrical level can be a high level or a low level. Hereinafter, the case where the first electrical level is a high level is taken as an example for illustration.

[0037] It can be understood that the value of the fractional part of the gamma data is positively correlated with the extended time of the effective level time of the first driving signal PWM1. Specifically, the larger the value of the fractional part of the gamma data, the more the number of control signals ctrl among ctrl1-ctrln at the first electrical level, the longer the extended time of the effective level time of the first driving signal PWM1, and the longer the extended time of the light-emitting time of the light-emitting element in the pixel unit corresponding to the first driving signal PWM1. Thus, the display compensation for the fractional part discarded when the display data is converted into gamma data can be realized, and the display effect of the display device is improved.

[0038] Among them, the preset time ≤ the effective level time of the first driving signal PWM1 corresponding to the case where the value of the gamma data is 1 / N. Assume that the high level time of the first driving signal PWM1 corresponding to the case where the value of the gamma data is 1 is 50 ns, and the number of N is 10, then the preset time ≤ 5 ns.

[0039] Figure 3 The circuit schematic diagram of the adjustment unit according to an embodiment of the present invention is shown.

[0040] In the embodiment of the present application, the structure of each adjustment unit is the same. Taking one of the adjustment units as an example, it includes 2M - stage serially connected inverters and an OR logic circuit, where M is a positive integer, and the OR logic circuit is used to perform an OR operation on the input signal IN of the adjustment unit and the output signal OUT1 of the last - stage inverter INV2M to obtain the output signal OUT of the adjustment unit.

[0041] In this embodiment, the OR logic circuit is implemented by an OR gate. In another embodiment, the OR logic circuit can also be implemented by other structures or computer programs that can implement the OR operation.

[0042] In an embodiment of the present invention, each inverter includes three input terminals and one output terminal. The output terminal of the first-stage inverter is connected to the input terminal of the adjustment unit, and the output terminal of the last-stage inverter is connected to one input terminal of the OR logic circuit. The other input terminal of the OR logic circuit receives the input signal IN of the adjustment unit. Except for the first-stage inverter, the first input terminal of each inverter is connected to the output terminal of the previous-stage inverter. Among them, in the 2M-stage series-connected inverters, the output terminals of the odd-stage inverters are connected to the power supply voltage VCC through the first switch and to the ground terminal through the load capacitor. The third input terminal of the odd-stage inverters is connected to the ground terminal through the second switch, and the second input terminal of the odd-stage inverters is connected to the power supply voltage VCC through the current mirror, so that the rising speed of the rising edge of the signal flowing through the odd-stage inverters is greatly slowed down, and finally the effect of delay is achieved, and at the same time, the duty cycle can be ensured to be roughly unchanged. The second input terminal of the even-stage inverters is connected to the power supply voltage VCC, and the third input terminal of the even-stage inverters is connected to the ground terminal. Among them, both the first switch and the second switch are controlled by the corresponding control signal ctrl of the adjustment unit. The first switch is turned on when the control signal ctrl is at the second level, and the second switch is turned on when the control signal ctrl is at the first level. For example, the first switch is a PMOS switch, and the second switch is an NMOS switch.

[0043] In Figure 3 , the odd-stage inverters are the 1st, 3rd... (2M - 1)th stage inverters, and the even-stage inverters refer to the 2nd, 4th... 2Mth stage inverters. The first switches corresponding to the 1st, 3rd... (2M - 1)th stage inverters are switches S2, S4... S2M respectively, the corresponding second switches are switches S1, S3... S2M - 1 respectively, and the corresponding current mirrors are current mirrors I1, I3... IM respectively.

[0044] Figure 4 shows Figure 3 the circuit schematic diagram of the odd-stage inverter in

[0045] Refer to Figure 4 , the odd-stage inverter is implemented by a series-connected transistor MP and transistor MN. The control terminals of the transistor MP and MN are the input terminals of the inverter, and the drain terminals of the transistor MP and the transistor MN are the output terminals of the inverter. Among them, the transistor MP is a PMOS transistor, the transistor MN is an NMOS transistor, the source terminal of the transistor MP is connected to the power supply voltage VCC through the current mirror, and the source terminal of the transistor MN is connected to the ground terminal through the second switch.

[0046] In an example, the even-stage inverter also adopts Figure 4 the inverter shown in

[0047] In another example, the even-level inverters can also be Schmitt inverters to eliminate possible noise interference.

[0048] Figures 5a - 5b Two different equivalent circuit diagrams of the adjustment unit according to embodiments of the present invention are respectively shown.

[0049] When the control signal ctrl is at the first level, the first switch is turned off and the second switch is turned on, and the adjustment unit is equivalent to Figure 5a the circuit of. At this time, the input signal IN of the adjustment unit will become a signal OUT1 with an extended effective level time after passing through the 2M-level inverter. The signal OUT1 and the input signal IN are subjected to an OR operation to obtain the output signal OUT of the adjustment unit, so as to achieve the effect of extending the effective level time of the input signal IN.

[0050] Specifically, taking the adjustment unit using a four-level inverter as an example. Refer to Figure 6 , the rising edge of the signal Stage1_OUT obtained after the input signal IN enters the adjustment unit and passes through the first-level inverter will become slower. After passing through another ordinary inverter, a signal Stage2_OUT with a widened high level will be obtained. The rising edge of the signal Stage3_OUT obtained after the signal Stage2_OUT passes through the third-level inverter becomes slower again. After passing through another ordinary inverter, a signal Stage4_OUT with a second widened high level will be obtained. The signal Stage4_OUT and the input signal IN perform an OR logic operation, and finally an output signal OUT with a widened high level compared to the input signal IN is obtained.

[0051] When the control signal ctrl is at the second level, the first switch is turned on and the second switch is turned off, and the adjustment unit is equivalent to Figure 5b the circuit of. At this time, all odd-level inverters are truncated and forced to be set to 1, and the outputs of all even-level inverters are 0. The output of the OR logic circuit is the input signal IN. Therefore, the effect of directly outputting the input signal IN can be achieved, that is, the effect of not changing the high level time of the input signal IN.

[0052] In the above embodiment, the column driving circuit 100 includes a plurality of PWM adjustment circuits 110, and each PWM adjustment circuit 110 is connected to a column line to individually adjust the pixel units controlled by each column line.

[0053] In another embodiment of the present application, the PWM adjustment circuit 110 includes a control signal generation module and a plurality of signal adjustment modules. The structure of the signal adjustment module in this embodiment is the same as that of the signal adjustment module 112 described above. The control signal generation module generates a plurality of control signals corresponding to each column line according to the gamma data corresponding to each column line. The plurality of signal adjustment modules are connected to the plurality of column lines in a one-to-one correspondence. Each signal adjustment module is connected to the corresponding column line and extends the effective level time of the first driving signal PWM1 corresponding to the column line according to the plurality of control signals corresponding to the column line to obtain the second driving signal PWM2 corresponding to the column line. Among them, the gamma data has an integer part and a fractional part. The first driving signal PWM1 corresponding to each column line is generated according to the integer part of the gamma data corresponding to it, and the control signal generation module controls the relative delay between the first driving signal PWM1 and the second driving signal PWM2 according to the fractional part of the gamma data corresponding to each column line. That is, in this embodiment, a control signal generation module provides control signals ctrl to a plurality of signal adjustment modules, so as to realize the synchronous adjustment of all column lines. Those skilled in the art can adopt different circuit modes according to different requirements.

[0054] Regardless of which embodiment, each column line corresponds to a signal adjustment module 112, that is, each first driving signal PWM1 will enter an independent signal adjustment module 112, which makes the extended time of the effective level time of different first driving signals PWM1 different.

[0055] Furthermore, the present invention also provides a PWM adjustment method, including the following steps:

[0056] Generate a plurality of control signals according to the input gamma data;

[0057] Extend the effective level time of the first driving signal according to the plurality of control signals to obtain a second driving signal, wherein the gamma data has an integer part and a fractional part, the fractional part of the gamma data controls the relative delay between the first driving signal and the second driving signal, and the first driving signal is generated according to the integer part of the gamma data.

[0058] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to only the specific embodiments. Obviously, according to the above description, many modifications and variations can be made. The present specification selects and specifically describes these embodiments in order to better explain the principle and practical application of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The protection scope of the present invention should be defined by the scope defined by the claims of the present invention and their equivalents.

Claims

1. A PWM adjustment circuit, comprising: A control signal generation module, configured to generate a plurality of control signals according to input gamma data; A signal adjustment module, connected to the control signal generation module, configured to extend the effective level time of a first driving signal according to the plurality of control signals to obtain a second driving signal, wherein the gamma data has an integer part and a fractional part, and the control signal generation module is configured to control the relative delay between the first driving signal and the second driving signal according to the fractional part of the gamma data.

2. The adjustment circuit according to claim 1, wherein, The signal adjustment module includes: A plurality of adjustment units connected in series, each adjustment unit receiving a corresponding control signal, wherein the control signal is used to control the turning on or off of the corresponding adjustment unit, and the adjustment unit is configured to extend the effective level time of an input signal by a preset time in an on state.

3. The adjustment circuit according to claim 1, wherein Each adjustment unit includes: A plurality of inverters connected in series, each inverter including three input terminals and one output terminal, a first input terminal of a first-stage inverter receiving the input signal of the adjustment unit, and a first input terminal of a second-to-last-stage inverter being connected to the output terminal of the previous stage inverter; and An OR logic circuit, configured to perform an OR operation on the input signal of the adjustment unit and the output signal of the last-stage inverter to obtain the output signal of the adjustment unit, wherein, for an odd-stage inverter, its output terminal is connected to a ground terminal via a load capacitor and to a power supply voltage via a first switch, its second input terminal is connected to the power supply voltage via a current mirror, and its third input terminal is connected to the ground terminal via a second switch; for an even-stage inverter, its second input terminal is connected to the power supply voltage, and its third input terminal is connected to the ground terminal.

4. The adjustment circuit according to claim 3, wherein, The first switch is implemented by a PMOS transistor, and the second switch is implemented by an NMOS transistor.

5. The adjustment circuit according to claim 3, wherein, The even-stage inverter is implemented by a Schmitt inverter.

6. A PWM adjustment method, comprising: Generating a plurality of control signals according to input gamma data; Extending the effective level time of a first driving signal according to the plurality of control signals to obtain a second driving signal, wherein the gamma data has an integer part and a fractional part, and the fractional part of the gamma data controls the relative delay between the first driving signal and the second driving signal.

7. A driving chip for driving a display panel, the display panel including a plurality of pixel units arranged in an array, the driving chip including: A column driving circuit and a plurality of column lines, each column line being connected to a column of pixel units, the column driving circuit being connected to the plurality of pixel units via the column lines, the column driving circuit including a plurality of PWM adjustment circuits according to any one of claims 1-5, each PWM adjustment circuit being connected to a corresponding column line to adjust the pixel units corresponding to each column line.

8. A driving chip for driving a display panel, the display panel including a plurality of pixel units arranged in an array, the driving chip including: A column driving circuit and a plurality of column lines, each column line being connected to a column of pixel units, the column driving circuit being connected to the plurality of pixel units via the column lines, The column driving circuit includes a PWM adjustment circuit, and the PWM adjustment circuit includes: A control signal generation module for generating a plurality of control signals corresponding to each column line according to the gamma data corresponding to each column line; and A plurality of signal adjustment modules, each signal adjustment module being connected to a corresponding column line, and each signal adjustment module being configured to extend the effective level time of the first driving signal corresponding to the column line connected thereto according to the plurality of control signals corresponding to the column line connected thereto to obtain a second driving signal corresponding to the column line, wherein the gamma data has an integer part and a fractional part, and the control signal generation module is configured to control the relative delay between the first driving signal and the second driving signal according to the fractional part of the gamma data corresponding to each column line.

9. The driving chip according to claim 8, wherein, Each signal adjustment module includes: A plurality of adjustment units connected in series, each adjustment unit receiving a corresponding control signal, wherein the control signal is used to control the turning on or off of the corresponding adjustment unit, and the adjustment unit is configured to extend the effective level time of the input signal by a preset time in the on state.

10. A display device, comprising: A display panel; And A driving chip as described in any one of claims 7-9, the driving chip being configured to drive the display panel.

11. The display device according to claim 10, wherein, The display panel includes at least one of a liquid crystal display panel, a micro light emitting diode display panel, a light emitting diode display panel, a mini light emitting diode display panel, a quantum dot light emitting diode display panel, an organic light emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electro-wetting display panel, and a small pitch display panel.

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