Driving circuit, display device and driving method

Abstract

The embodiment of the invention provides a driving circuit, a display device and a driving method, relates to the technical field of display, solves the problem of voltage change in a GOA circuit, and improves the display effect of a display. According to the specific scheme, the driving circuit comprises a plurality of array driving scanning GOA circuits, and each GOA circuit comprises a register circuit, an output circuit, a frequency control circuit and a reset circuit. And the output circuit is coupled with the register circuit, and is configured to generate a grid scanning signal in response to the voltage of the pull-up node and the voltage of the pull-down node of the register circuit, and output the grid scanning signal to a pixel circuit corresponding to the GOA circuit. The frequency control circuit and the output circuit are coupled to the first node, and are configured to receive a first frequency control signal to control the frequency of the gate scanning signal. The reset circuit and the output circuit are coupled to the first node and configured to control a voltage of the first node based on a reset signal. The embodiment of the invention is used for the process that the driving circuit sends the grid scanning signal to the pixel circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of display technologies, and in particular, to a driving circuit, a display device, and a driving method. Background Art

[0002] Currently, in order to improve the user's video or game experience, an organic light-emitting diode (OLED) display screen requires a very high refresh rate (e.g., 120 hertz (Hz)). A high refresh rate results in high power consumption of the display screen and reduced battery life. To reduce power consumption and improve battery life, existing OLED display screens use low-temperature polycrystalline oxide (LTPO) technology, using a higher refresh rate in video or game scenes and a lower refresh rate (e.g., 1 Hz) in static images, thereby effectively saving power.

[0003] Among them, a gate driven on array (GOA) circuit can control the refresh rate of a display. By adding a frequency control circuit to the GOA circuit, the refresh rate of a local display area can be reduced. When the GOA circuit enables the local refresh rate reduction function, the internal voltage change of the GOA circuit affects the display effect of the display. Summary of the Invention

[0004] Embodiments of the present application provide a driving circuit, a display device, and a driving method, which improve the problem of internal voltage change of the GOA circuit and enhance the display effect of the display.

[0005] To achieve the above object, the embodiments of the present application adopt the following technical solutions.

[0006] In a first aspect, embodiments of the present application provide a driving circuit. The driving circuit includes a plurality of gate driven on array (GOA) circuits. Each GOA circuit includes a register circuit, an output circuit, a frequency control circuit, and a reset circuit. The output circuit is coupled to the register circuit and is configured to generate a gate scan signal in response to the voltages of the pull-up node and the pull-down node of the register circuit, and output the gate scan signal to the pixel circuit corresponding to the GOA circuit. The frequency control circuit is coupled to the output circuit at a first node and is configured to receive a first frequency control signal to control the frequency of the gate scan signal. The reset circuit is coupled to the output circuit at the first node and is configured to control the voltage of the first node based on a reset signal.

[0007] Therefore, in the driving circuit provided by the embodiments of the present application, when the GOA circuit enables the local refresh frequency reduction function, the first node is conducted with the first frequency control signal. At this time, the voltage of the first node is different values, that is, it may be a positive value or a negative value. The driving circuit can control the voltage of the first node through the reset circuit to maintain the voltage of the first node at the same value, which can avoid the influence of the voltage change of the first node on the display effect of the display, improve the stability of the GOA circuit, and improve the display effect of the display.

[0008] In a possible design, the reset circuit includes a first transistor. The first end of the first transistor is coupled to the first node, the second end of the first transistor is coupled to the first voltage source, and the gate of the first transistor is used to receive the reset signal. The reset circuit is specifically configured to control the voltage of the first node through the voltage output by the first voltage source when the reset signal controls the first transistor to conduct. Therefore, the reset circuit can control the voltage of the first node through the voltage output by the first voltage source to maintain the voltage of the first node at the same value, which can avoid the influence of the voltage change of the first node on the display effect of the display, improve the stability of the GOA circuit, and improve the display effect of the display.

[0009] In a possible design, the reset circuit further includes a second transistor. The first end of the second transistor is coupled to the first end of the first transistor, the second end of the second transistor is coupled to the first node, and the gate of the second transistor is coupled to the gate of the first transistor. Therefore, adding a second transistor between the first node and the first transistor can reduce the cross voltage between the first end and the second end of the first transistor and improve the reliability of the GOA circuit. In addition, the first transistor and the second transistor adopt a common gate structure, which can improve the reliability of the transistor.

[0010] In a possible design, the frequency control circuit includes a third transistor. The first end of the third transistor is coupled to the register circuit, the second end of the third transistor is coupled to the output circuit, and the gate of the third transistor is used to receive the second frequency control signal. The frequency control circuit is further configured to receive the first frequency control signal and the second frequency control signal to control the frequency of the gate scan signal. Therefore, by jointly controlling the frequency of the gate scan signal through the first frequency control signal and the second frequency control signal, the GOA circuit can reduce the frequency of the clock signal during low-frequency driving to further reduce the power consumption of the driving circuit.

[0011] In a possible design, the output circuit further includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a first capacitor. The gate of the fourth transistor and the register circuit are coupled to the pull-up node. The first end of the fourth transistor is coupled to the gate high-voltage source. The second end of the fourth transistor is coupled to the first end of the fifth transistor. The second end of the fifth transistor is coupled to the gate low-voltage source. The gate of the fifth transistor and the register circuit are coupled to the pull-down node. The pull-up node is further coupled to the first end of the sixth transistor. The gate of the sixth transistor is coupled to the first node. The second end of the sixth transistor is coupled to the gate of the seventh transistor. The first end of the seventh transistor is coupled to the gate high-voltage source. The second end of the seventh transistor is coupled to the first end of the eighth transistor. The second end of the eighth transistor is coupled to the gate low-voltage source. The gate of the eighth transistor is coupled to the pull-down node. The first end of the first capacitor is coupled to the gate of the sixth transistor. The second end of the first capacitor is coupled to the second end of the sixth transistor.

[0012] In a possible design, the output circuit further includes a ninth transistor. The first end and the second end of the ninth transistor are both coupled to the first end of the fifth transistor. The gate of the ninth transistor is coupled to the pull-down node. Thus, the output circuit can reduce the rising edge step of the cascaded signal through the capacitive coupling effect of the ninth transistor and optimize the quality of the cascaded signal.

[0013] In a possible design, the output circuit further includes a tenth transistor. The first end of the tenth transistor is coupled to the pull-down node. The second end of the tenth transistor is coupled to the gate of the eighth transistor. The gate of the tenth transistor is coupled to the first node. Thus, the tenth transistor can prevent the eighth transistor from being accidentally turned on and improve the stability of the GOA circuit.

[0014] In a possible design, the output circuit further includes an eleventh transistor. The first end of the eleventh transistor is coupled to the gate high-voltage source. The second end of the eleventh transistor is coupled to the second end of the sixth transistor. The gate of the eleventh transistor is coupled to the gate of the eighth transistor. Thus, the voltage drop of the gate scan signal can be accelerated through the eleventh transistor.

[0015] In a second aspect, an embodiment of the present application provides a display device, which includes a pixel array, a peripheral driving circuit, and a plurality of sequentially cascaded driving circuits. The peripheral driving circuit includes at least one gate high-voltage source, and the at least one gate high-voltage source is coupled to a plurality of gate high-voltage signal lines. Adjacent driving circuits among the plurality of sequentially cascaded driving circuits are respectively coupled to different gate high-voltage signal lines.

[0016] Therefore, in the display device provided by the embodiments of the present application, the high gate voltage source is coupled to multiple high gate voltage signal lines, which can further reduce the resistance of the high gate voltage signal lines and optimize the signal quality. In addition, by coupling adjacent driving circuits to different high gate voltage signal lines respectively, voltage perturbation of the high gate voltage between adjacent rows can be reduced.

[0017] In a possible design, the peripheral driving circuit further includes a level conversion circuit, and at least one high gate voltage source includes a first high gate voltage source and a second high gate voltage source. The output circuits of multiple cascaded driving circuits are coupled to the first high gate voltage source, and the register circuits of multiple cascaded driving circuits and the level conversion circuit are coupled to the second high gate voltage source. Therefore, by providing the high gate voltage to the output circuits of the driving circuits only through the first high gate voltage source, and providing the high gate voltage source to other circuits through the second high gate voltage source, the stability of the gate scan signal output by the output circuits can be improved, and signal perturbation can be reduced.

[0018] In a possible design, the driving current of the first high gate voltage source is greater than that of the second high gate voltage source. Therefore, the first high gate voltage source can provide a larger driving current to the output circuits to ensure the stability of the gate scan signal output by the output circuits and reduce signal perturbation.

[0019] In a possible design, at least one high gate voltage source includes a first high gate voltage source and a second high gate voltage source. The first transistor in the output circuits of adjacent driving circuits is coupled to the high gate voltage signal line of the first high gate voltage source, and other transistors in the output circuits of adjacent driving circuits are coupled to the high gate voltage signal line of the second high gate voltage source. Therefore, the stability of the gate scan signal output by the output circuits can be improved, and signal perturbation can be reduced.

[0020] In a possible design, the output terminal of the first high gate voltage source is coupled to multiple parallel voltage stabilizing capacitors.

[0021] In a possible design, the first signal line of each output circuit is coupled to the corresponding high gate voltage signal line, and the length of the first signal line is such that each first signal line overlaps with multiple high gate voltage signal lines. Therefore, the impedances of multiple first signal lines are the same, and the difference in high gate voltage can be eliminated.

[0022] In a possible design, the high gate voltage signal line of the first high gate voltage source includes at least two metal layers, and the at least two metal layers are connected through at least one via. Therefore, the impedance on the high gate voltage signal line of the first high gate voltage source can be reduced.

[0023] In a third aspect, an embodiment of the present application provides a driving method, which is applied to a driving circuit. The driving circuit includes a plurality of GOA circuits. Each GOA circuit includes: a register circuit, an output circuit, a frequency control circuit, and a reset circuit. The frequency control circuit, the output circuit, and the reset circuit are coupled to a first node. The driving method includes: the output circuit generates a gate scanning signal in response to the voltages of the pull-up node and the pull-down node of the register circuit, and outputs the gate scanning signal to the pixel circuit corresponding to the GOA circuit. The frequency control circuit receives a first frequency control signal to control the frequency of the gate scanning signal. The reset circuit controls the voltage of the first node based on a reset signal.

[0024] In a possible design, the frequency control circuit receives a first frequency control signal to control the frequency of the gate scanning signal, including: the frequency control circuit receives a first frequency control signal and a second frequency control signal to control the frequency of the gate scanning signal.

[0025] In a fourth aspect, an embodiment of the present application provides a display device, which includes a processor and the driving circuit of the first aspect, and the driving circuit is coupled to the processor.

[0026] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, which includes computer instructions. When the computer instructions run on an electronic device, the electronic device is caused to execute the driving method in any possible implementation manner of the above third aspect.

[0027] In a sixth aspect, an embodiment of the present application provides a computer program product. When the computer program product runs on a computer or a processor, the computer or the processor is caused to execute the display driving method in any possible implementation manner of the above third aspect.

[0028] It can be understood that any of the above provided driving circuits, display devices, display apparatuses, computer-readable storage media, or computer program products can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods, and will not be elaborated here.

[0029] These aspects or other aspects of the present application will be more clearly understood in the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a structural diagram of a display device provided by an embodiment of the present application;

[0031] Figure 2 is a structural diagram of a pixel circuit provided by an embodiment of the present application;

[0032] Figure 3 is a timing diagram of a pixel circuit provided by an embodiment of the present application;

[0033] Figure 4 The structural diagram of a gate driving circuit provided by an embodiment of the present application;

[0034] Figure 5 The timing diagram of the gate scanning signal of a gate driving circuit provided by an embodiment of the present application;

[0035] Figure 6 The structural diagram of a peripheral driving circuit provided by an embodiment of the present application;

[0036] Figure 7 The structural diagram of a multi-stage GOA circuit provided by an embodiment of the present application;

[0037] Figure 8 The timing diagram of a multi-stage GOA circuit provided by an embodiment of the present application;

[0038] Figure 9 The timing diagram of another multi-stage GOA circuit provided by an embodiment of the present application;

[0039] Figure 10 The partition schematic diagram of a display panel provided by an embodiment of the present application;

[0040] Figure 11 The timing diagram of a driving circuit at different refresh cycles provided by an embodiment of the present application;

[0041] Figure 12 The voltage change diagram of an N1 node provided by an embodiment of the present application;

[0042] Figure 13 The waveform diagram of a signal provided by an embodiment of the present application;

[0043] Figure 14 The structural diagram of a driving circuit provided by an embodiment of the present application;

[0044] Figure 15 The timing diagram of another driving circuit provided by an embodiment of the present application;

[0045] Figure 16 The structural diagram of another driving circuit provided by an embodiment of the present application;

[0046] Figure 17 The structural diagram of yet another driving circuit provided by an embodiment of the present application;

[0047] Figure 18 The structural diagram of yet another driving circuit provided by an embodiment of the present application;

[0048] Figure 19 The structural diagram of yet another driving circuit provided by an embodiment of the present application;

[0049] Figure 20 Structural diagram of another driving circuit provided by an embodiment of the present application;

[0050] Figure 21 Timing diagram of another driving circuit provided by an embodiment of the present application;

[0051] Figure 22 Waveform diagram of a gate scanning signal provided by an embodiment of the present application;

[0052] Figure 23 Structural diagram of another display device provided by an embodiment of the present application;

[0053] Figure 24 Structural diagram of another display device provided by an embodiment of the present application;

[0054] Figure 25 Structural diagram of another display device provided by an embodiment of the present application;

[0055] Figure 26 Structural diagram of another display device provided by an embodiment of the present application;

[0056] Figure 27 Schematic diagram of a gate high - voltage signal line provided by an embodiment of the present application;

[0057] Figure 28 Flowchart of a driving method provided by an embodiment of the present application;

[0058] Figure 29 Timing diagram of another driving circuit provided by an embodiment of the present application;

[0059] Figure 30 Timing diagram of another driving circuit provided by an embodiment of the present application;

[0060] Figure 31 Timing diagram of another driving circuit provided by an embodiment of the present application;

[0061] Figure 32 Timing diagram of another driving circuit provided by an embodiment of the present application. Detailed implementation manners

[0062] The following will describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, unless otherwise specified, " / " means "or". For example, A / B may mean A or B; "and / or" herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B may mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present application, "a plurality of" means two or more than two.

[0063] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this embodiment, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0064] The embodiments of the present application use words such as "first" and "second" to distinguish objects with similar names, functions, or roles. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order. The term "coupled" is used to indicate an electrical connection, including directly connected through a wire or a connection terminal or indirectly connected through other devices. Therefore, "coupled" should be regarded as a broad sense of electronic communication connection.

[0065] It should be noted that in the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Exactly speaking, using words such as "exemplary" or "for example" aims to present relevant concepts in a specific manner.

[0066] In the circuit provided by the embodiments of the present disclosure, the first node, the second node, and the third node do not represent actually existing components, but represent the convergence points of relevant electrical connections in the circuit diagram. That is to say, these nodes are nodes equivalent to the convergence points of relevant electrical connections in the circuit diagram.

[0067] In the embodiments of the present application, the transistor may be a thin film transistor (TFT), such as an amorphous silicon (a-Si:H) TFT, a low temperature polycrystalline silicon (LTPS) TFT, and an amorphous oxide semiconductor (AOS) TFT. The transistors are divided into two types: N (negative) type transistors and P (positive) type transistors. The transistor includes a source, a drain, and a gate. By controlling the magnitude of the voltage input to the gate of the transistor, the conduction or cutoff of the transistor can be controlled. When the transistor is conducting, the source and the drain are conducting, generating a conduction current. Moreover, when the magnitude of the gate voltage of the transistor is different, the magnitude of the conduction current generated between the source and the drain is also different. When the transistor is cutoff or turned off, the source and the drain are not conducting, and only a very small off-state current is generated. In the embodiments of the present application, the source of the transistor is referred to as the first terminal, and the drain is referred to as the second terminal; or, the drain is referred to as the first terminal, and the source is referred to as the second terminal. In addition, the N-type transistor conducts when the level of the gate is high, the first terminal and the second terminal are conducting, and a conduction current is generated between the first terminal and the second terminal. The N-type transistor is cutoff when the level of the gate is low, the first terminal and the second terminal are not conducting, and only a very small off-state current is generated. The P-type transistor conducts when the level of the gate is low, the first terminal and the second terminal are conducting, and a conduction current is generated. The P-type transistor is cutoff when the level of the gate is high, the first terminal and the second terminal are not conducting, and only a very small off-state current is generated.

[0068] The technical solutions provided by the embodiments of the present application can be applied to various electronic devices including display devices. Such electronic devices are, for example, consumer electronic products with display functions, home electronic products, vehicle-mounted electronic products, and financial electronic devices. Consumer electronic products such as mobile phones, tablets, laptop computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronic products such as smart door locks, televisions, remote controls, refrigerators, small household appliances for charging (e.g., soybean milk makers, floor cleaning robots), etc. Vehicle-mounted electronic products such as vehicle navigation devices, vehicle-mounted high-density digital video discs (DVDs), etc. Financial electronic devices such as automated teller machines (ATMs), electronic devices for self-service business handling, etc. The embodiments of the present application do not impose special restrictions on the specific forms of the above-mentioned electronic devices.

[0069] For ease of understanding, the specific structure of the display device will be introduced first below.

[0070] As Figure 1 shown, Figure 1 FIG. 10 is a structural diagram of a display device provided by an embodiment of the present application. The display device 10 may include an active area (AA) 100, a non-active area (NA) 200, a data control circuit 300, and a peripheral driving circuit 400. Among them, the active area 100 and the non-active area 200 form the display panel 11. The active area 100 is the pixel light-emitting area, and the non-active area 200 is the area in the display panel 11 that does not emit light. The data control circuit 300 is configured to receive external image information and then provide data signals (DS) to the display panel 11. The data signals are digital signals that determine the pixel light-emitting current in pixel circuit programming. The peripheral driving circuit 400 is configured to provide multiple sets of control signals (CS) and pixel voltages (PV) required for multiple display panels.

[0071] Specifically, the effective display area 100 may include a plurality of pixels arranged in an array form (i.e., a pixel array), a plurality of data lines, and a plurality of gate scan lines. Each data line is coupled to a plurality of pixels in the Y direction, and each gate scan line is coupled to a plurality of pixels in the X direction. Each pixel is coupled to a data line, a gate scan line, a power supply voltage (positive power supply voltage (ELVDD) and negative power supply voltage (ELVSS)) line, and an initialization voltage (VINI) line. A pixel can be understood as a pixel circuit, and the pixel circuit may include a light-emitting diode and a circuit unit for controlling the light-emitting diode. The light-emitting diode can be an OLED, a quantum dot light-emitting diode (QLED), a mini LED, or a micro LED. Among them, the circuit unit executes a specific pixel circuit timing to control the current value from the positive power supply voltage (ELVDD) to the negative power supply voltage (ELVSS), and the light-emitting diode can emit light with a specific brightness at a specific current value.

[0072] The non-effective display area 200 is located on one or both sides of the effective display area 100 and may include a plurality of gate driving circuits. Since the GOA technology is adopted in the non-effective display area 200, the gate driving circuit is also called a GOA circuit. After receiving a control signal, the GOA circuit can generate a plurality of shift pulse signals output row by row, that is, a plurality of gate scan signals. Each gate signal line (gate lines, GL) is coupled to one or more rows of pixel circuits, and the gate scan signals are output row by row to control the thin-film transistor (TFT) in the pixel circuit to be turned on or off row by row. Continuing to refer to Figure 1 , the non-effective display area 200 may include k gate driving circuits, namely the first gate driving circuit, the second gate driving circuit, the third gate driving circuit,..., the kth gate driving circuit. Among them, each gate driving circuit outputs a gate scan signal for controlling multiple rows of pixel circuits. The gate scan signal for controlling the first row of pixel circuits is, for example, S1_1, S2_1, S3_1,..., Sk_1, and the gate scan signal for controlling the nth row of pixel circuits is, for example, S1_n, S2_n, S3_n,..., Sk_n.

[0073] The data control circuit 300 is used to provide multiple groups of data signals. The data control circuit 300 transmits the data signals to the pixel circuits in the display panel 11 through multiple data lines, so that the pixel circuits can work normally. Among them, the number of multiple data lines can be the same as the total number of columns of the pixel array composed of pixel circuits.

[0074] The peripheral driving circuit 400 is used to provide multiple sets of control signals, which may include a start frame signal (start voltage signal, STV), a clock signal (clock signal, CLK), a gate high-level voltage (gate high-level voltage, VGH), and a gate low-level voltage (gate low-level voltage, VGL). After receiving the control signals, the gate driving circuit generates corresponding gate scanning signals with high and low levels. In addition, the peripheral driving circuit 400 is also used to provide multiple sets of pixel voltages, which may include a power supply voltage (VDD and VSS) and an initialization voltage. The peripheral driving circuit 400 transmits the pixel voltage values to the pixel circuits in the display panel 11 through multiple signal lines, enabling the pixel circuits to operate normally.

[0075] After the display panel is loaded with the driving timing and voltage settings, it can configure the brightness and refresh rate of the pixel circuits. The driving timing is a set of gate control signals, including multiple signal waveforms with voltage changes over time. The refresh rate is the number of times the display panel can be refreshed per second. Each time the display panel is refreshed, the data voltage needs to be written from the pixel circuits in the first row to the pixel circuits in the last row. Limited by the data voltage writing speed, there is a maximum refresh rate N for the display panel, that is, only N frames of images will be refreshed per second, and the time for one frame of image is 1 / N seconds. At the maximum refresh rate, the pixel circuits always operate in the data refresh cycle, which contains N refresh frames per second. The refresh frame is the time for one frame when the data voltage is updated. During the refresh frame, the pixel circuits in the display panel execute the refresh frame driving timing. Taking the maximum refresh rate of 120Hz as an example, the display panel is refreshed 120 times per second. Assuming the cycle time for the display panel to be refreshed once is T, then T = 1 / 120s, approximately 8.333ms. At a low refresh rate, such as 1Hz, the display panel is refreshed once per second, including 1 refresh frame and 119 hold frames. Each frame time is still divided by 8.333ms. Assuming the display panel has a total of M rows of pixels in the effective display area, the charging time or refresh time H for one row of pixels satisfies the following relationship: H = T / M. Assuming M = 2844 and T = 8.333ms, then H = 8.333 / 2844ms, approximately 2.93us. The time of 1H can be flexibly set according to the number of display rows, the refresh rate, and the vertical blanking interval time, etc. The specific time length of 1H is not limited in the embodiments of this application.

[0076] Based on the Figure 1 display device shown below, the pixel circuit, the gate driving circuit, and the peripheral driving circuit will be further introduced.

[0077] Among them, the pixel circuit can adopt LTPO technology, such as Figure 2As shown in (a) therein, the pixel circuit may include a first transistor T1, a second transistor T2, a driving transistor Td, a capacitor C1, a light-emitting diode D1, a first driving circuit module, a second driving circuit module, and a third driving circuit module. Among them, the first transistor T1 is an N-type transistor, and the first transistor T1 may be indium gallium zinc oxide (IGZO). The second transistor T2 is a P-type transistor, and the second transistor T2 may be low temperature poly-silicon (LTPS). The gate scan signal of the first transistor T1 is S1, and the gate scan signal of the second transistor T2 is S2.

[0078] In a possible example, as Figure 2 shown in (b) therein, the first driving circuit module may include a fifth transistor T5 and a sixth transistor T6, the second driving circuit module includes a third transistor T3 and a seventh transistor T7, and the third driving circuit module includes a fourth transistor T4. This pixel circuit may also be referred to as an 8T1C circuit. Among them, the gate scan signal of the third transistor T3 is S3, the gate scan signal of the fourth transistor T4 is S4, the gate scan signal of the fifth transistor T5 is S5, and the gate scan signals of the sixth transistor T6 and the seventh transistor T7 are emission signals (EM). One end of the third transistor T3 is used to input a first initialization voltage (VINI1), one end of the fourth transistor T4 is used to input a second initialization voltage (VINI2), one end of the fifth transistor T5 is used to input a third initialization voltage (VINI3), and one end of the second transistor T2 is used to input a data signal (DATA). It can be understood that the structure of the pixel circuit may also be in other forms, such as 6T1C, 7T1C, 9T2C, and 9T3C, etc. The embodiments of the present application do not limit the specific structure of the pixel circuit.

[0079] The switching of the transistors in the pixel circuit is determined by the gate scan signal. The timing diagrams of S1 and S2 in the j-th refresh period and the j + 1-th refresh period are as Figure 3 shown. Among them, S1 is a positive waveform with a certain length during the non-emitting time, and the time is any time such as 2H or 6H. S2 is a negative waveform with a certain length during the non-emitting time, and the time can be any time such as 1H, 2H, or 0.7H. In order to ensure that the data signal can be fully written into the gate of the driving transistor, the pulse width of S1 is longer than that of S2. That is to say, the first transistor T1 is turned on earlier and turned off later than the second transistor T2.

[0080] Among them, the gate driving circuit may include multiple levels of circuit units, as Figure 4 shown, Figure 4The structural diagram of a gate driving circuit provided by an embodiment of the present application. Figure 4 In the figure, n - stage circuit units are shown, namely circuit unit 1, circuit unit 2, circuit unit 3, ……, circuit unit n. Circuit unit 1 outputs a gate scanning signal out_1, circuit unit 2 outputs a gate scanning signal out_2, circuit unit 3 outputs a gate scanning signal out_3, and circuit unit n outputs a gate scanning signal out_n. out_1 to out_n respectively correspond to the pixel circuits of the first row to the nth row. That is to say, one row of gate scanning signals can control one row of pixel circuits. Additionally, one row of gate scanning signals can also control two rows of pixel circuits. For example, the gate scanning signal out_1 can correspond to the pixel circuits of the first row and the second row, the gate scanning signal out_2 can correspond to the pixel circuits of the third row and the fourth row, and so on. The gate scanning signal out_n can correspond to the pixel circuits of the (2n - 1)th row and the 2nth row.

[0081] Continue to refer to Figure 4 , after receiving the start frame signal (STV), the first clock signal (CLK_1), the second clock signal (CLK_2), the gate high voltage (VGH), and the gate low voltage (VGL) generated by the peripheral driving circuit, circuit unit 1 responds to generate the gate scanning signals out_1 to out_n that are output row by row. Among them, circuit unit 1 is coupled to the start frame signal line, and other circuit units are respectively coupled to the output ends of the previous - stage circuit units. The gate scanning signal output by the previous - stage circuit unit serves as the start signal for the next - stage circuit unit. For example, the input end of circuit unit 2 is coupled to the output end of circuit unit 1, and the gate scanning signal out_1 output by circuit unit 1 serves as the input signal of circuit unit 2. Or, the input end of circuit unit 3 is coupled to the output end of circuit unit 2, and the gate scanning signal out_2 output by circuit unit 2 serves as the input signal of circuit unit 3. Additionally, each stage of circuit unit is connected to CLK_1 and CLK_2 in a fixed order. For example, circuit unit 1 is connected to CLK_1, CLK_2; circuit unit 2 is connected to CLK_2, CLK_1; circuit unit 3 is connected to CLK_1, CLK_2, etc.

[0082] As Figure 5 shown, Figure 5 is Figure 4 the timing diagram of the gate scanning signals of the gate driving circuit in Figure 5Specifically shown therein is a timing diagram of a start frame signal (STV), a first clock signal (CLK_1), a second clock signal (CLK_2), and gate scan signals out_1 to out_n. Among them, the gate scan signal is a square wave signal with high and low voltage switching. The high voltage value of the gate scan signal is equal to the voltage value of the gate signal high voltage (VGH1), and the low voltage value of the gate scan signal is equal to the voltage value of the gate signal low voltage (VGL1). The interval time between each row of gate scan signals can be 1H, 2H, 4H, or any equal time amount. The gate driving circuit can output a positive voltage pulse waveform row by row to achieve row-by-row scanning and voltage writing of the pixel circuit in the AA region.

[0083] Among them, the structural diagram of the peripheral driving circuit is as Figure 6 shown. The peripheral driving circuit can generate a control signal and a pixel voltage signal. Specifically, the peripheral driving circuit can include multiple voltage regulators, and the multiple voltage regulators can be a gate high voltage regulator, a gate low voltage regulator, an ELVSS voltage regulator, an ELVDD voltage regulator, and a VINI voltage regulator, etc. The gate high voltage regulator can generate VGH1 and VGH2, the gate low voltage regulator can generate VGL1 and VGL2, and the VINI voltage regulator can generate VINI1, VINI2, ……, VININ. The voltage regulator can be a low-dropout regulator (LDO), a buck–boost converter, or a charge pump, etc. The gate high voltage regulator and the gate low voltage regulator can also be integrated in the same module, such as a power management integrated circuit (PMIC), and the embodiments of the present application do not limit this.

[0084] In addition, continue to refer to Figure 6, the peripheral driving circuit may further include a digital voltage signal source, which can generate a start frame signal in digital form (data STV, DSTV) and a clock signal in digital form (dataCLK, DCLK). The peripheral driving circuit may further include a level conversion circuit, which can convert DSTV into STV_1 to STV_N and convert DCLK into CLK_1, CLK_2,..., CLK_N according to the voltage values of VGH1, VGH2, VGL1, and VGL2. The high voltage value of the converted start frame signal and clock signal may be VGH1 or VGH2, and the low voltage value may be VGL1 or VGL2. When the voltage values of VGH1, VGH2, VGL1, or VGL2 change, the voltage values of STV_1 to STV_N and CLK_1 to CLK_N also change dynamically. Further, the peripheral driving circuit also outputs a control signal to the gate driving circuit so that the gate driving circuit can output gate control signals with different high and low voltage values.

[0085] In order to reduce the driving power consumption of the display device, a method of partitioning and controlling the frequency is proposed. The GOA circuit in this method includes multiple circuit units, and each circuit unit includes a register circuit and an output circuit. Specifically, the output circuit includes a frequency control circuit and a first frequency control signal PS1. When PS1 is at a low level, the GOA circuit outputs a valid pulse signal. When PS1 is at a high level, the GOA circuit does not output a valid pulse signal. By switching the high and low levels of the PS1 waveform at a specific time, it is possible to control whether the GOA circuits of certain rows output valid pulse signals within this frame. For example, according to the user's usage scenario, the refresh rate of the pixel circuits of certain rows in the AA area can be selectively lower than that of the pixel circuits of other rows, thereby reducing the driving power consumption of the display device.

[0086] Taking the gate scan signal output by the GOA circuit as a positive voltage waveform of a certain length as an example, as Figure 7 shown, Figure 7The m-1th level GOA circuit, the mth level GOA circuit and the m+1th level GOA circuit are shown. Each GOA circuit includes a register circuit, an output circuit and a frequency control circuit, and the output circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a fifth transistor T5. Among them, the gate of the first transistor T1, the first end of the third transistor T3 and the register circuit are coupled to a pull-up (PU) node, the gate of the second transistor T2, the first end of the fifth transistor T5 and the register circuit are coupled to a pull-down (PD) node, the second end of the third transistor and the gate of the fourth transistor T4 are coupled to a buffer pull-up (BPU) node, and the partition control circuit and the gate of the third transistor T3 are coupled to the N1 node.

[0087] It can be understood that the first transistor of the m-1th GOA circuit is represented by T1_m-1, the first transistor of the mth GOA circuit is represented by T1_m, and the first transistor of the m+1th GOA circuit is represented by T1_m+1. The representation method is similar and will not be repeated here.

[0088] Taking the mth level GOA circuit as an example, the register circuit m receives the cascade signal SR_m-1 output by the previous level GOA circuit, and outputs the cascade signal SR_m of the current level GOA circuit to the register circuit m+1 of the next level GOA circuit, and the register circuit m also outputs the pull-up signal PU_m and the pull-down signal PD_m. When the local refresh frequency reduction function is turned off, the third transistor T3_m receives PU_m, and the fifth transistor T5_m receives PD_m, and the next level GOA circuit continues to receive SR_m and continues to transmit signals to the next level GOA circuit, and so on. When the local refresh frequency reduction function is turned on, the gate of the third transistor T3 is used to input PS1, and PS1 controls the third transistor T3 to be turned on or off. For example, if PS1 is at a high level, the third transistor T3 is turned off, and the fourth transistor T4 is also turned off. At this time, the GOA circuit does not output a valid gate scan signal.

[0089] Figure 7 A timing diagram of the GOA circuit in Figure 8 As shown, Figure 8 The timing diagram of each node and gate scanning signal when the m-th level GOA circuit outputs a valid pulse signal and the m+1-th level GOA circuit does not output a valid pulse signal is shown in FIG. That is, S1_m outputs a valid pulse signal, and S1_m+1 does not output a valid pulse signal. Among them, PS1 switches from a low level to a high level when the m-th level GOA circuit outputs SR_m.

[0090] When the register circuit in the m-th stage GOA circuit generates PU_m and PS1 is at a low level, the gate of the fourth transistor T4_m (i.e., the BPU node) is written with a low level, and the gate scan signal S1_m is normally output. When the register circuit in the (m + 1)-th stage GOA circuit generates PU_m+1 and PS1 is switched to a high level, the gate of the first transistor T1_m+1 remains at a high level, and the gate scan signal out_m+1 is not output. There can be 120 refresh frames within 1 s. PS1 can control S1_m to be output 120 times, while S1_m+1 is output 1 time, so as to achieve that different rows of pixels on the display panel exist at 120 Hz and 1 Hz simultaneously.

[0091] Figure 7 Another timing diagram of the GOA circuit in Figure 9 is shown as Figure 9 Only the timing diagrams of the gate scan signals of the (m - 1)-th stage GOA circuit, the m-th stage GOA circuit, the (m + 1)-th stage GOA circuit, and the (m + 2)-th stage GOA circuit are shown. Among them, S1_m+1 may not be output in the first frame and may be output in the subsequent second frame. That is to say, as long as it is ensured that the output frequency of S1_m+1 is lower than that of S1_m, a lower-frequency driving frequency display can be achieved. For example, the upper half area of the display panel can be 120 Hz and the lower half area can be 60 Hz.

[0092] As Figure 10 shown, Figure 10 is a graphical illustration after the display panel enables the zoning function. The zoning accuracy can be determined according to the requirements of the actual display picture. The zoning accuracy of the display screen can be 1 row, 2 rows, or multiple rows. Figure 10 In (a) of

[0093] Figure 10 shows an 8-stage GOA circuit, namely GOA1, GOA2, ……, GOA8. Among them, in Figure 10 in (b) includes 2 zones. Among them, the zone composed of GOA1 and GOA2 uses a refresh rate of 120 Hz, and the zone composed of GOA3 to GOA8 uses a refresh rate of 10 Hz. In Figure 10 in (c) also includes 2 zones. Among them, the zone composed of GOA1 to GOA4 uses a refresh rate of 120 Hz, and the zone composed of GOA5 to GOA8 uses a refresh rate of 10 Hz. In Figure 10(d) also includes two partitions. Among them, the partition composed of GOA1 to GOA6 uses a refresh rate of 120 Hz, and the partition composed of GOA7 to GOA8 uses a refresh rate of 10 Hz. In Figure 10 (e) includes three partitions. Among them, the partition composed of GOA1 to GOA2 uses a refresh rate of 120 Hz, the partition composed of GOA3 to GOA4 uses a refresh rate of 60 Hz, and the partition composed of GOA5 to GOA8 uses a refresh rate of 30 Hz. In Figure 10 (f) also includes three partitions. Among them, the partition composed of GOA1 to GOA2 uses a refresh rate of 120 Hz, the partition composed of GOA3 to GOA6 uses a refresh rate of 60 Hz, and the partition composed of GOA7 to GOA8 uses a refresh rate of 30 Hz. In Figure 10 (g) also includes three partitions. Among them, the partition composed of GOA1 to GOA4 uses a refresh rate of 120 Hz, the partition composed of GOA5 to GOA6 uses a refresh rate of 60 Hz, and the partition composed of GOA7 to GOA8 uses a refresh rate of 30 Hz. In Figure 10 (h) includes four partitions. Among them, the partition composed of GOA1 to GOA2 uses a refresh rate of 120 Hz, the partition composed of GOA3 to GOA4 uses a refresh rate of 60 Hz, the partition composed of GOA5 to GOA6 uses a refresh rate of 30 Hz, and the partition composed of GOA7 to GOA8 uses a refresh rate of 10 Hz.

[0094] However, due to the voltage difference of PS1 input by the frequency control circuit in the GOA circuit in the high and low frequency regions, there is also a voltage difference at the N1 node during high refresh rate output and low refresh rate output, that is, the N1 node is at a high level when the GOA circuit does not output an effective pulse signal, and is at a low level when the GOA circuit outputs an effective pulse signal.

[0095] As Figure 11 shown, Figure 11 shows the timing diagrams of the j-th refresh cycle and the (j + 1)-th refresh cycle. Figure 11 shows the timing diagrams of CLK1, CLK2, the first frequency control signal PS1, STV, and each node of the m-th GOA circuit and the (m + 1)-th GOA circuit of the driving circuit. Among them, the nodes of the m-th GOA circuit include: N1_m, PU_m, PD_m, BPU_m, S1_m, and SR_m, and the nodes of the (m + 1)-th GOA circuit include: N1_m+1, PU_m+1, PD_m+1, BPU_m+1, S1_m+1, and SR_m+1.

[0096] Among them, S1_m is the high-frequency output, and S1_m+1 is the low-frequency output. From the output interface of the j-th refresh cycle SR_m to the start of the output of the (j + 1)-th refresh cycle SR_m, N1_m always maintains a low-level state. From the end of the output of the j-th refresh cycle SR_m+1 to the start of the output of the (j + 1)-th refresh cycle SR_m+1, N1_m+1 always maintains a high-level state.

[0097] Specifically, in the j-th refresh cycle, S1_m is a valid pulse signal, and its working principle is as follows:

[0098] (1) During the t1 period: The voltage of the SR_m-1 signal changes from VGL to VGH, and the m-th level GOA circuit is activated. At this time, the first frequency control signal PS1 is VGL, and the potential of the N1_m node is also VGL. T3_m is turned on, and the potential of the PD_m node changes from VGL to VGH. T2_m and T5_m are turned off.

[0099] (2) During the t2 period: Since T3_m is turned on, the potential of the PU_m node changes from VGH to VGL, and the potential of the BPU_m node also changes from VGH to VGL. The potential of the N1_m node is pulled down to VGL* due to the capacitive coupling effect, where the amplitude of VGL* is close to 2*VGL - VGH. T1_m is turned on, SR_m starts to output, and T4_m is turned on, and S1_m starts to output.

[0100] (3) During the t4 period: The voltage of the SR_m-1 signal changes from VGH to VGL, and the GOA circuit will end the output of SR and S1 at the end of the t5 period.

[0101] (4) During the t5 period: The potential of the PU_m node changes from VGL to VGH, the potential of the PD_m node changes from VGH to VGL, the potential of the N1_m node is coupled from VGL* to VGL, and the potential of the BPU_m node changes from VGL to VGH. T1_m is turned off, T2_m is turned on, and the output of SR_m ends. T4_m is turned off, T5_m is turned on, and the output of S1_m ends.

[0102] In the j-th refresh cycle, S1_m+1 is an invalid pulse signal, and its working principle is as follows:

[0103] (1) During the t2 period: The voltage of the SR_m signal changes from VGL to VGH, and the (m + 1)-th level GOA circuit is activated. The reset circuit _m+1 is configured to be in a conducting state. At this time, the PS1 signal is VGH, the potential of the N1_m+1 node changes from VGL to VGH, the T3_m+1 transistor is turned off, the potential of the PD_m+1 node changes from VGL to VGH, and T2_m+1 and T5_m+1 are turned off.

[0104] (2) Time period t3: The potential of the PU_m+1 node changes from VGH to VGL. However, since T3_m+1 is turned off, the potentials of the PD_m+1 node and the BPU_m+1 node both remain at VGH. The potential of the N1_m+1 node remains at VGH, T1_m+1 is turned on, SR_m+1 starts to output, T4_m+1 is turned off, and S1_m+1 has no signal output.

[0105] (3) Time period t5: The signal voltage of SR_m changes from VGH to VGL, and the GOA_m+1 circuit will end the output at time period t6.

[0106] (4) Time period t6: The potential of the PU_m+1 node changes from VGL to VGH, the potential of the PD_m+1 node changes from VGH to VGL, T1_m is turned off, T2_m is turned on, and the output of SR_m+1 ends. The potentials of the N1_m+1 node and the BPU_m+1 node both remain at VGH, T4_m+1 is turned off, T5_m+1 is turned on, and the output of S1_m+1 ends.

[0107] In the (j + 1)-th refresh cycle, the PS1 signal always remains at VGL, and both S1_m and S1_m+1 output. The working principle is the same as that of S1_m in the j-th refresh cycle and will not be elaborated here.

[0108] In a possible example, as shown in Figure 12 (a), when the PS1 signal is at a low level, the voltage difference between the gate and the drain of the third transistor T3 is Vgd = 3.9V, and the voltage difference between the drain and the source of the third transistor T3 is Vds = 0V. As shown in Figure 12 (b), when the PS1 signal is at a low level, the voltage difference between the gate and the drain of the third transistor T3 is Vgd = -14.7V, and the voltage difference between the drain and the source of the third transistor T3 is Vds = 14.1V. Thus, if the partition function of the GOA circuit is continuously enabled at a fixed position for a long time, there will be a drift in the TFT device characteristics, resulting in uneven display in the high refresh rate area and the low refresh rate area.

[0109] In addition, as shown in Figure 13 , Figure 13 the waveforms of the PU node, the PD node, and the gate scan signal are shown. Among them, the waveform of the PU node changes earlier than that of the PD node, and there is a step noise when the voltage of the PU node rises in the cascade signal. Since the cascade signal is the signal for realizing the shift output of the GOA circuit, when there is a step noise at the rising edge of the cascade signal, the waveform of the gate scan signal will become uneven, which may cause distortion of the gate scan signal and affect the accuracy of the gate scan signal.

[0110] Therefore, the embodiments of the present application provide a driving circuit. A reset circuit is added to the driving circuit, and the driving circuit can control the voltage of the N1 node through the reset circuit to maintain the voltage of the N1 node at the same value, which can avoid the influence of the voltage change of the N1 node on the display effect of the display, improve the stability of the GOA circuit, and improve the display effect of the display.

[0111] Next, the driving circuit provided by the embodiments of the present application will be further described with reference to the accompanying drawings.

[0112] The embodiments of the present application provide a driving circuit, as Figure 14 shown. The driving circuit includes a plurality of GOA circuits, and each GOA circuit includes a register circuit, an output circuit, a frequency control circuit, and a reset circuit. Figure 14 The structural schematic diagrams of n GOA circuits are shown, which are GOA circuit_1, GOA circuit_2,..., GOA circuit_n respectively.

[0113] Among them, the output circuit is coupled to the register circuit, and the output circuit is configured to generate a gate scan signal in response to the voltages of the pull-up node and the pull-down node of the register circuit, and output the gate scan signal to the pixel circuit corresponding to the GOA circuit.

[0114] Exemplarily, the register circuit can receive a carry signal, and the carry signal can be a start frame signal or a cascade signal output by the previous-level GOA circuit. The register circuit and the output circuit are coupled to the pull-up node and the pull-down node, the signal of the pull-up node is the PU signal, and the signal of the pull-down node is the PD signal. When the PU signal is at a low level and the PD signal is at a high level, the output circuit outputs a high-level gate scan signal; when the PU signal is at a high level and the PD signal is at a low level, the output circuit outputs a low-level gate scan signal.

[0115] It can be understood that the gate scan signal provided by the embodiments of the present application is often used for the conduction or cut-off of the first transistor T1 in the pixel circuit, that is, the gate scan signal is S1.

[0116] Among them, the frequency control circuit is coupled to the output circuit at the first node, and the frequency control circuit is configured to receive a first frequency control signal to control the frequency of the gate scan signal.

[0117] Exemplarily, when the first frequency control signal is at a low level, the gate scan signal output by the output circuit is a valid pulse signal; when the first frequency control signal is at a high level, the gate scan signal output by the output circuit is an invalid pulse signal. Thus, the zoning function of the display screen can be realized through the frequency control circuit.

[0118] Among them, the reset circuit and the output circuit are coupled to the first node, and the reset circuit is configured to control the voltage of the first node based on a reset signal.

[0119] Exemplarily, the driving circuit can control the voltage of the first node through the reset circuit to eliminate the difference in the voltages of the first nodes of different stages of the GOA circuit being at different voltages for a long time, avoid the influence of the voltage change of the first node on the display effect of the display, improve the stability of the GOA circuit, and improve the display effect of the display.

[0120] Exemplarily, as Figure 15 shown, Figure 15 in Figure 11 also shows the timing diagrams of the frequency control circuit_m, the reset circuit_m, the frequency control circuit_m+1, and the reset circuit_m+1. Among them, the reset circuit_m is turned off when the frequency control circuit is turned on (at time t1), and is turned on again after the S1 output is completed (at time t6). It can be seen from Figure 15 that the voltages of N1_m and N1_m+1 remain at a low level for a period of time between two refresh cycles. Thus, the voltage change of the N1 node is avoided, the stability of the GOA circuit is improved, and the display effect of the display is improved.

[0121] Optionally, as Figure 16 shown, Figure 16 shows the schematic structural diagrams of the (m-1)-th stage GOA circuit, the m-th stage GOA circuit, and the (m+1)-th stage GOA circuit. The reset circuit includes a first transistor ( Figure 16 denoted as T1 in Figure 16 ), the first end of the first transistor T1 is coupled to the first node ( Figure 16 denoted as N1 in Figure 16 ), the second end of the first transistor T1 is coupled to the first voltage source ( Figure 16 denoted as V1 in Figure 16 ), and the gate of the first transistor T1 is used to receive the reset signal ( Figure 16 denoted as Vrs in Figure 16 ).

[0122] Among them, the reset circuit is specifically configured to control the voltage of the first node through the voltage output by the first voltage source when the reset signal controls the first transistor to conduct.

[0123] Exemplarily, the register circuit can include a register sub-circuit and a second node. The reset signal can come from a second node ( Figure 16 denoted as N2 in Figure 16 ) in the register circuit, and this second node N2 can also be called a bootstrap node. The second node N2 is coupled to the first end of the twelfth transistor ( Figure 16 denoted as T12 in Figure 16 ), the second end of the twelfth transistor T12 is coupled to the first clock signal CLK_1 or the second clock signal CLK_2. The second node N2 is also coupled to the fourth capacitorFigure 16 is coupled to the first end of the fourth capacitor (denoted as C4 in the text), and the second end of the fourth capacitor C4 is coupled to the third node ( Figure 16 denoted as N3 in the text).

[0124] Exemplarily, the voltage output by the first voltage source can be a low level. In a possible example, the voltage output by the first voltage source can be VGL, and the voltage output by the first voltage source can also be any voltage signal lower than VGH. When the first transistor T1 is turned on, due to the existence of the first transistor T1, the voltage of the first node is less than the voltage output by the first voltage source.

[0125] Optionally, as Figure 17 shown, Figure 17 on the basis of Figure 16 a schematic structural diagram of the (m - 1)-th stage GOA circuit, the m-th stage GOA circuit, and the (m + 1)-th stage GOA circuit is shown. The reset transistor further includes a second transistor ( Figure 17 denoted as T2 in the text), the first end of the second transistor T2 is coupled to the first end of the first transistor T1, the second end of the second transistor T2 is coupled to the first node N1, and the gate of the second transistor T2 is coupled to the gate of the first transistor T1.

[0126] Exemplarily, adding the second transistor T2 between the first node N1 and the first transistor T1 can reduce the cross-voltage between the first end and the second end of the first transistor T1, and improve the reliability of the GOA circuit. In addition, the first transistor T1 and the second transistor T2 adopt a common-gate structure, which can improve the reliability of the transistor.

[0127] Optionally, as Figure 18 shown, the frequency control circuit includes a third transistor ( Figure 18 denoted as T3 in the text). The first end of the third transistor T3 is coupled to the register circuit, the second end of the third transistor T3 is coupled to the output circuit, and the gate of the third transistor T3 is used to receive the second frequency control signal.

[0128] Wherein, the frequency control circuit is further configured to receive a first frequency control signal and a second frequency control signal to control the frequency of the gate scan signal.

[0129] Exemplarily, by jointly controlling the frequency of the gate scan signal through the first frequency control signal and the second frequency control signal, the GOA circuit can reduce the frequency of the clock signal during low-frequency driving to further reduce the power consumption of the driving circuit.

[0130] Optionally, referring to Figure 16 , Figure 17 or Figure 18, the output circuit includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C1. Among them, the gate of the fourth transistor T4 is coupled to the pull-up node by the register circuit, and the first end of the fourth transistor T4 and the gate high-voltage source ( Figure 16 , Figure 17 or Figure 18 denoted as VGH in) are coupled, the second end of the fourth transistor T4 is coupled to the first end of the fifth transistor T5, the second end of the fifth transistor T5 and the gate low-voltage source ( Figure 16 , Figure 17 or Figure 18 denoted as VGL in) are coupled, and the gate of the fifth transistor T5 is coupled to the pull-down node by the register circuit. The pull-up node is also coupled to the first end of the sixth transistor T6, the gate of the sixth transistor T6 is coupled to the first node N1, the second end of the sixth transistor T6 is coupled to the gate of the seventh transistor T7, the first end of the seventh transistor T7 is coupled to the gate high-voltage source VGH, the second end of the seventh transistor T7 is coupled to the first end of the eighth transistor T8, the second end of the eighth transistor T8 is coupled to the gate low-voltage source VGL, and the gate of the eighth transistor T8 is coupled to the pull-down node. The first end of the first capacitor C1 is coupled to the gate of the sixth transistor T6, and the second end of the first capacitor C2 is coupled to the second end of the sixth transistor T6.

[0131] Optionally, as shown in Figure 19 , the output circuit further includes a ninth transistor ( Figure 19 denoted as T9 in), the first end and the second end of the ninth transistor T9 are both coupled to the first end of the fifth transistor T5, and the gate of the ninth transistor T9 is coupled to the pull-down node.

[0132] Exemplarily, the output circuit can reduce the rising edge step of the cascaded signal through the capacitive coupling effect of the ninth transistor and optimize the quality of the cascaded signal.

[0133] Optionally, continuing to refer to Figure 19 , the output circuit further includes a tenth transistor ( Figure 19 denoted as T10 in), the first end of the tenth transistor T10 is coupled to the pull-down node, the second end of the tenth transistor T10 is coupled to the gate of the eighth transistor T8, and the gate of the tenth transistor T10 is coupled to the first node N1.

[0134] Exemplarily, the tenth transistor T10 can prevent the eighth transistor T8 from being accidentally turned on and improve the stability of the GOA circuit.

[0135] Optionally, continuing to refer to Figure 19 , the output circuit further includes an eleventh transistor ( Figure 19Among them, represented by T11, the first end and the gate of the eleventh transistor T11 are coupled to the high gate voltage source VGH, the second end of the eleventh transistor T11 is coupled to the second end of the sixth transistor T6, and the gate of the eleventh transistor T11 is coupled to the gate of the eighth transistor T8.

[0136] Exemplarily, the voltage drop of the gate scan signal can be accelerated by the eleventh transistor T11.

[0137] In addition, continue to refer to Figure 19 , the output circuit further includes a second capacitor ( Figure 19 represented by C2 in Figure 19 ) and a third capacitor (

[0138] represented by C3 in

[0139] ). The first end of the second capacitor C2 is coupled to the first end of the seventh transistor T7, the second end of the second capacitor C2 is coupled to the gate of the seventh transistor T7, the first end of the third capacitor C3 is coupled to the first end of the eighth transistor T8, and the second end of the third capacitor C3 is coupled to the gate of the eighth transistor T8.

[0138] Exemplarily, more capacitors can also be included in the driving circuit, and the capacitors can stabilize the node voltage to compensate for the voltage drop caused by power supply voltage fluctuations or other factors.

[0139] As Figure 20 shown, Figure 20 the specific circuit of the frequency control circuit is shown in Figure 20 , among which, the frequency control circuit may include a thirteenth transistor ( Figure 20 represented by T13 in Figure 20 ) and a fourteenth transistor (

[0140] represented by T14 in

[0141] Figure 20 Figure 20 ). The first end of the thirteenth transistor T13 is used to input the first frequency control signal PS1, the gate of the thirteenth transistor T13 is coupled to the fourth node of the previous-stage GOA circuit ( Figure 20 represented by N4_m-1 in

[0140] ), the second end of the thirteenth transistor T13 is coupled to the first end of the fourteenth transistor T14, the gate of the fourteenth transistor T14 is used to input the cascade signal, and the second end of the fourteenth transistor T14 is coupled to the first node N1.

[0140] Exemplarily, the gate signal of the transistor in the frequency control circuit can also be coupled to the nodes of other-stage GOA circuits. The gate of T13_m in the driving circuit can also be coupled to the fourth nodes of the GOA circuits of the previous two stages or more (such as N4_m-2, N4_m-3…N4_m-k, k≥2); the gate of T14_m in the driving circuit can also be coupled to the SR signals of the GOA circuits of the previous stage or more (such as SR_m-1, SR_m-2…SR_m-k, k≥1) to adjust the synchronization state between signals and reduce signal delay.

[0141] Figure 20The specific circuit of the register circuit is also shown therein. The register circuit may include a third node ( Figure 20 denoted as N3 in Figure 20 ), a fourth node (

[0142] denoted as N4 in Figure 21 ), a plurality of transistors (such as T15 to T26), and a plurality of capacitors (such as C5 and C6). The capacitors can stabilize the node voltage to compensate for the voltage drop caused by power supply voltage fluctuations or other factors. Figure 21 As shown in Figure 20 , the timing diagrams of the internal nodes and external signals in Figure 21 are shown. Specifically, Figure 15 based on Figure 21 , the timings of N4_m-1, N2_m, N4_m, and N2_m+1 are shown. It can be seen from

[0143] that the driving circuit can implement the function of reducing the local refresh frequency through the frequency control circuit. In addition, the voltages of N1_m and N1_m+1 remain at a low level during a period between two refresh cycles. Thus, the voltage difference of the N1 node is avoided, the stability of the GOA circuit is improved, and the display effect of the display is improved.

[0144] Among them, the driving circuit is usually powered by the same high gate voltage source, that is, multiple GOA circuits in the driving circuit are all coupled to the high gate voltage signal line of the high gate voltage source. When the gate scan signal of the previous row changes from VGH to VGL, there is a transient load reduction in the high gate voltage source and its signal line, and the potential of the high gate voltage source will be pulled down and noise ripples will be generated.

[0145] Specifically, as shown in Figure 22 , there are multiple ripples with a fixed time interval (such as 2H) when the gate scan signals (S1_m and S1_m+1) are in the high level state. Since in the pixel circuit, the opening degree of the first transistor T1 depends on the potential of the high level of S1, after the first transistor T1 is turned on through S1 and then the second transistor T2 is turned on through S2, the data voltage DATA is written into the gate of the driving transistor Td at the time end of S1. At this time, the high gate voltage source of the driving circuit that generates S1 should maintain a stable potential. Thus, if the ripple signals are too dense, it will cause disturbance to the writing of the data voltage, resulting in the problem of uneven brightness display effect.

[0146] To solve the above ripple problem, an embodiment of the present application provides a display device, as shown in Figure 23As shown, the display device includes a pixel array, a peripheral driving circuit, and a plurality of driving circuits cascaded in sequence. Among them, the driving circuit includes a plurality of GOA circuits, and the GOA circuit includes a register circuit and an output circuit. The driving circuit may include n GOA circuits. Figure 23 Registers 1 to n and output circuits 1 to n are shown therein. In addition, the driving circuit may further include redundant GOA circuits, and the redundant GOA circuit includes a virtual register circuit and a virtual output circuit. It can be understood that the GOA circuit may further include more components, such as the frequency control circuit and the reset circuit described above, and the embodiments of the present application do not limit this.

[0147] In addition, the peripheral driving circuit includes at least one gate high voltage source, and at least one gate high voltage source is coupled to a plurality of gate high voltage signal lines. Adjacent driving circuits among the plurality of driving circuits cascaded in sequence are respectively coupled to different gate high voltage signal lines.

[0148] Exemplarily, it is assumed that the peripheral driving circuit can provide j gate high voltage signal lines, where j is an integer greater than or equal to 1, that is, VGH1, VGH2,..., VGHj. Taking the output circuit in the driving circuit as an example, the output circuit can be connected to the j gate high voltage signal lines through k first signal lines, where k is an integer greater than or equal to 1, and the connection relationship may also be that adjacent first signal lines are connected to different gate high voltage signal lines.

[0149] In a possible implementation manner, continue to refer to Figure 23 , Figure 23 As shown therein, the first gate high voltage source VGH1 is respectively coupled to the first gate high voltage signal line VGH1_1 and the second gate high voltage signal line VGH1_2. Among them, the first signal lines of the output circuit and the gate high voltage signal lines are connected in an interlaced and alternating manner. For example, the first signal line of output circuit 1 is connected to VGH1_1, the first signal line of output circuit 2 is connected to VGH1_2, the first signal line of output circuit 3 is connected to VGH1_1, and the first signal line of output circuit 4 is connected to VGH1_2.

[0150] In another possible implementation manner, as Figure 24 shown, Figure 24The first gate high voltage source VGH1 and the second gate high voltage source VGH2 are shown. The first gate high voltage source VGH1 is respectively coupled to the first gate high voltage signal line VGH1_1 and the second gate high voltage signal line VGH1_2, and the second gate high voltage source VGH2 is respectively coupled to the third gate high voltage signal line VGH2_1 and the fourth gate high voltage signal line VGH2_2. Among them, the first signal line of the output circuit and the gate high voltage signal line are alternately connected. For example, the first signal line of output circuit 1 is connected to VGH1_1, the first signal line of output circuit 2 is connected to VGH2_1, the first signal line of output circuit 3 is connected to VGH1_2, and the first signal line of output circuit 4 is connected to VGH2_2. And so on, every 4 groups of GOA circuits can be connected to the gate high voltage signal line according to the connection method of output circuit 1 to output circuit 4.

[0151] Optionally, as Figure 25 shown, the peripheral driving circuit further includes a level conversion circuit, and at least one gate high voltage source includes a first gate high voltage source VGH1 and a second gate high voltage source VGH2. The output circuits of multiple cascaded driving circuits are coupled to the first gate high voltage source, and the register circuits and the level conversion circuit of multiple cascaded driving circuits are coupled to the second gate high voltage source.

[0152] Exemplarily, the first gate high voltage source VGH1 is respectively coupled to the first gate high voltage signal line VGH1_1 and the second gate high voltage signal line VGH1_2, and the second gate high voltage source VGH2 is respectively coupled to the third gate high voltage signal line VGH2_1 and the fourth gate high voltage signal line VGH2_2. The register circuit is connected to STV, CLK1, CLK2, VGH2_1, and VGH2_2. Among them, STV, CLK1, and CLK2 are generated according to the level conversion of VGH2, and the gate high voltage required for the operation of the register circuit is all provided by VGH2. In addition, the output circuit is separately connected to VGH1, and the gate high voltage required for the output circuit is all provided by VGH1. Thus, the driving ability of the VGH1 single power supply can be flexibly adjusted, which helps to improve the stability of the gate scan signal output by the output circuit and reduce signal disturbance.

[0153] Optionally, the driving current of the first gate high voltage source is greater than that of the second gate high voltage source.

[0154] Exemplarily, the driving current of VGH1 is greater than that of VGH2. VGH1 can output a more stable gate high voltage to the output circuit, which helps to improve the stability of the gate scan signal output by the output circuit and reduce signal disturbance.

[0155] Optionally, at least one gate high voltage source includes a first gate high voltage source and a second gate high voltage source. The gate high voltage signal line of the first transistor in the output circuit of adjacent driving circuits is coupled to the first gate high voltage source, and the gate high voltage signal line of the second gate high voltage source is coupled to other transistors in the output circuit of adjacent driving circuits.

[0156] Exemplarily, the first transistor may be the seventh transistor of the output circuit of the driving circuit described above, and the other transistors may be the eleventh transistor of the output circuit of the driving circuit described above. Thus, using the first gate high voltage source alone to provide the gate high voltage to the first end of the first transistor helps to improve the stability of the gate scan signal output by the output circuit and reduce signal perturbation.

[0157] Exemplarily, the line length of the signal line between the gate high voltage signal line of the first gate high voltage source and the output circuit may be within a preset range. In a possible example, the gate high voltage signal line of the first gate high voltage source may be arranged close to the output circuit to reduce the line length of the signal line between the gate high voltage signal line and the output circuit, so as to improve the signal transmission quality.

[0158] Optionally, the output terminal of the first gate high voltage source is coupled to a plurality of parallel voltage stabilizing capacitors.

[0159] Exemplarily, connecting a plurality of parallel voltage stabilizing capacitors at the output terminal of the first gate high voltage source can improve the stability of the gate high voltage output by the first gate high voltage source, help to improve the stability of the gate scan signal output by the output circuit, and reduce signal perturbation.

[0160] It can be understood that a plurality of parallel voltage stabilizing capacitors can also be connected at the output terminals of other gate high voltage sources in the peripheral driving circuit to improve the stability of the gate high voltage output by the gate high voltage source.

[0161] Optionally, the first signal line of each output circuit is coupled to the corresponding gate high voltage signal line, and the length of the first signal line is such that each first signal line overlaps with a plurality of gate high voltage signal lines.

[0162] Exemplarily, as Figure 26 shown, the gate high voltage signal lines may be distributed on the first conductive layer, the first signal lines may be distributed on the second conductive layer, the first conductive layer and the second conductive layer are arranged opposite to each other, and the first signal lines and the corresponding gate high voltage signal lines are connected through vias. Among them, taking the first signal line of output circuit 2 as an example, this first signal line is connected to VGH1_1 through a via, and the first signal line and other signal lines (such as STV, VGH2_2, and VGH2_2) form an overlapping capacitor. In addition, there is an extended portion of this first signal line, for example Figure 26The dashed part in forms an overlapping capacitor with the extended part and VGH1_2. It can be understood that there is no electrical connection between the extended part of the first signal line and other signal lines. Additionally, the first signal line can extend beyond VGH1_2, and the length of the line extending beyond VGH1_2 is not limited in the embodiments of the present application.

[0163] Thus, the impedance of the first signal line between the output circuit and the gate high-voltage signal line is the same, which can reduce the difference in the gate scan signals output by the output circuit.

[0164] Optionally, the gate high-voltage signal line of the first gate high-voltage source includes at least two metal layers, and the at least two metal layers are connected by at least one via hole.

[0165] Exemplarily, the gate high-voltage signal line of the first gate high-voltage source can be formed by overlapping multiple metal layers, with an inorganic layer between adjacent metal layers. The multiple metal layers can be connected by via holes at appropriate positions to achieve electrical conduction. Thus, the impedance of the gate high-voltage signal line of the first gate high-voltage source can be reduced.

[0166] Exemplarily, as Figure 27 shown, Figure 27 three metal layers and two inorganic layers are shown in , which are the first metal layer, the first inorganic layer, the second metal layer, the second inorganic layer, and the third metal layer arranged in sequence. The first metal layer and the second metal layer can be connected by a first via hole, and the second metal layer and the third metal layer can be connected by a second via hole.

[0167] In a possible example, the metal layer can be a three-layer titanium-aluminum-titanium metal or a single-layer molybdenum metal, and the inorganic layer can be silicon nitride or silicon oxide.

[0168] Next, the driving method provided by the embodiments of the present application will be further introduced with reference to the accompanying drawings.

[0169] Applied to the above driving circuit, the embodiments of the present application provide a driving method, as Figure 28 shown, this method includes the following processes.

[0170] S2801. The output circuit generates a gate scan signal in response to the voltages of the pull-up node and the pull-down node of the register circuit, and outputs the gate scan signal to the pixel circuit corresponding to the GOA circuit.

[0171] S2802. The frequency control circuit receives the first frequency control signal to control the frequency of the gate scan signal.

[0172] S2803. The reset circuit controls the voltage of the first node based on the reset signal.

[0173] Exemplarily, when the driving circuit does not enable the local refresh frequency reduction function, as Figure 29 shown, Figure 29 Figure 4 shows the timing diagrams of STV, CLK1, CLK2, each node (PU_1 to PU_8, PD_1 to PD_8, BPU_1 to BPU_8) of 8 GOA circuits, the first frequency control signal PS1, and the gate scan signals (S1_1 to S1_8) output by each GOA circuit. Among them, when the first frequency control signal PS1 is at a low level (VGL), at this time, 8 GOA circuits normally output gate scan signals, and the pulse width of each gate scan signal is 6H.

[0174] Exemplarily, when the driving circuit enables the local refresh frequency reduction function, as Figure 30 shown, Figure 30 Figure 5 shows the timing diagrams of STV, CLK1, CLK2, each node (PU_1 to PU_8, PD_1 to PD_8, BPU_1 to BPU_8) of 8 GOA circuits, the first frequency control signal PS1, and the gate scan signals (S1_1 to S1_8) output by each GOA circuit. Among them, when the first frequency control signal PS1 switches from a low level (VGL) to a high level (VGH) when it is enabled at S1_4, at this time, the signals of BPU_5 to BPU_8 are blocked, and thus the first 4 GOA circuits output gate scan signals in a certain frame of the picture, and the last 4 GOA circuits do not output gate scan signals.

[0175] Optionally, S2802 may include: the frequency control circuit receives the first frequency control signal and the second frequency control signal to control the frequency of the gate scan signal.

[0176] Exemplarily, when the driving circuit does not enable the local refresh frequency reduction function, as Figure 31 shown, Figure 31 Figure 6 shows the timing diagrams of STV, CLK1, CLK2, each node (PU_1 to PU_8, PD_1 to PD_8, BPU_1 to BPU_8) of 8 GOA circuits, the first frequency control signal PS1, the second frequency control signal PS2, and the gate scan signals (S1_1 to S1_8) output by each GOA circuit. Among them, when both the first frequency control signal PS1 and the second frequency control signal PS2 are at a low level (VGL), at this time, 8 GOA circuits normally output gate scan signals, and the pulse width of each gate scan signal is 6H.

[0177] Exemplarily, when the driving circuit enables the local refresh frequency reduction function, as Figure 32 shown, Figure 32The timing diagrams of STV, CLK1, CLK2, each node of eight GOA circuits (PU_1 to PU_8, PD_1 to PD_8, BPU_1 to BPU_8), the first frequency control signal PS1, the second frequency control signal PS2, and the gate scanning signals (S1_1 to S1_8) output by each GOA circuit are shown. Among them, the first frequency control signal PS1 switches from a low level (VGL) to a high level (VGH) when S1_4 is turned on. At this time, the signals of BPU_5 to BPU_8 are masked, so that the first four GOA circuits output gate scanning signals in a certain frame of the picture, and the latter four GOA circuits do not output gate scanning signals. Since S1_5 does not output a gate scanning signal, after the output of S1_4 ends, CLK1 and CLK2 can be changed to fixed voltage signals (such as high level), and PS2 changes from a low level to a high level to maintain the potential of the PU node. Thus, the power consumption can be further reduced.

[0178] An embodiment of the present application further provides a display device, which may include a processor and the driving circuit described above, and the driving circuit is coupled to the processor.

[0179] Exemplarily, the processor may be a display driver integrated circuit (DDIC) chip, the processor may also be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0180] An embodiment of the present application further provides a computer storage medium, in which computer instructions are stored. When the computer instructions are run on an electronic device, the electronic device is enabled to execute the above-related method steps to implement the driving method in the above embodiment.

[0181] An embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computer is enabled to execute the above-related steps to implement the driving method executed by the electronic device in the above embodiment.

[0182] In addition, an embodiment of the present application further provides a device, which may specifically be a chip, a component or a module. The device may include a processor and a memory connected to each other. The memory is used to store computer-executable instructions. When the device runs, the processor may execute the computer-executable instructions stored in the memory, so that the chip executes the driving method executed by the electronic device in the above method embodiments.

[0183] Among them, the driving circuit, the display device, the display equipment, the computer storage medium, the computer program product or the chip provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above, and will not be elaborated here.

[0184] Through the description of the above embodiments, those skilled in the art can understand that for the convenience and conciseness of description, only the above division of each functional module is used as an example. In actual applications, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0185] In several embodiments provided in the present application, it should be understood that the disclosed device and method can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in electrical, mechanical or other forms.

[0186] The unit described as a separated component may or may not be physically separated. The component displayed as a unit may be a physical unit or multiple physical units, that is, it may be located in one place, or may be distributed to multiple different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0187] In addition, each functional unit in each embodiment of the present application may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0188] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The software product is stored in a storage medium and includes several instructions for causing a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0189] The above content is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A driving circuit, characterized in that, Including a plurality of array-driven scan GOA circuits, the GOA circuit includes: a register circuit, an output circuit, a frequency control circuit, and a reset circuit; The output circuit is coupled to the register circuit and is configured to generate a gate scan signal in response to the voltages of the pull-up node and the pull-down node of the register circuit, and output the gate scan signal to the pixel circuit corresponding to the GOA circuit; The frequency control circuit is coupled to the output circuit at a first node and is configured to receive a first frequency control signal to control the frequency of the gate scan signal; The reset circuit is coupled to the output circuit at the first node and is configured to control the voltage of the first node based on a reset signal.

2. The drive circuit according to claim 1, wherein The reset circuit includes a first transistor; The first end of the first transistor is coupled to the first node, the second end of the first transistor is coupled to a first voltage source, and the gate of the first transistor is for receiving the reset signal; The reset circuit is specifically configured to control the voltage of the first node by the voltage output by the first voltage source when the reset signal controls the first transistor to conduct.

3. The drive circuit according to claim 2, wherein The reset circuit further includes a second transistor; The first end of the second transistor is coupled to the first end of the first transistor, the second end of the second transistor is coupled to the first node, and the gate of the second transistor is coupled to the gate of the first transistor.

4. The drive circuit according to any one of claims 1-3, characterized in that, The frequency control circuit includes a third transistor; The first end of the third transistor is coupled to the register circuit, the second end of the third transistor is coupled to the output circuit, and the gate of the third transistor is for receiving a second frequency control signal; The frequency control circuit is further configured to receive the first frequency control signal and the second frequency control signal to control the frequency of the gate scan signal.

5. The drive circuit according to any one of claims 1-4, characterized in that, The output circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a first capacitor; The gate of the fourth transistor is coupled to the register circuit at the pull-up node, the first end of the fourth transistor is coupled to a gate high voltage source, the second end of the fourth transistor is coupled to the first end of the fifth transistor, the second end of the fifth transistor is coupled to a gate low voltage source, and the gate of the fifth transistor is coupled to the register circuit at the pull-down node; The pull-up node is further coupled to the first end of the sixth transistor, the gate of the sixth transistor is coupled to the first node, the second end of the sixth transistor is coupled to the gate of the seventh transistor, the first end of the seventh transistor is coupled to the gate high voltage source, the second end of the seventh transistor is coupled to the first end of the eighth transistor, the second end of the eighth transistor is coupled to the gate low voltage source, and the gate of the eighth transistor is coupled to the pull-down node; The first end of the first capacitor is coupled to the gate of the sixth transistor, and the second end of the first capacitor is coupled to the second end of the sixth transistor.

6. The drive circuit according to claim 5, wherein The output circuit further includes a ninth transistor; The first end and the second end of the ninth transistor are both coupled to the first end of the fifth transistor, and the gate of the ninth transistor is coupled to the pull-down node.

7. The drive circuit according to claim 5 or 6, characterized in that The output circuit further includes a tenth transistor; The first end of the tenth transistor is coupled to the pull-down node, the second end of the tenth transistor is coupled to the gate of the eighth transistor, and the gate of the tenth transistor is coupled to the first node.

8. The drive circuit according to any one of claims 5-7, characterized in that, The output circuit further includes an eleventh transistor; The first end of the eleventh transistor is coupled to the gate high voltage source, the second end of the eleventh transistor is coupled to the second end of the sixth transistor, and the gate of the eleventh transistor is coupled to the gate of the eighth transistor.

9. A display device, characterized in that, Comprising: a pixel array, a peripheral driving circuit, and a plurality of driving circuits cascaded in sequence; The peripheral driving circuit includes at least one gate high voltage source, and the at least one gate high voltage source is coupled to a plurality of gate high voltage signal lines; Adjacent driving circuits among the plurality of driving circuits cascaded in sequence are respectively coupled to different gate high voltage signal lines.

10. The display device according to claim 9, characterized in that, The peripheral driving circuit further includes a level conversion circuit, and the at least one gate high voltage source includes a first gate high voltage source and a second gate high voltage source; The output circuits of the plurality of driving circuits cascaded in sequence are coupled to the first gate high voltage source; The register circuits of the plurality of driving circuits cascaded in sequence and the level conversion circuit are coupled to the second gate high voltage source.

11. The display device according to claim 10, characterized in that, The driving current of the first gate high voltage source is greater than the driving current of the second gate high voltage source.

12. The display device according to claim 9, characterized in that, The at least one gate high voltage source includes a first gate high voltage source and a second gate high voltage source; The first transistor in the output circuit of the adjacent driving circuits is coupled to the gate high voltage signal line of the first gate high voltage source; The other transistors in the output circuit of the adjacent driving circuits are coupled to the gate high voltage signal line of the second gate high voltage source.

13. The display device according to any one of claims 10 to 12, characterized in that, The output end of the first gate high voltage source is coupled to a plurality of parallel voltage stabilizing capacitors.

14. The display device according to any one of claims 10 to 13, characterized in that, The first signal line of each output circuit is coupled to the corresponding gate high voltage signal line, and the length of the first signal line is such that each first signal line overlaps with the plurality of gate high voltage signal lines.

15. The display device according to any one of claims 10-14, characterized in that, The gate high voltage signal line of the first gate high voltage source includes at least two metal layers, and the at least two metal layers are connected by at least one via hole.

16. A driving method, characterized in that, The method is applied to a driving circuit, the driving circuit includes a plurality of GOA circuits, the GOA circuit includes: a register circuit, an output circuit, a frequency control circuit, and a reset circuit, the frequency control circuit, the output circuit, and the reset circuit are coupled to a first node, and the method includes: The output circuit generates a gate scan signal in response to the voltage of the pull-up node and the voltage of the pull-down node of the register circuit, and outputs the gate scan signal to the pixel circuit corresponding to the GOA circuit; The frequency control circuit receives a first frequency control signal to control the frequency of the gate scan signal; The reset circuit controls the voltage of the first node based on a reset signal.

17. The driving method according to claim 16, wherein The frequency control circuit receives a first frequency control signal to control the frequency of the gate scanning signal, and includes: The frequency control circuit receives the first frequency control signal and a second frequency control signal to control the frequency of the gate scanning signal.

18. A display device, characterized in that, It includes a processor and the driving circuit according to any one of claims 1-9 above, and the driving circuit is coupled to the processor.

19. A computer-readable storage medium, characterized in that, When a computer instruction runs on the display device, the display device is caused to execute the method according to any one of claims 16-17 above.

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