Drive circuit, display device, and drive method

Abstract

Embodiments of the present application provide a driving circuit, a display device and a driving method, and relate to the technical field of display. The embodiments improve the problem of voltage change in the GOA circuit, and improve the display effect of the display. The specific scheme is as follows: the driving circuit comprises a plurality of array driving scanning GOA circuits. The GOA circuit comprises a register circuit, an output circuit, a frequency control circuit and a reset circuit. The output circuit and the register circuit are coupled, configured to generate a gate scanning signal in response to the voltage of a pull-up node and the voltage of a pull-down node of the register circuit, and output the gate scanning signal to the corresponding pixel circuit of the GOA circuit. The frequency control circuit and the output circuit are coupled to a first node, configured to receive a first frequency control signal to control the frequency of the gate scanning signal. The reset circuit and the output circuit are coupled to the first node, configured to control the voltage of the first node based on a reset signal. The embodiments of the present application are used in the process of the driving circuit sending the gate scanning signal to the pixel circuit.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a driving circuit, a display device and a driving method. BACKGROUND

[0002] At present, in order to improve the user's video or game experience, the organic light emitting diode (OLED) display screen needs a very high refresh frequency (for example, 120 hertz (Hz)), and the high refresh frequency will cause the power consumption of the display screen to be large and the battery endurance to be reduced. In order to reduce the power consumption and improve the battery endurance, the existing OLED display screen uses low-temperature polycrystalline oxide (LTPO) technology, that is, a higher refresh frequency is used in a video or game scene, and a lower refresh frequency (for example, 1 Hz) is used in a static picture, thereby effectively saving the power consumption.

[0003] Among them, the array driving scanning (GOA) circuit can control the refresh frequency of the display, and by increasing the frequency control circuit in the GOA circuit, the refresh frequency of the local display area can be reduced. When the GOA circuit opens the local refresh frequency reduction function, the internal voltage change of the GOA circuit will affect the display effect of the display. SUMMARY

[0004] Embodiments of the present application provide a driving circuit, a display device and a driving method, which improve the problem of internal voltage change of the GOA circuit and improve the display effect of the display.

[0005] To achieve the above object, the embodiments of the present application adopt the following technical solutions.

[0006] In a first aspect, the embodiments of the present application provide a driving circuit, which includes a plurality of array driving scanning (GOA) circuits. The GOA circuit includes a register circuit, an output circuit, a frequency control circuit and a reset circuit. The output circuit and the register circuit are coupled and configured to generate a gate scanning signal in response to the voltage of a pull-up node and the voltage of a pull-down node of the register circuit, and output the gate scanning signal to the corresponding pixel circuit of the GOA circuit. The frequency control circuit and the output circuit are coupled at a first node, and configured to receive a first frequency control signal to control the frequency of the gate scanning signal. The reset circuit and the output circuit are coupled at the first node, and configured to control the voltage of the first node based on a reset signal.

[0007] Therefore, when the GOA circuit starts the local refresh frequency reduction function, the first node and the first frequency control signal are turned on, and the voltage of the first node is different, that is, the voltage of the first node can be positive or negative. The driving circuit can control the voltage of the first node through the reset circuit to maintain the voltage of the first node as the same value, so as to avoid the influence of the voltage change of the first node on the display effect of the display, improve the stability of the GOA circuit, and improve the display effect of the display.

[0008] In a possible design, the reset circuit includes a first transistor, a first end of the first transistor is coupled to the first node, a second end of the first transistor is coupled to the first voltage source, and a gate of the first transistor is configured to receive a reset signal. The reset circuit is specifically configured to control the voltage of the first node by the voltage output by the first voltage source when the reset signal controls the first transistor to be turned on. Therefore, the reset circuit can control the voltage of the first node by the voltage output by the first voltage source to maintain the voltage of the first node as the same value, so as to avoid the influence of the voltage change of the first node on the display effect of the display, improve the stability of the GOA circuit, and improve the display effect of the display.

[0009] In a possible design, the reset circuit further includes a second transistor, a first end of the second transistor is coupled to the first end of the first transistor, a second end of the second transistor is coupled to the first node, and a gate of the second transistor is coupled to the gate of the first transistor. Therefore, the second transistor is added between the first node and the first transistor, so as to reduce the cross voltage between the first end and the second end of the first transistor, and improve the reliability of the GOA circuit. In addition, the first transistor and the second transistor adopt a common gate structure, so as to improve the reliability of the transistor.

[0010] In a possible design, the frequency control circuit includes a third transistor, a first end of the third transistor is coupled to the register circuit, a second end of the third transistor is coupled to the output circuit, and a gate of the third transistor is configured to receive a second frequency control signal. The frequency control circuit is further configured to receive the first frequency control signal and the second frequency control signal to control the frequency of the gate scanning signal. Therefore, the frequency of the gate scanning signal is controlled by the first frequency control signal and the second frequency control signal, so that the GOA circuit can reduce the frequency of the clock signal when the GOA circuit is driven at a low frequency, so as to further reduce the power consumption of the driving circuit.

[0011] In a possible design, the output circuit further includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a first capacitor. A gate of the fourth transistor is coupled to an upper pull node, a first terminal of the fourth transistor is coupled to a gate high voltage source, a second terminal of the fourth transistor is coupled to a first terminal of the fifth transistor, a second terminal of the fifth transistor is coupled to a gate low voltage source, a gate of the fifth transistor is coupled to the upper pull node and a register circuit. The upper pull node is further coupled to a first terminal of the sixth transistor, a gate of the sixth transistor is coupled to the first node, a second terminal of the sixth transistor is coupled to a gate of the seventh transistor, a first terminal of the seventh transistor is coupled to the gate high voltage source, a second terminal of the seventh transistor is coupled to a first terminal of the eighth transistor, a second terminal of the eighth transistor is coupled to the gate low voltage source, and a gate of the eighth transistor is coupled to a lower pull node. A first terminal of the first capacitor is coupled to the gate of the sixth transistor, and a second terminal of the first capacitor is coupled to the second terminal of the sixth transistor.

[0012] In a possible design, the output circuit further includes a ninth transistor. A first terminal and a second terminal of the ninth transistor are both coupled to the first terminal of the fifth transistor, and a gate of the ninth transistor is coupled to the lower pull node. In this way, the output circuit can reduce the rising edge step of the cascade signal through the capacitive coupling effect of the ninth transistor, and optimize the quality of the cascade signal.

[0013] In a possible design, the output circuit further includes a tenth transistor. A first terminal of the tenth transistor is coupled to the lower pull node, a second terminal of the tenth transistor is coupled to the gate of the eighth transistor, and a gate of the tenth transistor is coupled to the first node. In this way, the tenth transistor can prevent the eighth transistor from being mistakenly turned on, and can improve the stability of the GOA circuit.

[0014] In a possible design, the output circuit further includes an eleventh transistor. A first terminal of the eleventh transistor is coupled to the gate high voltage source, a second terminal of the eleventh transistor is coupled to the second terminal of the sixth transistor, and a gate of the eleventh transistor is coupled to the gate of the eighth transistor. In this way, the eleventh transistor can accelerate the voltage drop of the gate scanning signal.

[0015] In a second aspect, an embodiment of the present application provides a display device. The display device includes a pixel array, a peripheral driving circuit and a plurality of driving circuits which are sequentially cascaded. The peripheral driving circuit includes at least one gate high voltage source, and the at least one gate high voltage source is coupled to a plurality of gate high voltage signal lines. Adjacent driving circuits in the plurality of driving circuits which are sequentially cascaded are respectively coupled to different gate high voltage signal lines.

[0016] Therefore, the display device provided by the embodiments of the present application can further reduce the resistance of the gate high voltage signal line and optimize the signal quality by coupling the gate high voltage source and the plurality of gate high voltage signal lines. In addition, the voltage disturbance of the gate high voltage between adjacent rows can be reduced by coupling the adjacent driving circuits to different gate high voltage signal lines.

[0017] In a possible design, the peripheral driving circuit further includes a level conversion circuit, and the at least one gate high voltage source includes a first gate high voltage source and a second gate high voltage source. The output circuit of the plurality of driving circuits connected in series is coupled to the first gate high voltage source, and the register circuit of the plurality of driving circuits connected in series is coupled to the second gate high voltage source. Therefore, the stability of the gate scanning signal output by the output circuit can be improved, and the signal disturbance can be reduced by providing the gate high voltage to the output circuit of the driving circuit by the first gate high voltage source and providing the gate high voltage to other circuits by the second gate high voltage source.

[0018] In a possible design, the driving current of the first gate high voltage source is greater than the driving current of the second gate high voltage source. Therefore, the first gate high voltage source can provide greater driving current to the output circuit, so as to ensure the stability of the gate scanning signal output by the output circuit and reduce the signal disturbance.

[0019] In a possible design, the at least one gate high voltage source includes a first gate high voltage source and a second gate high voltage source. The first transistor in the output circuit of the adjacent driving circuit is coupled to the gate high voltage signal line of the first gate high voltage source, and the other transistors in the output circuit of the adjacent driving circuit are coupled to the gate high voltage signal line of the second gate high voltage source. Therefore, the stability of the gate scanning signal output by the output circuit can be improved, and the signal disturbance can be reduced.

[0020] In a possible design, the output end of the first gate high voltage source is coupled to the plurality of parallel voltage stabilizing capacitors.

[0021] In a possible design, the first signal line of each output circuit is coupled to the corresponding gate high voltage signal line, and the length of the first signal line is such that each first signal line overlaps with the plurality of gate high voltage signal lines. Therefore, the impedances of the plurality of first signal lines are the same, and the difference in gate high voltage can be eliminated.

[0022] In a possible design, the gate high voltage signal line of the first gate high voltage source includes at least two metal layers, and the at least two metal layers are connected by at least one connection hole. Therefore, the impedance on the gate high voltage signal line of the first gate high voltage source can be reduced.

[0023] In a third aspect, an embodiment of the present application provides a driving method, the driving method being applied to a driving circuit, the driving circuit comprising a plurality of GOA circuits, each GOA circuit comprising a register circuit, an output circuit, a frequency control circuit and a reset circuit, the frequency control circuit, the output circuit and the reset circuit being coupled to a first node. The driving method comprises: the output circuit generating a gate scan signal in response to a voltage of a pull-up node and a voltage of a pull-down node of the register circuit, and outputting the gate scan signal to a pixel circuit corresponding to the GOA circuit; the frequency control circuit receiving a first frequency control signal to control a frequency of the gate scan signal; and the reset circuit controlling a voltage of the first node based on a reset signal.

[0024] In a possible design, the frequency control circuit receives the first frequency control signal to control the frequency of the gate scan signal, including: the frequency control circuit receiving a first frequency control signal and a second frequency control signal to control the frequency of the gate scan signal.

[0025] In a fourth aspect, an embodiment of the present application provides a display device, which comprises a processor and the driving circuit of the first aspect, and the driving circuit and the processor are coupled.

[0026] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, which comprises computer instructions, and when the computer instructions run on an electronic device, the electronic device executes the driving method in any possible implementation manner of the third aspect.

[0027] In a sixth aspect, an embodiment of the present application provides a computer program product, which, when running on a computer or a processor, causes the computer or the processor to execute the display driving method in any possible implementation manner of the third aspect.

[0028] It can be understood that any one of the driving circuit, the display device, the display device, the computer-readable storage medium or the computer program product provided above can be applied to the corresponding method provided above, and thus the beneficial effects achieved thereby can refer to the beneficial effects in the corresponding method, which will not be described herein again.

[0029] These aspects or other aspects of the present application will be more apparent in the following description. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A structural diagram of a display device provided by an embodiment of the present application;

[0031] Figure 2 A structural diagram of a pixel circuit provided by an embodiment of the present application;

[0032] Figure 3 A timing diagram of a pixel circuit provided by an embodiment of the present application;

[0033] Figure 4 A structure diagram of a gate driving circuit provided for an embodiment of the present application;

[0034] Figure 5 A timing diagram of a gate scanning signal of a gate driving circuit provided for an embodiment of the present application;

[0035] Figure 6 A structure diagram of a peripheral driving circuit provided for an embodiment of the present application;

[0036] Figure 7 A structure diagram of a multi-stage GOA circuit provided for an embodiment of the present application;

[0037] Figure 8 A timing diagram of a multi-stage GOA circuit provided for an embodiment of the present application;

[0038] Figure 9 A timing diagram of another multi-stage GOA circuit provided for an embodiment of the present application;

[0039] Figure 10 A partition schematic diagram of a display panel provided for an embodiment of the present application;

[0040] Figure 11 A timing diagram of a driving circuit in different refresh periods provided for an embodiment of the present application;

[0041] Figure 12 A voltage change diagram of an N1 node provided for an embodiment of the present application;

[0042] Figure 13 A waveform diagram of a signal provided for an embodiment of the present application;

[0043] Figure 14 A structure diagram of a driving circuit provided for an embodiment of the present application;

[0044] Figure 15 A timing diagram of another driving circuit provided for an embodiment of the present application;

[0045] Figure 16 A structure diagram of another driving circuit provided for an embodiment of the present application;

[0046] Figure 17 A structure diagram of still another driving circuit provided for an embodiment of the present application;

[0047] Figure 18 A structure diagram of still another driving circuit provided for an embodiment of the present application;

[0048] Figure 19 A structure diagram of still another driving circuit provided for an embodiment of the present application;

[0049] Figure 20 A structure diagram of another driving circuit provided for an embodiment of the present application;

[0050] Figure 21 A timing diagram of another driving circuit provided for an embodiment of the present application;

[0051] Figure 22 A waveform diagram of a gate scanning signal provided for an embodiment of the present application;

[0052] Figure 23 A structure diagram of another display device provided for an embodiment of the present application;

[0053] Figure 24 A structure diagram of another display device provided for an embodiment of the present application;

[0054] Figure 25 A structure diagram of another display device provided for an embodiment of the present application;

[0055] Figure 26 A structure diagram of another display device provided for an embodiment of the present application;

[0056] Figure 27 A schematic diagram of a gate high-voltage signal line provided for an embodiment of the present application;

[0057] Figure 28 A flow chart of a driving method provided for an embodiment of the present application;

[0058] Figure 29 A timing diagram of another driving circuit provided for an embodiment of the present application;

[0059] Figure 30 A timing diagram of another driving circuit provided for an embodiment of the present application;

[0060] Figure 31 A timing diagram of another driving circuit provided for an embodiment of the present application;

[0061] Figure 32 A timing diagram of another driving circuit provided for an embodiment of the present application. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " represents the meaning of or, for example, A / B can represent A or B; in this document, "and / or" is merely a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist together, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0063] Hereinafter, the terms "first", "second" are used for description purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the embodiments, unless otherwise specified, the meaning of "multiple" is two or more than two.

[0064] The embodiments of the present application use "first" and "second" and the like to distinguish objects with similar names or functions or effects. Those skilled in the art can understand that "first" and "second" and the like do not limit the number and execution order. The word "coupled" is used to represent electrical connection, including direct connection through wires or connection terminals or indirect connection through other devices. Therefore, "coupled" should be regarded as a general electronic communication connection.

[0065] It should be noted that in the present application, the words "exemplary" or "for example" are used to represent an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the use of "exemplary" or "for example" is intended to present the relevant concept in a specific manner.

[0066] In the circuit provided by the embodiments of the present disclosure, the first node, the second node and the third node do not represent actual existing components, but represent the convergence point of the relevant electrical connection in the circuit diagram, that is, these nodes are nodes equivalent to the convergence point of the relevant electrical connection in the circuit diagram.

[0067] In embodiments of the present application, the transistor can adopt a thin film transistor (TFT) such as a hydrogenated amorphous silicon (a-Si:H) TFT, a low temperature poly silicon (LTPS) TFT, an amorphous oxide semiconductor (AOS) TFT, and the like. The transistor is divided into two types of N (negative) type transistor and P (positive) type transistor. The transistor includes a source, a drain, and a gate, and the on or off of the transistor can be controlled by controlling the voltage size of the input transistor gate. When the transistor is on, the source and the drain are on, and a conduction current is generated, and the size of the conduction current generated between the source and the drain is different when the voltage size of the transistor gate is different; when the transistor is off or turned off, the source and the drain are not on, and only a small off-state current is generated. In embodiments of the present application, the source of the transistor is referred to as the first end, and the drain is referred to as the second end; or, the drain is referred to as the first end, and the source is referred to as the second end. In addition, the N-type transistor is on when the gate level is high, the first end and the second end are on, and a conduction current is generated between the first end and the second end; the N-type transistor is off when the gate level is low, the first end and the second end are not on, and only a small off-state current is generated. The P-type transistor is on when the gate level is low, the first end and the second end are on, and a conduction current is generated; the P-type transistor is off when the gate level is high, the first end and the second end are not on, and only a small off-state current is generated.

[0068] The technical scheme provided by the embodiments of the present application can be applied to various electronic devices including display devices. The electronic devices are, for example, consumer electronic products, household electronic products, vehicle-mounted electronic products, and financial electronic device products with display functions. The consumer electronic products are, for example, mobile phones, pads, notebook computers, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop displays, smart wearable products (for example, smart watches and smart bands), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, and unmanned aerial vehicles. The household electronic products are, for example, smart door locks, televisions, remote controls, refrigerators, and small household appliances (for example, soybean milk machines and sweeping robots) for charging. The vehicle-mounted electronic products are, for example, vehicle-mounted navigation devices and vehicle-mounted high-density digital video discs (DVDs). The financial electronic device products are, for example, automated teller machines (ATMs) and self-service electronic devices. The embodiments of the present application do not specially limit the specific forms of the above electronic devices.

[0069] For ease of understanding, the specific structure of the display device will be introduced first.

[0070] As shown in FIG. 1, Figure 1 Figure 1 is a structural diagram of a display device provided by the embodiments of the present application. The display device 10 can include an active area (AA) 100, a non-active area (NA) 200, a data control circuit 300, and a peripheral driving circuit 400. The active area 100 and the non-active area 200 form a display panel 11, the active area 100 is a pixel light-emitting area, and the non-active area 200 is an area in the display panel 11 that does not emit light. The data control circuit 300 is configured to provide data signals (DS) to the display panel 11 after receiving external image information, and the data signals are digital signals that determine the pixel light-emitting current in the pixel circuit programming. The peripheral driving circuit 400 is configured to provide multiple sets of control signals (CS) and multiple pixel voltages (PVs) required by the display panel.

[0071] ​Specifically, the active display area 100 can include a plurality of pixels arranged in an array (i.e., a pixel array), a plurality of data lines, and a plurality of gate scanning lines. Each data line is coupled to a plurality of pixels along the Y direction, and each gate scanning line is coupled to a plurality of pixels along the X direction. Each pixel is coupled to a data line, a gate scanning line, a power voltage (a positive power voltage (ELVDD) and a negative power voltage (ELVSS)) line, and an initialization voltage (VINI) line. The pixel can be understood as a pixel circuit, which can include a light-emitting diode and a circuit unit for controlling the light-emitting diode. The light-emitting diode can be an OLED, a quantum dot light-emitting diode (QLED), a mini LED, or a micro LED. The circuit unit can control the current value of the positive power voltage (ELVDD) to the negative power voltage (ELVSS) when executing a specific pixel circuit timing, and the light-emitting diode can emit light of a specific brightness under a specific current value.

[0072] The non-active display area 200 is located on one side or both sides of the active display area 100, and can include a plurality of gate driving circuits. Since the non-active display area 200 adopts the GOA technology, the gate driving circuit is also called a GOA circuit. After receiving a control signal, the GOA circuit can generate a plurality of row-by-row output shift pulse signals, i.e., a plurality of gate scanning signals. Each gate signal line (GL) is coupled to one or more rows of pixel circuits, and the gate scanning signal is output row by row to control the thin-film transistor (TFT) in the pixel circuit to open or close row by row. Continuing to refer to Figure 1 , the non-active display area 200 can include k gate driving circuits, which are a first gate driving circuit, a second gate driving circuit, a third gate driving circuit, …, and a kth gate driving circuit. Each gate driving circuit outputs a gate scanning signal for controlling a plurality of rows of pixel circuits, such as S1_1, S2_1, S3_1, …, and Sk_1 for controlling the first row of pixel circuits, and S1_n, S2_n, S3_n, …, and Sk_n for controlling the nth row of pixel circuits.

[0073] The data control circuit 300 is used to provide a plurality of groups of data signals. The data control circuit 300 transmits data signals to the pixel circuits in the display panel 11 through a plurality of data lines, so that the pixel circuits can work normally. The number of the plurality of data lines can be the same as the total number of columns of the pixel array composed of the pixel circuits.

[0074] The peripheral driving circuit 400 is configured to provide a plurality of groups of control signals, which can include a start voltage signal (STV), a clock signal (CLK), a gate high-level voltage (VGH), and a gate low-level voltage (VGL). After receiving the control signals, the gate driving circuit generates corresponding gate scanning signals with high and low levels. In addition, the peripheral driving circuit 400 is also configured to provide a plurality of groups of pixel voltages, which can include power voltages (VDD and VSS) and an initialization voltage. The peripheral driving circuit 400 transmits the pixel voltage values to the pixel circuits in the display panel 11 through a plurality of signal lines, so that the pixel circuits can work normally.

[0075] After the display panel is loaded with the driving timing and voltage settings, the brightness and refresh rate of the pixel circuits can be configured. The driving timing refers to a group of gate control signals, which includes a plurality of signal waveforms with voltage changes over time. The refresh rate refers to the number of times the display panel can be refreshed per second. Each time the display panel is refreshed, the data voltage needs to be written from the first row of pixel circuits to the last row of pixel circuits. Limited by the data voltage writing speed, the display panel has a maximum refresh rate N, that is, only N frames of images will be refreshed per second, and the time of one frame of image is 1 / N second. At the maximum refresh rate, the pixel circuits always operate in the data refresh period, which includes N refresh frames per second. The refresh frame is a frame of time in which the data voltage is updated, and the pixel circuits of the display panel execute the refresh frame driving timing within the refresh frame. Taking 120 Hz as an example, the display panel is refreshed 120 times per second. Assuming that the period of one refresh of the display panel is T, then T = 1 / 120 s, which is about 8.333 ms. At a low refresh rate, for example, 1 Hz, the display panel is refreshed once per second, including 1 refresh frame and 119 hold frames, and each frame time is still divided by 8.333 ms. Assuming that the display panel has a total of M rows of pixels in the effective display area, the charging time or refresh time H of one row of pixels satisfies the following relationship: H = T / M. Assuming that M = 2844 and T = 8.333 ms, then H = 8.333 / 2844 ms, which is about 2.93 us. The 1H time can be flexibly set according to the number of display rows, the refresh rate, and the vertical blanking area time, and the specific time length of 1H is not limited in the embodiments of the present application.

[0076] In Figure 1 Based on the display device shown in FIG. 1, the pixel circuit, the gate driving circuit, and the peripheral driving circuit are further introduced below.

[0077] The pixel circuit can adopt the LTPO technology, for example, as shown in FIG. 2. Figure 2As shown in (a), the pixel circuit may include a first transistor T1, a second transistor T2, a driving transistor Td, a capacitor C1, a light-emitting diode D1, a first driving circuit module, a second driving circuit module, and a third driving circuit module. The first transistor T1 is an N-type transistor and may be indium gallium zinc oxide (IGZO). The second transistor T2 is a P-type transistor and may be low-temperature polysilicon (LTPS). The gate scan signal for the first transistor T1 is S1, and the gate scan signal for the second transistor T2 is S2.

[0078] In one possible example, such as Figure 2 As shown in (b), the first driving circuit module may include a fifth transistor T5 and a sixth transistor T6, the second driving circuit module includes a third transistor T3 and a seventh transistor T7, and the third driving circuit module includes a fourth transistor T4. This pixel circuit can also be called an 8T1C circuit, wherein the gate scan signal of the third transistor T3 is S3, the gate scan signal of the fourth transistor T4 is S4, the gate scan signal of the fifth transistor T5 is S5, and the gate scan signals of the sixth transistor T6 and the seventh transistor T7 are emission signals (EM). One end of the third transistor T3 is used to input a first initialization voltage (VINI1), one end of the fourth transistor T4 is used to input a second initialization voltage (VINI2), one end of the fifth transistor T5 is used to input a third initialization voltage (VINI3), and one end of the second transistor T2 is used to input a data signal (DATA). It is understood that the pixel circuit structure can also be in other forms, such as 6T1C, 7T1C, 9T2C, and 9T3C, etc. This application embodiment does not limit the specific structure of the pixel circuit.

[0079] The switching of transistors within the pixel circuit is determined by the gate scan signal. The timing diagrams of S1 and S2 in the j-th and j+1-th refresh cycles are shown below. Figure 3 As shown in the diagram. S1 is a positive waveform of a certain length during the non-light-emitting period, with a duration of any value such as 2H or 6H. S2 is a negative waveform of a certain length during the non-light-emitting period, with a duration of any value such as 1H, 2H, or 0.7H. To ensure that sufficient data signal can be written to the gate of the driving transistor, the pulse width of S1 is longer than that of S2. That is, the first transistor T1 turns on earlier and turns off later than the second transistor T2.

[0080] The gate drive circuit may include multiple levels of circuit units, such as... Figure 4 As shown, Figure 4A structural diagram of a gate drive circuit is provided for an embodiment of the present application. Figure 4 The n-stage circuit units are shown in FIG. 1, which are circuit unit 1, circuit unit 2, circuit unit 3, …, and circuit unit n. Circuit unit 1 outputs a gate scanning signal out_1, circuit unit 2 outputs a gate scanning signal out_2, circuit unit 3 outputs a gate scanning signal out_3, and circuit unit n outputs a gate scanning signal out_n. out_1 to out_n correspond to the 1st row of pixel circuits to the nth row of pixel circuits, that is, one row of gate scanning signals can control one row of pixel circuits. In addition, one row of gate scanning signals can also control two rows of pixel circuits, for example, the gate scanning signal out_1 can correspond to the 1st row of pixel circuits and the 2nd row of pixel circuits, the gate scanning signal out_2 can correspond to the 3rd row of pixel circuits and the 4th row of pixel circuits, and so on, the gate scanning signal out_n can correspond to the (2n-1)th row of pixel circuits and the 2nth row of pixel circuits.

[0081] Continuing to refer to Figure 4 , after circuit unit 1 receives the start frame signal (STV), the first clock signal (CLK_1), the second clock signal (CLK_2), the gate high voltage (VGH), and the gate low voltage (VGL) generated by the peripheral drive circuit, it responds to generate the row-by-row output gate scanning signals out_1 to out_n. Among them, circuit unit 1 is coupled with the start frame signal line, and the other circuit units are respectively coupled with the output end of the previous stage circuit unit, and the gate scanning signal output by the previous stage circuit unit serves as the start signal of the next stage circuit unit. For example, the input end of circuit unit 2 is coupled with the output end of circuit unit 1, and the gate scanning signal out_1 output by circuit unit 1 serves as the input signal of circuit unit 2. Alternatively, the input end of circuit unit 3 is coupled with the output end of circuit unit 2, and the gate scanning signal out_2 output by circuit unit 2 serves as the input signal of circuit unit 3. In addition, the CLK_1 and CLK_2 are connected in a fixed order for each stage of circuit units, for example, circuit unit 1 is connected with CLK_1 and CLK_2, circuit unit 2 is connected with CLK_2 and CLK_1, circuit unit 3 is connected with CLK_1 and CLK_2, and so on.

[0082] As shown in Figure 5 , Figure 5 is a timing diagram of the gate scanning signals of the gate drive circuit in Figure 4 , Figure 5The timing diagram of the start frame signal (STV), the first clock signal (CLK_1), the second clock signal (CLK_2), and the gate scanning signals out_1 to out_n is specifically shown. The gate scanning signals are square wave signals switching between high and low voltages, the high voltage value of the gate scanning signals is equal to the voltage value of the high gate signal voltage (VGH1), and the low voltage value of the gate scanning signals is equal to the voltage value of the low gate signal voltage (VGL1). The interval time between each row of gate scanning signals can be 1H, 2H, 4H, or any equal amount of time, and the gate driving circuit can output a positive voltage pulse waveform row by row to achieve row-by-row scanning and voltage writing of the AA zone pixel circuit.

[0083] The structure diagram of the peripheral driving circuit is shown in Figure 6 The peripheral driving circuit can generate control signals and pixel voltage signals. Specifically, the peripheral driving circuit can include various voltage regulators, such as a gate high voltage regulator, a gate low voltage regulator, an ELVSS voltage regulator, an ELVDD voltage regulator, and a VINI voltage regulator. The gate high voltage regulator can generate VGH1 and VGH2, the gate low voltage regulator can generate VGL1 and VGL2, and the VINI voltage regulator can generate VINI1, VINI2, …, and VININ. The voltage regulator can be a low-dropout regulator (LDO), a buck-boost converter, or a charge pump, etc. The gate high voltage regulator and the gate low voltage regulator can also be integrated in the same module, such as a power management integrated circuit (PMIC), which is not limited in the embodiments of the present application.

[0084] In addition, continuing to refer to Figure 6The peripheral driving circuit can further include a digital voltage signal source which can generate a digital form of the start frame signal (data STV, DSTV) and a digital form of the clock signal (data CLK, DCLK). The peripheral driving circuit can further include a level conversion circuit which can convert the DSTV into STV_1 to STV_N and convert the DCLK into CLK_1, CLK_2, …, CLK_N according to the voltage values of VGH1, VGH2, VGL1 and VGL2. The high voltage value of the converted start frame signal and clock signal can be VGH1 or VGH2, and the low voltage value can be VGL1 or VGL2. When the voltage values of VGH1, VGH2, VGL1 or VGL2 change, the voltage values of STV_1 to STV_N and CLK_1 to CLK_N also dynamically change. Further, the peripheral driving circuit also outputs a control signal to the gate driving circuit, so that the gate driving circuit can output gate control signals with different high and low voltage values.

[0085] In order to reduce the driving power consumption of the display device, a partition control frequency mode is proposed. The GOA circuit in this mode includes a plurality of circuit units, each of which includes a register circuit and an output circuit. Specifically, the output circuit includes a frequency control circuit and a first frequency control signal PS1. When PS1 is low, the GOA circuit outputs an effective pulse signal, and when PS1 is high, the GOA circuit does not output an effective pulse signal. By switching the high and low levels of PS1 waveform at a certain time, it can be controlled whether the GOA circuit of some rows outputs an effective pulse signal within the frame. For example, according to the user's usage scenario, the refresh rate of the pixel circuit of some rows in the AA area can be selectively lower than that of some other rows of pixel circuit, thereby reducing the driving power consumption of the display device.

[0086] Taking the positive voltage waveform of a certain length of the gate scanning signal output by the GOA circuit as an example, as shown in Figure 7 Figure 7 ​The m-1th, mth and m+1th GOA circuits are shown in FIG. 1. Each GOA circuit includes a register circuit, an output circuit and a frequency control circuit, and the output circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a fifth transistor T5. The gate of the first transistor T1, the first terminal of the third transistor T3 and the register circuit are coupled to a pull up (PU) node, the gate of the second transistor T2, the first terminal of the fifth transistor T5 and the register circuit are coupled to a pull down (PD) node, the second terminal of the third transistor and the gate of the fourth transistor T4 are coupled to a buffer pull up (BPU) node, and the gate of the third transistor T3 and a partition control circuit are coupled to an N1 node.

[0087] It can be understood that the first transistor of the m-1th GOA circuit is denoted as T1_m-1, the first transistor of the mth GOA circuit is denoted as T1_m, and the first transistor of the m+1th GOA circuit is denoted as T1_m+1. The following denotation method is similar and will not be described in detail.

[0088] Taking the mth GOA circuit as an example, the register circuit m receives a cascade signal SR_m-1 output by the previous stage GOA circuit, and outputs a cascade signal SR_m of the GOA circuit to the register circuit m+1 of the next stage GOA circuit, and the register circuit m also outputs a pull up signal PU_m and a pull down signal PD_m. When the local refresh frequency reduction function is closed, the third transistor T3_m receives PU_m, and the fifth transistor T5_m receives PD_m, the next stage GOA circuit continues to receive SR_m and continues to transmit signals to the next stage GOA circuit, and so on. When the local refresh frequency reduction function is opened, the gate of the third transistor T3 is used to input PS1, and PS1 controls the conduction or closing of the third transistor T3. For example, if PS1 is high, the third transistor T3 is closed, and the fourth transistor T4 is also closed, at this time the GOA circuit does not output a valid gate scanning signal.

[0089] Figure 7 A timing diagram of the GOA circuit in FIG. 1 is shown in FIG. 2. Figure 8 A timing diagram of the GOA circuit in FIG. 1 is shown in FIG. 2. Figure 8 A timing diagram of the GOA circuit in FIG. 1 is shown in FIG. 2.

[0090] When the register circuit in the mth-stage GOA circuit generates PU_m, PS1 is low, the gate of the fourth transistor T4_m (i.e. the BPU node) is written with low, and the gate scanning signal S1_m is normally output. When the register circuit in the m+1th-stage GOA circuit generates PU_m+1, PS1 is switched to high, the gate of the first transistor T1_m+1 remains high, and the gate scanning signal out_m+1 is not output. Within 1s, there can be 120 refresh frames, and PS1 can control S1_m to output 120 times and S1_m+1 to output 1 time, so that 120Hz and 1Hz exist simultaneously for different rows of pixels of the display panel.

[0091] Figure 7 Another timing diagram of the GOA circuit in FIG. 8 is shown in FIG. 9, Figure 9 Figure 9 In FIG. 9, only the timing diagrams of the gate scanning signals of the m-1th-stage GOA circuit, the mth-stage GOA circuit, the m+1th-stage GOA circuit and the m+2th-stage GOA circuit are shown. Among them, S1_m+1 can not be output in the first frame, and can be output in the subsequent second frame. That is, as long as the output frequency of S1_m+1 is lower than that of S1_m, a lower frequency driving frequency display can be realized, for example, the upper half of the display panel can be 120Hz, and the lower half can be 60Hz.

[0092] As shown in FIG. 10, Figure 10 Figure 10 FIG. 11 is a graphical illustration of a display panel after the partition function is turned on. The partitioning accuracy can be determined by the actual display picture requirement. The partitioning accuracy of the display screen can be 1 row, 2 rows or multiple rows, Figure 10 (a) in FIG. 12 shows the partitioning of a display screen with a partitioning accuracy of 2 rows. The number of partitions is greater than or equal to 2, and the frequency of each partition can be 240Hz, 144Hz, 120Hz, 60Hz, 30Hz, 10Hz, 1Hz and 0.1Hz, etc. The display device can have the same or different display frequencies in any number of display regions, such as 2, 3 or 4.

[0093] Figure 10 FIG. 13 shows an 8-stage GOA circuit, which is GOA1, GOA2, …, GOA8. In Figure 10 (b) in FIG. 14 includes 2 partitions, in which the partition composed of GOA1 and GOA2 uses a refresh rate of 120Hz, and the partition composed of GOA3 to GOA8 uses a refresh rate of 10Hz. In Figure 10 (c) in FIG. 15 also includes 2 partitions, in which the partition composed of GOA1 to GOA4 uses a refresh rate of 120Hz, and the partition composed of GOA5 to GOA8 uses a refresh rate of 10Hz. In Figure 10 ​​The (d) section also includes two partitions: partitions GOA1 to GOA6 use a 120Hz refresh rate, while partitions GOA7 to GOA8 use a 10Hz refresh rate. Figure 10 (e) in the diagram includes three partitions: partitions GOA1 to GOA2 use a 120Hz refresh rate, partitions GOA3 to GOA4 use a 60Hz refresh rate, and partitions GOA5 to GOA8 use a 30Hz refresh rate. Figure 10 The (f) in the diagram also includes three partitions: partitions GOA1 to GOA2 use a 120Hz refresh rate, partitions GOA3 to GOA6 use a 60Hz refresh rate, and partitions GOA7 to GOA8 use a 30Hz refresh rate. Figure 10 The (g) in the code also includes three partitions: partitions GOA1 to GOA4 use a 120Hz refresh rate, partitions GOA5 to GOA6 use a 60Hz refresh rate, and partitions GOA7 to GOA8 use a 30Hz refresh rate. Figure 11 The (h) in the figure includes four partitions: partitions consisting of GOA1 to GOA2 use a refresh rate of 120Hz, partitions consisting of GOA3 to GOA4 use a refresh rate of 60Hz, partitions consisting of GOA5 to GOA6 use a refresh rate of 30Hz, and partitions consisting of GOA7 to GOA8 use a refresh rate of 10Hz.

[0094] However, due to the voltage difference of PS1, the input of the frequency control circuit in the GOA circuit, in the high and low frequency regions, the voltage of node N1 also differs when the refresh rate output is high and the refresh rate output is low. That is, node N1 is at a high level when the GOA circuit does not output a valid pulse signal, and at a low level when the GOA circuit outputs a valid pulse signal.

[0095] like Figure 11 As shown, Figure 11 The timing diagrams for the j-th refresh cycle and the (j+1)-th refresh cycle are shown in the figure. Figure 12 The diagram shows the timing diagrams of CLK1, CLK2, the first frequency control signal PS1, STV, and the nodes of the m-th and (m+1)-th stage GOA circuits of the drive circuit. The nodes of the m-th stage GOA circuit include: N1_m, PU_m, PD_m, BPU_m, S1_m, and SR_m. The nodes of the (m+1)-th stage GOA circuit include: N1_m+1, PU_m+1, PD_m+1, BPU_m+1, S1_m+1, and SR_m+1.

[0096] Wherein, S1_m is high frequency output, S1_m+1 is low frequency output. From the jth refresh cycle SR_m output interface to the j+1th refresh cycle SR_m output open this time, N1_m is always maintained in low level state. From the jth refresh cycle SR_m+1 output end to the j+1th refresh cycle SR_m+1 output open this time, N1_m+1 is always maintained as high level state.

[0097] Specifically, in the jth refresh cycle, S1_m is an effective pulse signal, and its working principle is as follows:

[0098] (1) t1 period: SR_m-1 signal voltage is converted from VGL to VGH, the mth GOA circuit is activated, at this time, the first frequency control signal PS1 is VGL, the potential of N1_m node is also VGL, T3_m is opened, the potential of PD_m node is converted from VGL to VGH, T2_m and T5_m are closed.

[0099] (2) t2 period: because T3_m is opened, the potential of PU_m node is converted from VGH to VGL, the potential of BPU_m node is also converted from VGH to VGL, the potential of N1_m node is pulled down to VGL* due to the capacitive coupling effect, wherein the amplitude of VGL* is close to 2*VGL-VGH. T1_m is opened, SR_m starts to output, T4_m is opened, S1_m starts to output.

[0100] (3) t4 period: SR_m-1 signal voltage is converted from VGH to VGL, the GOA circuit will end the output of SR and S1 in t5 period.

[0101] (4) t5 period: the potential of PU_m node is converted from VGL to VGH, the potential of PD_m node is converted from VGH to VGL, the potential of N1_m node is coupled from VGL* to VGL, the potential of BPU_m node is converted from VGL to VGH. T1_m is closed, T2_m is opened, SR_m output ends. T4_m is closed, T5_m is opened, S1_m output ends.

[0102] In the jth refresh cycle, S1_m+1 is an invalid pulse signal, and its working principle is as follows:

[0103] (1) t2 period: SR_m signal voltage is converted from VGL to VGH, the m+1th GOA circuit is activated, reset circuit_m+1 is configured to be in conduction state, at this time, PS1 signal is VGH, the potential of N1_m+1 node is converted from VGL to VGH, T3_m+1 transistor is closed, the potential of PD_m+1 node is converted from VGL to VGH, T2_m+1, T5_m+1 are closed.

[0104] (2) During time period t3: The potential of node PU_m+1 changes from VGH to VGL, but since T3_m+1 is off, the potentials of nodes PD_m+1 and BPU_m+1 remain at VGH. The potential of node N1_m+1 remains at VGH, T1_m+1 is on, SR_m+1 starts outputting, T4_m+1 is off, and S1_m+1 has no signal output.

[0105] (3) t5 period: The SR_m signal voltage changes from VGH to VGL, and the GOA_m+1 circuit will output at the end of the t6 period.

[0106] (4) During time period t6: The potential of node PU_m+1 changes from VGL to VGH, the potential of node PD_m+1 changes from VGH to VGL, T1_m is turned off, T2_m is turned on, and the output of SR_m+1 ends. The potentials of nodes N1_m+1 and BPU_m+1 remain at VGH, T4_m+1 is turned off, T5_m+1 is turned on, and the output of S1_m+1 ends.

[0107] During the (j+1)th refresh cycle, the PS1 signal always maintains VGL, and both S1_m and S1_m+1 are output. The working principle and the type of S1_m in the jth refresh cycle will not be elaborated here.

[0108] In one possible example, such as Figure 12 As shown in (a), when the PS1 signal is low, the voltage difference between the gate and drain of the third transistor T3 is Vgd = 3.9V, and the voltage difference between the drain and source of the third transistor T3 is Vds = 0V. Figure 13 As shown in (b), when the PS1 signal is low, the voltage difference between the gate and drain of the third transistor T3 is Vgd = -14.7V, and the voltage difference between the drain and source of the third transistor T3 is Vds = 14.1V. Therefore, if the partitioning function of the GOA circuit is enabled in a fixed position for a long period, TFT device characteristic drift will occur, resulting in uneven display between high refresh rate and low refresh rate areas.

[0109] In addition, such as Figure 13 As shown, Figure 14 The diagram shows the waveforms of the PU node, PD node, and gate scan signal. The PU node waveform changes earlier than the PD node, and step noise appears in the cascaded signal when the PU node voltage rises. Since the cascaded signal is used to implement the shift output of the GOA circuit, the presence of step noise on the rising edge of the cascaded signal will cause the gate scan signal waveform to become unsmooth, potentially leading to gate scan signal distortion and affecting its accuracy.

[0110] Therefore, the embodiment of the present application provides a driving circuit, the driving circuit increases the reset circuit, the voltage of the N1 node can be controlled by the reset circuit, the voltage of the N1 node can be maintained as the same value, the influence of the voltage change of the N1 node on the display effect of the display can be avoided, the stability of the GOA circuit is improved, and the display effect of the display is improved.

[0111] The driving circuit provided by the embodiment of the present application will be further described below with reference to the accompanying drawings.

[0112] The embodiment of the present application provides a driving circuit, as shown in the figure, Figure 14 The driving circuit includes a plurality of GOA circuits, and the GOA circuit includes a register circuit, an output circuit, a frequency control circuit and a reset circuit. Figure 15 The structure diagrams of n GOA circuits are shown in the figure, which are GOA circuit_1, GOA circuit_2, …, and GOA circuit_n respectively.

[0113] The output circuit and the register circuit are coupled, and the output circuit is configured to generate a gate scanning signal in response to the voltage of the pull-up node and the voltage of the pull-down node of the register circuit, and output the gate scanning signal to the corresponding pixel circuit of the GOA circuit.

[0114] For example, the register circuit can receive a carry signal, which can be a start frame signal or a cascade signal output by the previous GOA circuit. The register circuit and the output circuit are coupled to the pull-up node and the pull-down node, the signal of the pull-up node is PU signal, and the signal of the pull-down node is PD signal. When the PU signal is low and the PD signal is high, the output circuit outputs a high-level gate scanning signal; when the PU signal is high and the PD signal is low, the output circuit outputs a low-level gate scanning signal.

[0115] It can be understood that the gate scanning signal provided by the embodiment of the present application is commonly used for turning on or turning off the first transistor T1 in the pixel circuit, that is, the gate scanning signal is S1.

[0116] The frequency control circuit and the output circuit are coupled to the first node, and the frequency control circuit is configured to receive a first frequency control signal to control the frequency of the gate scanning signal.

[0117] For example, when the first frequency control signal is low, the gate scanning signal output by the output circuit is an effective pulse signal; when the first frequency control signal is high, the gate scanning signal output by the output circuit is an ineffective pulse signal. Therefore, the partition function of the display screen can be realized by the frequency control circuit.

[0118] The reset circuit and the output circuit are coupled to the first node, and the reset circuit is configured to control the voltage of the first node based on the reset signal.

[0119] For example, the driving circuit can control the voltage of the first node through the reset circuit to eliminate the difference in voltage between the first nodes of different GOA circuits over a long period of time. This can avoid the impact of voltage changes of the first node on the display effect of the monitor, improve the stability of the GOA circuit, and improve the display effect of the monitor.

[0120] For example, such as Figure 15 As shown, Figure 11 In China Figure 15 Based on this, timing diagrams for frequency control circuit _m, reset circuit _m, frequency control circuit _m+1, and reset circuit _m+1 are also shown. The reset circuit _m is turned off when the frequency control circuit is turned on (at time t1) and turns on again after S1 output is complete (at time t6). From... Figure 16 As can be seen, the voltages of N1_m and N1_m+1 remain at a low level for a period of time between two refresh cycles. This avoids voltage fluctuations at node N1, improves the stability of the GOA circuit, and enhances the display's performance.

[0121] Optional, such as Figure 16 As shown, Figure 16 The diagram shows the structural schematics of the (m-1)th stage GOA circuit, the mth stage GOA circuit, and the (m+1)th stage GOA circuit. The reset circuit includes the first transistor ( Figure 16 (represented by T1), the first terminal and the first node of the first transistor T1 ( Figure 16 (represented by N1) is coupled, the second terminal of the first transistor T1 and the first voltage source ( Figure 16 (represented by V1) coupling, the gate of the first transistor T1 is used to receive the reset signal ( Figure 16 (represented by Vrs in Chinese).

[0122] Specifically, the reset circuit is configured to control the voltage of the first node by means of the voltage output from the first voltage source when the reset signal controls the first transistor to turn on.

[0123] For example, the register circuit may include a register sub-circuit and a second node. The reset signal may originate from a second node in the register circuit. Figure 16 (Represented by N2 in the diagram), this second node N2 can also be called a bootstrap node. The second node N2 and the twelfth transistor ( Figure 16 The first terminal of the twelfth transistor T12 is coupled to either the first clock signal CLK_1 or the second clock signal CLK_2. The second node N2 is also coupled to the fourth capacitor (…).Figure 16 a first end of the fourth capacitor C4 is coupled to the first node N1, and a second end of the fourth capacitor C4 is coupled to a third node N3. Figure 17

[0124] For example, the voltage outputted by the first voltage source can be a low level, and in one possible example, the voltage outputted by the first voltage source can be VGL. The voltage outputted by the first voltage source can also be any voltage signal lower than VGH. When the first transistor T1 is turned on, the voltage of the first node N1 is lower than the voltage outputted by the first voltage source due to the presence of the first transistor T1.

[0125] Optionally, as shown in Figure 17 , Figure 16 based on Figure 17 , a structure diagram of the m-1th GOA circuit, the mth GOA circuit and the m+1th GOA circuit is shown. The reset transistor further includes a second transistor (denoted as T2). Figure 18 The first end of the second transistor T2 is coupled to the first end of the first transistor T1, the second end of the second transistor T2 is coupled to the first node N1, and the gate of the second transistor T2 is coupled to the gate of the first transistor T1.

[0126] For example, adding the second transistor T2 between the first node N1 and the first transistor T1 can reduce the voltage across the first end and the second end of the first transistor T1, thereby improving the reliability of the GOA circuit. In addition, the first transistor T1 and the second transistor T2 adopt a common gate structure, which can improve the reliability of the transistor.

[0127] Optionally, as shown in Figure 18 , the frequency control circuit includes a third transistor (denoted as T3). Figure 16 The first end of the third transistor T3 is coupled to the register circuit, the second end of the third transistor T3 is coupled to the output circuit, and the gate of the third transistor T3 is configured to receive a second frequency control signal.

[0128] The frequency control circuit is further configured to receive the first frequency control signal and the second frequency control signal to control the frequency of the gate scanning signal.

[0129] For example, by jointly controlling the frequency of the gate scanning signal through the first frequency control signal and the second frequency control signal, the GOA circuit can reduce the frequency of the clock signal when driven at a low frequency, thereby further reducing the power consumption of the driving circuit.

[0130] Optionally, as shown in Figure 17 , Figure 18 or Figure 16 ​The output circuit includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a first capacitor C1. The gate and register circuit of the fourth transistor T4 are coupled to a pull-up node, and the first terminal of the fourth transistor T4 is connected to a high-voltage source at its gate (…). Figure 17 , Figure 18 or Figure 16 (represented by VGH) coupling, the second terminal of the fourth transistor T4 is coupled to the first terminal of the fifth transistor T5, and the second terminal of the fifth transistor T5 is coupled to the gate low voltage source ( Figure 17 , Figure 18 or Figure 19 The fifth transistor T5 (represented by VGL) is coupled to the pull-down node, with its gate and register circuit coupled to the pull-up node. The pull-up node is also coupled to the first terminal of the sixth transistor T6. The gate of the sixth transistor T6 is coupled to the first node N1. The second terminal of the sixth transistor T6 is coupled to the gate of the seventh transistor T7. The first terminal of the seventh transistor T7 is coupled to the gate high-voltage source VGH. The second terminal of the seventh transistor T7 is coupled to the first terminal of the eighth transistor T8. The second terminal of the eighth transistor T8 is coupled to the gate low-voltage source VGL. The gate of the eighth transistor T8 is coupled to the pull-down node. The first terminal of the first capacitor C1 is coupled to the gate of the sixth transistor T6, and the second terminal of the first capacitor C2 is coupled to the second terminal of the sixth transistor T6.

[0131] Optional, such as Figure 19 As shown, the output circuit also includes a ninth transistor ( Figure 19 (represented by T9 in the text), the first and second terminals of the ninth transistor T9 are both coupled to the first terminal of the fifth transistor T5, and the gate and pull-down node of the ninth transistor T9 are coupled.

[0132] For example, the output circuit can reduce the rising edge step of the cascaded signal and optimize the quality of the cascaded signal by using the capacitive coupling effect of the ninth transistor.

[0133] Optional, please continue reading Figure 19 The output circuit also includes the tenth transistor ( Figure 19 (represented by T10 in the text), the first terminal of the tenth transistor T10 is coupled to the pull-down node, the second terminal of the tenth transistor T10 is coupled to the gate of the eighth transistor T8, and the gate of the tenth transistor T10 is coupled to the first node N1.

[0134] For example, the tenth transistor T10 can prevent the eighth transistor T8 from turning on accidentally, which can improve the stability of the GOA circuit.

[0135] Optional, please continue reading Figure 19 The output circuit also includes an eleventh transistor ( Figure 19(represented by T11 in the text), the first terminal of the eleventh transistor T11 is coupled to the gate high voltage source VGH, the second terminal of the eleventh transistor T11 is coupled to the second terminal of the sixth transistor T6, and the gate of the eleventh transistor T11 is coupled to the gate of the eighth transistor T8.

[0136] For example, the voltage drop of the gate scan signal can be accelerated by the eleventh transistor T11.

[0137] In addition, please continue to refer to Figure 19 The output circuit also includes a second capacitor ( Figure 19 (represented by C2) and the third capacitor ( Figure 20 (represented by C3 in the text), the first end of the second capacitor C2 is coupled to the first end of the seventh transistor T7, the second end of the second capacitor C2 is coupled to the gate of the seventh transistor T7, the first end of the third capacitor C3 is coupled to the first end of the eighth transistor T8, and the second end of the third capacitor C3 is coupled to the gate of the eighth transistor T8.

[0138] For example, the drive circuit may also include more capacitors, which can stabilize the node voltage to compensate for voltage drops caused by power supply voltage fluctuations or other factors.

[0139] like Figure 20 As shown, Figure 20 The diagram shows the specific circuitry of the frequency control circuit, which may include a thirteenth transistor (…). Figure 20 (represented by T13) and the fourteenth transistor ( Figure 20 (Represented by T14 in the diagram). The first terminal of the thirteenth transistor T13 is used to input the first frequency control signal PS1. The gate of the thirteenth transistor T13 and the fourth node of the previous stage GOA circuit ( Figure 20 The thirteenth transistor T13 is coupled to the first terminal of the fourteenth transistor T14 (represented by N4_m-1). The gate of the fourteenth transistor T14 is used to input cascaded signals. The second terminal of the fourteenth transistor T14 is coupled to the first node N1.

[0140] For example, the gate signal of the transistor in the frequency control circuit can also be coupled to the nodes of other GOA circuits. The gate of T13_m in the driving circuit can also be coupled to the fourth node (such as N4_m-2, N4_m-3…N4_m-k, k≥2) of the GOA circuit two or more levels above. The gate of the driving circuit T14_m can also be coupled to the SR signal (such as SR_m-1, SR_m-2…SR_m-k, k≥1) of the GOA circuit one level above. This is used to adjust the synchronization state between signals and reduce signal delay.

[0141] Figure 20The diagram also shows the specific circuitry of the register circuit, which may include a third node ( Figure 20 (represented by N3), the fourth node ( Figure 21 This consists of N4, multiple transistors (e.g., T15 to T26), and multiple capacitors (e.g., C5 and C6). The capacitors stabilize the node voltage to compensate for voltage drops caused by power supply voltage fluctuations or other factors.

[0142] like Figure 21 As shown, Figure 20 It shows Figure 21 The timing diagram of the internal nodes and external signals. Specifically, Figure 15 exist Figure 21 The timing diagrams for N4_m-1, N2_m, N4_m, and N2_m+1 are shown based on this. Figure 22 As can be seen, the driving circuit can achieve the function of reducing the local refresh rate through the frequency control circuit. In addition, the voltages of N1_m and N1_m+1 remain at a low level for a period of time between two refresh cycles. This avoids voltage differences at node N1, improves the stability of the GOA circuit, and enhances the display effect.

[0143] The following description, in conjunction with the accompanying drawings, provides a further description of a display device provided in an embodiment of this application.

[0144] In this circuit, the driving circuit typically uses the same gate high voltage source for power supply, meaning that multiple GOA circuits in the driving circuit are coupled to the gate high voltage signal line of this gate high voltage source. When the output gate scan signal of the previous row changes from VGH to VGL, there is a transient load reduction in the gate high voltage source and its signal line. The potential of the gate high voltage source is pulled down, which will generate noise ripple.

[0145] Specifically, such as Figure 23 As shown, the gate scan signals (S1_m and S1_m+1) exhibit multiple ripples with fixed time intervals (e.g., 2H) when in a high-level state. Since the activation level of the first transistor T1 in the pixel circuit depends on the high-level potential of S1, after the first transistor T1 is activated via S1, the second transistor T2 is activated via S2. The data voltage DATA is written to the gate of the driving transistor Td at the time point of S1. At this time, the high-voltage source of the driving circuit generating S1 should maintain a stable potential. Therefore, if the ripple signal is too dense, it will disturb the data voltage writing, resulting in uneven brightness in the display.

[0146] To address the aforementioned ripple problem, embodiments of this application provide a display device, such as... Figure 23As shown, the display device includes a pixel array, peripheral driving circuitry, and multiple cascaded driving circuits. Each driving circuit includes multiple GOA (Graphical Object Array) circuits, each comprising a register circuit and an output circuit. The driving circuitry may include n GOA circuits. Figure 23 The diagram illustrates register circuits 1 to 2, and output circuits 1 to 2. In addition, the drive circuit may include redundant GOA circuitry, which includes virtual register circuitry and virtual output circuitry. It is understood that the GOA circuitry may also include more components, such as the frequency control circuitry and reset circuitry mentioned above; however, this application does not limit the scope of the embodiments in this regard.

[0147] In addition, the peripheral driving circuit includes at least one gate high voltage source, which is coupled to multiple gate high voltage signal lines. Adjacent driving circuits in the multiple cascaded driving circuits are coupled to different gate high voltage signal lines.

[0148] For example, suppose the peripheral driving circuit can provide j gate high voltage signal lines, where j is an integer greater than or equal to 1, i.e., VGH1, VGH2, ..., VGHj. Taking the output circuit in the driving circuit as an example, the output circuit can be connected to the j gate high voltage signal lines through k first signal lines, where k is an integer greater than or equal to 1. The connection relationship can also be that adjacent first signal lines are connected to different gate high voltage signal lines.

[0149] In one possible implementation, see below. Figure 23 , Figure 24 The diagram shows a first gate high voltage source VGH1, which is coupled to a first gate high voltage signal line VGH1_1 and a second gate high voltage signal line VGH1_2. The first signal lines and gate high voltage signal lines of the output circuits are connected alternately in a row; for example, the first signal line of output circuit 1 is connected to VGH1_1, the first signal line of output circuit 2 is connected to VGH1_2, the first signal line of output circuit 3 is connected to VGH1_1, and the first signal line of output circuit 4 is connected to VGH1_2.

[0150] In another possible implementation, such as Figure 24 As shown, Figure 25The first gate high voltage source VGH1 and the second gate high voltage source VGH2 are shown in FIG. 1. The first gate high voltage source VGH1 is coupled with the first gate high voltage signal line VGH1_1 and the second gate high voltage signal line VGH1_2 respectively. The second gate high voltage source VGH2 is coupled with the third gate high voltage signal line VGH2_1 and the fourth gate high voltage signal line VGH2_2 respectively. The first signal line of the output circuit and the gate high voltage signal line are connected alternately. For example, the first signal line of the output circuit 1 is connected with VGH1_1, the first signal line of the output circuit 2 is connected with VGH2_1, the first signal line of the output circuit 3 is connected with VGH1_2, and the first signal line of the output circuit 4 is connected with VGH2_2. In this way, every four groups of GOA circuits can be connected with the gate high voltage signal line according to the connection mode of the output circuit 1 to the output circuit 4.

[0151] Optionally, as shown in FIG. 1, the peripheral driving circuit further comprises a level conversion circuit, and the at least one gate high voltage source comprises a first gate high voltage source VGH1 and a second gate high voltage source VGH2. The output circuit of the plurality of driving circuits cascaded in sequence is coupled with the first gate high voltage source, and the register circuit of the plurality of driving circuits cascaded in sequence is coupled with the second gate high voltage source and the level conversion circuit. Figure 26 Optionally, as shown in FIG. 1, the peripheral driving circuit further comprises a level conversion circuit, and the at least one gate high voltage source comprises a first gate high voltage source VGH1 and a second gate high voltage source VGH2. The output circuit of the plurality of driving circuits cascaded in sequence is coupled with the first gate high voltage source, and the register circuit of the plurality of driving circuits cascaded in sequence is coupled with the second gate high voltage source and the level conversion circuit.

[0152] Optionally, the driving current of the first gate high voltage source is greater than the driving current of the second gate high voltage source.

[0153] Optionally, the driving current of the first gate high voltage source is greater than the driving current of the second gate high voltage source.

[0154] Optionally, the driving current of the first gate high voltage source is greater than the driving current of the second gate high voltage source.

[0155] Optionally, at least one gate high voltage source includes a first gate high voltage source and a second gate high voltage source. The first transistor in the output circuit of an adjacent driving circuit is coupled to the gate high voltage signal line of the first gate high voltage source, and other transistors in the output circuit of an adjacent driving circuit are coupled to the gate high voltage signal line of the second gate high voltage source.

[0156] For example, the first transistor can be the seventh transistor of the output circuit of the driving circuit described above, and the other transistors can be the eleventh transistor of the output circuit of the driving circuit described above. Therefore, using a single first gate high-voltage source to provide a gate high voltage to the first terminal of the first transistor helps improve the stability of the gate scan signal output by the output circuit and reduces signal disturbances.

[0157] For example, the length of the signal line between the gate high voltage signal line of the first gate high voltage source and the output circuit can be within a preset range. In one possible example, the gate high voltage signal line of the first gate high voltage source can be positioned close to the output circuit to reduce the length of the signal line between the gate high voltage signal line and the output circuit, thereby improving signal transmission quality.

[0158] Optionally, the output of the first gate high voltage source is coupled to multiple parallel voltage-regulating capacitors.

[0159] For example, connecting multiple voltage-regulating capacitors in parallel at the output terminal of the first gate high voltage source can improve the stability of the gate high voltage output by the first gate high voltage source, which helps to improve the stability of the gate scan signal output by the output circuit and reduce signal disturbance.

[0160] Understandably, multiple voltage-regulating capacitors can be connected in parallel at the output of other gate high voltage sources in the peripheral driving circuit to improve the stability of the gate high voltage output by the gate high voltage source.

[0161] Optionally, the first signal line of each output circuit is coupled to the corresponding gate high voltage signal line, and the length of the first signal line is such that each first signal line overlaps with multiple gate high voltage signal lines.

[0162] For example, such as Figure 26 As shown, the gate high-voltage signal line can be distributed on the first conductive layer, and the first signal line can be distributed on the second conductive layer. The first and second conductive layers are disposed opposite to each other, and the first signal line and the corresponding gate high-voltage signal line are connected through a connection hole. Taking the first signal line of output circuit 2 as an example, this first signal line is connected to VGH1_1 through a connection hole, and the first signal line forms an overlapping capacitance with other signal lines (e.g., STV, VGH2_2, and VGH2_2). In addition, this first signal line also has an extension portion, for example... Figure 27The dashed portion in the first signal line, the extension portion and the VGH1_2 form an overlapping capacitor. It can be understood that there is no electrical connection between the extension portion of the first signal line and other signal lines, and in addition, the first signal line can extend beyond the VGH1_2, and the application does not limit the length of the line extending beyond the VGH1_2.

[0163] Therefore, the impedance of the first signal line between the output circuit and the gate high voltage signal line is the same, and the difference of the gate scanning signal output by the output circuit can be reduced.

[0164] Optionally, the gate high voltage signal line of the first gate high voltage source includes at least two metal layers connected by at least one connection hole.

[0165] Illustratively, the gate high voltage signal line of the first gate high voltage source can be formed by overlapping multiple metal layers, and the adjacent metal layers are inorganic layers. The multiple metal layers can be connected by the connection hole at the appropriate position to realize electrical conduction. Therefore, the impedance of the gate high voltage signal line of the first gate high voltage source can be reduced.

[0166] Illustratively, as shown in Figure 27 , Figure 28 Three metal layers and two inorganic layers are shown in

[0167] In one possible example, the metal layer can be a three-layer titanium-aluminum-titanium metal or a one-layer molybdenum metal, and the inorganic layer can be silicon nitride or silicon oxide.

[0168] The driving method provided by the embodiments of the application will be further described below with reference to the accompanying drawings.

[0169] Applied to the above driving circuit, the embodiments of the application provide a driving method, as shown in Figure 29 , the method includes the following processes.

[0170] S2801, the output circuit generates a gate scanning signal in response to the voltage of the pull-up node and the voltage of the pull-down node of the register circuit, and outputs the gate scanning signal to the corresponding pixel circuit of the GOA circuit.

[0171] S2802, the frequency control circuit receives a first frequency control signal to control the frequency of the gate scanning signal.

[0172] S2803, the reset circuit controls the voltage of the first node based on the reset signal.

[0173] For example, when the driving circuit does not start the local refresh frequency reduction function, as shown in Figure 29 Figure 30 The timing diagram of STV, CLK1, CLK2, each node (PU_1~PU_8, PD_1~PD_8, BPU_1~BPU_8) of the 8 GOA circuits, the first frequency control signal PS1, and the gate scanning signal (S1_1~S1_8) output by each GOA circuit is shown in FIG. 8. When the first frequency control signal PS1 is at low level (VGL), the 8 GOA circuits normally output the gate scanning signal, and the pulse width of each gate scanning signal is 6H.

[0174] For example, when the driving circuit starts the local refresh frequency reduction function, as shown in Figure 30 Figure 31 The timing diagram of STV, CLK1, CLK2, each node (PU_1~PU_8, PD_1~PD_8, BPU_1~BPU_8) of the 8 GOA circuits, the first frequency control signal PS1, and the gate scanning signal (S1_1~S1_8) output by each GOA circuit is shown in FIG. 8. When the first frequency control signal PS1 is at low level (VGL), the 8 GOA circuits normally output the gate scanning signal, and the pulse width of each gate scanning signal is 6H.

[0175] Optionally, S2802 can include that the frequency control circuit receives the first frequency control signal and the second frequency control signal to control the frequency of the gate scanning signal.

[0176] For example, when the driving circuit does not start the local refresh frequency reduction function, as shown in Figure 31 Figure 32 The timing diagram of STV, CLK1, CLK2, each node (PU_1~PU_8, PD_1~PD_8, BPU_1~BPU_8) of the 8 GOA circuits, the first frequency control signal PS1, and the gate scanning signal (S1_1~S1_8) output by each GOA circuit is shown in FIG. 8. When the first frequency control signal PS1 is at low level (VGL), the 8 GOA circuits normally output the gate scanning signal, and the pulse width of each gate scanning signal is 6H.

[0177] For example, when the driving circuit starts the local refresh frequency reduction function, as shown in Figure 32 ​ ​​​​The timing diagrams of the STV, CLK1, CLK2, the first frequency control signal PS1, the second frequency control signal PS2, and the gate scanning signals (S1_1-S1_8) output by each GOA circuit of the eight GOA circuits are shown in FIG. 8. The first frequency control signal PS1 is switched from a low voltage (VGL) to a high voltage (VGH) when S1_4 is enabled, at which time the BPU_5 to BPU_8 signals are masked, so that the first four GOA circuits output the gate scanning signals in a frame, and the last four GOA circuits do not output the gate scanning signals. Since S1_5 does not output the gate scanning signal, after the output of S1_4 is completed, CLK1 and CLK2 can be converted to a fixed voltage signal (such as a high voltage), and PS2 is converted from a low voltage to a high voltage to maintain the potential of the PU node. In this way, the power consumption can be further reduced.

[0178] The display device can include a processor and the driving circuit described above. The driving circuit and the processor are coupled.

[0179] The processor can be a display driver integrated circuit (DDIC) chip, a central processing unit (CPU), another general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or another programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, or the like. The general-purpose processor can be a microprocessor or any conventional processor.

[0180] The embodiments of the present application also provide a computer storage medium having computer instructions stored therein, and when the computer instructions are executed on an electronic device, the electronic device performs the above-mentioned related method steps to implement the driving method in the above-mentioned embodiments.

[0181] The embodiments of the present application also provide a computer program product, and when the computer program product is executed on a computer, the computer performs the above-mentioned related steps to implement the driving method executed by the electronic device in the above-mentioned embodiments.

[0182] In addition, the embodiment of the present application further provides a device, which can be a chip, a component or a module, and the device can include a processor and a memory connected to each other; the memory is used to store computer-executed instructions; when the device is running, the processor can execute the computer-executed instructions stored in the memory, so that the chip executes the driving method performed by the electronic device in the above method embodiments.

[0183] The driving circuit, the display device, the display equipment, the computer storage medium, the computer program product or the chip provided in the embodiment are used to execute the corresponding method provided above, and thus the beneficial effects achieved thereby can refer to the beneficial effects of the corresponding method provided above, which will not be repeated here.

[0184] Through the description of the above embodiments, those skilled in the art can understand that, for the convenience and brevity, only the division of the above functional modules is taken as an example, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

[0185] In the several embodiments provided in the present application, it should be understood that the disclosed device and method can be implemented in other ways. For example, the device embodiments described above are only schematic, and the division of the modules or units is only a logical function division, and there can be another division way in actual implementation, for example, a plurality of units or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the displayed or discussed mutual coupling or direct coupling or communication connection between each other can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0186] The units described as separate components can or can not be physically separate, and the components displayed as units can be one physical unit or multiple physical units, that is, can be located in one place, or can be distributed to multiple different places. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0187] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware, or in the form of software functional unit.

[0188] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application essentially or say the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The software product is stored in a storage medium, including a plurality of instructions to make a device (which can be a single-chip microcomputer, a chip, etc.) or a processor execute all or part of the steps of the method described in various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0189] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A driving circuit, characterized in that, It includes multiple array-driven scanning GOA circuits, wherein the GOA circuit includes: a register circuit, an output circuit, a frequency control circuit, and a reset circuit; The output circuit is coupled to the register circuit and is configured to generate a gate scan signal in response to the voltage of the pull-up node and the voltage of the pull-down node of the register circuit, and output the gate scan signal to the pixel circuit corresponding to the GOA circuit. The frequency control circuit and the output circuit are coupled to the first node and are configured to receive a first frequency control signal to control the frequency of the gate scan signal. The reset circuit and the output circuit are coupled to the first node and are configured to control the voltage of the first node based on a reset signal, which comes from the second node in the register circuit.

2. The driving circuit according to claim 1, characterized in that, The reset circuit includes a first transistor; The first terminal of the first transistor is coupled to the first node, the second terminal of the first transistor is coupled to the first voltage source, and the gate of the first transistor is used to receive the reset signal; The reset circuit is specifically configured to control the voltage of the first node by means of the voltage output from the first voltage source when the reset signal controls the first transistor to turn on.

3. The driving circuit according to claim 2, characterized in that, The reset circuit also includes a second transistor; The first terminal of the second transistor is coupled to the first terminal of the first transistor, the second terminal of the second transistor is coupled to the first node, and the gate of the second transistor is coupled to the gate of the first transistor.

4. The driving circuit according to any one of claims 1-3, characterized in that, The frequency control circuit includes a third transistor; The first terminal of the third transistor is coupled to the register circuit, the second terminal of the third transistor is coupled to the output circuit, and the gate of the third transistor is used to receive the second frequency control signal. The frequency control circuit is further configured to receive the first frequency control signal and the second frequency control signal to control the frequency of the gate scan signal.

5. The driving circuit according to claim 1, characterized in that, The output circuit includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a first capacitor; The gate of the fourth transistor and the register circuit are coupled to the pull-up node; the first terminal of the fourth transistor is coupled to the gate high voltage source; the second terminal of the fourth transistor is coupled to the first terminal of the fifth transistor; the second terminal of the fifth transistor is coupled to the gate low voltage source; and the gate of the fifth transistor and the register circuit are coupled to the pull-down node. The pull-up node is also coupled to the first terminal of the sixth transistor, the gate of the sixth transistor is coupled to the first node, the second terminal of the sixth transistor is coupled to the gate of the seventh transistor, the first terminal of the seventh transistor is coupled to the gate high voltage source, the second terminal of the seventh transistor is coupled to the first terminal of the eighth transistor, the second terminal of the eighth transistor is coupled to the gate low voltage source, and the gate of the eighth transistor is coupled to the pull-down node. The first terminal of the first capacitor is coupled to the gate of the sixth transistor, and the second terminal of the first capacitor is coupled to the second terminal of the sixth transistor.

6. The driving circuit according to claim 5, characterized in that, The output circuit also includes a ninth transistor; The first and second terminals of the ninth transistor are both coupled to the first terminal of the fifth transistor, and the gate of the ninth transistor is coupled to the pull-down node.

7. The driving circuit according to claim 5 or 6, characterized in that, The output circuit also includes a tenth transistor; The first terminal of the tenth transistor is coupled to the pull-down node, the second terminal of the tenth transistor is coupled to the gate of the eighth transistor, and the gate of the tenth transistor is coupled to the first node.

8. The driving circuit according to claim 5 or 6, characterized in that, The output circuit also includes an eleventh transistor; The first terminal of the eleventh transistor is coupled to the gate high voltage source, the second terminal of the eleventh transistor is coupled to the second terminal of the sixth transistor, and the gate of the eleventh transistor is coupled to the gate of the eighth transistor.

9. A display device, characterized in that, include: A pixel array, a peripheral driving circuit, and a plurality of driving circuits cascaded in sequence as described in any one of claims 1-8; The peripheral driving circuit includes at least one gate high voltage source, and the at least one gate high voltage source is coupled to a plurality of gate high voltage signal lines; In the plurality of cascaded driving circuits, adjacent driving circuits are coupled to different gate high-voltage signal lines.

10. The display device according to claim 9, characterized in that, The peripheral driving circuit also includes a level conversion circuit, and the at least one gate high voltage source includes a first gate high voltage source and a second gate high voltage source. The output circuit of the plurality of cascaded driving circuits is coupled to the first gate high voltage source. The register circuit of the plurality of cascaded drive circuits and the level conversion circuit are coupled to the second gate high voltage source.

11. The display device according to claim 10, characterized in that, The drive current of the first gate high voltage source is greater than the drive current of the second gate high voltage source.

12. The display device according to claim 9, characterized in that, The at least one gate high voltage source includes a first gate high voltage source and a second gate high voltage source; The first transistor in the output circuit of the adjacent driving circuit is coupled to the gate high voltage signal line of the first gate high voltage source. The other transistors in the output circuit of the adjacent driving circuit are coupled to the gate high voltage signal line of the second gate high voltage source.

13. The display device according to any one of claims 10-12, characterized in that, The output terminal of the first gate high voltage source is coupled to multiple parallel voltage-regulating capacitors.

14. The display device according to any one of claims 10-12, characterized in that, The first signal line of each output circuit is coupled to the corresponding gate high voltage signal line, and the length of the first signal line is such that each first signal line overlaps with the plurality of gate high voltage signal lines.

15. The display device according to any one of claims 10-12, characterized in that, The gate high voltage signal line of the first gate high voltage source includes at least two metal layers, and the at least two metal layers are connected through at least one connection hole.

16. A driving method, characterized in that, The method is applied to a driving circuit, which includes multiple GOA circuits. Each GOA circuit includes a register circuit, an output circuit, a frequency control circuit, and a reset circuit. The frequency control circuit, the output circuit, and the reset circuit are coupled to a first node. The method includes: The output circuit generates a gate scan signal in response to the voltage of the pull-up node and the voltage of the pull-down node of the register circuit, and outputs the gate scan signal to the pixel circuit corresponding to the GOA circuit. The frequency control circuit receives a first frequency control signal to control the frequency of the gate scan signal; The reset circuit controls the voltage of the first node based on a reset signal, which comes from the second node in the register circuit.

17. The driving method according to claim 16, characterized in that, The frequency control circuit receives a first frequency control signal to control the frequency of the gate scan signal, including: The frequency control circuit receives the first frequency control signal and the second frequency control signal to control the frequency of the gate scan signal.

18. A display device, characterized in that, It includes a processor and a driving circuit as described in any one of claims 1-8, wherein the driving circuit is coupled to the processor.

19. A computer-readable storage medium, characterized in that, When computer instructions are executed on a display device, the display device causes the display device to perform the method described in any one of claims 16-17.

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