Word line driving module, word line decoding circuit and memory chip

Abstract

The invention provides a word line driving module, a word line decoding circuit and a memory chip, and the word line driving module comprises a voltage transmission unit. The voltage transmission unit comprises a first voltage transmission part and a second voltage transmission part, the first voltage transmission part is turned on or turned off based on the first control signal and the second control signal and transmits and outputs the first voltage signal when turned on, and the second voltage transmission part is turned on or turned off based on the first control signal and transmits and outputs the second voltage signal when turned on. And the second voltage transmission part is used for transmitting and outputting a second voltage signal when being turned on, is realized by adopting a PMOS (P-channel Metal Oxide Semiconductor) tube and is turned on when the first control signal is negative voltage. According to the invention, the problems of high cost and large area of a memory chip caused by the fact that a voltage transmission unit is realized by adopting four thick gate oxide MOS (Metal Oxide Semiconductor) tubes in the prior art are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor memories, and particularly to a word line driving module, a word line decoding circuit, and a memory chip. Background Art

[0002] With the rapid development and wide application of modern electronic devices and embedded structures, the demand for high-integration circuit chips is increasing day by day, which has given rise to a series of requirements for restricting the area of integrated circuit chips. For memory chips, reducing the area of memory chips has always been the goal pursued by large-capacity or even ultra-large-capacity storage designs.

[0003] During the programming operation of non-volatile memories, the selected word lines require a positive high voltage, and during the erasing operation, the selected word lines require a negative high voltage; the word line driving module injects different voltages into the corresponding word lines under different operations through a voltage transmission unit. Among them, the voltage transmission unit is usually composed of two PMOS transistors and two NMOS transistors, but the operating voltage ranges of the MOS transistors fluctuate greatly, which requires the MOS transistors to be able to withstand high voltages. Therefore, thick-gate-oxide MOS transistors need to be selected. However, thick-gate-oxide MOS transistors have high costs and large areas, which is not conducive to the memory chip to achieve low costs and small areas.

[0004] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present invention and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present invention. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a word line driving module, a word line decoding circuit, and a memory chip, which are used to solve the problems in the prior art that the voltage transmission unit is implemented by four thick-gate-oxide MOS transistors, resulting in high costs and large areas of the memory chip.

[0006] To achieve the above purpose and other related purposes, the present invention provides a word line driving module, and the word line driving module includes:

[0007] A voltage transmission unit, including a first voltage transmission part and a second voltage transmission part; the first voltage transmission part is turned on or off based on a first control signal and a second control signal, and when turned on, transmits and outputs a first voltage signal; the second voltage transmission part is turned on or off based on the first control signal, and when turned on, transmits and outputs a second voltage signal;

[0008] Wherein, the second voltage transmission part is implemented by a PMOS transistor and is turned on when the first control signal is a negative voltage.

[0009] Optionally, the first voltage transmission unit includes an NMOS transistor and a first PMOS transistor. The gate of the NMOS transistor is connected to the first control signal, the gate of the first PMOS transistor is connected to the second control signal. The drain of the NMOS transistor is connected to the source of the first PMOS transistor and receives the first voltage signal. The source of the NMOS transistor is connected to the drain of the first PMOS transistor and serves as the output terminal of the first voltage transmission unit. Wherein, the output terminal of the first voltage transmission unit is connected to the output terminal of the second voltage transmission unit and serves as the output terminal of the voltage transmission unit.

[0010] Optionally, the second voltage transmission unit includes a second PMOS transistor. The gate of the second PMOS transistor is connected to the first control signal, the source of the second PMOS transistor receives the second voltage signal. The drain of the second PMOS transistor serves as the output terminal of the second voltage transmission unit. Wherein, the output terminal of the second voltage transmission unit is connected to the output terminal of the first voltage transmission unit and serves as the output terminal of the voltage transmission unit.

[0011] Optionally, the word line driving module further includes:

[0012] A level conversion unit, including a first level conversion unit, a second level conversion unit, and a third level conversion unit; the first level conversion unit outputs different first voltage signals based on a first input signal under different operations, the second level conversion unit outputs different second voltage signals based on a second input signal under different operations, and the third level conversion unit outputs different first control signals and second control signals based on a third input signal under different operations;

[0013] Wherein, the first control signal and the second control signal control the corresponding PMOS transistors to turn on based on a negative voltage.

[0014] Optionally, in the first level conversion unit:

[0015] During a programming operation, if the first input signal is a logic high level, the first voltage signal is a positive voltage; if the first input signal is a logic low level, the first voltage signal is a first power supply voltage;

[0016] During an erasing operation, if the first input signal is a logic high level, the first voltage signal is a first negative voltage; if the first input signal is a logic low level, the first voltage signal is a second power supply voltage;

[0017] Wherein, the first power supply voltage is less than the second power supply voltage.

[0018] Optionally, in the second level conversion unit:

[0019] Under programming operation, the second input signal is at a logic low level, and the second voltage signal is the first power supply voltage;

[0020] Under erasing operation, the second input signal is at a logic high level, and the second voltage signal is the second power supply voltage;

[0021] Wherein, the first power supply voltage is less than the second power supply voltage.

[0022] Optionally, in the third level conversion unit:

[0023] Under programming operation, if the third input signal is at a logic high level, the first control signal is a positive voltage and the second control signal is a second negative voltage; if the third input signal is at a logic low level, the first control signal is the second negative voltage and the second control signal is a positive voltage;

[0024] Under erasing operation, if the third input signal is at a logic high level, the first control signal is the second power supply voltage and the second control signal is a first negative voltage; if the third input signal is at a logic low level, the first control signal is the first negative voltage and the second control signal is the second power supply voltage;

[0025] Wherein, the first negative voltage is less than the second negative voltage.

[0026] The present invention further provides a word line decoding circuit, which includes: the word line driving module as described in any one of the above.

[0027] The present invention further provides a memory chip, which includes: the word line decoding circuit as described above.

[0028] Optionally, the memory chip is a NOR FLASH memory chip.

[0029] As described above, for the word line driving module, word line decoding circuit and memory chip of the present invention, by introducing a negative voltage (i.e., the second negative voltage) during programming operation, the number of MOS transistors in the voltage transmission unit is reduced from four to three, thereby reducing costs and decreasing the area; for large-capacity or even ultra-large-capacity storage designs, it is particularly obvious in reducing costs and decreasing the area. Description of the Drawings

[0030] Figure 1 Shows a schematic structural diagram of a traditional word line driving module.

[0031] Figure 2 Shows Figure 1 A schematic diagram of the corresponding relationships of the signals in the shown level conversion unit under programming and erasing operations.

[0032] Figure 3 It shows a schematic structural diagram of the word line driving module in the embodiment of the present invention.

[0033] Figure 4 Shown as Figure 3 A schematic diagram of the corresponding relationship of each signal in the shown level conversion unit under programming and erasing operations.

[0034] Description of component labels

[0035] 100, 200 Word line driving module

[0036] 110, 210 Level conversion unit

[0037] 111, 211 First level conversion part

[0038] 112, 212 Second level conversion part

[0039] 113, 213 Third level conversion part

[0040] 120, 220 Voltage transmission unit

[0041] 121, 221 First voltage transmission part

[0042] 122, 222 Second voltage transmission part Detailed implementation manners

[0043] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] Please refer to Figures 1 to 4 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The forms, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the layout form of the components may also be more complex.

[0045] Figure 1 A word line driving module 100 is shown, including a level conversion unit 110 and a voltage transmission unit 120; wherein, the level conversion unit 110 includes a first level conversion part 111, a second level conversion part 112, and a third level conversion part 113, and the voltage transmission unit 120 includes a first voltage transmission part 121 and a second voltage transmission part 122.

[0046] The first level conversion unit 111 receives the first input signal A and outputs a first voltage signal GWL. Wherein: as Figure 2 shown, under the programming operation, if the first input signal A is a logic high level, the first voltage signal GWL is the positive voltage Vpos; if the first input signal A is a logic low level, the first voltage signal GWL is the first power supply voltage Vpwr1; under the erase operation, if the first input signal A is a logic high level, the first voltage signal GWL is the negative voltage Vneg; if the first input signal A is a logic low level, the first voltage signal GWL is the second power supply voltage Vpwr2.

[0047] The second level conversion unit 112 receives the second input signal B and outputs a second voltage signal VB. Wherein: as Figure 2 shown, under the programming operation, the second input signal B is a logic low level, and the second voltage signal VB is the first power supply voltage Vpwr1; under the erase operation, the second input signal B is a logic high level, and the second voltage signal VB is the second power supply voltage Vpwr2.

[0048] The third level conversion unit 113 receives the third input signal C and outputs a first control signal VN and a second control signal VP. Wherein: as Figure 2 shown, under the programming operation, if the third input signal C is a logic high level, the first control signal VN is the positive voltage Vpos, and the second control signal VP is the zero voltage; if the third input signal C is a logic low level, the first control signal VN is the zero voltage, and the second control signal VP is the positive voltage Vpos; under the erase operation, if the third input signal C is a logic high level, the first control signal VN is the second power supply voltage Vpwr2, and the second control signal VP is the negative voltage Vneg; if the third input signal C is a logic low level, the first control signal VN is the negative voltage Vneg, and the second control signal VP is the second power supply voltage Vpwr2.

[0049] The first voltage transmission unit 121 is turned on or off based on the first control signal VN and the second control signal VP, and when turned on, transmits and outputs the first voltage signal GWL. Wherein: the first voltage transmission unit 121 includes a first NMOS transistor M1 and a first PMOS transistor M2; the gate of the first NMOS transistor M1 is connected to the first control signal VN, the gate of the first PMOS transistor M2 is connected to the second control signal VP, the drain of the first NMOS transistor M1 is connected to the source of the first PMOS transistor M2 and receives the first voltage signal GWL, and the source of the first NMOS transistor M1 is connected to the drain of the first PMOS transistor M2 and serves as the output terminal of the first voltage transmission unit 121.

[0050] The second voltage transmission unit 122 is turned on or off based on the first control signal VN and the second control signal VP, and when turned on, transmits and outputs the second voltage signal VB. Specifically: The second voltage transmission unit 122 includes a second NMOS transistor M3 and a second PMOS transistor M4; the gate of the second NMOS transistor M3 is connected to the second control signal VP, the gate of the second PMOS transistor M4 is connected to the first control signal VN, the drain of the second NMOS transistor M3 is connected to the source of the second PMOS transistor M4 and receives the second voltage signal VB, and the source of the second NMOS transistor M3 is connected to the drain of the second PMOS transistor M4 and serves as the output terminal of the second voltage transmission unit 122. Additionally, the output terminal of the first voltage transmission unit 121 is connected to the output terminal of the second voltage transmission unit 122 and serves as the output terminal of the voltage transmission unit 120 to output the word line driving signal LWL.

[0051] In the above word line driving module 100, whether it is a programming operation or an erasing operation, when the first input signal A and the third input signal C are both at a logic high level simultaneously, it represents being selected, and in other cases, it represents not being selected; additionally, during the programming operation, the second input signal B is always at a logic low level; during the erasing operation, the second input signal B is always at a logic high level. Next, please combine Figure 1 and Figure 2 to illustrate the working processes of the programming operation and the erasing operation of the above word line driving module 100.

[0052] During the programming operation:

[0053] For the case where both the first input signal A and the third input signal C are at a logic high level, the first control signal VN is a positive voltage Vpos, and the second control signal VP is a zero voltage. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned on, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned off. In this way, the positive voltage Vpos is output as the word line driving signal LWL;

[0054] For the case where the first input signal A is at a logic high level and the third input signal C is at a logic low level, the first control signal VN is a zero voltage, and the second control signal VP is a positive voltage Vpos. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned off, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned on. In this way, the first power supply voltage Vpwr1 is output as the word line driving signal LWL;

[0055] For the case where the first input signal A is at a logic low level and the third input signal C is at a logic high level, the first control signal VN is a positive voltage Vpos, and the second control signal VP is a zero voltage. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned on, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned off. In this way, the first power supply voltage Vpwr1 is output as the word line drive signal LWL;

[0056] For the case where both the first input signal A and the third input signal C are at a logic low level, the first control signal VN is a zero voltage, and the second control signal VP is a positive voltage Vpos. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned off, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned on. In this way, the first power supply voltage Vpwr1 is output as the word line drive signal LWL.

[0057] During the erasing operation:

[0058] For the case where both the first input signal A and the third input signal C are at a logic high level, the first control signal VN is the second power supply voltage Vpwr2, and the second control signal VP is a negative voltage Vneg. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned on, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned off. In this way, the negative voltage Vneg is output as the word line drive signal LWL;

[0059] For the case where the first input signal A is at a logic high level and the third input signal C is at a logic low level, the first control signal VN is a negative voltage Vneg, and the second control signal VP is the second power supply voltage Vpwr2. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned off, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned on. In this way, the second power supply voltage Vpwr2 is output as the word line drive signal LWL;

[0060] For the case where the first input signal A is at a logic low level and the third input signal C is at a logic high level, the first control signal VN is the second power supply voltage Vpwr2, and the second control signal VP is a negative voltage Vneg. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned on, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned off. In this way, the second power supply voltage Vpwr2 is output as the word line drive signal LWL;

[0061] For the case where both the first input signal A and the third input signal C are at logic low level, the first control signal VN is a negative voltage Vneg, and the second control signal VP is the second power supply voltage Vpwr2. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned off, and the second NMOS transistor M3 and the second PMOS transistor M4 in the second voltage transmission unit 122 are turned on. In this way, the second power supply voltage Vpwr2 is output as the word line driving signal LWL.

[0062] It can be seen that the word line driving module 100 realizes the following functions: during the programming operation, a positive voltage Vpos is applied to the selected word line, and the first power supply voltage Vpwr1 is applied to the unselected word lines; during the erasing operation, a negative voltage Vneg is applied to the selected word line, and the second power supply voltage Vpwr2 is applied to the unselected word lines. Among them, the positive voltage Vpos is the programming voltage, which can realize injecting electrons into the gate of the memory transistor corresponding to the selected word line; the negative voltage Vneg is the erasing voltage, which can realize erasing electrons from the gate of the memory transistor corresponding to the selected word line; in addition, the second power supply voltage Vpwr2 is the power supply voltage of the word line driving circuit 100, and the first power supply voltage Vpwr1 is a voltage less than the second power supply voltage Vpwr2.

[0063] In the above word line driving module 100, the voltage transmission unit 120 is composed of two PMOS transistors and two NMOS transistors, and is used to transmit different voltage values of the same or different signals; due to the large fluctuation range of the operating voltage of each MOS transistor, it is required that each MOS transistor must be able to withstand high voltages, so thick gate oxide MOS transistors need to be selected. However, thick gate oxide MOS transistors have high cost and large area, which is not conducive to the memory chip to achieve low cost and small area. In view of this, the applicant proposes the word line driving module 200 of the embodiment of the present application, which reduces the cost and area by reducing one MOS transistor.

[0064] As Figure 3 shown, this embodiment provides a word line driving module 200, including a voltage transmission unit 220; further, it also includes a level conversion unit 210.

[0065] The level conversion unit 210 is used to provide the first voltage signal GWL, the second voltage signal VB, the first control signal VN, and the second control signal VP to the voltage transmission unit 220. In one example, the level conversion unit 210 includes a first level conversion part 211, a second level conversion part 212, and a third level conversion part 213.

[0066] The first level conversion part 211 outputs different first voltage signals GWL based on the first input signal A under different operations. Among them: As Figure 4As shown, under the programming operation, if the first input signal A is at a logic high level (i.e., A = 1), the first voltage signal GWL is the positive voltage Vpos; if the first input signal A is at a logic low level (i.e., A = 0), the first voltage signal GWL is the first power supply voltage Vpwr1. Under the erase operation, if the first input signal A is at a logic high level, the first voltage signal GWL is the first negative voltage Vneg1; if the first input signal A is at a logic low level, the first voltage signal GWL is the second power supply voltage Vpwr2.

[0067] In one embodiment, the first level conversion unit 211 includes a first selector and a second selector (not shown in the figure). Among them, the first selector is triggered by a programming instruction and switches based on the first input signal A to output the positive voltage Vpos or the first power supply voltage Vpwr1. The second selector is triggered by an erase instruction and switches based on the first input signal A to output the first negative voltage Vneg1 or the second power supply voltage Vpwr2. Of course, this embodiment is only illustrative. It is also feasible for the first level conversion unit 211 to adopt other circuit structures that can achieve the above functions, and no limitation is imposed thereon.

[0068] The second level conversion unit 212 outputs different second voltage signals VB based on the second input signal B under different operations. Among them: as Figure 4 shown, under the programming operation, the second input signal B is at a logic low level (i.e., B = 0), and the second voltage signal VB is the first power supply voltage Vpwr1. Under the erase operation, the second input signal B is at a logic high level (i.e., B = 1), and the second voltage signal VB is the second power supply voltage Vpwr2.

[0069] In one embodiment, the second level conversion unit 212 includes a third selector and a fourth selector (not shown in the figure). Among them, the third selector is triggered by a programming instruction and switches based on the second input signal B to output the first power supply voltage Vpwr1. Since the second input signal B is always at a logic low level under the programming operation, the high selection terminal of the two-way selector in the third selector is floating and the low selection terminal is connected to the first power supply voltage Vpwr1. The fourth selector is triggered by an erase instruction and switches based on the second input signal B to output the second power supply voltage Vpwr2. Since the second input signal B is always at a logic high level under the erase operation, the high selection terminal of the two-way selector in the fourth selector is connected to the second power supply voltage Vpwr2 and the low selection terminal is floating. Of course, this embodiment is only illustrative. It is also feasible for the second level conversion unit 212 to adopt other circuit structures that can achieve the above functions, and no limitation is imposed thereon.

[0070] The third level conversion unit 213 outputs different first control signals VN and second control signals VP under different operations based on the third input signal C. Among them, at least the first control signal VN controls the turn-on of the second PMOS transistor M3 based on a negative voltage. Further, both the first control signal VN and the second control signal VP control the turn-on of the corresponding PMOS transistors (including the first PMOS transistor M2 and the second PMOS transistor M3) based on a negative voltage. Wherein: as Figure 4 shown, in the programming operation, if the third input signal C is a logic high level (i.e., C = 1), the first control signal VN is a positive voltage Vpos, and the second control signal VP is a second negative voltage Vneg2. If the third input signal C is a logic low level (i.e., C = 0), the first control signal VN is the second negative voltage Vneg2, and the second control signal VP is a positive voltage Vpos; in the erase operation, if the third input signal C is a logic high level, the first control signal VN is the second power supply voltage Vpwr2, and the second control signal VP is a first negative voltage Vneg1. If the third input signal C is a logic low level, the first control signal VN is the first negative voltage Vneg1, and the second control signal VP is the second power supply voltage Vpwr2.

[0071] In an implementation manner, the third level conversion unit 212 includes a fifth selector, a sixth selector, a seventh selector, and an eighth selector (not shown in the figure). Among them, the fifth selector is triggered by a programming instruction and performs a switchover based on the third input signal C to output a positive voltage Vpos or a second negative voltage Vneg2. The sixth selector is also triggered by a programming instruction and performs a switchover based on the third input signal C to output a second negative voltage Vneg2 or a positive voltage Vpos. The seventh selector is triggered by an erase instruction and performs a switchover based on the third input signal C to output a second power supply voltage Vpwr2 or a first negative voltage Vneg1. The eighth selector is also triggered by an erase instruction and performs a switchover based on the third input signal C to output a first negative voltage Vneg1 or a second power supply voltage Vpwr2. Of course, this implementation manner is only illustrative. It is also feasible for the third level conversion unit 213 to adopt other circuit structures that can achieve the above functions, and no limitation is imposed thereon.

[0072] Regarding each voltage, where: the forward voltage Vpos is the programming voltage, which can inject electrons into the gate of the corresponding memory cell, and is usually a positive high voltage; the first negative voltage Vneg1 is the erasing voltage, which can erase electrons from the gate of the corresponding memory cell, and is usually a negative high voltage; the second power supply voltage Vpwr2 is the power supply voltage of the word line driving circuit 200, and the first power supply voltage Vpwr1 is a voltage less than the second power supply voltage Vpwr2; the second negative voltage Vneg2 is the driving voltage that can control the PMOS transistor to be fully turned on. Usually, the second negative voltage Vneg2 is a negative voltage greater than the first negative voltage Vneg1. In addition, taking the above embodiments as an example, the word line driving module 200 may further include an instruction generating unit that generates a programming instruction or an erasing instruction based at least on the second input signal B.

[0073] The voltage transmission unit 220 includes a first voltage transmission part 221 and a second voltage transmission part 222. Among them, in the programming operation or the erasing operation, the first voltage transmission part 221 and the second voltage transmission part 222 are in a mutually exclusive state, that is, when the first voltage transmission part 221 is turned on, the second voltage transmission part 222 is turned off, and when the first voltage transmission part 221 is turned off, the second voltage transmission part 222 is turned on; in addition, the output end of the first voltage transmission part 221 is connected to the output end of the second voltage transmission part 222 and serves as the output end of the voltage transmission unit 220 to output the word line driving signal LWL.

[0074] The first voltage transmission part 221 is turned on or off based on the first control signal VN and the second control signal VP, and when it is turned on, it transmits and outputs the first voltage signal GWL.

[0075] In one embodiment, the first voltage transmission part 221 includes an NMOS transistor M1 and a first PMOS transistor M2; among them, the gate of the NMOS transistor M1 is connected to the first control signal VN, the gate of the first PMOS transistor M2 is connected to the second control signal VP, the drain of the NMOS transistor M1 is connected to the source of the first PMOS transistor M2 and receives the first voltage signal GWL, and the source of the NMOS transistor M1 is connected to the drain of the first PMOS transistor M2 and serves as the output end of the first voltage transmission part 221.

[0076] The second voltage transmission part 222 is turned on or off based on the first control signal VN, and when it is turned on, it transmits and outputs the second voltage signal VB.

[0077] Specifically, the second voltage transmission unit 222 is implemented by a PMOS transistor and is turned on when the first control signal VN is a negative voltage (the second negative voltage Vneg2 during the programming operation and the first negative voltage Vneg1 during the erasing operation). In one embodiment, the second voltage transmission unit 222 includes a second PMOS transistor M3. The gate of the second PMOS transistor M3 is connected to the first control signal VN, the source of the second PMOS transistor M3 receives the second voltage signal VB, and the drain of the second PMOS transistor M3 serves as the output terminal of the second voltage transmission unit 222. By introducing the second negative voltage Vneg2 during the programming operation to turn on the second PMOS transistor M3, the second voltage signal VB can be completely transmitted to the output, thus realizing the reduction of one NMOS transistor.

[0078] In the word line driving module 200 of this embodiment, whether it is a programming operation or an erasing operation, when the first input signal A and the third input signal C are both at a logic high level, it represents being selected, and in other cases, it represents not being selected. Additionally, during the programming operation, the second input signal B is at a logic low level; during the erasing operation, the second input signal B is at a logic high level. Next, please refer to Figure 3 and Figure 4 to illustrate the working processes of the programming operation and the erasing operation of the word line driving module 200 of this embodiment.

[0079] During the programming operation:

[0080] For the case where both the first input signal A and the third input signal C are at a logic high level, the first control signal VN is the positive voltage Vpos, and the second control signal VP is the second negative voltage Vneg2. At this time, the NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 221 are turned on, and the second PMOS transistor M3 in the second voltage transmission unit 222 is turned off. Thus, the positive voltage Vpos is output as the word line driving signal LWL.

[0081] For the case where the first input signal A is at a logic high level and the third input signal C is at a logic low level, the first control signal VN is the second negative voltage Vneg2, and the second control signal VP is the positive voltage Vpos. At this time, the NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 221 are turned off, and the second PMOS transistor M3 in the second voltage transmission unit 222 is turned on. Thus, the first power supply voltage Vpwr1 is output as the word line driving signal LWL.

[0082] For the case where the first input signal A is at a logic low level and the third input signal C is at a logic high level, the first control signal VN is a positive voltage Vpos, and the second control signal VP is a second negative voltage Vneg2. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 121 are turned on, and the second PMOS transistor M3 in the second voltage transmission unit 222 is turned off. Thus, the first power supply voltage Vpwr1 is output as the word line drive signal LWL;

[0083] For the case where both the first input signal A and the third input signal C are at a logic low level, the first control signal VN is a second negative voltage Vneg2, and the second control signal VP is a positive voltage Vpos. At this time, the NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 221 are turned off, and the second PMOS transistor M3 in the second voltage transmission unit 222 is turned on. Thus, the first power supply voltage Vpwr1 is output as the word line drive signal LWL.

[0084] During the erase operation:

[0085] For the case where both the first input signal A and the third input signal C are at a logic high level, the first control signal VN is a second power supply voltage Vpwr2, and the second control signal VP is a first negative voltage Vneg1. At this time, the first NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 221 are turned on, and the second PMOS transistor M3 in the second voltage transmission unit 222 is turned off. Thus, the first negative voltage Vneg1 is output as the word line drive signal LWL;

[0086] For the case where the first input signal A is at a logic high level and the third input signal C is at a logic low level, the first control signal VN is a first negative voltage Vneg1, and the second control signal VP is a second power supply voltage Vpwr2. At this time, the NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 221 are turned off, and the second PMOS transistor M3 in the second voltage transmission unit 222 is turned on. Thus, the second power supply voltage Vpwr2 is output as the word line drive signal LWL;

[0087] For the case where the first input signal A is at a logic low level and the third input signal C is at a logic high level, the first control signal VN is a second power supply voltage Vpwr2, and the second control signal VP is a first negative voltage Vneg1. At this time, the NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 221 are turned on, and the second PMOS transistor M3 in the second voltage transmission unit 222 is turned off. Thus, the second power supply voltage Vpwr2 is output as the word line drive signal LWL;

[0088] For the case where both the first input signal A and the third input signal C are at logic low level, the first control signal VN is the first negative voltage Vneg1, and the second control signal VP is the second power supply voltage Vpwr2. At this time, the NMOS transistor M1 and the first PMOS transistor M2 in the first voltage transmission unit 221 are turned off, and the second PMOS transistor M3 in the second voltage transmission unit 222 is turned on. Thus, the second power supply voltage Vpwr2 is output as the word line driving signal LWL.

[0089] It can be seen that the output result of the word line driving module 200 in this embodiment is the same as that of the traditional word line driving module 100. However, only three MOS transistors are required for the voltage transmission unit 220 in the word line driving module 200 of this embodiment, which is one less than the voltage transmission unit 120 in the traditional word line driving module 100. Therefore, the word line driving module 200 in this embodiment has a lower cost and a smaller area, which is more conducive to realizing the low cost and small area of the memory chip.

[0090] Correspondingly, this embodiment also provides a word line decoding circuit, including the word line driving module 200; wherein, the word line driving module 200 is implemented by using the module structure described above. For relevant content, please refer to the above, and details are not described here again. Of course, the word line decoding circuit may also include other module structures, such as a decoding module, etc., and no limitation is made thereto.

[0091] Correspondingly, this embodiment also provides a memory chip, including the word line decoding circuit; wherein, the word line decoding circuit is implemented by using the circuit structure described above. For relevant content, please refer to the above, and details are not described here again. Of course, the memory chip may also include other circuit structures, such as a memory array, a readout circuit, etc., and no limitation is made thereto. In practical applications, the memory chip of this embodiment is usually a NOR FLASH (non-volatile flash) memory chip.

[0092] In summary, a word line driving module, a word line decoding circuit and a memory chip of the present invention introduce a negative voltage (i.e., the second negative voltage) during the programming operation, reduce the number of MOS transistors in the voltage transmission unit from four to three, thereby reducing the cost and the area; for large-capacity or even ultra-large-capacity storage designs, the reduction in cost and area is particularly obvious. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0093] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A word line driving module, characterized in that, The word line driving module includes: A voltage transmission unit, including a first voltage transmission part and a second voltage transmission part; the first voltage transmission part is turned on or off based on a first control signal and a second control signal, and when turned on, transmits and outputs a first voltage signal; the second voltage transmission part is turned on or off based on the first control signal, and when turned on, transmits and outputs a second voltage signal; Wherein, the second voltage transmission part is implemented by a PMOS transistor and is turned on when the first control signal is a negative voltage.

2. The word line driving module according to claim 1, wherein The first voltage transmission part includes an NMOS transistor and a first PMOS transistor. The gate of the NMOS transistor is connected to the first control signal, the gate of the first PMOS transistor is connected to the second control signal, the drain of the NMOS transistor is connected to the source of the first PMOS transistor and receives the first voltage signal, and the source of the NMOS transistor is connected to the drain of the first PMOS transistor and serves as the output end of the first voltage transmission part. Wherein, the output end of the first voltage transmission part is connected to the output end of the second voltage transmission part and serves as the output end of the voltage transmission unit.

3. The word line driving module according to claim 1, characterized in that, The second voltage transmission part includes a second PMOS transistor. The gate of the second PMOS transistor is connected to the first control signal, the source of the second PMOS transistor receives the second voltage signal, and the drain of the second PMOS transistor serves as the output end of the second voltage transmission part. Wherein, the output end of the second voltage transmission part is connected to the output end of the first voltage transmission part and serves as the output end of the voltage transmission unit.

4. The word line driving module according to any one of claims 1 to 3, characterized in that The word line driving module further includes: A level conversion unit, including a first level conversion part, a second level conversion part, and a third level conversion part; the first level conversion part outputs different first voltage signals under different operations based on a first input signal, the second level conversion part outputs different second voltage signals under different operations based on a second input signal, and the third level conversion part outputs different first control signals and second control signals under different operations based on a third input signal; Wherein, the first control signal and the second control signal control the corresponding PMOS transistors to be turned on based on a negative voltage.

5. The word line driving module according to claim 4, characterized in that, In the first level conversion part: Under a programming operation, if the first input signal is a logic high level, the first voltage signal is a positive voltage; if the first input signal is a logic low level, the first voltage signal is a first power supply voltage; Under an erasing operation, if the first input signal is a logic high level, the first voltage signal is a first negative voltage; if the first input signal is a logic low level, the first voltage signal is a second power supply voltage; Wherein, the first power supply voltage is less than the second power supply voltage.

6. The word line driving module according to claim 4, wherein In the second level conversion part: Under a programming operation, the second input signal is a logic low level, and the second voltage signal is a first power supply voltage; Under an erasing operation, the second input signal is a logic high level, and the second voltage signal is a second power supply voltage; Wherein, the first power supply voltage is less than the second power supply voltage.

7. The word line driving module according to claim 4, characterized in that In the third level conversion part: Under programming operation, if the third input signal is a logic high level, the first control signal is a positive voltage and the second control signal is a second negative voltage; if the third input signal is a logic low level, the first control signal is a second negative voltage and the second control signal is a positive voltage; Under erasure operation, if the third input signal is a logic high level, the first control signal is a second power supply voltage and the second control signal is a first negative voltage; if the third input signal is a logic low level, the first control signal is a first negative voltage and the second control signal is a second power supply voltage; Wherein, the first negative voltage is less than the second negative voltage.

8. A word line decoding circuit, characterized in that The word line decoding circuit includes: the word line driving module according to any one of claims 1 to 7.

9. A memory chip, characterized in that, The memory chip includes: the word line decoding circuit according to claim 8.

10. The memory chip according to claim 9, characterized in that, The memory chip is a NOR FLASH memory chip.

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