Method for erasing memory cell of flash memory device and flash memory device using same

Abstract

The invention discloses a method for erasing a memory cell of a flash memory device and the flash memory device using the method. The method comprises the following steps: executing a first erasing operation for erasing a block of the memory cell of the flash memory device; increasing the erase bias voltage in a step-by-step manner until the lower edge of the threshold voltage distribution of the block of the memory cell is lower than the erase low-side verify voltage; performing a first post-program operation until a lower edge of a threshold voltage distribution of a block of memory cells is higher than a post-verify voltage; and performing a second erase operation to determine whether the upper edge of the threshold voltage distribution of the block of the memory cell is lower than the erase high-side verify voltage.

Description

Technical Field

[0001] The present disclosure relates to a method for erasing storage units of a flash memory device and a flash memory device using the method. Background Art

[0002] Typical flash memory devices must be erased before being programmed. Although programming operations can be performed sequentially byte by byte, erasing operations must be performed on entire blocks of storage units. A flash memory device has two states, which are "programmed" or "erased". To determine the state of a cell, a read operation must be performed on the cell. To perform a read operation, a reference voltage (V TREF ) is applied to the gate of a metal oxide field effect transistor (MOSFET) to determine whether the MOSFET is conducting. If the MOSFET is conducting, the logic state of the MOSFET is "1". If the MOSFET is not conducting, the logic state of the MOSFET is "0". If the value stored in the MOSFET is 1, the MOSFET is considered to be in the erased state. If the value stored in the MOSFET is 0, the MOSFET is considered to be in the programmed state. For a MOSFET in the erased state, the gate-to-source threshold voltage (V GSTH ) of the MOSFET is less than V TREF . For a MOSFET in the programmed state, the gate-to-source threshold voltage (V GSTH ) of the MOSFET is greater than V TREF .

[0003] The programming operation of a MOSFET is performed by applying a high positive voltage (e.g., 9 volts) to the gate of the MOSFET and a lower positive voltage (e.g., 4 volts) to the drain of the MOSFET so that electrons fill the floating gate of the MOSFET device. The erasing operation of a MOSFET is performed by applying a high positive voltage (e.g., 8 volts) to the common p-well of the MOSFET and a strong negative voltage (e.g., -10 volts) to the gate of the MOSFET so that electrons are repelled from the floating gate of the MOSFET device.

[0004] After plotting a histogram of the threshold voltages of all cells in a memory block or page (where the x-axis is the threshold voltage and the y-axis is the number of cells), it is well known that cells in the erased state are distributed in a Gaussian manner to the left of V TREF , assuming that V TREF is in the middle of the graph, and cells in the programmed state are distributed in a Gaussian manner to the right of VTREF On the right side. However, when the gate-to-source threshold voltage of the cells in the left edge of the distribution approaches zero, leakage current may occur. These cells are typically referred to as "over erased cells". Therefore, a post-programming (i.e., soft programming) operation is performed after the erase operation to recover the over erased cells. Generally, although the erase operation is performed on the entire block or entire page of the memory cells, the post-programming operation can be performed on a cell-by-cell basis.

[0005] If the erase operation is suspended due to reasons such as power loss before the post-programming operation is completed, there may be problems in attempting to recover the over erased cells. In such a case, the over erased cells may not be recoverable and may cause leakage current on the bit line where the over erased cells are located. The leakage current may cause the cells storing binary "0" to output a binary "1" reading due to the leakage current. In Figure 1 shows the problems caused by the suspension of the erase operation.

[0006] As Figure 1 shown, the distribution of all the memory cells in the memory block is generally divided into the distribution of the programmed cells 101 holding the binary value "0" and the distribution of the erased cells 102 holding the binary value "1". After the erase operation is performed, it is assumed that a post-programming operation for recovering the individual over erased cells is performed on the erased cells 102. After the post-programming operation, the distribution of the erased cells 102 will ideally have a smaller threshold voltage between the erase verification target 103 and the post-programming verification target 104. The distance between the erase verification target 103 and V TREF is generally referred to as the erase margin. The purpose of the post-programming verification target 104 is to serve as the target threshold voltage for recovering the over erased cells. In other words, the gate-to-source threshold voltage of the erased cells should be greater than the post-programming verification target 104 so that the cells avoid causing leakage current. However, in Figure 1 the illustrated example, it is assumed that a power loss event has occurred before the post-programming operation is completed. Therefore, a part of the distribution of the erased cells 102 as indicated by the arrow may cause leakage current due to the power loss event. Therefore, a more robust method for erasing the flash memory device may be advantageous. SUMMARY OF THE INVENTION

[0007] The present disclosure relates to a method for erasing memory cells of a flash memory device and a flash memory device using the method.

[0008] The present disclosure relates to a method for erasing storage units of a flash memory device. The method includes: performing a first erasing operation for erasing a block of the storage units by applying an erasing bias voltage to the block of the storage units of the flash memory device; increasing the erasing bias voltage in a stepwise manner until a lower edge of a threshold voltage distribution of the block of the storage units is lower than an erase low-side verification voltage; performing a first post-programming operation for recovering over-erased storage units of the block of the storage units until the lower edge of the threshold voltage distribution of the block of the storage units is higher than a post-verification voltage; performing a second erasing operation for erasing the block of the storage units to determine whether an upper edge of the threshold voltage distribution of the block of the storage units is lower than an erase high-side verification voltage; and determining that the block of the storage units has been completely erased after the threshold voltage distribution of the block of the storage units is completely within the post-verification voltage and the erase high-side verification voltage.

[0009] The present disclosure relates to a flash memory device, the flash memory device including a block of storage units and a memory controller. The memory controller is electrically connected to the block of storage units and is configured to: perform a first erasing operation for erasing the block of the storage units by applying an erasing bias voltage to the block of the storage units of the flash memory device; increase the erasing bias voltage in a stepwise manner until a lower edge of a threshold voltage distribution of the block of the storage units is lower than an erase low-side verification voltage; perform a first post-programming operation for recovering over-erased storage units until the lower edge of the threshold voltage distribution of the block of the storage units is higher than a post-verification voltage; perform a second erasing operation for erasing the block of the storage units until an upper edge of the threshold voltage distribution of the block of the storage units is lower than an erase high-side verification voltage; and determine that the block of the storage units has been completely erased after the threshold voltage distribution of the block of the storage units is completely within the post-verification voltage and the erase high-side verification voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a threshold voltage distribution of erased units and programmed units of a memory block after an erasing operation is paused;

[0011] Figure 2 is a flowchart of a method for erasing storage units of a flash memory device according to an embodiment of the present disclosure;

[0012] Figure 3 is an erasing bias voltage increasing in a stepwise manner according to an embodiment of the present disclosure;

[0013] Figure 4 is an illustration of performing an erase low-side verification operation according to an embodiment of the present disclosure;

[0014] Figure 5 is an iterative erase operation according to an embodiment of the present disclosure;

[0015] Figure 6 is an iterative erase operation according to another embodiment of the present disclosure;

[0016] Figure 7 is according to an embodiment of the present disclosure, illustrating the hardware settings for performing a low-side erase verification operation;

[0017] Figure 8 is according to an embodiment of the present disclosure, illustrating the hardware settings for performing a post-programming operation;

[0018] Figure 9 is according to an embodiment of the present disclosure, illustrating the hardware block diagram for performing a post-programming operation;

[0019] Figure 10 is a flowchart outlining a method for erasing storage cells of a flash memory device according to an embodiment of the present disclosure;

[0020] Figure 11 is according to an embodiment of the present disclosure, illustrating an example of performing a post-programming operation.

[0021] [Symbol Explanation]

[0022] 101: Programmed cell

[0023] 102: Erased cell

[0024] 103: Erase verification target

[0025] 104: Post-programming verification target

[0026] 301, 412, 512, 612: Erase low-side verification voltage

[0027] 302: Constant voltage

[0028] 401, 501, 601: First curve

[0029] 402, 502, 602: Second curve

[0030] 411: High-side verification voltage / Erase high-side verification voltage

[0031] 413, 511, 611: Post-verification voltage

[0032] 414, 415: Lower edge

[0033] 503, 603: Third curve

[0034] 701: Bit line

[0035] 800: Hardware circuit / Flash memory device

[0036] 801: Current detector

[0037] 802: Post-programming word line regulator

[0038] 803: Memory cell / Block of memory cells

[0039] 805, 904: Bit line current detector

[0040] 900: Hardware circuit

[0041] 901: Memory array

[0042] 902: Y decoder

[0043] 903: X decoder

[0044] 905: Post-programming word line regulator

[0045] 1101: Increase

[0046] 1102, 1103: Predetermined current threshold

[0047] S202, S203, S204, S205, S206, S207, S1001, S1002, S1003, S1004, S1005: Steps Detailed implementation mode

[0048] The present disclosure provides a method for erasing memory cells of a flash memory device and a flash memory device using the method. An overview of the method is shown in Figure 10 . In step S1001 (i.e., S202), the flash memory device (e.g., 800) will perform a first erase operation for erasing a block of memory cells by applying an erase bias voltage to a block of memory cells (e.g., 803) of the flash memory device. In step S1002, the flash memory device will increase the erase bias voltage in a stepwise manner (which will be in Figure 3as shown until the threshold voltage of the lower edge 414 of the threshold voltage distribution of the block of memory cells is lower than the erase low-side verification voltage 412 (i.e., S203). In step S1003 (i.e., S204), the flash memory device will perform a first post-programming operation for recovering over-erased memory cells of the block of memory cells until the lower edge of the threshold voltage distribution of the block of memory cells is higher than the post-verification voltage 511. In step S1004, the flash memory device will perform a second erase operation (i.e., S206) for erasing the block of memory cells to determine whether the upper edge of the threshold voltage distribution of the block of memory cells is lower than the erase high-side verification voltage 411 (i.e., S205). In step S1005, after the threshold voltage distribution of the block of memory cells is completely within the post-verification voltages 413, 511, 611 and the erase high-side verification voltage 411, the flash memory device will infer that the block of memory cells has been completely erased. To further clarify the above concepts, the present disclosure provides the following several exemplary embodiments.

[0049] Figure 2 More specifically shows a method of erasing memory cells of a flash memory device. In step S201, it is assumed that the flash memory device has received a command to erase a block of memory cells (e.g., 803). In step S202, the memory controller (e.g., word line post-programming regulator 802, 905) may perform a first erase operation by applying an erase bias voltage to the block of memory cells. In step S203, the memory controller may derive the threshold voltage of the block of memory cells so that the memory controller can determine whether the threshold voltage of the lower edge 414 of the threshold voltage distribution of the block of memory cells is lower than (or exceeds) the erase low-side verification voltage 412 during the first erase operation. If the threshold voltage of the lower edge 414 is not lower than (or exceeds) the erase low-side verification voltage 412, then proceed to step S202; if the threshold voltage of the lower edge 414 is lower than (or exceeds) the erase low-side verification voltage 412, then proceed to step S204.

[0050] In step S204, the memory controller may start a post-programming operation for recovering over-erased memory cells. The post-programming operation is automatically performed by the memory controller in a column-by-column manner (e.g., in a bit-line-by-bit-line manner). It should be noted that although the memory cells must be erased as a block, the post-programming operation can recover over-erased memory cells on a per-cell basis and in a one-bit-line-at-a-time manner. When the post-programming operation is completed, the threshold voltage of the lower edge 414 of the threshold voltage distribution of the block of memory cells should be higher than the post-verification voltages 413, 511, 611. In step S205, the memory controller may determine whether the threshold voltage of the upper edge of the threshold voltage distribution of the block of memory cells is lower than the erase high-side verification voltage 411. If the threshold voltage of the upper edge is lower than the erase high-side verification voltage 411, then in step S206, the memory controller may perform a second erase operation on the block of memory cells and proceed with the process from step S204. Otherwise, the erase operation is considered complete. In this case, the threshold voltage of the lower edge of the threshold voltage distribution of the block of memory cells should be higher than the post-verification voltage, and the threshold voltage of the upper edge of the threshold voltage distribution of the block of memory cells should be lower than the erase high-side verification voltage.

[0051] The erase low-side verification voltage 412, the post-verification voltage 413, and the erase high-side verification voltage 411 are predetermined voltages. The purpose of the erase low-side verification voltage 412 is to provide a target to be achieved before performing the post-programming operation in step S204 for the erase operation during step S202. The purpose of the post-verification voltage 413 is to provide a margin to avoid the possibility of leakage current output from memory cells whose threshold voltages are lower than the post-verification voltage 413. The purpose of the high-side verification voltage 411 is to provide an erase margin (i.e., the safety distance between V TREF and V GSTH ). The post-verification voltage 413 is higher than the erase low-side verification voltage 412.

[0052] Steps S202 and S203 may make the erase operation an iterative process, and each iteration of step S202 will cause the erase bias voltage to increase in a stepwise manner. In other words, in step S203, if the threshold voltage of the lower edge 414 of the threshold voltage distribution of the block of memory cells is not lower than the erase low-side verification voltage, step S202 is repeated by increasing the erase bias voltage in one step. The increase of the erase bias voltage in a stepwise manner is shown in Figure 3 . If the threshold voltage of the lower edge 414 of the threshold voltage distribution of the block of memory cells is lower than the erase low-side verification voltage 301, the erase bias voltage is maintained at a constant voltage 302. The voltage difference between the post-verification voltage and the erase low-side verification voltage may be less than the step increase amount of the erase bias voltage during the stepwise increase of the erase bias voltage.

[0053] InFigure 4 is further elaborated in Figure 2 the method shown in Figure 4 In [reference], the first curve graph 401 shows the result of an erase operation (e.g., S202) just before the threshold voltage at the lower edge 414 of the threshold voltage distribution of the block of memory cells reaches the target of the erase low-side verification voltage 412, and the second curve graph 402 shows the result of the next iteration of the erase operation (e.g., S202) after undergoing step S203. After the next iteration of the erase operation shown in the second curve graph 402, the threshold voltage at the lower edge 415 of the threshold voltage distribution of the block of erased memory cells has exceeded the target of the erase low-side verification voltage 412. Subsequently, the threshold voltage at the lower edge 415 of the threshold voltage distribution of the block of memory cells must be adjusted to be higher than the post-verification voltage 413 in order to have a safety margin for avoiding or minimizing leakage current.

[0054] In Figure 5 is shown in more detail in Figure 4 the method shown in Figure 5 Seven iterations of the erase operation of step S202 are shown in the first curve graph 501 shown in [reference]. In the 6th iteration of the erase operation of step S202, the threshold voltage at the lower edge of the threshold voltage distribution of the block of memory cells approaches the post-verification voltage 511 but has not reached the erase low-side verification voltage 512. In the last iteration of the erase operation of step S202, the erase low-side verification voltage 512 has been reached. In this case, the threshold voltage at the lower edge of the threshold voltage distribution of the block of memory cells is lower than the erase low-side verification voltage 512. In Figure 5 An example of the post-programming operation of step S204 is shown in the second curve graph 502 shown in [reference]. After step S204, the lower edge of the threshold voltage distribution of the block of memory cells is lower than the post-verification voltage 511, but the threshold voltage at the upper edge of the threshold voltage distribution of the block of memory cells is not lower than the erase high-side verification voltage 513, which is a necessary condition for proceeding from step S205 to step S207. Therefore, another erase operation must be performed in step S206, and the method will proceed from step S204. In Figure 5 The third curve graph 503 shown in [reference] shows the threshold voltage distribution when the threshold voltage distribution of the block of memory cells in step S207 is between the post-verification voltage 511 and the erase high-side verification voltage 513.

[0055] In Figure 6 is shown an example similar to Figure 5 in Figure 6In the first graph 601, the last iteration of the erase operation causes the threshold voltage of the lower edge of the threshold voltage distribution of the block of memory cells to exceed the erase low-side verification voltage 612. In this case, in the second graph 602, the post-programming operation will cause the lower edge of the threshold voltage distribution of the block of memory cells to be within the post-verification voltage 611. Similar to Figure 5 Since the threshold voltage of the upper edge of the threshold voltage distribution of the block of memory cells is not lower than the erase high-side verification voltage 613, another iteration of steps S206, S204, and S205 must be performed in order to achieve Figure 6 the threshold voltage distribution shown in the third graph 603.

[0056] In order to determine in step S203 whether the threshold voltage of the lower edge of the threshold voltage distribution of the block of memory cells is lower than the erase low-side verification voltage, the hardware setting for performing step S203 is shown in Figure 7 . In the Figure 7 shown hardware setting, a first voltage is fed to the word line, and the first voltage can be, for example, 1 volt. The bit lines are turned on one by one, and a second voltage can be applied to the turned-on bit line. The second voltage can be, for example, 0.8 volts. The second voltage can be the erase low-side verification voltage or close to the erase low-side verification voltage. For the turned-on bit line 701, the bit line is set using the second voltage to determine whether the bit line is turned on. If the bit line 701 is turned on when the bias voltage is 0.8 volts, the threshold voltage of the lower edge of the threshold voltage distribution of the block of memory cells has reached the erase low-side verification voltage. If the bit line 701 is not turned on, the bias voltage of the bit line can be set lower.

[0057] In Figure 8 the hardware circuit 800 for performing the Figure 2 shown method is shown. In Figure 8 it is assumed that the memory cell is the block 803 of memory cells to be erased. In this exemplary embodiment, the erase operation is performed by the word line post-programming regulator 802, which is part of the memory controller, and the memory controller is usually provided in the flash memory device. When performing the post-programming operation of step S204, the over-erased memory cells are restored one bit line at a time. In the bit line (for example, 804) being subjected to the post-programming operation, a constant bias voltage is applied to the bit line 804. The constant bias voltage can be, for example, 4 volts. At the same time, while the bit line current detector 805 monitors the leakage current on the bit line 804, a gradually increasing word line voltage is applied to the word line, and the current detector 801 detects the current reflected from the bit line 804.

[0058] Figure 9 Shown in more detail is Figure 8 the hardware circuit 800 shown. Similar toFigure 8 In contrast, Figure 9 the hardware circuit 900 shown further includes an X decoder 903 for controlling each respective word line and a Y decoder 902 for controlling each respective bit line, and the memory array 901 is the same as the block 803 of memory cells. Each of the bit lines can be connected to a respective bit line current detector 904 (e.g., 805). Figure 2 The selection of the word lines and bit lines shown and related operations can be performed by the word line post-programming regulator 905.

[0059] In Figure 11 an example of voltage control of the post-programming operation is shown. In Figure 11 the example shown, during the post-programming operation for recovering an over-erased memory cell in step S204, when the leakage current measured by the current detector (e.g., 801) exceeds a predetermined current threshold, the word line voltage increases from a first negative voltage 1101 to a second negative voltage. The first negative voltage can be, for example, -3 volts. The second negative voltage is higher than the first negative voltage. The predetermined current threshold can be, for example, 80 microamperes (microamp, uA). When it is detected that the leakage current is less than the predetermined current threshold 1102 as a result of the post-programming operation, the word line voltage is maintained at the second negative voltage. As for the bit line voltage, it is maintained at a constant bias voltage (e.g., 4V) until it is detected that the leakage current is less than the predetermined current threshold 1103. However, it should be noted that since the rate at which the leakage current of the bit line drops below the predetermined current threshold is different for each bit line, the duration of maintaining the bit line at a constant voltage is different among the bit lines.

[0060] In summary, the present disclosure is suitable for use in a flash memory device, and even if the erase operation for recovering an over-erased memory cell is interrupted due to the suspension of the erase operation or the power-off of the flash memory device, the present disclosure can still automatically perform the erase operation.

[0061] Unless explicitly stated otherwise, the elements, actions, or instructions used in the detailed description of the disclosed embodiments of the present application should not be considered absolutely critical or essential to the present disclosure.

[0062] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person of ordinary skill in the art in the technical field to which the present invention pertains, without departing from the spirit and scope of the present invention, may make some modifications and refinements. Therefore, the protection scope of the present invention shall be defined by the appended claims.

Claims

1. A method for erasing memory cells of a flash memory device, the method comprising: Performing a first erase operation by applying an erase bias voltage to a block of memory cells of the flash memory device to erase the block of memory cells of the flash memory device; Increasing the erase bias voltage in a stepwise manner until a lower edge of a threshold voltage distribution of the block of memory cells is lower than an erase low-side verification voltage; Performing a first post-programming operation for recovering over-erased memory cells of the block of memory cells until the lower edge of the threshold voltage distribution of the block of memory cells is higher than a post-verification voltage; Performing a second erase operation to erase the block of memory cells to determine whether an upper edge of the threshold voltage distribution of the block of memory cells is lower than an erase high-side verification voltage; And Determining that the block of memory cells has been completely erased after the threshold voltage distribution of the block of memory cells is completely within the post-verification voltage and the erase high-side verification voltage.

2. The method according to claim 1, wherein the erase low-side verification voltage and the post-verification voltage are predetermined threshold voltages, and the post-verification voltage is higher than the erase low-side verification voltage.

3. The method according to claim 2, wherein a voltage difference between the post-verification voltage and the erase low-side verification voltage is less than a step increase amount of the erase bias voltage during increasing the erase bias voltage in the stepwise manner.

4. The method according to claim 3, wherein the erase bias voltage is kept constant in response to the lower edge of the threshold voltage distribution of the block of memory cells being lower than the erase low-side verification voltage.

5. The method according to claim 1, wherein the erase high-side verification voltage is a predetermined threshold voltage, and the predetermined threshold voltage provides an erase margin from a reference voltage, and the reference voltage is between the threshold voltage distribution of the block of memory cells to be erased and the threshold voltage distribution of a block of another programmed memory cell.

6. The method according to claim 2, wherein the erase low-side verification voltage provides a margin from a threshold voltage level at which leakage current occurs.

7. The method according to claim 1, wherein increasing the erase bias voltage in the stepwise manner until the lower edge of the threshold voltage distribution of the block of memory cells is lower than the erase low-side verification voltage includes: Determining whether the lower edge of the threshold voltage distribution of the block of memory cells is lower than the erase low-side verification voltage; Performing the first post-programming operation in response to the lower edge of the threshold voltage distribution of the block of memory cells being lower than the erase low-side verification voltage; And Automatically increasing the erase bias voltage by one voltage step in response to the lower edge of the threshold voltage distribution of the block of memory cells being higher than the erase low-side verification voltage.

8. The method according to claim 1, wherein performing the second erasure operation for erasing the block of the storage cells to determine whether an upper edge of the threshold voltage distribution of the block of the storage cells is lower than the erase high-side verification voltage includes: performing a second programming operation for recovering over-erased storage cells of the block of the storage cells; determining whether the upper edge of the threshold voltage distribution of the block of the storage cells is lower than the erase high-side verification voltage; and performing a third erasure operation for erasing the block of the storage cells in response to the upper edge of the threshold voltage distribution of the block of the storage cells being higher than the erase high-side verification voltage.

9. The method according to claim 1, wherein performing the first post-programming operation for recovering over-erased storage cells of the block of the storage cells includes: setting a bit line of the block of the storage cells to a predetermined voltage; and adjusting a word line voltage connected to the bit line in an increasing manner until a leakage current of the bit line is less than a predetermined threshold.

10. The method according to claim 7, wherein determining whether a lower edge of the threshold voltage distribution of the block of the storage cells is lower than the erase low-side verification voltage includes: determining whether the bit line is conducting while setting the bit line to the erase low-side verification voltage and setting each word line to a constant voltage.

11. A flash memory device, comprising: a block of storage cells; and a memory controller electrically connected to the block of the storage cells and configured to: perform a first erasure operation by applying an erase bias voltage to the block of the storage cells of the flash memory device to erase the block of the storage cells of the flash memory device; increase the erase bias voltage in a stepwise manner until a lower edge of the threshold voltage distribution of the block of the storage cells is lower than the erase low-side verification voltage; perform a first post-programming operation for recovering over-erased storage cells until the lower edge of the threshold voltage distribution of the block of the storage cells is higher than a post-verification voltage; perform a second erasure operation to erase the block of the storage cells until an upper edge of the threshold voltage distribution of the block of the storage cells is lower than the erase high-side verification voltage; and determine that the block of the storage cells has been completely erased after the threshold voltage distribution of the block of the storage cells is completely within the post-verification voltage and the erase high-side verification voltage.

12. The flash memory device according to claim 11, wherein the erase low-side verification voltage and the post-verification voltage are predetermined threshold voltages, and the post-verification voltage is higher than the erase low-side verification voltage.

13. The flash memory device according to claim 12, wherein a voltage difference between the post-verification voltage and the erase low-side verification voltage is less than a step increase amount of the erase bias voltage during the stepwise increase of the erase bias voltage.

14. The flash memory device according to claim 13, wherein in response to the lower edge of the threshold voltage distribution of the block of the memory cells being lower than the erase low-side verification voltage, the memory controller maintains the erase bias voltage constant.

15. The flash memory device according to claim 11, wherein the erase high-side verification voltage is a predetermined threshold voltage that provides an erase margin from a reference voltage, the reference voltage being between the threshold voltage distribution of the block of the memory cells to be erased and the threshold voltage distribution of the block of another programmed memory cell.

16. The flash memory device according to claim 12, wherein the erase low-side verification voltage provides a margin from a threshold voltage level at which leakage current occurs.

17. The flash memory device according to claim 11, wherein the memory controller is configured to increase the erase bias voltage in the stepwise manner until the lower edge of the threshold voltage distribution of the block of the memory cells is lower than the erase low-side verification voltage, including: determining whether the lower edge of the threshold voltage distribution of the block of the memory cells is lower than the erase low-side verification voltage, performing the first post-programming operation in response to the lower edge of the threshold voltage distribution of the block of the memory cells being lower than the erase low-side verification voltage, and automatically increasing the erase bias voltage by one voltage step in response to the lower edge of the threshold voltage distribution of the block of the memory cells being higher than the erase low-side verification voltage.

18. The flash memory device according to claim 11, wherein the memory controller is configured to perform a second erase operation for erasing the block of the memory cells until the upper edge of the threshold voltage distribution of the block of the memory cells is lower than the erase high-side verification voltage, including: performing a second programming operation for restoring the over-erased memory cells of the block of the memory cells, determining whether the upper edge of the threshold voltage distribution of the block of the memory cells is lower than the erase high-side verification voltage, and performing a third erase operation for erasing the block of the memory cells in response to the upper edge of the threshold voltage distribution of the block of the memory cells being higher than the erase high-side verification voltage.

19. The flash memory device according to claim 11, wherein the memory controller is configured to perform the first post-programming operation for restoring the over-erased memory cells of the block of the memory cells, including: setting the bit line of the block of the memory cells to a predetermined negative voltage, and adjusting the word line voltage connected to the bit line in an increasing manner until the leakage current of the bit line is less than a predetermined threshold.

20. The flash memory device according to claim 17, wherein the memory controller is configured to determine whether the lower edge of the threshold voltage distribution of the block of the memory cells is lower than the erase low-side verification voltage, including: While setting the bit line to the erase low-side verification voltage and setting each word line to a constant voltage, determine whether the bit line is conducting.

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