Erasing method of select gate shared split gate flash memory and related equipment
By selecting two floating gate storage structures at the same time in the selection gate shared gate flash memory for erasing verification, the problem of insufficient erasing efficiency is solved, and a faster and more efficient erasing process is achieved.
Patent Information
- Application Number
- CN202510358216.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2025-07-04
AI Technical Summary
The existing selection gate shared gate flash erasing process is inefficient, requires a long erase time and high-intensity erase conditions, and the introduction of the verification process will affect the efficiency.
During the erase process, the erase is completed by selecting the two floating gate storage structures of each gate sub-unit cell simultaneously for erase verification, and combining the erase processing, including connecting the control gate to the 0V voltage to make the floating gate storage structure not conducting, and determining the erase state by reading the on current.
It effectively reduces erase time and conditions, saves half of the verification time, and improves erase efficiency.
Smart Images
Figure CN120260650A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of memories, and in particular, to an erasing method and related devices for a select-gate shared split-gate flash memory. Background Art
[0002] The select-gate shared split-gate flash memory has advantages such as a small cell area, no over-erasure phenomenon, and scalability, and has good development prospects.
[0003] The split-gate cell is the memory body of the select-gate shared split-gate flash memory, and its structure is as Figure 1 shown. It has two floating-gate storage structures (CELL A, CELL B) and a shared select-gate connected to a word line (WL). Each floating-gate storage structure can store one bit of data independently, corresponding to one bit. The two floating-gate storage structures have corresponding control gates (CG0, CG1). When operating on one of the bits, the select-gate and the other floating-gate storage structure can be regarded as a conducting transmission gate. Among them, the floating gate corresponding to the selected floating-gate storage structure is defined as the target control gate (target cg), and the floating gate corresponding to the floating-gate storage structure used as the conducting transmission gate is defined as the pass control gate (pass cg).
[0004] The select-gate shared split-gate flash memory solves the serious over-erase problem of traditional NOR flash memories based on its dual floating-gate storage structure. Therefore, its erasing process generally does not require an erasing verification process. However, relatively speaking, a longer erasing time and high-intensity erasing conditions need to be set to ensure that data can be erased smoothly. If an erasing verification process is introduced, data reading and verification need to be performed on the two floating-gate storage structures of each split-gate cell respectively, which affects the erasing efficiency of the entire erasing process. Therefore, the existing select-gate shared split-gate flash memories have the disadvantage of insufficient erasing efficiency.
[0005] In view of the above problems, there is currently no effective technical solution. Summary of the Invention
[0006] The purpose of the present application is to provide an erasing method and related devices for a select-gate shared split-gate flash memory to reduce the erasing time and erasing conditions and improve the erasing efficiency.
[0007] In a first aspect, the present application provides an erasing method for a select-gate shared split-gate flash memory, and the method includes the following steps: S1. Obtain a target area to be erased; S2. Apply an erasing pulse to the target area for erasing processing; S3. Perform an erase verification on the target area based on simultaneously selecting two floating-gate storage structures in each split-gate cell in the target area. If the erase verification fails, return to step S2. If the erase verification passes, end the erasure.
[0008] The erase method of the select-gate shared split-gate flash memory of the present application introduces an erase verification during the erasure process by simultaneously selecting two floating-gate storage structures in each split-gate cell in the target area to determine whether the split-gate cell is successfully erased. The erasure of the select-gate shared split-gate flash memory is completed by means of erasure processing combined with erase verification, which can effectively reduce the erasure time and erasure conditions used in the erasure processing of the select-gate shared split-gate flash memory. The practice of simultaneously selecting two floating-gate storage structures of the split-gate cell for erase verification can also save half of the time required for erase verification.
[0009] The erase method of the select-gate shared split-gate flash memory, wherein, in step S3, the process of simultaneously selecting two floating-gate storage structures of the split-gate cell includes: Simultaneously apply a 0V voltage to the control gates corresponding to the two floating-gate storage structures of the split-gate cell.
[0010] This example simultaneously selects the two control gates of the split-gate cell, making both floating-gate storage structures non-conductive and forming a data reading whole, so that the erase verification process is transformed into reading the current conduction ability of the superimposed state of the two floating-gate storage structures in the split-gate cell, in order to realize the composite verification of the erase states of the two floating-gate storage structures of the split-gate cell, thereby improving the verification efficiency of the erase verification.
[0011] The erase method of the select-gate shared split-gate flash memory, wherein, in step S3, the process of performing an erase verification on the target area includes: Read the data of the split-gate cell in ascending order of address in the target area for erase verification.
[0012] The erase method of the select-gate shared split-gate flash memory, wherein the process of reading the data of the split-gate cell includes: Apply a read voltage to the split-gate cell to generate a conduction current; Compare the magnitude of the conduction current with a preset reference current to generate a data reading result, wherein the data reading result is that the conduction current is greater than the reference current indicating that the stored data of the corresponding split-gate cell is 11, and the data reading result is that the conduction current is less than or equal to the reference current indicating that the stored data of the corresponding split-gate cell is 01, 10 or 00.
[0013] The erasing method of the select-gate shared split-gate flash memory, wherein the process of performing data reading on the split-gate cells in the target area in ascending order of addresses for erasing verification includes: In the target area in ascending order of addresses, start performing data reading on the split-gate cells for erasing verification based on the addresses that failed the verification in the previous round.
[0014] The erasing method of the select-gate shared split-gate flash memory, wherein the method further includes a step executed between step S1 and step S2: SA. Perform an initialization check on the target area to obtain a starting check address, where the starting check address is the address of the split-gate cell in the non-erased state determined in ascending order of addresses in the target area; In step S3, the first erasing verification starts from the starting check address.
[0015] The erasing method of the select-gate shared split-gate flash memory, wherein in step S3, the process of returning to step S2 if the erasing verification fails includes: If the erasing verification fails, reduce the erasing pulse time for the next erasing process, and then return to step S2.
[0016] In a second aspect, the present application also provides an erasing device for a select-gate shared split-gate flash memory, the device includes: An acquisition module for acquiring a target area to be erased; An erasing module for applying an erasing pulse to the target area for erasing processing; A verification module for performing erasing verification on the target area by simultaneously selecting two floating-gate storage structures in each split-gate cell in the target area. If the erasing verification fails, trigger the erasing module to perform erasing processing again. If the erasing verification passes, end the erasing.
[0017] The erasing device of the select-gate shared split-gate flash memory of the present application introduces an erasing verification by simultaneously selecting two floating-gate storage structures in each split-gate cell in the target area during the erasing process to determine whether the split-gate cell is successfully erased, and completes the erasing of the select-gate shared split-gate flash memory through the means of erasing processing combined with erasing verification. It can effectively reduce the erasing time and erasing conditions used in the erasing processing of the select-gate shared split-gate flash memory. The practice of simultaneously selecting two floating-gate storage structures of the split-gate cell for erasing verification can also save half of the time required for erasing verification.
[0018] In a third aspect, the present application further provides a storage chip, including a controller and a storage array composed of split-gate cells. The controller is configured to execute the steps in the erasing method of the select-gate shared split-gate flash memory provided in the first aspect above to erase the storage array.
[0019] In a fourth aspect, the present application further provides an electronic device, including the storage chip provided in the third aspect.
[0020] As can be seen from the above, the present application provides an erasing method for a select-gate shared split-gate flash memory and related devices. Among them, in the erasing method of the select-gate shared split-gate flash memory, an erasing verification is introduced during the erasing process by simultaneously selecting two floating-gate storage structures in each split-gate cell in the target area to determine whether the split-gate cell is successfully erased. The erasing of the select-gate shared split-gate flash memory is completed by means of erasing processing combined with erasing verification, which can effectively reduce the erasing time and erasing conditions used in the erasing process of the select-gate shared split-gate flash memory. The practice of simultaneously selecting two floating-gate storage structures of the split-gate cell for erasing verification can also save half of the time required for erasing verification. That is, this method improves the efficiency of the erasing process by introducing an erasing verification means with low consumption, and can effectively improve the erasing efficiency of the entire erasing process. Description of the Drawings
[0021] Figure 1 It is a schematic structural diagram of a split-gate cell.
[0022] Figure 2 It is a flowchart of the erasing method for the select-gate shared split-gate flash memory provided in the embodiment of the present application.
[0023] Figure 3 It is a schematic structural diagram of the erasing device for the select-gate shared split-gate flash memory provided in the embodiment of the present application.
[0024] Reference numerals: 201, acquisition module; 202, erasing module; 203, verification module. Detailed Embodiments
[0025] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Usually, the components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application to be protected, but only represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.
[0026] It should be noted that like reference numerals and letters refer to like items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of the present application, terms such as "first" and "second" are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.
[0027] In a first aspect, please refer to Figure 2 , some embodiments of the present application provide an erasing method for a select-gate shared split-gate flash memory, and the method includes the following steps: S1. Obtain a target area to be erased; S2. Apply an erasing pulse to the target area for erasing; S3. Based on simultaneously selecting two floating-gate storage structures in each split-gate unit in the target area to perform an erasing verification on the target area. If the erasing verification fails, return to step S2. If the erasing verification passes, end the erasing.
[0028] Specifically, the target area is an area in the storage array of the select-gate shared split-gate flash memory that needs to be erased, generally manifested as one or more continuous address areas; the erasing process is an operation of applying an erasing pulse with a preset time length and a preset voltage magnitude to all split-gate units in a specific area to change the threshold voltage of the CELL in the split-gate unit.
[0029] More specifically, in order to save erasing time and reduce erasing conditions, the erasing method of the select-gate shared split-gate flash memory in the embodiments of the present application introduces an erasing verification process for determining whether the split-gate units in the target area are successfully erased after each application of the erasing pulse. Among them, due to the introduction of the erasing verification process, the erasing process in step S2 can adopt erasing conditions and erasing time weaker than those of the existing select-gate shared split-gate flash memory erasing process, and it determines whether the erasing process is successful through erasing verification to realize the erasing of the target area by using multiple erasing process behaviors.
[0030] More specifically, for each split-gate cell in the select-gate shared split-gate flash memory, if all the data therein needs to be read, one control gate in the split-gate cell needs to be selected, and the other control gate is used as the conduction control gate to perform two read operations respectively, that is, the stored data of only one CELL in the split-gate cell can be read each time; different from the general erase verification or data reading process, the erase verification process in the embodiment of the present application is based on simultaneously selecting two floating-gate storage structures in each split-gate cell, and it no longer reads the stored data in each CELL (floating-gate storage structure) in the traditional way for verification. It is equivalent to regarding the two CELLs in the split-gate cell as a whole for data reading and verification, and can combine the two read and verification behaviors corresponding to each split-gate cell into one read and verification behavior, thus saving half of the erase verification time and also saving half of the address selection space.
[0031] It should be noted that the erase verification process based on simultaneously selecting two floating-gate storage structures in each split-gate cell is similar to the verification process of NOR flash memory. The read data generated in the erase verification process of the present application is manifested as the magnitude value of the conduction current. The magnitude value of this conduction current cannot be directly used as the discrimination criterion for whether the stored data of a single CELL is data 1 or data 0 like the conduction current in NOR flash memory. However, considering the characteristic that the smaller the threshold voltage (Vth) of the CELL, the larger the generated conduction current, the more CELLs with data 1 (erased state) in the split-gate cell, the larger the corresponding conduction current. Therefore, only by configuring appropriate current judgment conditions for the conduction current according to the actual measurement situation, it is possible to judge whether the entire split-gate cell is successfully erased when simultaneously selecting two floating-gate storage structures in each split-gate cell.
[0032] The erase method of the select-gate shared split-gate flash memory in the embodiment of the present application introduces an erase verification process based on simultaneously selecting two floating-gate storage structures in each split-gate cell in the target area to determine whether the split-gate cell is successfully erased, and completes the erase of the select-gate shared split-gate flash memory through the means of erase processing combined with erase verification. It can effectively reduce the erase time and erase conditions used in the erase processing of the select-gate shared split-gate flash memory. The method of simultaneously selecting two floating-gate storage structures in the split-gate cell for erase verification can also save half of the time required for erase verification, that is, this method improves the efficiency of erase processing by introducing a low-time-consuming erase verification means, and can effectively improve the erase efficiency of the entire erase process.
[0033] In some preferred embodiments, in step S3, the process of simultaneously selecting two floating-gate storage structures in the split-gate cell includes: Applying a 0V voltage to the control gates corresponding to the two floating-gate storage structures of the split-gate cell simultaneously.
[0034] Specifically, based on the foregoing, it can be known that applying a conduction voltage to the control gate can transform the control gate into a conductive control gate, and then make the corresponding CELL conductive for use as a transmission gate; and the above steps are to apply a 0V voltage to the two control gates of the split gate unit to simultaneously select the two control gates of the split gate unit, so that both floating gate storage structures are not conductive to form a data reading whole, and the erase verification process is transformed into reading the current conduction ability of the superimposed state of the two floating gate storage structures in the split gate unit, so as to realize the composite verification of the erase states of the two floating gate storage structures in the split gate unit, thereby improving the verification efficiency of the erase verification.
[0035] It should be noted that the above steps only limit the selection method for a single split gate unit, and the erase verification process is actually a process of successively selecting and verifying multiple split gate units.
[0036] In some preferred embodiments, in step S3, the process of performing erase verification on the target area includes: Reading data from the split gate units in the target area in ascending order of addresses for erase verification.
[0037] Specifically, performing erase verification on the split gate units in ascending order of addresses can effectively ensure the orderliness of the erase verification process.
[0038] It should be noted that the data reading method in the erase verification process is combined with the data reading ability of the corresponding select-gate shared split-gate flash memory. For example, if its reading ability is 1 byte, then 8 split gate units' data are read each time for erase verification, directly completing the erase verification of all split gate units in the target area or detecting the split gate units with failed verification.
[0039] In some preferred embodiments, the process of reading data from the split gate units includes: Applying a read voltage to the split gate unit to generate a conduction current; Comparing the magnitude of the conduction current with a preset reference current to generate a data reading result. Among them, the data reading result that the conduction current is greater than the reference current indicates that the stored data of the corresponding split gate unit is 11, and the data reading result that the conduction current is less than or equal to the reference current indicates that the stored data of the corresponding split gate unit is 01, 10 or 00.
[0040] Specifically, the reference current can be determined by measuring the conduction current according to some split gate units whose stored data are respectively 11, 01, and 10 in design, that is, the erase method of the select-gate shared split-gate flash memory in the embodiments of the present application can determine the reference current that can distinguish the two types of data reading results through experimental measurement.
[0041] It should be noted that the data reading result indicating that the stored data of the split-gate cell is 11 represents that the verification passes, that is, the corresponding split-gate cell is in the erased state, and the data reading result indicating that the stored data of the split-gate cell is 01, 10 or 00 represents that the verification fails.
[0042] In some preferred embodiments, the process of performing data reading on split-gate cells in ascending order of addresses in the target area for erase verification includes: In the target area, in ascending order of addresses, starting from the address where the verification failed in the previous round, data reading is performed on the split-gate cells for erase verification.
[0043] Specifically, steps S2 and S3 are processes that are executed in a loop, and the end node is that all split-gate cells in the target area are erased; based on the foregoing, it can be seen that the select-gate shared split-gate flash memory itself will not have an overerase problem, so the split-gate cells that pass the verification based on the address order will always remain in the successfully erased state. Therefore, the loop-executed S3 can start the verification based on the split-gate cells that failed the verification last time, so as to further save the time required for erase verification and improve the overall erase efficiency.
[0044] It should be noted that when step S3 detects a split-gate cell with a failed verification, it will record the address of the corresponding split-gate cell and start the erase verification based on this address when step S3 is executed next time.
[0045] In some preferred embodiments, the method further includes a step executed between step S1 and step S2: SA. Perform an initialization check on the target area to obtain a starting check address, which is the address of the split-gate cell in the non-erased state determined in ascending order of addresses in the target area; In step S3, the first erase verification is started based on the starting check address.
[0046] Specifically, the initialization check is used to check whether the target area really needs to be erased, and in the case where erasure is required, the address of the first split-gate cell in the non-erased state is determined in ascending order of addresses as the starting address for subsequent erase verification, so as to further save the time for erase verification.
[0047] It should be noted that if no starting check address is found in the initialization check, it indicates that the target area itself is already in the erased state and no erasure processing is required, and the erasure is directly ended.
[0048] More specifically, in order to further improve the efficiency of the initialization check, the initialization check is preferably performed in ascending order of addresses, and data is read from the target area based on simultaneously selecting two floating gate storage structures in each split gate cell in the target area; this processing method is similar to that in step S3. By simultaneously selecting two floating gate storage structures of the split gate cell, it is determined whether the stored data in the split gate cell is 11 to improve the check efficiency.
[0049] In some preferred embodiments, in step S3, the process of returning to step S2 if the erase verification fails includes: If the erase verification fails, the erase pulse time for the next erase process is reduced, and then the process returns to step S2.
[0050] Specifically, by designing the erase pulse time in a decreasing manner, the erase pulse time can be more reused to complete the erase of the target area, avoiding the situation where the erase pulse time is designed too long and restricting the erase efficiency.
[0051] More specifically, the reduction value of the erase pulse time is preferably 1 / 8 of the previous erase pulse time.
[0052] In some preferred embodiments, in step S3, the process of returning to step S2 if the erase verification fails includes: If the erase verification fails and the address that fails the verification is different from the address that failed the verification in the previous round, the erase pulse time for the next erase process is reduced, and then the process returns to step S2.
[0053] Specifically, if the address that fails the verification is the same as the address that failed the verification in the previous round, it indicates that the corresponding split gate cell is difficult to be erased. Therefore, the same erase pulse time is maintained to continue the erase process in step S2 to ensure that the split gate cell that fails the verification can be successfully erased.
[0054] In a second aspect, please refer to Figure 3 , some embodiments of the present application further provide an erase device for a select gate shared split gate flash memory, and the device includes: An acquisition module 201 for acquiring a target area to be erased; An erase module 202 for applying an erase pulse to the target area for erase processing; A verification module 203 for performing an erase verification on the target area based on simultaneously selecting two floating gate storage structures in each split gate cell in the target area. If the erase verification fails, the erase module is triggered to perform the erase process again. If the erase verification passes, the erase ends.
[0055] In the erasing device of the select-gate sharing split-gate flash memory according to the embodiment of the present application, an erasing verification is introduced during the erasing process, in which two floating-gate storage structures in each split-gate cell in the target area are simultaneously selected for erasing verification to determine whether the split-gate cell is successfully erased. By means of combining the erasing process with the erasing verification, the erasing of the select-gate sharing split-gate flash memory is completed. This can effectively reduce the erasing time and erasing conditions used in the erasing process of the select-gate sharing split-gate flash memory. The method of simultaneously selecting two floating-gate storage structures in the split-gate cell for erasing verification can also save half of the time required for erasing verification. That is, the device improves the efficiency of the erasing process by introducing an erasing verification means with low time consumption, and can effectively improve the erasing efficiency of the entire erasing process.
[0056] In some preferred embodiments, the verification module 203 is further configured to perform an initialization check on the target area to obtain a starting check address, which is the address of the split-gate cell in the target area that is in a non-erased state and is determined in ascending order of addresses. The first erasing verification performed by the verification module 203 starts from the starting check address.
[0057] In some preferred embodiments, the erasing device of the select-gate sharing split-gate flash memory according to the embodiment of the present application is used to execute the erasing method of the select-gate sharing split-gate flash memory provided in the first aspect above.
[0058] In a third aspect, some embodiments of the present application further provide a storage chip, including a controller and a storage array composed of split-gate cells. The controller is configured to execute the steps in the erasing method of the select-gate sharing split-gate flash memory provided in the first aspect to erase the storage array.
[0059] In a fourth aspect, some embodiments of the present application further provide an electronic device, including the storage chip provided in the third aspect.
[0060] In the embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections between each other can be through some communication interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical or other forms.
[0061] In addition, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or may be distributed over multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0062] Furthermore, in each embodiment of the present application, the various functional modules may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.
[0063] In this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
[0064] The above description is only for the embodiments of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A method for erasing a select-gate shared split-gate flash memory, characterized in that, The method includes the following steps: S1. Obtain a target area to be erased; S2. Apply an erasure pulse to the target area for erasure processing; S3. Based on simultaneously selecting two floating gate storage structures in each split gate cell in the target area, perform an erasure verification on the target area. If the erasure verification fails, return to step S2. If the erasure verification passes, end the erasure.
2. The erasing method of the select-gate shared split-gate flash memory according to claim 1, wherein In step S3, the process of simultaneously selecting two floating gate storage structures of the split gate cell includes: Simultaneously apply a 0V voltage to the control gates corresponding to the two floating gate storage structures of the split gate cell.
3. The erasing method of the select-gate shared split-gate flash memory according to claim 1, wherein In step S3, the process of performing the erasure verification on the target area includes: In the target area, read data from the split gate cells in ascending order of address for erasure verification.
4. The erasing method of the select-gate shared split-gate flash memory according to claim 3, characterized in that, The process of reading data from the split gate cell includes: Apply a read voltage to the split gate cell to generate a conduction current; Compare the magnitude of the conduction current with a preset reference current to generate a data read result. Among them, the data read result is that the conduction current is greater than the reference current, indicating that the stored data of the corresponding split gate cell is 11. The data read result is that the conduction current is less than or equal to the reference current, indicating that the stored data of the corresponding split gate cell is 01, 10 or 00.
5. The erasing method of the select-gate shared split-gate flash memory according to claim 3, wherein The process of reading data from the split gate cells in ascending order of address in the target area for erasure verification includes: In the target area, start reading data from the split gate cells for erasure verification in ascending order of address based on the address where the verification failed in the previous round.
6. The erasing method of the select-gate sharing split-gate flash memory according to claim 3, wherein The method further includes a step executed between step S1 and step S2: SA. Perform an initialization check on the target area to obtain a starting check address, where the starting check address is the address of the split gate cell in the target area that is in a non-erased state determined in ascending order of address; In step S3, the first erasure verification starts based on the starting check address.
7. The erasing method of the select-gate shared split-gate flash memory according to claim 1, characterized in that, In step S3, the process of returning to step S2 if the erasure verification fails includes: If the erasure verification fails, reduce the erasure pulse time for the next erasure process, and then return to step S2.
8. An erasing device for a select-gate shared split-gate flash memory, characterized in that, The device includes: An acquisition module for obtaining a target area to be erased; An erasure module for applying an erasure pulse to the target area for erasure processing; A verification module for performing an erasure verification on the target area based on simultaneously selecting two floating gate storage structures in each split gate cell in the target area. If the erasure verification fails, trigger the erasure module to perform erasure processing again. If the erasure verification passes, end the erasure.
9. A storage chip, characterized in that, It includes a controller and a storage array composed of split gate cells. The controller is used to execute the steps in the erasure method of the select-gate-sharing split-gate flash memory according to any one of claims 1-7 to erase the storage array.
10. An electronic device, characterized in that, It includes a storage chip as described in claim 9.