Programming reliability checking method of select gate shared split gate flash memory and related equipment
By using the buffer to perform consistency analysis in the selected gate shared gate flash memory, the problem of programming checking of the on-control gate is solved, ensuring the accuracy of data reading and improving the reliability of the memory.
Patent Information
- Application Number
- CN202510358215.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2025-07-04
AI Technical Summary
The prior art cannot effectively check whether the floating gate storage structure corresponding to the on-control gate in the selected gate shared gate flash memory has overprogramming problems, resulting in data reading errors.
By obtaining the byte address information of the programming task and the data to be programmed, the first buffer is cached and written to the second buffer, and after programming processing is performed, the consistency analysis is performed to check whether there are overprogramming problems in the floating gate storage structure corresponding to the turn-on control gate.
Accurately analyze whether there are overprogramming problems in the floating gate storage structure corresponding to the conduction control gate, avoid data reading errors, and improve the reliability of selecting gate-shared sub-gate flash memory.
Smart Images
Figure CN120260652A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of memories, and more particularly, to a method for checking the programming reliability of a select-gate shared split-gate flash memory and related devices. Background Art
[0002] The select-gate shared split-gate flash memory has advantages such as a small cell area, no over-erase phenomenon, and scalability, and has good development prospects.
[0003] The split-gate cell is the memory body of the select-gate shared split-gate flash memory, and its structure is as Figure 1 shown. It has two floating-gate storage structures (CELL A, CELL B) and a shared select-gate connected to a word line (WL). Each floating-gate storage structure can store one bit of data independently, corresponding to one bit. The two floating-gate storage structures have corresponding control gates (CG0, CG1). When operating on one of the bits, the select-gate and the other floating-gate storage structure can be regarded as a conducting transmission gate. Among them, the floating gate corresponding to the selected floating-gate storage structure is defined as the target control gate (target cg), and the floating gate corresponding to the floating-gate storage structure used as the conducting transmission gate is defined as the pass control gate (pass cg).
[0004] The select-gate shared split-gate flash memory solves the serious over-erase problem of traditional NOR flash memories, but there is still an over-program problem. The over-program checking method of traditional NOR flash memories is not applicable to the select-gate shared split-gate flash memory, and it cannot effectively check whether the floating-gate storage structure corresponding to the pass control gate has an over-program problem, which is likely to cause data read errors.
[0005] In view of the above problems, there is currently no effective technical solution. Summary of the Invention
[0006] The purpose of this application is to provide a method for checking the programming reliability of a select-gate shared split-gate flash memory and related devices to check whether the floating-gate storage structure corresponding to the pass control gate has an over-program problem.
[0007] In a first aspect, this application provides a method for checking the programming reliability of a select-gate shared split-gate flash memory for performing an over-program check on the split-gate storage structure in the programmed select-gate shared split-gate flash memory. The method includes the following steps: S1. Obtain the byte address information to be programmed and the corresponding data information to be programmed, and write them into the first buffer; S2. Extract the first data information according to the byte address information, and write the first data information into the second buffer. The first data information includes the data of the storage units corresponding to all the conducting control gates in the split-gate memory structure corresponding to the byte address information; S3. Perform a programming process on the split-gate memory structure according to the byte address information cached in the first buffer and the corresponding data information to be programmed; S4. Read the second data information according to the byte address information, and perform an over-programming check based on the consistency between the first data information and the second data information. The second data information includes the data of the storage units corresponding to all the conducting control gates in the programmed split-gate memory structure corresponding to the byte address information.
[0008] The programming reliability checking method of the select-gate shared split-gate flash memory of the present application realizes the over-programming check of the storage units corresponding to the conducting control gates by using the second buffer to cache the first data information before the programming process for consistency analysis with the second data information after the programming process, can accurately analyze whether there is an over-programming problem in the floating-gate memory structure corresponding to the conducting control gate, as a basis for subsequent repair processing or to inform the user, avoid data reading errors, and improve the reliability of the operation of the select-gate shared split-gate flash memory.
[0009] In the programming reliability checking method of the select-gate shared split-gate flash memory, step S2 includes: S21. Perform data reading on the split-gate memory structure according to the conducting control gate corresponding to the byte address information to obtain the first data information, and write the first data information into the second buffer.
[0010] The above steps are equivalent to temporarily swapping the types of the target control gate and the conducting control gate corresponding to the programming task to read the twin byte data corresponding to the byte address information of the programming task to achieve the caching of the first data information.
[0011] In the programming reliability checking method of the select-gate shared split-gate flash memory, step S3 includes: S31. Perform programming on the split-gate memory structure according to the address of the target control gate corresponding to the byte address information cached in the first buffer and the corresponding data information to be programmed.
[0012] In the programming reliability checking method of the select-gate shared split-gate flash memory, step S4 includes: S41. Perform data reading on the programmed split-gate memory structure according to the conducting control gate corresponding to the byte address information to obtain the second data information; S42. Extract the first data information cached in the second buffer; S43. Based on the byte address information, compare the first data information and the second data information bit by bit to check if they are the same. If so, it is considered that no programming phenomenon has occurred.
[0013] The programming reliability checking method for the select-gate shared split-gate flash memory, wherein step S43 includes: S431. Screen and obtain the non-0 byte data in the first data information, and based on the byte address information, compare the non-0 byte data and the second data information bit by bit or byte by byte to check if they are the same. If so, it is considered that no programming phenomenon has occurred.
[0014] The programming reliability checking method for the select-gate shared split-gate flash memory, wherein in step S4, the second data information is read based on a first voltage, and the first voltage is less than the reference read voltage.
[0015] The programming reliability checking method for the select-gate shared split-gate flash memory, wherein both the first buffer and the second buffer are static random access memories.
[0016] In a second aspect, the present application further provides a programming reliability checking device for a select-gate shared split-gate flash memory, which is used to perform over-programming check on the split-gate storage structure in the programmed select-gate shared split-gate flash memory. The device includes: A first buffer module, configured to obtain the byte address information to be programmed and the corresponding data information to be programmed, and write them into a first buffer; A second buffer module, configured to extract the first data information according to the byte address information and write the first data information into a second buffer. The first data information includes the data of the storage units corresponding to all the conducting control gates corresponding to the byte address information in the split-gate storage structure; A programming module, configured to perform programming processing on the split-gate storage structure according to the byte address information cached in the first buffer and the corresponding data information to be programmed; An inspection module, configured to read the second data information according to the byte address information, and perform over-programming check according to the consistency between the first data information and the second data information. The second data information includes the data of the storage units corresponding to all the conducting control gates corresponding to the byte address information in the programmed split-gate storage structure.
[0017] The programming reliability checking device of the select-gate shared split-gate flash memory of the present application realizes over-programming checking of the storage cells corresponding to the conduction control gate by using the second buffer to cache the first data information before programming processing and performing consistency analysis with the second data information after programming processing, and can accurately analyze whether there is an over-programming problem in the floating-gate storage structure corresponding to the conduction control gate, so as to be used as the basis for subsequent repair processing or inform the user, avoid data reading errors, and improve the reliability of the operation of the select-gate shared split-gate flash memory.
[0018] In a third aspect, the present application further provides a storage chip, including a Flash controller and a split-gate storage structure, where the Flash controller is used to execute the steps in the programming reliability checking method of the select-gate shared split-gate flash memory provided in the first aspect above to program and check the split-gate storage structure.
[0019] In a fourth aspect, the present application further provides an electronic device, including the storage chip provided in the third aspect.
[0020] As can be seen from the above, the present application provides a programming reliability checking method and related devices for a select-gate shared split-gate flash memory. Among them, the programming reliability checking method of the select-gate shared split-gate flash memory realizes over-programming checking of the storage cells corresponding to the conduction control gate by using the second buffer to cache the first data information before programming processing and performing consistency analysis with the second data information after programming processing, and can accurately analyze whether there is an over-programming problem in the floating-gate storage structure corresponding to the conduction control gate, so as to be used as the basis for subsequent repair processing or inform the user, avoid data reading errors, and improve the reliability of the operation of the select-gate shared split-gate flash memory. Description of the Drawings
[0021] Figure 1 It is a schematic structural diagram of a split-gate unit.
[0022] Figure 2 It is a flowchart of the programming reliability checking method for the select-gate shared split-gate flash memory provided by the embodiment of the present application.
[0023] Figure 3 It is a schematic structural diagram of the programming reliability checking device for the select-gate shared split-gate flash memory provided by the embodiment of the present application.
[0024] Reference numerals: 201, first buffer module; 202, second buffer module; 203, programming module; 204, checking module. Detailed Embodiments
[0025] Next, in combination with the accompanying drawings in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.
[0026] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, terms such as "first" and "second" are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.
[0027] In a first aspect, please refer to Figure 2 , some embodiments of the present application provide a programming reliability checking method for a select-gate shared split-gate flash memory, which is used to perform over-programming checking on the split-gate storage structure in the programmed select-gate shared split-gate flash memory. The method includes the following steps: S1. Obtain the byte address information to be programmed and the corresponding data information to be programmed, and write them into the first buffer; S2. Extract the first data information according to the byte address information, and write the first data information into the second buffer. The first data information includes the data of the storage units corresponding to all the conduction control gates in the split-gate storage structure corresponding to the byte address information; S3. Perform programming processing on the split-gate storage structure according to the byte address information cached in the first buffer and the corresponding data information to be programmed; S4. Read the second data information according to the byte address information, and perform over-programming checking according to the consistency between the first data information and the second data information. The second data information includes the data of the storage units corresponding to all the conduction control gates in the programmed split-gate storage structure corresponding to the byte address information.
[0028] Specifically, over-program usually refers to the situation during programming where non-target storage cells (non-programming objects) are disturbed, causing a change in their state. It may reach the critical point where the state changes from data 1 (unprogrammed state) to data 0 (programmed state), or even change to data 0. This phenomenon will damage the integrity of the data and affect the reliability of the memory. In the select-gate shared split-gate flash memory, this interference phenomenon will also occur in the floating-gate storage structure corresponding to the conduction control gate. For example, when reading the data of CELL B, a conduction control voltage V needs to be applied to the control gate of CELL A. pass cg , due to the over-program problem in CELL A, its threshold voltage V th will increase, resulting in the state of V th >V pass cg , making CELL A unable to turn on and conduct, which in turn causes an error in reading the data of CELL B.
[0029] More specifically, the programming reliability checking method of the select-gate shared split-gate flash memory according to the embodiments of the present application aims to accurately check whether the over-program phenomenon occurs in the floating-gate storage structure corresponding to the conduction control gate, so as to serve as the basis for subsequent repair processing or inform the user, improving the reliability of the operation of the select-gate shared split-gate flash memory.
[0030] More specifically, the split-gate storage structure refers to the storage array of the select-gate shared split-gate flash memory, which includes multiple split-gate cells as shown in Figure 1 . In the structure of this split-gate cell, CELL A and CELL B are each other's twin bits. That is, when selecting CELL A for programming, the control gate of CALL A is the target control gate, CELL B is the floating-gate storage structure that needs to conduct, and the control gate of CELL B is the conduction control gate. Thus, it can be seen that the control gate of each floating-gate storage structure can actually switch types between the target control gate and the conduction control gate, and its type depends on whether the programming object of the currently executed programming task is CELL A or CELL B. That is, for the programming task corresponding to the selected floating-gate storage structure to be programmed, its control gate is the target control gate, and the control gate corresponding to its twin bit is the conduction control gate.
[0031] More specifically, in a selected-gate shared split-gate flash memory, the read process usually takes a byte as the processing unit, and the programming process usually takes multiple bytes as the processing unit. Therefore, the programming process needs to obtain the corresponding several byte address information and the data information to be programmed, and then write the data information to be programmed into the corresponding byte address information. Due to the particularity of the split-gate storage structure, when the programming process writes data into one byte, one byte of the floating-gate storage structure corresponding to it is in the conducting state. For example, when writing 8-bit data, 8 twin bits in the corresponding 8 split-gate units are in the conducting state, and these 8 twin bits form a twin byte; among them, the first data information read from the cache in step S2 is the stored data of all twin bytes corresponding to the corresponding programming task before the programming process, and the second data information read in step S4 is the stored data of all twin bytes corresponding to the corresponding programming task after the programming process. Based on the byte as the processing unit conforms to the data processing criteria of the read process and the programming process of the selected-gate shared split-gate flash memory.
[0032] More specifically, before performing the data writing operation, the programming reliability checking method of the selected-gate shared split-gate flash memory according to the embodiment of the present application caches the address and data to be written in step S1, that is, caches the programming task, and then caches the data of all storage units (CELLs) corresponding to the conducting control gates as the reference data for subsequent checking in S2, and after performing the actual programming using the cached programming task in S3, in step S4, compares the cached reference data with the stored data of all twin bytes read to accurately check whether over-programming has occurred in the floating-gate storage structure corresponding to the conducting control gate.
[0033] The programming reliability checking method of the selected-gate shared split-gate flash memory according to the embodiment of the present application realizes the over-programming check of the storage unit corresponding to the conducting control gate by using the second buffer to cache the first data information before the programming process for consistency analysis with the second data information after the programming process, and can accurately analyze whether over-programming has occurred in the floating-gate storage structure corresponding to the conducting control gate, so as to be used as the basis for subsequent repair processing or inform the user, avoid data reading errors, and improve the reliability of the operation of the selected-gate shared split-gate flash memory.
[0034] In some preferred embodiments, step S2 includes: S21. Read the data of the split-gate storage structure according to the conducting control gate corresponding to the byte address information to obtain the first data information, and write the first data information into the second buffer.
[0035] Specifically, the above steps are equivalent to temporarily swapping the types of the target control gate and the conduction control gate corresponding to the programming task to read the twin byte data corresponding to the byte address information corresponding to the programming task, so as to implement the caching of the first data information.
[0036] More specifically, in order to ensure that the subsequent matching analysis of the first data information and the second data information can be carried out smoothly, the first data information is preferably written into the second buffer in sequence based on the byte address information, or in step S21, the first data information and the byte address information are written into the second buffer simultaneously, so that in step S4, the consistency comparison of the first data information and the second data information can be carried out according to the data sequence relationship or the byte address information.
[0037] In some preferred embodiments, step S3 includes: S31. Program the split-gate memory structure according to the address of the target control gate corresponding to the byte address information cached in the first buffer and the corresponding data information to be programmed.
[0038] Specifically, this programming process is actually: determining multiple split-gate units that need to be programmed according to the byte address information, selecting the control gates of the CELLs that need to be programmed among the multiple split-gate units, simultaneously turning on the control gates of the CELLs as twin bits, and then applying a programming pulse voltage to achieve programming; in this embodiment, the CELL corresponding to the turned-on control gate is equivalent to a turned-on transmission gate, so that the split-gate unit is transformed into a common memory unit similar to that in a NOR flash memory, and the process of applying the programming pulse voltage for programming can specifically be implemented by a programming method similar to or consistent with that of a NOR flash memory, such as repeatedly executing applying a programming pulse (program), programming verification (program verify), until the data of all CELLs that need to be programmed are programmed to data 0.
[0039] It should be noted that the programming reliability check method of the select-gate shared split-gate flash memory in the embodiments of the present application aims to provide an over-programming check means for post-programming processing. The byte address information that needs to be programmed should be an erased area. If there is written data in the areas corresponding to these byte address information, the NOR flash memory should perform an erase process on these areas before executing step S1.
[0040] In some preferred embodiments, step S4 includes: S41. Read data from the programmed split-gate memory structure according to the conduction control gate corresponding to the byte address information to obtain the second data information; S42. Extract the first data information cached in the second buffer; S43. Compare each bit of the first data information and the second data information based on the byte address information. If they are the same, it is considered that no programming phenomenon has occurred.
[0041] Specifically, the reading processes of the second data information and the first data information are the same, and the reading objects are the same. They respectively correspond to the twin byte data before and after the programming process. If no programming phenomenon has occurred, the two should maintain data consistency.
[0042] More specifically, if no programming phenomenon has occurred, the selected-gate shared split-gate flash memory can continue to execute subsequent operations normally. If a programming phenomenon has occurred, the selected-gate shared split-gate flash memory will perform relevant over-programming repair processing operations or generate relevant error messages to inform the user.
[0043] In some preferred embodiments, step S43 includes: S431. Screen and obtain the non-zero byte data in the first data information, and compare the non-zero byte data and the second data information bit by bit or byte by byte based on the byte address information. If they are the same, it is considered that no programming phenomenon has occurred.
[0044] Specifically, the byte data is 8-bit binary data. Therefore, the 0-byte data corresponds to 00000000, and the non-zero byte data is a combination form other than this data. If the data of a certain twin byte in the first data information is 0-byte data, no over-programming phenomenon will occur due to the programming process. Therefore, step S431 can skip the comparison process of these twin bytes, thereby improving the data comparison efficiency and effectively reducing the data analysis volume.
[0045] More specifically, the specific comparison method can use bit comparison or byte comparison, and the latter can further improve the comparison efficiency.
[0046] In some preferred embodiments, step S4 reads the second data information based on the first voltage, and the first voltage is less than the reference reading voltage.
[0047] Specifically, reading data based on the first voltage can read the data of the twin bit whose threshold voltage is critical to data 0 as data 0, and then regard the CELL that is at the over-programming critical point (about to possibly have an over-programming phenomenon) during this programming process as having had an over-programming phenomenon, thereby improving the reliability of the over-programming check in step S4 and ensuring the smooth progress of subsequent data reading processing.
[0048] In some preferred embodiments, the first voltage is 5 - 15% less than the reference reading voltage, preferably 10% less. The set value of this first voltage can ensure that step S4 can accurately analyze whether an over-programming phenomenon or a critical over-programming phenomenon has occurred in the previously executed programming process.
[0049] In some preferred embodiments, both the first buffer and the second buffer are static random access memories.
[0050] Specifically, the static random access memory, i.e., SRAM, is used for data caching. Based on SRAM for data caching, it can optimize the data processing and comparison efficiency of the select-gate shared split-gate flash memory, bringing significant advantages in terms of speed, lifespan, power consumption, reliability, and system design flexibility. It can effectively improve the real-time performance of data processing, ensure that the over-programming check process can be carried out efficiently, and does not affect the normal programming process.
[0051] Second, please refer to Figure 3 , some embodiments of the present application also provide a programming reliability checking device for a select-gate shared split-gate flash memory, which is used to perform an over-programming check on the split-gate storage structure in the programmed select-gate shared split-gate flash memory. The device includes: A first buffer module 201, configured to obtain the byte address information to be programmed and the corresponding data information to be programmed, and write them into the first buffer; A second buffer module 202, configured to extract first data information according to the byte address information and write the first data information into the second buffer. The first data information includes the data of the storage units corresponding to all the conducting control gates in the split-gate storage structure corresponding to the byte address information; A programming module 203, configured to perform a programming process on the split-gate storage structure according to the byte address information cached in the first buffer and the corresponding data information to be programmed; An inspection module 204, configured to read second data information according to the byte address information, and perform an over-programming check based on the consistency between the first data information and the second data information. The second data information includes the data of the storage units corresponding to all the conducting control gates in the programmed split-gate storage structure corresponding to the byte address information.
[0052] The programming reliability checking device for the select-gate shared split-gate flash memory according to the embodiments of the present application realizes the over-programming check on the storage units corresponding to the conducting control gates by using the second buffer to cache the first data information before the programming process and performing a consistency analysis with the second data information after the programming process. It can accurately analyze whether there is an over-programming problem in the floating-gate storage structure corresponding to the conducting control gate, which can be used as a basis for subsequent repair processing or inform the user, avoiding data read errors and improving the reliability of the operation of the select-gate shared split-gate flash memory.
[0053] In some preferred embodiments, the programming reliability checking device for the select-gate shared split-gate flash memory according to the embodiments of the present application is used to execute the programming reliability checking method for the select-gate shared split-gate flash memory provided in the first aspect above.
[0054] In a third aspect, some embodiments of the present application further provide a storage chip, including a Flash controller and a split-gate storage structure. The Flash controller is configured to execute the steps in the programming reliability checking method of the select-gate shared split-gate flash memory provided in the first aspect to program and check the split-gate storage structure.
[0055] In a fourth aspect, some embodiments of the present application further provide an electronic device, including the storage chip provided in the third aspect.
[0056] In the embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some communication interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical or other forms.
[0057] In addition, the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place, or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0058] Furthermore, in each embodiment of the present application, the various functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.
[0059] In this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
[0060] The above are only the embodiments of the present application and are not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A programming reliability checking method for a select-gate shared split-gate flash memory, which is used to perform over-programming checking on the split-gate storage structure in the programmed select-gate shared split-gate flash memory, characterized in that The method includes the following steps: S1. Obtain the byte address information to be programmed and the corresponding data information to be programmed, and write them into the first buffer; S2. Extract the first data information according to the byte address information, and write the first data information into the second buffer. The first data information includes the data of the storage units corresponding to all the conducting control gates corresponding to the byte address information in the split-gate memory structure; S3. Perform a programming process on the split-gate memory structure according to the byte address information cached in the first buffer and the corresponding data information to be programmed; S4. Read the second data information according to the byte address information, and perform an over-programming check based on the consistency between the first data information and the second data information. The second data information includes the data of the storage units corresponding to all the conducting control gates corresponding to the byte address information in the programmed split-gate memory structure.
2. The programming reliability checking method of the select-gate shared split-gate flash memory according to claim 1, characterized in that Step S2 includes: S21. Read the data of the split-gate memory structure according to the conducting control gate corresponding to the byte address information to obtain the first data information, and write the first data information into the second buffer.
3. The programming reliability checking method of the select-gate shared split-gate flash memory according to claim 1, wherein Step S3 includes: S31. Program the split-gate memory structure according to the address of the target control gate corresponding to the byte address information cached in the first buffer and the corresponding data information to be programmed.
4. The programming reliability checking method of the select-gate shared split-gate flash memory according to claim 1, wherein Step S4 includes: S41. Read the data of the programmed split-gate memory structure according to the conducting control gate corresponding to the byte address information to obtain the second data information; S42. Extract the first data information cached in the second buffer; S43. Compare the first data information and the second data information bit by bit based on the byte address information. If they are the same, it is considered that no over-programming phenomenon occurs.
5. The programming reliability checking method of the select-gate shared split-gate flash memory according to claim 4, characterized in that Step S43 includes: S431. Filter and obtain the non-0 byte data in the first data information, and compare the non-0 byte data and the second data information bit by bit or byte by byte based on the byte address information. If they are the same, it is considered that no over-programming phenomenon occurs.
6. The programming reliability checking method of the select-gate shared split-gate flash memory according to claim 1, wherein Step S4 reads the second data information based on a first voltage, and the first voltage is less than the reference read voltage.
7. The programming reliability checking method for the select-gate shared split-gate flash memory according to claim 6, wherein Both the first buffer and the second buffer are static random access memories.
8. A programming reliability checking device for a select-gate shared split-gate flash memory, which is used to perform over-programming checks on the split-gate memory structure in the programmed select-gate shared split-gate flash memory, and is characterized in that, The device includes: A first buffer module, configured to obtain the byte address information to be programmed and the corresponding data information to be programmed, and write them into the first buffer; A second buffer module, configured to extract the first data information according to the byte address information, and write the first data information into the second buffer. The first data information includes the data of the storage units corresponding to all the conducting control gates corresponding to the byte address information in the split-gate memory structure; A programming module, configured to perform a programming process on the split-gate memory structure according to the byte address information cached in the first buffer and the corresponding data information to be programmed; A checking module is configured to read second data information according to the byte address information, and perform a over-programming check based on the consistency between the first data information and the second data information. The second data information includes data of storage cells corresponding to all the turned-on control gates corresponding to the byte address information in the programmed split-gate memory structure.
9. A storage chip, characterized in that, It includes a Flash controller and a split-gate memory structure. The Flash controller is configured to execute the steps in the programming reliability checking method of the select-gate sharing type split-gate flash memory according to any one of claims 1-7 to program and check the split-gate memory structure.
10. An electronic device, characterized in that, It includes a storage chip as claimed in claim 9.