Memory test method and device, equipment and medium

Abstract

The embodiment of the invention provides a memory testing method and device, equipment and a medium, and the method comprises the steps: obtaining the write-in data and read-out data of a plurality of memory units, the write-in data of different memory units being the same, and the read-out data of different memory units being the read write-in data; according to the read data of the storage units included in the target storage unit group, a first test result of the target storage unit group is determined, and any storage unit group comprises a first storage unit and a second storage unit; determining a second test result of the storage units included in the target storage unit group according to the write-in data and the read data of the storage units included in the target storage unit group; according to the first test result of the target storage unit group and the second test result of the storage units included in the target storage unit group, the read-write states of the storage units included in the target storage unit group are determined, and the states of the write operation and the read operation of the two storage units included in each storage unit group are determined.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of memory technologies and related technologies. Specifically, it relates to a memory test method, apparatus, device, and medium. Background Art

[0002] With the rapid development of integrated circuits, the functions of chips are becoming increasingly complex. The test and verification work in chip design has become the most time-consuming work in the chip R & D process, and the proportion of the R & D cycle it occupies is getting larger and larger. The workload of verification has accounted for 65% to 70% of the entire chip R & D. In the process of verification, building a verification platform, debugging the verification platform, and waveform inspection work occupy a relatively large workload. Therefore, how to improve the efficiency of verification has become crucial.

[0003] In the prior art, most of them use a simple UVM verification platform to complete the construction of scenarios, generate simulation waveforms, and check the read and write operations of asynchronous memory chips by manually opening the waveforms to determine whether the read and write are correct. This method cannot implement the read and write check of all-address data of asynchronous memory chips, and can only randomly check whether the read and write data of some addresses in some scenarios are correct. Moreover, waveform inspection will consume a lot of time and there are situations of manual inspection errors. Summary of the Invention

[0004] Embodiments described herein provide a memory test method, apparatus, device, and medium, which solve the problems existing in the prior art.

[0005] In a first aspect, according to the content of the present disclosure, there is provided a memory test method, including: Obtaining write data and read data of multiple storage units, where the write data of different storage units is the same, and the read data of different storage units is the written data read; Determining a first test result of the target storage unit group according to the read data of the storage units included in the target storage unit group, where any storage unit group includes a first storage unit and a second storage unit; Determining a second test result of the storage units included in the target storage unit group according to the write data and read data of the storage units included in the target storage unit group; Determining the read and write status of the storage units included in the target storage unit group according to the first test result of the target storage unit group and the second test result of the storage units included in the target storage unit group.

[0006] In some embodiments of the present disclosure, the method further includes: Determining the read and write status of the memory according to the read and write status of the storage units included in different target storage unit groups.

[0007] Before determining the first test result of the target storage cell group based on the read data of the storage cells included in the target storage cell group in some embodiments of the present disclosure, the following steps are further included: Based on the storage cells included in the memory, multiple groups of storage cell groups are obtained by combining the storage cells in pairs.

[0008] In some embodiments of the present disclosure, determining the first test result of the target storage cell group based on the read data of the storage cells included in the target storage cell group includes: Obtain the first read data of the first storage cell included in the target storage cell group and the second read data of the second storage cell included in the target storage cell group; Compare the data of the same number of bits in the first read data and the second read data in sequence, and determine the first test result of the target storage cell group according to the comparison result of the data of the same number of bits in the first read data and the second read data.

[0009] In some embodiments of the present disclosure, determining the second test result of the storage cells included in the target storage cell group based on the write data and read data of the storage cells included in the target storage cell group includes: Obtain the first read data and first write data of the first storage cell included in the target storage cell group, and the second read data and second write data of the second storage cell included in the target storage cell group; Compare the data of the same number of bits in the first read data and the first write data in sequence, and determine the third test result of the first storage cell according to the comparison result of the data of the same number of bits in the first read data and the first write data; Compare the data of the same number of bits in the second read data and the second write data in sequence, and determine the fourth test result of the second storage cell according to the comparison result of the data of the same number of bits in the second read data and the second write data.

[0010] In some embodiments of the present disclosure, determining the read-write state of the storage cells included in the target storage cell group based on the first test result of the target storage cell group and the second test result of the storage cells included in the target storage cell group includes: When the second test results of the storage cells included in the target storage cell group are all low levels and the first test result of the target storage cell group is a low level, the read state and write state of the storage cells included in the target storage cell group are normal; When the first test result of the target memory cell group is at a high level, there is a read state abnormality or a write state abnormality in one of the memory cells included in the target memory cell group.

[0011] In some embodiments of the present disclosure, when the first test result of the target memory cell group is at a high level, there is a read state abnormality or a write state abnormality in one of the memory cells included in the target memory cell group, including: When the first test result of the target memory cell group is at a high level, if the third test results of the first memory cells included in the target memory cell group are all at a low level, and the fourth test results of the second memory cells included in the target memory cell group are all at a high level, then the read state of the second memory cells included in the target memory cell group is abnormal; When the first test result of the target memory cell group is at a high level, if the third test results of the first memory cells included in the target memory cell group are all at a high level, and the fourth test results of the second memory cells included in the target memory cell group are all at a low level, then the read state of the first memory cells included in the target memory cell group is abnormal; When the first test result of the target memory cell group is at a high level, if the third test results of the first memory cells included in the target memory cell group are all at a low level, and the fourth test results of the second memory cells included in the target memory cell group are all at a low level, then the write state of the first memory cells included in the target memory cell group is abnormal, or the write state of the second memory cells included in the target memory cell group is abnormal.

[0012] In a second aspect, according to the content of the present disclosure, a memory test device is provided, including: A data acquisition module, configured to acquire write data and read data of a plurality of memory cells, wherein the write data of different memory cells is the same, and the read data of different memory cells is the written data read; A first test result determination module, configured to determine a first test result of the target memory cell group according to the read data of the memory cells included in the target memory cell group, wherein any memory cell group includes a first memory cell and a second memory cell; A second test result determination module, configured to determine a second test result of the memory cells included in the target memory cell group according to the write data and the read data of the memory cells included in the target memory cell group; A read / write state determination module, configured to determine the read / write state of the memory cells included in the target memory cell group according to the first test result of the target memory cell group and the second test result of the memory cells included in the target memory cell group.

[0013] In a third aspect, according to the content of the present disclosure, a computer device is provided, including: One or more processors; A storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method described in any one of the first aspect.

[0014] In a fourth aspect, according to the content of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, the method described in any one of the first aspect is implemented.

[0015] The memory test method, device, equipment and medium provided by the embodiments of the present disclosure first obtain the written data and read data of multiple storage units, wherein the written data of different storage units is the same, and the read data of different storage units is the written data read; then determine the first test result of the target storage unit group according to the read data of the storage units included in the target storage unit group; and determine the second test result of the storage units included in the target storage unit group according to the written data and read data of the storage units included in the target storage unit group; finally, determine the read-write state of the storage units included in the target storage unit group according to the first test result of the target storage unit group and the second test result of the storage units included in the target storage unit group. Compared with the prior art that only compares the written data and read data of the storage units to determine whether there is an abnormality in the read operation of the storage units, the embodiments of the present disclosure write the test data stored in the register into different storage units, compare the read data of the storage unit group composed of any two storage units to obtain the first test result, and compare the written data and read data of the two storage units included in the storage unit group to obtain two second test results. Through the first test result and the second test result, the states of the write operation and read operation of the two storage units included in the storage unit group can be determined. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where: Figure 1 Is a flowchart of a memory test method provided by an embodiment of the present disclosure; Figure 2 Is a structural diagram of a memory test device provided by an embodiment of the present disclosure; Figure 3 Is a structural diagram of a computer device provided by an embodiment of the present disclosure. Detailed Embodiments

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts also fall within the scope of protection of the present disclosure.

[0018] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the subject matter of the present disclosure belongs. Further, it will be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless expressly defined otherwise herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0019] In all embodiments of the present disclosure, terms such as "first" and "second" are only used to distinguish one component (or a part of the component) from another component (or another part of the component).

[0020] Unless the context clearly indicates otherwise, the singular forms of the words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, it generally includes the plural of the corresponding term. Similarly, the phrases "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the terms "including" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used herein, especially when it is located after a group of terms, the said "example" is merely illustrative and explanatory, and should not be considered exclusive or extensive.

[0021] Based on the problems existing in the prior art, an embodiment of the present disclosure provides a memory testing method. Figure 1 is a schematic flowchart of a memory testing method provided by an embodiment of the present disclosure. As Figure 1 shown, the memory testing method includes: S110. Obtain the write data and read data of multiple storage units.

[0022] Among them, the write data of different storage units is the same, and the read data of different storage units is the written data read.

[0023] In a specific embodiment, when the memory is in the test mode, each memory cell performs a write operation to write the test data stored in the register, obtaining the written data. Then, each memory cell performs a read operation to read the written data, obtaining the read data.

[0024] In the prior art, only by comparing the written data and the read data of each memory cell, it is determined whether the read data is consistent with the written data, but it is impossible to determine whether the process of writing the written data is correctly written. Based on the problems existing in the prior art, in the memory test method provided by the embodiments of the present disclosure, first, the test data stored in the register is written into each memory cell. When there is no abnormality in the read operation of each memory cell, at this time, by comparing the read data of any two memory cells, it can be determined whether the write operation of each memory cell is abnormal.

[0025] Therefore, in the memory test method provided by the embodiments of the present disclosure, first, the written data and the read data of multiple memory cells are obtained, where the written data is the data obtained by writing the test data stored in the register into each memory cell based on the write operation of each memory cell, and the read data is the data obtained by reading the written data of each memory cell based on the read operation of each memory cell.

[0026] S120. Determine a first test result of the target memory cell group according to the read data of the memory cells included in the target memory cell group.

[0027] Wherein, any memory cell group includes a first memory cell and a second memory cell.

[0028] To determine whether there is an abnormality in the process of writing the written data of the memory, in the memory test method provided by the embodiments of the present disclosure, before performing step S120, it further includes: combining the memory cells included in the memory in two to obtain multiple memory cell groups.

[0029] In a specific embodiment, according to the memory cells included in the memory, the memory cells are combined in pairs to obtain multiple memory cell groups.

[0030] A specific and exemplary case is as follows. If the number of storage units included in the memory is 8, namely storage unit 01, storage unit 02, storage unit 03, storage unit 04, storage unit 05, storage unit 06, storage unit 07, and storage unit 08, then storage unit 01 and storage unit 02 are combined to form the first storage unit group 001, storage unit 03 and storage unit 04 are combined to form the second storage unit group 002, storage unit 05 and storage unit 06 are combined to form the third storage unit group 003, and storage unit 07 and storage unit 08 are combined to form the fourth storage unit group 004. At this time, by comparing the read data of storage unit 01 and storage unit 02 in the first storage unit group 001, a first test result is obtained; by comparing the read data of storage unit 03 and storage unit 04 in the second storage unit group 002, a first test result is obtained; by comparing the read data of storage unit 05 and storage unit 06 in the third storage unit group 003, a first test result is obtained; and by comparing the read data of storage unit 07 and storage unit 08 in the fourth storage unit group 004, a first test result is obtained.

[0031] It should be noted that in the above embodiment, "exemplary" represents a combination method of storage unit groups. It can also be that storage unit 01 and storage unit 08 form a storage unit group, storage unit 02 and storage unit 07 form a storage unit group, storage unit 03 and storage unit 06 form a storage unit group, and storage unit 04 and storage unit 05 form a storage unit group. The embodiments of the present disclosure do not limit the specific combination method of storage unit groups.

[0032] As a specific implementable manner, determining the first test result of the target storage unit group according to the read data of the storage units included in the target storage unit group includes: obtaining the first read data of the first storage unit included in the target storage unit group and the second read data of the second storage unit included in the target storage unit group; sequentially comparing the data with the same number of bits in the first read data and the second read data, and determining the first test result of the target storage unit group according to the comparison results of the data with the same number of bits in the first read data and the second read data.

[0033] The following embodiments will be specifically described by taking the first storage unit included in the target storage unit group as storage unit 01 and the second storage unit included in the target storage unit group as storage unit 02 as an example.

[0034] First, obtain the first read data of storage unit 01 included in the target storage unit group and the second read data of storage unit 02 included in the target storage unit group. Specifically, by way of example, if the test data stored in the register is Testcode<7:0>, the first write data of storage unit 01 is Write1<7:0>, the first read data of storage unit 01 is Read1<7:0>, the second write data of storage unit 02 is Write2<7:0>, and the second read data of storage unit 02 is Read2<7:0>, if there is no abnormality in the process of storage unit 01 performing a read operation to read the first write data Write1<7:0> and there is no abnormality in the process of storage unit 02 performing a read operation to read the second write data Write2<7:0>, then based on the first test result determined by the first read data Read1<7:0> and the second read data Read2<7:0>, it can be determined whether there is an abnormality in the process of storage unit 01 performing a write operation to write the test data stored in the register into storage unit 01 and the process of storage unit 02 performing a write operation to write the test data stored in the register into storage unit 02.

[0035] In the process of the above embodiment, whether there is an abnormality in the process of storage unit 01 performing a read operation to read the first write data Write1<7:0> and whether there is an abnormality in the process of storage unit 02 performing a read operation to read the second write data Write2<7:0> can be determined based on step S130.

[0036] In a specific embodiment, both the first read data Read1<7:0> and the second read data Read2<7:0> are 8 bits. Compare the first bit data Read1<0> of the first read data with the first bit data Read2<0> of the second read data, compare the second bit data Read1<1> of the first read data with the second bit data Read2<1> of the second read data,...., compare the eighth bit data Read1<7> of the first read data with the eighth bit data Read2<7> of the second read data. When the first bit data Read1<0> of the first read data is the same as the first bit data Read2<0> of the second read data, the second bit data Read1<1> of the first read data is the same as the second bit data Read2<1> of the second read data,...., and the eighth bit data Read1<7> of the first read data is the same as the eighth bit data Read2<7> of the second read data, then there is no abnormality in the write operation and read operation of storage unit 01 and storage unit 02. When at least one group of the first read data and the second read data of a certain bit among the first bit data Read1<0> of the first read data and the first bit data Read2<0> of the second read data, the second bit data Read1<1> of the first read data and the second bit data Read2<1> of the second read data,...., the eighth bit data Read1<7> of the first read data and the eighth bit data Read2<7> of the second read data are different, then there may be an abnormality in the read operation or write operation of storage unit 01, or there may be an abnormality in the read operation or write operation of storage unit 02.

[0037] It should be noted that in the above embodiment, when the first read data Read1<7:0> of storage unit 01 is the same as the second read data Read2<7:0> of storage unit 02, the first test result of storage unit group 001 where storage unit 01 and storage unit 02 are located is at a low level. When at least one group of the first read data and the second read data of a certain bit among the first read data Read1<7:0> of storage unit 01 and the second read data Read2<7:0> of storage unit 02 are different, the first test result of storage unit group 001 where storage unit 01 and storage unit 02 are located is at a high level.

[0038] S130. Determine the second test result of the storage units included in the target storage unit group according to the write data and read data of the storage units included in the target storage unit group.

[0039] In a specific embodiment, determining a second test result of the storage units included in the target storage unit group according to the written data and read data of the storage units included in the target storage unit group includes: obtaining first read data and first written data of a first storage unit included in the target storage unit group, and second read data and second written data of a second storage unit included in the target storage unit group; sequentially comparing the data of the same bit positions in the first read data and the first written data, and determining a third test result of the first storage unit according to the comparison result of the data of the same bit positions in the first read data and the first written data; sequentially comparing the data of the same bit positions in the second read data and the second written data, and determining a fourth test result of the second storage unit according to the comparison result of the data of the same bit positions in the second read data and the second written data.

[0040] In a specific embodiment, both the first read data Read1<7:0> and the first written data Write1<7:0> are 8 bits. Compare the first bit data Read1<0> of the first read data with the first bit data Write1<0> of the first written data, compare the second bit data Read1<1> of the first read data with the second bit data Write1<1> of the first written data,..., compare the eighth bit data Read1<7> of the first read data with the eighth bit data Write1<7> of the first written data. If the first bit data Read1<0> of the first read data is the same as the first bit data Write1<0> of the first written data, the second bit data Read1<1> of the first read data is the same as the second bit data Write1<1> of the first written data,..., and the eighth bit data Read1<7> of the first read data is the same as the eighth bit data Write1<7> of the first written data, then the read operation of storage unit 01 is normal. If there is at least one group of the first read data and the first written data of a certain bit that are different among the first bit data Read1<0> of the first read data and the first bit data Write1<0> of the first written data, the second bit data Read1<1> of the first read data and the second bit data Write1<1> of the first written data,..., and the eighth bit data Read1<7> of the first read data and the eighth bit data Write1<7> of the first written data, then the read operation of storage unit 01 is abnormal.

[0041] Similarly, both the second read data Read2<7:0> and the second write data Write2<7:0> are 8 bits. Compare the first bit data Read2<0> of the second read data with the first bit data Write2<0> of the second write data, compare the second bit data Read2<1> of the second read data with the second bit data Write2<1> of the second write data,...., compare the eighth bit data Read2<7> of the second read data with the eighth bit data Write2<7> of the second write data. If the first bit data Read2<0> of the second read data is the same as the first bit data Write2<0> of the second write data, the second bit data Read2<1> of the second read data is the same as the second bit data Write2<1> of the second write data,...., and the eighth bit data Read2<7> of the second read data is the same as the eighth bit data Write2<7> of the second write data, then the read operation of memory cell 01 is normal. If there is at least one group where the second read data and the second write data of a certain bit among the first bit data Read2<0> of the second read data and the first bit data Write2<0> of the second write data, the second bit data Read2<1> of the second read data and the second bit data Write2<1> of the second write data,...., the eighth bit data Read2<7> of the second read data and the eighth bit data Write2<7> of the second write data are different, then the read operation of memory cell 02 is abnormal.

[0042] It should be noted that in the above embodiment, when the first read data Read1<7:0> of memory cell 01 is the same as the first write data Write1<7:0> of memory cell 01, the third test result of memory cell 01 is low level. When the second read data Read2<7:0> of memory cell 02 is the same as the second write data Write2<7:0> of memory cell 02, the fourth test result of memory cell 02 is low level.

[0043] If there is at least one group where the first read data and the first write data of a certain bit among the first read data Read1<7:0> of memory cell 01 and the first write data Write1<7:0> of memory cell 01 are different, the third test result of memory cell 01 is high level. If there is at least one group where the second read data and the second write data of a certain bit among the second read data Read2<7:0> of memory cell 02 and the second write data Write2<7:0> of memory cell 02 are different, the fourth test result of memory cell 02 is high level.

[0044] By comparing the written data and the read data of the same storage unit, it can be determined whether the written data and the read data are consistent. If the written data and the read data are inconsistent, there is an abnormality in the read operation of the storage unit. If the written data and the read data are consistent, there is no abnormality in the read operation of the storage unit.

[0045] S140. Determine the read-write status of the storage units included in the target storage unit group according to the first test result of the target storage unit group and the second test result of the storage units included in the target storage unit group.

[0046] In a specific implementation manner, determining the read-write status of the storage units included in the target storage unit group according to the first test result of the target storage unit group and the second test result of the storage units included in the target storage unit group includes: when the second test results of the storage units included in the target storage unit group are all low levels and the first test result of the target storage unit group is a low level, the read status and the write status of the storage units included in the target storage unit group are normal; when the first test result of the target storage unit group is a high level, there is an abnormality in the read status or the write status of one of the storage units included in the target storage unit group.

[0047] Since comparing the written data and the read data of the storage unit can only determine whether there is an abnormality in the read operation of the storage unit, when there is an abnormality in the write operation of the storage unit, it cannot be judged only by comparing the written data and the read data of the storage unit. Therefore, in the embodiments of the present disclosure, the test data stored in the register is written into different storage units, the read data of two storage units in the same storage unit group is compared to obtain the first test result, and the written data and the read data of two storage units included in the storage unit group are compared to obtain two second test results. Finally, through the first test result and the second test result, the states of the read operation and the write operation of the two storage units included in the storage unit group can be determined.

[0048] An exemplary target storage cell group includes a first storage cell as storage cell 01 and a second storage cell as storage cell 02. If the third test result based on the first write data and the first read data of storage cell 01 is a low level, the fourth test result based on the second write data and the second read data of storage cell 02 is a low level, and the first test result based on the first read data of storage cell 01 and the second read data of storage cell 02 in the target storage cell group is a low level, then there is no abnormality in the read and write operations of storage cell 01, and there is no abnormality in the read and write operations of storage cell 02; if the first test result based on the first read data of storage cell 01 and the second read data of storage cell 02 in the target storage cell group is a high level, the third test result based on the first write data and the first read data of storage cell 01 is a high level, and the fourth test result based on the second write data and the second read data of storage cell 02 is a low level, then there is an abnormality in the read operation of storage cell 01. If the first test result based on the first read data of storage cell 01 and the second read data of storage cell 02 in the target storage cell group is a high level, the third test result based on the first write data and the first read data of storage cell 01 is a low level, and the fourth test result based on the second write data and the second read data of storage cell 02 is a high level, then there is an abnormality in the read operation of storage cell 02. If the first test result based on the first read data of storage cell 01 and the second read data of storage cell 02 in the target storage cell group is a high level, the third test result based on the first write data and the first read data of storage cell 01 is a low level, and the fourth test result based on the second write data and the second read data of storage cell 02 is a low level, then there is an abnormality in the write operation of storage cell 01 or storage cell 02.

[0049] The memory test method provided by the embodiments of the present disclosure first obtains the write data and read data of multiple memory cells. Among them, the write data of different memory cells is the same, and the read data of different memory cells is the read write data. Then, according to the read data of the memory cells included in the target memory cell group, the first test result of the target memory cell group is determined. And according to the write data and read data of the memory cells included in the target memory cell group, the second test result of the memory cells included in the target memory cell group is determined. Finally, according to the first test result of the target memory cell group and the second test result of the memory cells included in the target memory cell group, the read-write state of the memory cells included in the target memory cell group is determined. Compared with the prior art that only compares the write data and read data of memory cells to determine whether there is an abnormality in the read operation of memory cells, in the embodiments of the present disclosure, the test data stored in the register is written into different memory cells, and the read data of any memory cell group composed of two memory cells is compared to obtain the first test result, and the write data and read data of the two memory cells included in the memory cell group are compared to obtain two second test results. Through the first test result and the second test result, the states of the write operation and read operation of the two memory cells included in the memory cell group can be determined.

[0050] Based on the above embodiments, the embodiments of the present disclosure further provide a memory test device. Figure 2 It is a schematic structural diagram of a memory test device provided by the embodiments of the present disclosure. As Figure 2 shown, the memory test device includes: A data acquisition module 210, configured to acquire the write data and read data of multiple memory cells. Among them, the write data of different memory cells is the same, and the read data of different memory cells is the read write data. A first test result determination module 220, configured to determine the first test result of the target memory cell group according to the read data of the memory cells included in the target memory cell group, where any memory cell group includes a first memory cell and a second memory cell. A second test result determination module 230, configured to determine the second test result of the memory cells included in the target memory cell group according to the write data and read data of the memory cells included in the target memory cell group. A read-write state determination module 240, configured to determine the read-write state of the memory cells included in the target memory cell group according to the first test result of the target memory cell group and the second test result of the memory cells included in the target memory cell group.

[0051] The memory test device provided by the embodiments of the present disclosure first obtains the write data and read data of multiple memory cells. Among them, the write data of different memory cells is the same, and the read data of different memory cells is the read write data. Then, according to the read data of the memory cells included in the target memory cell group, the first test result of the target memory cell group is determined. And according to the write data and read data of the memory cells included in the target memory cell group, the second test result of the memory cells included in the target memory cell group is determined. Finally, according to the first test result of the target memory cell group and the second test result of the memory cells included in the target memory cell group, the read-write state of the memory cells included in the target memory cell group is determined. Compared with the prior art that only compares the write data and read data of the memory cells to determine whether there is an abnormality in the read operation of the memory cells, the embodiments of the present disclosure write the test data stored in the register into different memory cells, compare the read data of any two memory cell groups formed by the memory cells to obtain the first test result, and compare the write data and read data of the two memory cells included in the memory cell group to obtain two second test results. Through the first test result and the second test result, the states of the write operation and read operation of the two memory cells included in the memory cell group can be determined.

[0052] In a specific implementation manner, the method further includes: Determine the read-write state of the memory according to the read-write states of the memory cells included in different target memory cell groups.

[0053] Before determining the first test result of the target memory cell group according to the read data of the memory cells included in the target memory cell group, the method further includes: Pairwise combine the memory cells according to the memory cells included in the memory to obtain multiple groups of memory cell groups.

[0054] In a specific implementation manner, determining the first test result of the target memory cell group according to the read data of the memory cells included in the target memory cell group includes: Obtain the first read data of the first memory cell included in the target memory cell group and the second read data of the second memory cell included in the target memory cell group; Compare the data of the same number of bits in the first read data and the second read data in sequence, and determine the first test result of the target memory cell group according to the comparison result of the data of the same number of bits in the first read data and the second read data.

[0055] In a specific implementation manner, determining the second test result of the memory cells included in the target memory cell group according to the write data and read data of the memory cells included in the target memory cell group includes: Obtain the first read data and the first write data of the first storage unit included in the target storage unit group, and the second read data and the second write data of the second storage unit included in the target storage unit group; Compare the data of the same bit positions in the first read data and the first write data in sequence, and determine the third test result of the first storage unit according to the comparison result of the data of the same bit positions in the first read data and the first write data; Compare the data of the same bit positions in the second read data and the second write data in sequence, and determine the fourth test result of the second storage unit according to the comparison result of the data of the same bit positions in the second read data and the second write data.

[0056] In a specific embodiment, the determining the read-write state of the storage units included in the target storage unit group according to the first test result of the target storage unit group and the second test results of the storage units included in the target storage unit group includes: When the second test results of the storage units included in the target storage unit group are all low level, and the first test result of the target storage unit group is low level, the read state and the write state of the storage units included in the target storage unit group are normal; When the first test result of the target storage unit group is high level, there is an abnormal read state or an abnormal write state in one of the storage units included in the target storage unit group.

[0057] In a specific embodiment, the when the first test result of the target storage unit group is high level, there is an abnormal read state or an abnormal write state in one of the storage units included in the target storage unit group includes: When the first test result of the target storage unit group is high level, if the third test results of the first storage unit included in the target storage unit group are all low level, and the fourth test results of the second storage unit included in the target storage unit group are all high level, the read state of the second storage unit included in the target storage unit group is abnormal; When the first test result of the target storage unit group is high level, if the third test results of the first storage unit included in the target storage unit group are all high level, and the fourth test results of the second storage unit included in the target storage unit group are all low level, the read state of the first storage unit included in the target storage unit group is abnormal; When the first test result of the target storage unit group is at a high level, if the third test results of the first storage units included in the target storage unit group are all at a low level, and the fourth test results of the second storage units included in the target storage unit group are all at a low level, then the write state of the first storage units included in the target storage unit group is abnormal, or the write state of the second storage units is abnormal.

[0058] The embodiments of the present application further provide a computer device. For details, please refer to Figure 3 , Figure 3 which is the basic structural block diagram of the computer device in this embodiment.

[0059] The computer device includes a memory 510 and a processor 520 that communicate with each other through a system bus. It should be noted that only the computer device with components 510-520 is shown in the figure. However, it should be understood that it is not required to implement all the shown components, and more or fewer components can be alternatively implemented. Among them, those skilled in the art of the present technology can understand that the computer device here is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0060] The computer device can be a desktop computer, a notebook, a palm computer, a cloud server and other computing devices. The computer device can perform human-computer interaction with users through a keyboard, a mouse, a remote control, a touchpad or a voice control device and other means.

[0061] The memory 510 includes at least one type of readable storage medium, which includes non-volatile memory or volatile memory, such as flash memory, hard disk, multimedia card, card-type memory (such as SD or DX memory, etc.), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disc, etc. The RAM may include static RAM or dynamic RAM. In some embodiments, the memory 510 may be an internal storage unit of the computer device, such as the hard disk or memory of the computer device. In other embodiments, the memory 510 may also be an external storage device of the computer device, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the computer device. Of course, the memory 510 may also include both the internal storage unit and the external storage device of the computer device. In this embodiment, the memory 510 is generally used to store the operating system and various application software installed on the computer device, such as the program code of the above method. In addition, the memory 510 may also be used to temporarily store various data that have been output or will be output.

[0062] The processor 520 is generally used to execute the overall operations of the computer device. In this embodiment, the memory 510 is used to store program code or instructions, and the program code includes computer operation instructions. The processor 520 is used to execute the program code or instructions stored in the memory 510 or process data, such as running the program code of the above method.

[0063] In this text, the bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. This bus system can be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience in representation, only a thick line is used in the figure to represent it, but it does not mean that there is only one bus or one type of bus.

[0064] Another embodiment of the present application further provides a computer-readable medium, which can be a computer-readable signal medium or a computer-readable storage medium. A processor in the computer reads the computer-readable program code stored in the computer-readable medium, enabling the processor to execute the functional actions specified in each step or the combination of steps in the above method; and generating a device for implementing the functional actions specified in each block or the combination of blocks in the block diagram.

[0065] The computer-readable medium includes but is not limited to electronic, magnetic, optical, electromagnetic, infrared memories or semiconductor systems, devices or apparatuses, or any suitable combination of the foregoing. The memory is used to store program code or instructions, and the program code includes computer operation instructions. The processor is used to execute the program code or instructions of the above method stored in the memory.

[0066] For the definitions of the memory and the processor, reference can be made to the description of the foregoing computer device embodiments, which will not be elaborated herein.

[0067] In several embodiments provided by the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical, mechanical or other form.

[0068] In each embodiment of the present application, each functional unit or module can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0069] When an integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks, or optical discs that can store program codes.

[0070] Unless the context clearly indicates otherwise, the singular forms of words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the corresponding plural term is usually included. Similarly, the terms "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the term "including" and "or" should be interpreted as inclusive, unless such an interpretation is explicitly prohibited in this specification. Where the term "exemplary" is used in this specification, particularly when it is located after a group of terms, the "exemplary" is merely illustrative and explanatory and should not be considered exclusive or extensive.

[0071] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that the various aspects of this application can be implemented alone or in combination with one or more other aspects. It should also be understood that the description herein and the specific embodiments are for illustrative purposes only and are not intended to limit the scope of this application.

[0072] The above has described several embodiments of the present disclosure in detail. However, obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A memory test method, characterized in that, Including: Obtain the write data and read data of multiple storage units, wherein the write data of different storage units is the same, and the read data of different storage units is the read write data; Determine the first test result of the target storage unit group according to the read data of the storage units included in the target storage unit group, wherein any storage unit group includes a first storage unit and a second storage unit; Determine the second test result of the storage units included in the target storage unit group according to the write data and read data of the storage units included in the target storage unit group; Determine the read / write status of the storage units included in the target storage unit group according to the first test result of the target storage unit group and the second test result of the storage units included in the target storage unit group.

2. The method according to claim 1, wherein The method further includes: Determine the read / write status of the memory according to the read / write status of the storage units included in different target storage unit groups.

3. The method according to claim 1, wherein Before determining the first test result of the target storage unit group according to the read data of the storage units included in the target storage unit group, it further includes: Perform pairwise combination of the storage units according to the storage units included in the memory to obtain multiple groups of storage unit groups.

4. The method according to claim 1, wherein The determining the first test result of the target storage unit group according to the read data of the storage units included in the target storage unit group includes: Obtain the first read data of the first storage unit included in the target storage unit group and the second read data of the second storage unit included in the target storage unit group; Compare the data of the same bits in the first read data and the second read data in sequence, and determine the first test result of the target storage unit group according to the comparison result of the data of the same bits in the first read data and the second read data.

5. The method according to claim 1, wherein The determining the second test result of the storage units included in the target storage unit group according to the write data and read data of the storage units included in the target storage unit group includes: Obtain the first read data and first write data of the first storage unit included in the target storage unit group, and the second read data and second write data of the second storage unit included in the target storage unit group; Compare the data of the same bits in the first read data and the first write data in sequence, and determine the third test result of the first storage unit according to the comparison result of the data of the same bits in the first read data and the first write data; Compare the data of the same bits in the second read data and the second write data in sequence, and determine the fourth test result of the second storage unit according to the comparison result of the data of the same bits in the second read data and the second write data.

6. The method according to claim 1, wherein The determining the read / write status of the storage units included in the target storage unit group according to the first test result of the target storage unit group and the second test result of the storage units included in the target storage unit group includes: When the second test results of the storage units included in the target storage unit group are all low levels, and the first test result of the target storage unit group is a low level, the read status and write status of the storage units included in the target storage unit group are normal; When the first test result of the target storage unit group is a high level, there is a storage unit with an abnormal read status or an abnormal write status among the storage units included in the target storage unit group.

7. The method according to claim 6, characterized in that, When the first test result of the target storage unit group is a high level, there is a storage unit with an abnormal read status or an abnormal write status among the storage units included in the target storage unit group, including: When the first test result of the target storage unit group is a high level, if the third test results of the first storage units included in the target storage unit group are all low levels, and the fourth test results of the second storage units included in the target storage unit group are all high levels, the read status of the second storage units included in the target storage unit group is abnormal; When the first test result of the target storage unit group is a high level, if the third test results of the first storage units included in the target storage unit group are all high levels, and the fourth test results of the second storage units included in the target storage unit group are all low levels, the read status of the first storage units included in the target storage unit group is abnormal; When the first test result of the target storage unit group is a high level, if the third test results of the first storage units included in the target storage unit group are all low levels, and the fourth test results of the second storage units included in the target storage unit group are all low levels, the write status of the first storage units included in the target storage unit group is abnormal, or the write status of the second storage units is abnormal.

8. A memory test device, characterized in that, Including: A data acquisition module, configured to acquire the written data and read data of multiple storage units, wherein the written data of different storage units is the same, and the read data of different storage units is the written data read; A first test result determination module, configured to determine the first test result of the target storage unit group according to the read data of the storage units included in the target storage unit group, wherein any storage unit group includes a first storage unit and a second storage unit; A second test result determination module, configured to determine the second test result of the storage units included in the target storage unit group according to the written data and read data of the storage units included in the target storage unit group; A read / write status determination module, configured to determine the read / write status of the storage units included in the target storage unit group according to the first test result of the target storage unit group and the second test result of the storage units included in the target storage unit group.

9. A computer device, characterized in that, Including: One or more processors; A storage device, configured to store one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, the method according to any one of claims 1 to 7 is implemented.

Images