Cathode electron source array structure and preparation method thereof

Abstract

The invention provides a cathode electron source array structure and a preparation method thereof, and relates to the field of electron sources. The method comprises the following steps: preparing a first electrode layer on an insulating substrate, wherein the first electrode layer is composed of a plurality of strip-shaped electrodes which are isolated from one another; forming a porous polycrystalline silicon layer on the first electrode layer, and passivating the porous polycrystalline silicon layer to form an electron emission layer; and preparing a second electrode layer which has the same structure as the first electrode layer and is arranged in a spatial crossing manner on the electron emission layer so as to realize addressing control. The controllable field electron emission is realized through the accurate array electrode design, the simple addressing mode is realized through the unique cross electrode structure design, the complex independent wiring problem is avoided, and the high-density integration of the cathode source is facilitated.

Description

Technical Field

[0001] The present invention relates to the field of electron sources, and more specifically, to a cathode electron source array structure and a preparation method thereof. Background Art

[0002] Field Emission technology has important application value in the field of vacuum electronic devices of large-area addressable arrays due to its advantages such as instantaneous response characteristics and low power consumption. Typical application scenarios include X-ray sources, imaging detectors, terahertz devices, field emission displays (FEDs), and flat light sources, etc.

[0003] The key technology for the integration of field emitter arrays lies in the patterned preparation of emitter materials using matrix addressing methods. Although traditional processes such as nanoimprinting, nanosphere lithography, and photolithography technology have been applied, their inherent defects such as high energy consumption, high pollution, and high cost have restricted the further development of this technology.

[0004] The Spindt-type cathode source based on micro-electro-mechanical system (MEMS) processing technology is another representative cathode source array. As the first thin-film metal field emission cathode prepared using modern microfabrication technology, the Spindt-type cathode source consists of micron-scale emission tips, insulating layers, and gates to form an array structure. Its working principle relies on the nano-scale curvature radius of the microtips and the micro-spacing characteristics between the tips and the gates, and can achieve significant field-induced electron emission at a relatively low bias voltage. High-density tip array integration can be achieved through micro-nano processing technology, thereby obtaining a higher total emission current and current density.

[0005] However, for the above Spindt-type cathode source, its three-dimensional structure faces the problem of precise control of key parameters such as tip morphology and electrode position in the multi-layer deposition process, resulting in insufficient array uniformity and easily causing device failure problems such as local arc discharge, and the non-uniformity increases significantly with the increase of the array size.

[0006] In addition, as a typical external field emission source, the Spindt cathode has strict requirements for the working vacuum degree (10 -9 Torr). As an alternative, the carbon nanotube (CNTs) field emission cathode can achieve the cathode function without constructing a tip structure. Compared with the Spindt cathode, the carbon nanotube field emission cathode requires a lower driving voltage, but still faces technical bottlenecks such as high vacuum dependence and environmental sensitivity.

[0007] During the long-term working process, the deterioration of the vacuum condition will trigger the synergistic effect of electron / ion bombardment and thermal effect, resulting in the accumulation of CNTs structural defects until the function completely fails, and finally causing the irreversible decline of the field emission performance. This failure mechanism seriously restricts the lifespan and practical application reliability of the CNTs cathode array. Summary of the Invention

[0008] In view of the above problems, the present invention provides a cathode electron source array structure and a preparation method thereof.

[0009] On the one hand, the present invention provides a preparation method of a cathode electron source array structure, including: preparing a first electrode layer on an insulating substrate, the first electrode layer being composed of a plurality of mutually isolated strip electrodes; forming a porous polysilicon layer on the first electrode layer, and performing passivation treatment on the porous polysilicon layer to form an electron emission layer; preparing a second electrode layer on the electron emission layer, which has the same structure as the first electrode layer and is arranged in a spatial cross pattern, so as to achieve addressing control. According to an embodiment of the present invention, a mask plate opposite to the required pattern of the first electrode layer is covered on the surface of the insulating substrate; deposition is performed above the mask plate to obtain a metal layer with the same thickness as required for the first electrode layer; the mask plate is removed to obtain the first electrode layer. According to an embodiment of the present invention, photolithography treatment is performed on the surface of the insulating substrate, and the surface of the treated insulating substrate has a photoresist opposite to the required pattern of the first electrode layer; deposition is performed above the photoresist to obtain a metal layer with the same thickness as required for the first electrode layer; the photoresist is removed to obtain the first electrode layer. According to an embodiment of the present invention, the insulating substrate is one of silicon-based epitaxial silicon oxide, silicon-based epitaxial silicon nitride, thermal silicon oxide, high-resistance silicon, high-resistance germanium or organic glass.

[0010] According to an embodiment of the present invention, after deposition treatment above the first electrode layer, a polysilicon layer or an amorphous silicon layer is formed, and the amorphous silicon layer is crystallized to form a polysilicon layer; the polysilicon layer is subjected to structure treatment to form a porous polysilicon layer, and the structure treatment is one or a combination of anodic oxidation method, photochemical etching method, galvanic corrosion method, hydrothermal corrosion method or spark discharge method.

[0011] According to an embodiment of the present invention, the deposition treatment includes physical vapor deposition or chemical vapor deposition.

[0012] According to an embodiment of the present invention, the crystallization treatment is one or a combination of metal-induced crystallization, liquid-phase epitaxial crystallization, solid-phase crystallization, zone melting recrystallization, laser crystallization.

[0013] According to an embodiment of the present invention, annealing treatment is adopted, and the annealing treatment is one or a combination of rapid thermal annealing treatment, excimer laser annealing treatment or flash lamp annealing treatment.

[0014] According to an embodiment of the present invention, the passivation treatment is one or a combination of more of electrochemical oxidation, rapid thermal oxidation, or high-temperature steam oxidation.

[0015] On the other hand, the present invention provides a cathode electron source array structure, including: an insulating substrate, a first electrode layer, an electron emission layer, and a second electrode layer stacked in sequence, wherein: the first electrode layer and the second electrode layer are respectively composed of a plurality of mutually isolated strip electrodes, and the second electrode layer is arranged in a spatial cross pattern with the first electrode layer.

[0016] The cathode electron source array structure and its preparation method provided by the present invention can achieve the following beneficial effects:

[0017] (1) By adopting a preparation method compatible with standard semiconductor processes, the limitation of the substrate size by traditional electron sources is broken through, and large-area uniform preparation of the array structure can be realized;

[0018] (2) Based on the internal field emission characteristics, the working voltage of the porous polysilicon electron emission layer is significantly lower than that of traditional field emission cathode sources, and the emission performance is less affected by the external environment. Controllable field-induced electron emission is achieved through precise array electrode design.

[0019] (3) The unique cross-electrode structure design realizes a simple addressing method, avoids complex independent wiring problems, and is conducive to high-density integration of the cathode source;

[0020] (4) By optimizing the spatial arrangement of the surface electrode and the back electrode in the structure of the present invention, a local enhanced electric field is formed only in the overlapping area between the two, thereby inducing electron emission at specific positions. The overall preparation process of the present invention is compatible with existing silicon-based microfabrication technologies, has the characteristics of high yield and controllable cost, and at the same time its addressing drive control is more flexible. Description of the Drawings

[0021] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0022] Figure 1 Schematically shows a flowchart of a preparation method of a cathode electron source array structure according to an embodiment of the present invention;

[0023] Figure 2 Schematically shows a schematic diagram of a preparation method of a cathode electron source array structure according to an embodiment of the present invention.

[0024] Explanation of the Reference Numerals in the Drawings:

[0025] 100 - insulating substrate; 101 - first electrode layer; 102 - amorphous silicon layer; 103 - polysilicon layer; 104 - electron emission layer; 105 - second electrode layer. Detailed implementation manners

[0026] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In the following detailed description, for the sake of explanation, numerous specific details are set forth in order to provide a comprehensive understanding of the embodiments of the present invention. However, obviously, one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0027] The terms used herein are merely for describing specific embodiments and are not intended to limit the present invention. The terms "including", "comprising", etc. used herein indicate the presence of features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0028] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0029] In view of this, the present invention provides a cathode electron source array structure and a preparation method thereof.

[0030] Figure 1 A flowchart of a preparation method of a cathode electron source array structure according to an embodiment of the present invention is schematically shown.

[0031] As Figure 1 , according to the preparation method of the cathode electron source array structure of this embodiment, it may include step S1 to step S3.

[0032] In step S1, a first electrode layer 101 is prepared on an insulating substrate 100, and the first electrode layer 101 is composed of a plurality of mutually isolated strip electrodes.

[0033] For example, the insulating substrate 100 is selected from but not limited to at least one of silicon-based silicon oxide, silicon-based silicon nitride, thermally oxidized silicon, high-resistance silicon, or organic glass; wherein, the material type and thickness of the epitaxial insulating layer can be optimized and configured based on device electrical performance and process compatibility requirements.

[0034] The first electrode layer 101 is formed by magnetron sputtering, vacuum thermal evaporation, or electron beam evaporation processes; the implementation methods of its structure include: (a) covering the surface of the insulating substrate 100 with a mask plate having a pattern opposite to that of the first electrode layer 101, then depositing a target metal layer with the same thickness as required for the first electrode layer 101, forming the required metal pattern on the surface of the insulating substrate 100 under the blocking action of the mask plate, and finally removing the mask plate; (b) performing a photolithography process on the surface of the insulating substrate 100, retaining the photoresist opposite to the target metal pattern on the substrate surface, then depositing a metal layer, and finally removing the photoresist to form a patterned metal electrode. The geometric parameters (including shape, line width, spacing, and thickness) of the first electrode layer 101 can be adaptively designed according to the requirements of the electron emission region and array integration density.

[0035] In step S2, a porous polysilicon layer 103 is formed on the first electrode layer 101, and the porous polysilicon layer 103 is passivated to form an electron emission layer 104.

[0036] For example, the polysilicon layer 103 can be prepared by physical vapor deposition, including reactive sputtering, magnetron sputtering, pulsed laser deposition, or by chemical vapor deposition processes, including low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition.

[0037] For example, if the deposited silicon film is an amorphous silicon layer 102, it is transformed into a polysilicon layer 103 by one or a combination of metal-induced crystallization, liquid-phase epitaxy, solid-phase crystallization, and zone melting recrystallization.

[0038] For example, the polysilicon layer 103 is structurally processed to form porous polysilicon, and the structural processing method can include one or a combination of anodic oxidation, photochemical etching, galvanic corrosion, or hydrothermal corrosion methods to form a porous morphology with a specific pore structure.

[0039] For example, the above-mentioned porous polysilicon is passivated to form an electron emission layer 104, and the passivation treatment can adopt one or a combination of electrochemical oxidation, rapid thermal oxidation, or high-temperature steam oxidation processes.

[0040] For example, an annealing process in an inert atmosphere or vacuum environment can be combined to further reduce the interface defects of the porous polysilicon layer 103 and improve the film stability, and the annealing process includes one or a combination of rapid thermal annealing treatment, excimer laser annealing treatment, or flash lamp annealing treatment.

[0041] In step S3, a second electrode layer 105 having the same structure as the first electrode layer 101 and arranged in a spatially crossed manner is prepared on the electron emission layer 104.

[0042] Among them, the preparation process of the second electrode layer 105 can be the same as that of the first electrode layer 101. As an implementation manner, both the first electrode layer 101 and the second electrode layer 105 are composed of parallel discrete electrodes. The spatial arrangement angle between the second electrode layer 105 and the first electrode layer 101 can be adjusted within the range of 0° to 90°, such as a 90° orthogonal arrangement, and the two electrode layers are cross-set to achieve the matrix addressing function; as another implementation manner, the first electrode layer 101 is composed of a plurality of electrodes with radially equiangular distribution and electrical isolation, and the second electrode layer 105 is a concentric ring-shaped electrically isolated electrode that intersects with it. The geometric parameters of the two electrode layers (including shape, line width, spacing, and thickness) can be adaptively designed according to the electron emission region and array integration requirements.

[0043] Figure 2 Schematically shows the schematic diagram of the preparation method of the cathode electron source array structure according to an embodiment of the present invention.

[0044] Such as Figure 2 shown, in this embodiment, the specific process parameters need to be specifically optimized and adjusted according to the actual material system and target application scenario, specifically including step S1 1~ S31:

[0045] In step S11, select the insulating substrate 100.

[0046] Select 4-inch (100) crystal-oriented silicon-based silicon dioxide as the surface insulating substrate 100 (SiO2 / Si, oxide layer thickness 300 ), and perform wet cleaning and drying treatment on the above-mentioned silicon-based silicon dioxide substrate.

[0047] In step S12, form the patterned first electrode layer 101.

[0048] Adopt photolithography technology to form a photoresist pattern on the surface of the insulating substrate 100 that is opposite to the pattern of the first electrode layer 101, deposit a 100 thick nickel layer on the above-mentioned insulating substrate 100 by electron beam evaporation, and finally strip the photoresist by wet process to form the patterned first electrode layer 101.

[0049] In step S21, deposit the amorphous silicon layer 102.

[0050] Adopt a low-pressure chemical vapor deposition system (SiH4 flow rate 200 , pressure 300 , temperature 550 °C) to epitaxially grow a 3.0 thick amorphous silicon layer 102 on the surface of the first electrode layer 101.

[0051] Step S22, crystallize the amorphous silicon layer 102.

[0052] The above amorphous silicon layer 102 is irradiated by flash lamp annealing (pulse width 20 ), and is crystallized by solid-phase epitaxial crystallization to form a polysilicon layer 103 thereby.

[0053] Step S23: Form an electron emission layer 104.

[0054] The polysilicon layer 103 is subjected to photochemical etching treatment (HF / H2O2 / H2O = 1:1:10) to form porous polysilicon, and then high-temperature steam oxidation treatment is performed to form the required electron emission layer 104 thereby.

[0055] Step S31: Form a second electrode layer 105.

[0056] A photoresist pattern opposite to the pattern of the second electrode layer 105 is formed on the surface of the electron emission layer 104 by photolithography. High-purity gold is selected as the electrode material, and then electron beam evaporation is used with a deposition rate of 0.3 nm / s to deposit a 100 gold layer on the above photoresist surface, and finally the photoresist layer is removed by wet etching to form the patterned second electrode layer 105.

[0057] It should be noted that in order to ensure that the cathode electron source has excellent thermal stability and a high emission current density, the thickness of the amorphous silicon layer 102 is usually greater than 2 . However, due to the relatively shallow thermal penetration depth of traditional excimer laser annealing, it is difficult to achieve a complete crystallization transformation of such a thick amorphous silicon layer 102. Therefore, the present invention preferably uses a millisecond-level flash lamp annealing process for crystallization treatment. This technology has a deeper energy penetration depth and can achieve a uniform transformation of thick-layer amorphous silicon into polysilicon. Flash lamp annealing also has obvious advantages in mass production compared with traditional furnace annealing or laser annealing: First, the millisecond-level processing time is more than 1000 times faster than rapid thermal annealing (minute-level), which can greatly improve the production line efficiency; second, direct room temperature treatment or only low-temperature preheating is required, and the heating and cooling time of the traditional process can be saved; finally, large-area uniform irradiation can be achieved through a multi-lamp tube array design, which can meet wafer-level processing.

[0058] It should be noted that for the crystallization treatment of thin-layer amorphous silicon, when using the traditional rapid thermal annealing process, the substrate material and the characteristics of the bottom electrode layer need to be comprehensively considered. In order to prevent thermal damage to the substrate and the first electrode layer 101 during the high-temperature annealing process, the upper limit of the annealing temperature and the total thermal budget must be strictly controlled. In actual process design, the selection of the crystallization method and process parameters should be dynamically optimized according to the device structure characteristics and application requirements.

[0059] It should also be noted that the planar porous polysilicon electron source (PPS) is a cold cathode field emission electron source based on the internal field emission mechanism. The electron emission process is mainly driven by the strong internal electric field of the material and has the characteristics of quasi-ballistic transport. Among them, the PPS material is composed of a large number of interconnected nanocrystals (about 5 ), and after appropriate oxidation or passivation treatment, these nanocrystal networks will form effective electron acceleration microchannels. When a working voltage of dozens of volts is applied to the PPS layer, an internal built-in electric field of up to 10 5 V / cm magnitude will be generated inside it. This built-in electric field will significantly modulate the energy band structure of the porous polysilicon layer and induce a large number of hot electrons. These hot electrons will be effectively accelerated in the nanocrystal channels, and the electrons with energy exceeding the surface metal work function will pass through the surface electrode to form a field emission current. This PPS electron source based on internal field emission has a series of advantages such as low driving voltage, good electron emission collimation, and insensitivity to the atmosphere environment. At the same time, it also shows significant advantages in terms of emission efficiency, stability, and process compatibility, providing an important technical path for the development of new cold cathode devices.

[0060] In summary, the embodiments of the present invention provide a cathode electron source array structure and a preparation method thereof. Porous polysilicon is used as the electron emission functional layer, and combined with a precise array electrode design to achieve a high-performance controllable field-induced electron emission array. The technical advantages of this electron source array structure are reflected in the following aspects:

[0061] (1) Porous polysilicon is selected as the electron emission functional layer, and its unique porous nanocrystal structure can provide natural electron emission sites. After optimizing the key preparation process, this material will have excellent electron transport characteristics and good thermal stability, so it has a longer service life compared with traditional metal microtip arrays or planar CNT arrays.

[0062] (2) Adopt a "sandwich" type layered structure, including a substrate, a first electrode layer 101, an intermediate PPS functional layer, and a top second electrode layer 105. By precisely controlling the spatial arrangement of the surface electrode and the back electrode, a unique electric field modulation structure is constructed, and at the same time, the electrode patterning with micron-level accuracy is realized by using the lithography process to ensure the consistency of the array units.

[0063] (3) When an addressing driving voltage is applied, a local electric field is formed only in the overlapping area of the first electrode layer 101 and the second electrode layer 105. By adjusting the electrode spacing and the applied voltage waveform, the electron emission intensity and spatial distribution in the array structure can be precisely controlled. At the same time, a sub-region independent addressing driving design is adopted to flexibly realize the selective activation of the emission points.

[0064] Those skilled in the art can understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, without departing from the spirit and teachings of the present invention, the features described in the various embodiments of the present invention can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present invention.

[0065] The embodiments of the present invention have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although the embodiments have been described separately above, this does not mean that the measures in the respective embodiments cannot be used advantageously in combination. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present invention.

Claims

1. A preparation method of a cathode electron source array structure, characterized in that, Comprising: Preparing a first electrode layer on an insulating substrate, the first electrode layer being composed of a plurality of mutually isolated strip electrodes; Forming a porous polysilicon layer on the first electrode layer, and performing passivation treatment on the porous polysilicon layer to form an electron emission layer; Preparing a second electrode layer on the electron emission layer, which has the same structure as the first electrode layer and is arranged in a spatially crossed manner, to achieve addressing control.

2. The method according to claim 1, wherein, The step of preparing the first electrode layer on the insulating substrate, where the first electrode layer is composed of a plurality of mutually parallel and electrically isolated strip electrodes, includes: Covering a mask plate opposite to the pattern required for the first electrode layer on the surface of the insulating substrate; Performing deposition above the mask plate to obtain a metal layer with the same thickness as that required for the first electrode layer; Removing the mask plate to obtain the first electrode layer.

3. The method according to claim 1, wherein, The step of preparing the first electrode layer on the insulating substrate, where the first electrode layer is composed of a plurality of mutually isolated strip electrodes, further includes: Performing photolithography treatment on the surface of the insulating substrate; The surface of the treated insulating substrate has a photoresist opposite to the pattern required for the first electrode layer; Performing deposition above the photoresist to obtain a metal layer with the same thickness as that required for the first electrode layer; Removing the photoresist to obtain the first electrode layer.

4. The method according to claim 1, characterized in that, The insulating substrate is one of silicon-based epitaxial silicon oxide, silicon-based epitaxial silicon nitride, thermal silicon oxide, high-resistance silicon, high-resistance germanium, or polymethyl methacrylate.

5. The method according to claim 1, wherein, Forming a porous polysilicon layer on the first electrode layer includes: After performing deposition treatment above the first electrode layer, forming a polysilicon layer or an amorphous silicon layer, and performing crystallization treatment on the amorphous silicon layer to form the polysilicon layer; Performing structure treatment on the polysilicon layer to form a porous polysilicon layer, and the structure treatment is one or a combination of anodic oxidation method, photochemical etching method, galvanic corrosion method, hydrothermal corrosion method, or spark discharge method.

6. The method according to claim 5, wherein The deposition treatment includes physical vapor deposition or chemical vapor deposition.

7. The method according to claim 5, wherein The crystallization treatment is one or a combination of metal-induced crystallization, liquid-phase epitaxial crystallization, solid-phase crystallization, zone melting recrystallization, or laser crystallization.

8. The method according to claim 5, wherein, The step of performing crystallization treatment on the amorphous silicon layer to form the polysilicon layer further includes: adopting annealing treatment, and the annealing treatment is one or a combination of rapid thermal annealing treatment, excimer laser annealing treatment, or flash lamp annealing treatment.

9. The method according to claim 1, characterized in that The passivation treatment is one or a combination of electrochemical oxidation, rapid thermal oxidation, or high-temperature steam oxidation.

10. A cathode electron source array structure, characterized in that, Including an insulating substrate, a first electrode layer, an electron emission layer, and a second electrode layer stacked in sequence, where: The first electrode layer and the second electrode layer are respectively composed of a plurality of mutually isolated strip electrodes, and the second electrode layer is arranged in a spatially crossed manner with the first electrode layer.

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