Semiconductor element with catalytically conductive layer and method for manufacturing same

Abstract

The invention discloses a semiconductor element and a manufacturing method of the semiconductor element. The semiconductor device includes: a substrate; the nick is positioned in the substrate and comprises a bottom surface and two side walls; and a catalytic conductive layer on the bottom surface of the score. The bottom surface of the score is parallel to a top surface of the substrate. The two sidewalls of the score are substantially perpendicular.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 2024104686714, filed on April 18, 2024, with the invention title of "Semiconductor Element with Catalytic Conductive Layer and Method for Manufacturing the Same". Application No. 2024104686714 claims the priority and benefits of U.S. Provisional Application No. 18 / 401,760, filed on January 2, 2024, the content of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor element and a method for manufacturing the same. More particularly, the present disclosure relates to a semiconductor element with a catalytic conductive layer and a method for manufacturing the same. Background Art

[0003] Semiconductor elements are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor elements has been continuously shrinking to meet the increasing demand for computing power. However, during the process of size reduction, many problems have arisen and these problems are still increasing. Therefore, there are still challenges in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The discussion of the prior art paragraphs only provides background information. The statements in the discussion of the prior art paragraphs do not admit that the content disclosed in this paragraph constitutes the prior art of the present disclosure, and any part of the discussion in the prior art paragraphs shall not be used as an admission that any part of this application, including the part in the discussion of the prior art paragraphs, constitutes the prior art of the present disclosure. Summary of the Invention

[0005] One aspect of the present disclosure provides a semiconductor element, comprising: a substrate; a notch located within the substrate and including a bottom surface and two sidewalls; and a catalytic conductive layer located on the bottom surface of the notch. The bottom surface of the notch is parallel to a top surface of the substrate. The two sidewalls of the notch are substantially perpendicular.

[0006] Another aspect of the present disclosure provides a semiconductor element, comprising: a substrate; a first trench located within the substrate and including a bottom surface and two sidewalls; and a catalytic conductive layer located on the bottom surface of the first trench; wherein the bottom surface of the first trench is parallel to a top surface of the substrate. The two sidewalls of the first trench are substantially perpendicular. The depth-to-width ratio of the first trench is between about 4:1 and about 12:1.

[0007] Another aspect of the present disclosure provides a method of manufacturing a semiconductor device, comprising: providing a substrate; forming a catalytic conductive layer on the substrate; patterning the catalytic conductive layer to form an opening exposing an exposed portion of the substrate while leaving a covered portion of the substrate covered by the catalytic conductive layer; performing a trench etching process to recess the covered portion of the substrate to form a first trench; removing the catalytic conductive layer; and forming an isolation layer in the first trench.

[0008] Due to the design of the semiconductor device of the present disclosure, the trench etching process using this catalytic conductive layer does not generate a large amount of by-products. Therefore, this eliminates the need for a thorough post-cleaning process, thereby reducing the cost and complexity involved in manufacturing the semiconductor device.

[0009] The technical features and advantages of the present disclosure have been outlined quite extensively above, so that a better understanding of the following detailed description of the present disclosure can be obtained. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those of ordinary skill in the art to which the present disclosure pertains should understand that the concepts disclosed below and specific embodiments can be quite easily used as a basis for modifying or designing other structures or processes to achieve the same purpose as the present disclosure. Those of ordinary skill in the art to which the present disclosure pertains should also understand that such equivalent structures cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] When considering the embodiments and the claims in conjunction with the drawings, a more comprehensive understanding of the disclosure of the present application can be obtained. It should be noted that, in accordance with the standard industry practice, the features are not drawn to scale. For the sake of clarity in discussion, the dimensions of various features can be increased or decreased arbitrarily.

[0011] Figure 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0012] Figure 2 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure;

[0013] Figure 3 is a cross-sectional view illustrating a part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure taken along the cutting line A-A' in Figure 2 ;

[0014] Figure 4 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure;

[0015] Figure 5 is a cross-sectional view illustrating a part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure taken along the cutting line A-A' in Figure 4Part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along the cutting line A-A';

[0016] Figure 6 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure;

[0017] Figure 7 is a cross-sectional view illustrating Figure 6 Part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along the cutting line A-A';

[0018] Figure 8 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure;

[0019] Figure 9 is a cross-sectional view illustrating Figure 8 Part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along the cutting line A-A';

[0020] Figure 10 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure;

[0021] Figures 11 to 14 is a cross-sectional view illustrating Figure 10 Part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along the cutting line A-A';

[0022] Figure 15 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure;

[0023] Figure 16 is a cross-sectional view illustrating Figure 15 Part of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along the cutting line A-A';

[0024] Figure 17 and Figure 18 is a cross-sectional view illustrating part of the manufacturing process of a semiconductor device according to another embodiment of the present disclosure; and

[0025] Figure 19 is a cross-sectional view illustrating part of the manufacturing process of a semiconductor device according to another embodiment of the present disclosure.

[0026] Wherein, the reference numerals are explained as follows:

[0027] 1A: Semiconductor device

[0028] 1B: Semiconductor device

[0029] 1C: Semiconductor device

[0030] 10: Method

[0031] 101: Substrate

[0032] 101C: Covered Portion

[0033] 101E: Exposed Portion

[0034] 101P: Protruding Portion

[0035] 101TS: Top Surface

[0036] 103: Isolation Layer

[0037] 200: Catalytic Conductive Layer

[0038] 301: Isolation Material

[0039] 401: Liner

[0040] 401TS: Top Surface

[0041] 403: Liner Material

[0042] 801: Bottom Layer

[0043] 803: Hard Mask Layer

[0044] 805: Mask Layer

[0045] AA: Active Region

[0046] OP1: Opening

[0047] S11: Step

[0048] S13: Step

[0049] S15: Step

[0050] TR1: First Trench

[0051] TRB: Bottom Surface

[0052] TRS: Sidewall Detailed Implementation Manner

[0053] The present disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations described below simplify the present disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature above or on top of a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features are formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may reuse element symbols and / or letters in various examples. Such repetition is for simplicity and clarity purposes, and does not itself limit the relationship between the various embodiments and / or configurations being discussed.

[0054] Furthermore, for ease of description, spatially relative terms may be used herein, such as "below", "beneath", "lower", "above", "upper", or other similar terms, to describe the relative relationship of one element or feature shown in the drawings to another element or feature. In addition to the orientation depicted in the figures, the spatially relative terms are intended to encompass different orientations of the element during use or operation. This element may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0055] It should be understood that when a component or layer is referred to as "connected to" or "coupled to" another component or layer, it may be directly connected to or coupled to the other component or layer, or there may be intervening components or intervening layers.

[0056] It should be understood that although terms such as first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise specified, these terms are only used to distinguish one component from another. Thus, for example, a first component, first member, or first portion discussed below may be referred to as a second component, second member, or second portion without departing from the teachings of the present disclosure.

[0057] Unless otherwise indicated in the context, terms such as "same", "equal", "plane", or "coplanar" as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other metric when referring to orientation, layout, position, shape, size, quantity, or other metric, but are intended to cover orientations, layouts, positions, shapes, sizes, quantities, or other metrics that are nearly the same within an acceptable range of variations that may occur (e.g., due to the manufacturing process). The term "substantially" may be used herein to reflect this meaning. For example, an article described as "substantially the same", "substantially equal", or "substantially coplanar" may be exactly the same, equal, or coplanar, or may be nearly the same, equal, or coplanar within an acceptable range of variations that may occur (e.g., due to the manufacturing process).

[0058] In the present disclosure, a semiconductor element generally refers to an element that can operate using semiconductor characteristics, and electro-optic elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

[0059] It should be noted that in the description of the present disclosure, above (or upper) corresponds to the arrow direction in the Z direction, and below (or lower) corresponds to the opposite direction of the arrow in the Z direction.

[0060] Figure 1 is a flowchart illustrating a manufacturing method 10 of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 2 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figure 3 is a cross-sectional view illustrating a part of the manufacturing process of a semiconductor element 1A according to an embodiment of the present disclosure taken along the cutting line A-A' in Figure 2 .

[0061] See Figures 1 to 3 , in step S11, a substrate 101 may be provided, and a catalytic conductive layer 200 may be formed on the substrate 101.

[0062] See Figure 2 and Figure 3, in some embodiments, the substrate 101 can be formed of the following materials, such as: silicon, germanium, silicon germanium, silicon carbide, silicon carbide germanium, gallium, gallium arsenide, indium arsenide, indium phosphide, or other group IV-IV, III-V or II-VI semiconductor materials. In some embodiments, the substrate 101 can be formed of the following materials, such as: indium antimonide, gallium nitride, gallium phosphide, gallium antimonide, gallium arsenide phosphide, gallium arsenide nitride, indium gallium arsenide, indium gallium phosphide, aluminum gallium arsenide, aluminum gallium indium, aluminum gallium phosphide, aluminum gallium indium phosphide, indium gallium arsenide, indium gallium nitride, indium gallium phosphide, indium gallium antimonide, indium gallium arsenide antimonide, aluminum nitride, aluminum gallium nitride, zinc selenide, diamond (C) or gallium oxide (Ga2O3). In some embodiments, the substrate 101 can be doped with various types of dopants, such as but not limited to: boron, aluminum, gallium, indium, arsenic or phosphorus.

[0063] In some embodiments, the substrate 101 can include an organic semiconductor or a layered semiconductor, such as: silicon / silicon germanium, silicon on insulator or silicon germanium on insulator. When the substrate 101 is formed of silicon on insulator, the substrate 101 can include a top semiconductor layer and a bottom semiconductor layer formed of silicon, and a buried insulating layer that can separate the top semiconductor layer from the bottom semiconductor layer. This buried insulating layer can include, for example, crystalline or amorphous oxides, nitrides, or any combination of the above.

[0064] In some embodiments, the crystal orientation of the substrate 101 (or the top semiconductor layer) can be <100>, <110> or <111>. In this embodiment, the substrate 101 can be formed of silicon.

[0065] See Figure 2 and Figure 3 , a catalytic conductive layer 200 can be formed on the top surface 101TS of the substrate 101. At the current stage, the top surface 101TS can be completely covered by the catalytic conductive layer 200. In some embodiments, the catalytic conductive layer 200 can be formed of a noble metal such as silver or gold. In some embodiments, the catalytic conductive layer 200 can be formed of, for example, Schottky metals. In some embodiments, the catalytic conductive layer 200 can be formed of the following materials, such as: silver, gold, cobalt, chromium, copper, iron, hafnium, iridium, manganese, molybdenum, palladium, platinum, rubidium, rhenium, rhodium, tantalum, titanium, vanadium, tungsten, zinc or zirconium. In some embodiments, the catalytic conductive layer 200 can be formed of the following materials, such as: aluminum, titanium, nickel, iron, zinc, cadmium, indium, tin, antimony, tellurium, lead, bismuth, vanadium, chromium, manganese, ruthenium, molybdenum or other transition metals. In some embodiments, the catalytic conductive layer 200 can be formed of, for example, titanium nitride.

[0066] In some embodiments, the catalytic conductive layer 200 may be formed by, for example, sputtering, physical vapor deposition, electroplating, electroless plating, atomic layer deposition, or other suitable deposition processes. In some embodiments, the process pressure for depositing the catalytic conductive layer 200 may be between about 2 mTor and about 20 mTorr. In some embodiments, the process pressure for depositing the catalytic conductive layer 200 may be about 5 mTorr. In some embodiments, the thickness of the catalytic conductive layer 200 may be between about 1 nm and about 100 nm. In some embodiments, the thickness of the catalytic conductive layer 200 may be between about 2 nm and about 20 nm.

[0067] In some embodiments, a planarization process, such as chemical mechanical polishing, may be performed as needed to provide a substantially flat surface for subsequent process steps.

[0068] Figure 4 is a top view illustrating a semiconductor element at an intermediate stage of an embodiment of the present disclosure. Figure 5 is a cross-sectional view illustrating Figure 4 a part of the manufacturing process of the semiconductor element 1A of an embodiment of the present disclosure taken along the section line A-A' in Figure 6 is a top view illustrating a semiconductor element at an intermediate stage of an embodiment of the present disclosure. Figure 7 is a cross-sectional view illustrating Figure 6 a part of the manufacturing process of the semiconductor element 1A of an embodiment of the present disclosure taken along the section line A-A' in Figure 8 is a top view illustrating a semiconductor element at an intermediate stage of an embodiment of the present disclosure. Figure 9 is a cross-sectional view illustrating Figure 8 a part of the manufacturing process of the semiconductor element 1A of an embodiment of the present disclosure taken along the section line A-A' in

[0069] See Figure 1 and Figures 4 to 9 , in step S13, the catalytic conductive layer 200 may be patterned to expose a plurality of exposed portions 101E of the substrate 101 while leaving covered portions 101C of the substrate 101 that are still covered by the catalytic conductive layer 200.

[0070] See Figure 4 and Figure 5 , a bottom layer 801 may be formed on the catalytic conductive layer 200, a hard mask layer 803 may be formed on the bottom layer 801, and a mask layer 805 may be formed on the hard mask layer 803.

[0071] In some embodiments, the underlying layer 801 may include a self-planarizing material, such as spin-on glass or spin-on low-k dielectric material. The use of a self-planarizing dielectric material can obviate the need for subsequent planarization steps. In some embodiments, the underlying layer 801 may be configured as an anti-reflection layer. In some embodiments, the underlying layer 801 may be composed of a thin film structure of alternating layers having a contrasting refractive index. The thickness of the underlying layer 801 may be selected to produce destructive interference in the reflected light beam from the interface and constructive interference in the corresponding transmitted light beam. By way of example and not limitation, the underlying layer 801 may be formed of materials such as oxides, sulfides, fluorides, nitrides, selenides, or combinations thereof. In some embodiments, the underlying layer 801 may improve the resolution of the lithography process. In some embodiments, the underlying layer 801 may be formed by a deposition process, including, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, spin coating, or other suitable deposition processes.

[0072] In some embodiments, the hard mask layer 803 may be formed of materials such as boron nitride, silicon boron nitride, phosphorus boron nitride, or boroncarbon silicon nitride. In some embodiments, the hard mask layer 803 may be formed by, for example, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes. In some embodiments, the hard mask layer 803 may be formed by a film-forming process and a processing process. Specifically, in the film-forming process, a first precursor, which may be a boron-based precursor, may be introduced onto the catalytic conductive layer 200 to form a boron-based layer. Subsequently, in the processing process, a second precursor, which may be a nitrogen-based precursor, may be introduced to react with the boron-based layer to convert the boron-based layer into the hard mask layer 803.

[0073] In some embodiments, the first precursor may be, for example, diborane, borazine, or an alkyl-substituted derivative of borazine. In some embodiments, the first precursor may be introduced at a flow rate between about 5 sccm (standard cubic centimeters per minute) and about 50 slm (standard liters per minute) or between about 10 sccm and about 1 slm. In some embodiments, the first precursor may be introduced by a dilution gas, such as nitrogen, hydrogen, argon, or combinations thereof. The dilution gas may be introduced at a flow rate between about 5 sccm and about 50 slm or between about 1 slm and about 10 slm.

[0074] In some embodiments, the film forming process can be carried out without plasma assistance. In this case, the substrate temperature of the film forming process can be between about 100°C and about 1000°C. For example, the substrate temperature of the film forming process can be between about 300°C and about 500°C. The process pressure of the film forming process can be between about 10 mTor and about 760 Torr. For example, the process pressure of the film forming process can be between about 2 Torr and about 10 Torr.

[0075] In some embodiments, the film forming process can be carried out in the presence of plasma. In this case, the substrate temperature of the film forming process can be between about 100°C and about 1000°C. For example, the substrate temperature of the film forming process can be between about 300°C and about 500°C. The process pressure of the film forming process can be between about 10 mTor and about 760 Torr. For example, the process pressure of the film forming process can be between about 2 Torr and about 10 Torr. The plasma can be generated by a radio frequency (RF) power between 2 W and 5000 W. For example, the RF power can be between 30 W and 1000 W.

[0076] In some embodiments, the second precursor can be, for example, ammonia or hydrazine. In some embodiments, the second precursor can be introduced at a flow rate between about 5 sccm and about 50 slm or between about 10 sccm and about 1 slm.

[0077] In some embodiments, an oxygen-based precursor can be introduced together with the second precursor during the processing. The oxygen-based precursor can be, for example, oxygen, nitric oxide, nitrous oxide, carbon dioxide, or water.

[0078] In some embodiments, a silicon-based precursor can be introduced together with the second precursor during the processing. The silicon-based precursor can be, for example, silane, trimethylsilylamine, trimethylsilane, or silazane (such as hexamethylcyclotrisilazane).

[0079] In some embodiments, a phosphorus-based precursor can be introduced together with the second precursor during the processing. The phosphorus-based precursor can be, for example, phosphine.

[0080] In some embodiments, an oxygen-based precursor, a silicon-based precursor, or a phosphorus-based precursor can be introduced together with the second precursor during the processing.

[0081] In some embodiments, the processing process can be carried out with the assistance of a plasma process, a UV curing process, a thermal annealing process, or a combination thereof.

[0082] When the processing is carried out with the assistance of a plasma process, the plasma of the plasma process can be generated by RF power. In some embodiments, at a single low frequency between about 100 kHz and up to about 1 MHz, the RF power can be between about 2 W and about 5000 W. In some embodiments, at a single high frequency greater than about 13.6 MHz, the RF power can be between about 30 W and about 1000 W. In this case, the substrate temperature of the processing process can be between about 20 °C and about 1000 °C. The process pressure of the processing process can be between about 10 mTorr and about 760 Torr.

[0083] When the processing is carried out with the assistance of a UV curing process, in this case, the substrate temperature of the processing process can be between about 20 °C and about 1000 °C. The process pressure of the processing process can be between about 10 mTorr and about 760 Torr. The UV can be provided by any UV light source, such as a mercury microwave arc lamp, a pulsed xenon flash lamp, or a high-efficiency UV light-emitting diode array. The UV light source can have a wavelength between about 170 nm and about 400 nm. The UV light source provides photon energy between about 0.5 eV and about 10 eV, or between about 1 eV and about 6 eV. The assistance of the UV curing process can remove hydrogen from the hard mask layer 803. Since hydrogen may diffuse into other regions of the semiconductor element 1A and may reduce the reliability of the semiconductor element 1A, therefore, removing hydrogen with the assistance of the UV curing process can improve the reliability of the semiconductor element 1A. In addition, the UV curing process can increase the density of the hard mask layer 803.

[0084] When the processing is carried out with the assistance of a thermal annealing process, in this case, the substrate temperature of the processing process can be between about 20 °C and about 1000 °C. The process pressure of the processing process can be between about 10 mTorr and about 760 Torr.

[0085] In some embodiments, the hard mask layer 803 can be a carbon film. As used herein, the term "carbon film" is used to describe a material whose mass is mainly carbon, whose structure is mainly defined by carbon atoms, or whose physical and chemical properties are determined by its carbon content. The term "carbon film" is intended to exclude materials that simply contain carbon mixtures or compounds, such as dielectric materials, such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polysilicon. In some embodiments, the hard mask layer 803 can be composed of carbon and hydrogen. In some embodiments, the hard mask layer 803 can be composed of carbon, hydrogen, and oxygen. In some embodiments, the hard mask layer 803 can be composed of carbon, hydrogen, and fluorine.

[0086] In some embodiments, a carbon film may be deposited by a process including introducing a process gas mixture composed of one or more hydrocarbon compounds into a processing chamber. This hydrocarbon compound has the chemical formula C x H y , where x ranges from 2 to 4 and y ranges from 2 to 10. This hydrocarbon compound may be, for example, propylene, propyne, propane, butane, butene, butadiene, or acetylene or a combination thereof.

[0087] In some embodiments, the mask layer 805 may be a photoresist layer and may include a plurality of openings OP1. The plurality of openings OP1 may define the pattern of the mask layer 805.

[0088] See Figure 6 and Figure 7 , a hard mask etching process using the mask layer 805 as a photoresist may be performed to etch and remove a plurality of portions of the hard mask layer 803. After the hard mask etching process, the plurality of openings OP1 may be extended to reach the underlying layer 801, transferring the pattern from the mask layer 805 to the hard mask layer 803. This causes portions of the top surface of the underlying layer 801 to be exposed through the plurality of openings OP1. After transferring the pattern of the mask layer 805 to the hard mask layer 803, the mask layer 805 may be removed using an ashing process or other suitable semiconductor processes.

[0089] See Figure 8 and Figure 9 , a pattern etching process using the hard mask layer 803 as a photomask may be performed to remove a plurality of portions of the underlying layer 801 and the catalytic conductive layer 200. In some embodiments, the pattern etching process may be a multi-stage etching process, using different etching chemistries at different stages to selectively remove the target layers.

[0090] After the pattern etching process, the plurality of openings OP1 may extend to the substrate 101. Some portions of the top surface 101TS of the substrate 101 may be exposed through the plurality of openings OP1 and may be referred to as a plurality of exposed portions 101E of the substrate 101. At the same time, the remaining portions of the top surface 101TS of the substrate 101 that are still covered (or masked) by the catalytic conductive layer 200 may be referred to as the covered portions 101C of the substrate 101.

[0091] In some embodiments, the underlying layer 801 and the hard mask layer 803 may be used as needed. That is, the mask layer 805 may be formed directly on the catalytic conductive layer 200. The pattern of the mask layer 805 (i.e., the plurality of openings OP1) may be directly transferred to the catalytic conductive layer 200.

[0092] Figure 10is a top view illustrating a semiconductor device at an intermediate stage of an embodiment of the present disclosure. Figures 11 to 14 is a cross-sectional view illustrating Figure 10 a part of the manufacturing process of the semiconductor device 1A of an embodiment of the present disclosure taken along the cutting line A-A’ in Figure 15 is a top view illustrating a semiconductor device at an intermediate stage of an embodiment of the present disclosure. Figure 16 is a cross-sectional view illustrating Figure 15 a part of the manufacturing process of the semiconductor device 1A of an embodiment of the present disclosure taken along the cutting line A-A’ in

[0093] Refer to Figure 1 and Figures 10 to 16 , in step S15, the covered portion 101C can be recessed to form the first trench TR1, the catalytic conductive layer 200 can be removed, and the isolation layer 103 can be formed in the first trench TR1.

[0094] Refer to Figure 10 and Figure 11 , the hard mask layer 803 and the underlying layer 801 can be removed. A plurality of exposed portions 101E can be exposed through a plurality of openings OP1 of the catalytic conductive layer 200. The covered portion 101C can be covered by the catalytic conductive layer 200.

[0095] Refer to Figure 12 , a trench etching process can be performed to recess the covered portion 101C to form the first trench TR1. In contrast, after the trench etching process, the exposed portion 101E can be intact to form a plurality of protruding feature structures, which are referred to as a plurality of protruding portions 101P.

[0096] In some embodiments, the trench etching process can be a metal-assisted chemical etching process. In some embodiments, the metal-assisted chemical etching process can use an etchant solution. In some embodiments, the metal-assisted chemical etching process can include applying a patterned metal film (i.e., the catalytic conductive layer 200) on the substrate 101, and using this patterned metal film as an etching catalyst when exposed to a suitable etchant, and the above etchant is usually a combination of the following: an oxidant (such as hydrogen peroxide or potassium permanganate) and an acid (such as hydrofluoric acid). During the etching process, the metal catalyst reduces the oxidant, and free voids are generated at the metal-semiconductor interface, and this reaction selectively oxidizes the semiconductor under the metal (i.e., the covered portion 101C). Then, the acid dissolves the oxidized semiconductor, and allows the etching to proceed continuously in a direction approximately perpendicular to the semiconductor-metal interface.

[0097] In some embodiments, the oxidizing agent of the etchant for the trench etching process may include, for example, hydrogen peroxide, potassium permanganate, nitric acid, silver nitrate, or sodium persulfate. In some embodiments, the acid of the etchant for the trench etching process may include, for example, hydrofluoric acid or nitric acid.

[0098] In some embodiments, this process may include using a dilute hydrofluoric acid bath, in which an oxidizing agent, such as hydrogen peroxide or oxygen, is bubbled through. In some embodiments, Figure 11 the intermediate semiconductor element shown can be immersed in a solution of an acid (e.g., hydrofluoric acid) and an oxidizing agent (e.g., hydrogen peroxide) for a duration between about 10 seconds and about 20 minutes, between about 30 seconds and 15 minutes, between about 30 seconds and about 5 minutes, or between about 1 minute and 3 minutes. In some embodiments, the concentration ratio of hydrofluoric acid to the oxidizing agent can be between about 0.67:1 and about 3:1, between about 1:1 and about 2.5:1, or between about 1.5:1 and about 2:1. The concentration of the etchant solution plays an important role in determining the etching direction and surface morphology of the resulting intermediate semiconductor element.

[0099] Alternatively, when the catalytic conductive layer 200 is formed of titanium nitride, the trench etching process can employ a gaseous etchant. In some embodiments, the gaseous etchant may include an evaporated oxidizing agent and an acid, such as hydrogen peroxide and hydrofluoric acid. In this case, although the catalytic conductive layer 200 formed of titanium nitride is non-metallic, it can act as a catalyst due to its high work function and electrochemical potential and its tolerance to hydrofluoric acid. The gaseous oxidizing agent can oxidize the substrate region (i.e., the covered portion 101C) under the catalytic conductive layer 200, and then, the gaseous acid removes these oxidized regions, causing the catalytic conductive layer 200 to sink into the substrate 101 and form the first trench TR1.

[0100] In some embodiments, the substrate 101 can be heated to a temperature between about 25°C and about 100°C or between about 30°C and about 95°C (also referred to as the substrate temperature). Heating of the substrate 101 can help to facilitate etching and the formation of high aspect ratio features (e.g., the first trench TR1). The gaseous etchant can be maintained at a temperature similar to that of the substrate 101 to minimize condensation, which would impede the diffusion of the etchant and by-product vapors through the catalytic conductive layer 200. In other words, the process temperature of the gaseous etchant can be between about 25°C and about 100°C or between about 30°C and about 95°C. In some embodiments, the trench etching process can be carried out in a controlled environment, such as an inert gas or a vacuum, to maintain stability.

[0101] In some embodiments, the gaseous etchant may include hydrogen peroxide, potassium permanganate, potassium persulfate, and / or sodium persulfate. In some embodiments, the gaseous acid may include hydrofluoric acid and / or nitric acid.

[0102] In some embodiments, the formation of the gaseous etchant may involve separately heating the source materials containing the oxidant and the acid to separately generate their vapors (i.e., gaseous oxidant and gaseous acid). Then, these vapors may be transported via a carrier gas, which may be nitrogen, argon, or helium, in a closed chamber to Figure 11 the intermediate semiconductor element shown. The flow rate of each vapor can be precisely controlled to achieve a specific ratio of oxidant to acid, which is important for the desired etching result.

[0103] In some embodiments, the process duration of the trench etching process using the gaseous etchant can be between about 10 seconds and about 60 minutes, or between about 1 minute and about 30 minutes, or between about 5 minutes and about 20 minutes.

[0104] In some embodiments, the vapor partial pressures of the gaseous oxidant and the gaseous acid can be selected according to the desired molar ratio that affects the etching direction and rate. For example, the gaseous oxidant can have a vapor partial pressure between about 1 Torr and about 10 Torr, while the gaseous acid can be in the range between about 20 Torr and about 60 Torr. In some embodiments, the molar ratio of the gaseous oxidant to the gaseous acid can be between about 0.02 and about 10.

[0105] Referring to Figure 13 , the catalytic conductive layer 200 can be removed. In some embodiments, the removal of the catalytic conductive layer 200 can be achieved by wet etching or dry etching. In some embodiments, the etchant for removing the catalytic conductive layer 200 can include, for example, hydrochloric acid, nitric acid, or a mixture of ammonium hydroxide and hydrogen peroxide.

[0106] In some embodiments, in a cross-sectional view, the first trench TR1 may include a plurality of bottom surfaces TRB and a plurality of sidewalls TRS. For the sake of simplicity, clarity, and convenience of description, only one bottom surface TRB and one sidewall TRS are described. In some embodiments, the bottom surface TRB may be substantially flat. In some embodiments, the bottom surface TRB may be parallel to the top surface 101TS of the substrate 101. In some embodiments, the sidewall TRS may be substantially vertical. In some embodiments, the sidewall TRS may be perpendicular to the top surface 101TS or the bottom surface TRB of the substrate 101. In some embodiments, the aspect ratio of the first trench TR1 can be between about 4:1 and about 12:1 or between about 6:1 and about 8:1.

[0107] It should be noted that in the description of the present disclosure, if there is a vertical plane and the root mean square roughness of a surface deviating from the vertical plane does not exceed three times the root mean square roughness of the surface, it means that the surface is "substantially vertical".

[0108] Referring to Figure 14 , an isolation material 301 can be formed to completely fill the first trench TR1. In some embodiments, the isolation material 301 can include, for example, silicon oxide or other suitable insulating materials. In some embodiments, the isolation material 301 can be formed by, for example, chemical vapor deposition or other suitable deposition processes.

[0109] Referring to Figure 15 and Figure 16 , a planarization process, such as chemical mechanical polishing, can be performed until the top surface 101TS of the substrate 101 is exposed to remove the excess material and provide a substantially flat surface for subsequent process steps. After the planarization process, the remaining isolation material 301 in the first trench TR1 can be referred to as the isolation layer 103. The protruding portion 101P of the substrate 101 surrounded by the isolation layer 103 can be configured as a plurality of active regions AA.

[0110] Conventionally, forming trenches may involve an anisotropic dry etching process that generates a large amount of by-products, requiring a strong cleaning process to remove these by-products. However, due to the Laplace pressure and the high aspect ratio characteristics of the profile, such a strong cleaning process may cause the collapse of the profile (e.g., the protruding portion 101P), thus requiring an additional restoration process (e.g., oxidation, oxide etching, and silicon deposition). In contrast, the trench etching process using the catalytic conductive layer 200 does not generate a large amount of by-products, thus eliminating the need for a strong post-cleaning treatment. The reduction of processing steps can reduce the cost and complexity of manufacturing the semiconductor element 1A. In addition, the by-products of the trench etching process using the catalytic conductive layer 200 can be easily removed using an etching solution, which is also beneficial for reducing the complexity of manufacturing the semiconductor element 1A.

[0111] Figure 17 and Figure 18 are cross-sectional views illustrating a part of the manufacturing process of the semiconductor element 1B according to another embodiment of the present disclosure. Figure 19 are cross-sectional views illustrating a part of the manufacturing process of the semiconductor element 1C according to another embodiment of the present disclosure.

[0112] Referring to Figure 17 , it can be similar to Figures 2 to 13The intermediate semiconductor element is fabricated by the process shown, and its description will not be repeated here. A liner material 403 can be conformally formed in the first trench TR1 and on the top surface 101TS of the substrate 101. In some embodiments, the liner material 403 can be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxynitride.

[0113] In some embodiments, the liner material 403 can be formed by performing rapid thermal oxidation on the Figure 13 intermediate semiconductor element shown in an oxide / nitrogen oxide environment. In some embodiments, the process temperature of the rapid thermal oxidation can be about 1000 °C. In some embodiments, the corners of the first trench TR1 can be rounded (not shown) after the rapid thermal oxidation.

[0114] Alternatively, in some embodiments, the liner material 403 can be formed by a deposition process that simultaneously flows tetraethyl orthosilicate (TEOS) and ozone to the Figure 13 intermediate semiconductor element shown. The substrate temperature during the deposition process can be greater than 400 °C, greater than 500 °C, or greater than 600 °C. Additives such as, for example, water (steam), hexamethyldisilazane (HMDS), and 1,1,3,3 - tetramethyldisiloxane (TMDSO) can be added to ensure a smoother or more even deposition. The exemplary flow rate of TEOS can be greater than 0.1 gm / min (grams per minute), greater than 0.5 gm / min, greater than 1 gm / min, or greater than 3 gm / min. The exemplary flow rate of ozone can be greater than 1000 sccm (standard cubic centimeters per minute), greater than 3000 sccm, greater than 10000 sccm, or greater than 30000 sccm. The liner material 403 can improve adhesion and reduce the incidence of delamination and cracking during and after subsequent processes. In addition, the liner material 403 can present a smoother outer surface, which can have a positive impact on the deposition dynamics in subsequent processes.

[0115] Refer to Figure 18 and an isolation material 301 can be formed using a process similar to that of Figure 14 shown, and its description will not be repeated here. A planarization process, such as chemical mechanical polishing, can be performed until the liner material 403 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps. This process is similar to the processes of Figure 15 and Figure 16 and its description will not be repeated here.

[0116] Refer to Figure 19 and the semiconductor element 1C can have a structure similar to that of Figure 18 shown. In Figure 19 those that are the same or similar to Figure 18Elements have been marked with similar element symbols, and repeated descriptions are omitted.

[0117] In the semiconductor element 1C, a planarization process can be performed until the top surface 101TS of the substrate 101 is exposed. The liner material 403 can be separated into multiple segments and can be referred to as multiple liners 401. The top surfaces 401TS of the multiple liners 401 and the top surface 101TS of the protruding portion 101P (or the substrate 101) can be substantially coplanar.

[0118] One aspect of the present disclosure provides a semiconductor element, including: a substrate; a notch located within the substrate and including a bottom surface and two sidewalls; and a catalytic conductive layer located on the bottom surface of the notch. The bottom surface of the notch and a top surface of the substrate are parallel to each other. The two sidewalls of the notch are substantially perpendicular.

[0119] Another aspect of the present disclosure provides a semiconductor element, including: a substrate; a first trench located within the substrate and including a bottom surface and two sidewalls; and a catalytic conductive layer located on the bottom surface of the first trench; wherein the bottom surface of the first trench and a top surface of the substrate are parallel to each other. The two sidewalls of the first trench are substantially perpendicular. The depth-to-width ratio of the first trench is between about 4:1 and about 12:1.

[0120] Another aspect of the present disclosure provides a method for manufacturing a semiconductor element, including: providing a substrate; forming a catalytic conductive layer on the substrate; patterning the catalytic conductive layer to form an opening exposing an exposed portion of the substrate while leaving a covered portion of the substrate covered by the catalytic conductive layer; performing a trench etching process to recess the covered portion of the substrate to form a first trench; removing the catalytic conductive layer; and forming an isolation layer in the first trench.

[0121] Due to the design of the semiconductor element of the present disclosure, the trench etching process using this catalytic conductive layer 200 does not generate a large amount of by-products. Therefore, this eliminates the need for a thorough post-cleaning process, thereby reducing the cost and complexity involved in manufacturing the semiconductor element 1A.

[0122] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the above processes can be implemented in different ways, and many of the above processes can be replaced by other processes or combinations thereof.

[0123] Moreover, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure herein that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that perform the same function or achieve substantially the same result as the corresponding embodiments described herein can be used in accordance with the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included within the claims of the present application.

Claims

1. A method for manufacturing a semiconductor device, comprising: Providing a substrate; Forming a catalytic conductive layer on the substrate; Patterning the catalytic conductive layer to form an opening exposing an exposed portion of the substrate, while leaving a covered portion of the substrate covered by the catalytic conductive layer; Performing a trench etching process to recess the covered portion of the substrate to form a first trench; Removing the catalytic conductive layer; And Forming an isolation layer in the first trench, Wherein performing the trench etching process includes applying an etchant to the catalytic conductive layer and the substrate.

2. The manufacturing method according to claim 1, wherein the catalytic conductive layer comprises silver, gold, cobalt, chromium, copper, iron, hafnium, iridium, manganese, molybdenum, palladium, platinum, rubidium, rhenium, rhodium, tantalum, titanium, vanadium, tungsten, zinc or zirconium.

3. The manufacturing method according to claim 2, wherein the substrate comprises silicon, germanium, silicon germanium, silicon carbide, silicon carbide germanium, gallium, gallium arsenide, indium arsenide or indium phosphide.

4. The manufacturing method according to claim 3, wherein the aspect ratio of the first trench is between about 4:1 and about 12:

1.

5. The manufacturing method according to claim 1, wherein the etchant comprises an oxidizing agent and an acid.

6. The manufacturing method according to claim 5, wherein the oxidizing agent comprises hydrogen peroxide, potassium permanganate, nitric acid, silver nitrate or sodium persulfate.

7. The manufacturing method according to claim 5, wherein the acid comprises hydrofluoric acid or nitric acid.

8. The manufacturing method according to claim 5, wherein the process duration of the trench etching process is between about 10 seconds and about 20 minutes.

9. The manufacturing method according to claim 5, wherein the concentration ratio of the acid to the oxidizing agent is between about 0.67:1 and about 3:

1.

10. The manufacturing method according to claim 1, wherein the catalytic conductive layer comprises titanium nitride.

11. The manufacturing method according to claim 10, wherein the etchant is a vapor etchant.

12. The manufacturing method according to claim 11, wherein the vapor etchant comprises a vapor oxidizing agent and a vapor acid.

13. The manufacturing method according to claim 12, wherein the vapor oxidizing agent comprises hydrogen peroxide, potassium permanganate, potassium persulfate or sodium persulfate.

14. The manufacturing method according to claim 12, wherein the vapor acid comprises hydrofluoric acid or nitric acid.

15. The manufacturing method according to claim 12, wherein the substrate temperature of the trench etching process is between about 25 °C and about 100 °C.

16. The manufacturing method according to claim 12, wherein the vapor etchant is delivered to the substrate and the catalytic conductive layer by a carrier gas.

17. The manufacturing method according to claim 16, wherein the carrier gas comprises nitrogen, argon or helium.

18. The manufacturing method according to claim 12, wherein the molar ratio of the vapor oxidizing agent to the vapor acid is between about 0.02 and about 10.

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