Packaging method for stacking chips on rewiring layer in staggered manner
By misaligning the stacking of chips on the rewiring layer, the problem of thickness limitation of traditional substrate packaging is solved, and a thinner and more efficient chip packaging is achieved, suitable for consumer electronic products.
Patent Information
- Application Number
- CN202411963603.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-07-04
AI Technical Summary
It is difficult to make ultra-thin chip packaging structures in the prior art, and the thickness of traditional substrate packaging has reached the limits of process and equipment, and cannot meet the needs of consumer electronic products.
The chip is stacked on the rewiring layer by dislocating the rewiring layer, and a rewiring layer is made on the temporary bonding adhesive layer, and bonding wires are used between the electrode area of the chip and the metal pad, and then plastic sealing and debonding are carried out to form a multi-layer packaging structure.
A thinner packaging structure is achieved, reducing costs, improving yield, and simplifying the packaging process.
Smart Images
Figure CN120261303A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and particularly to the packaging of stacked chips. Background Art
[0002] Nowadays, the advanced packaging industry is booming, and the requirements for the thickness of chip packaging are getting thinner and thinner. However, the thickness of the chip packaging achieved by the existing traditional substrate packaging has reached the limits of the process and equipment, and there is an urgent need for a new interconnection method to fabricate a thinner packaging structure.
[0003] In the traditional memory chip packaging structure, chips are stacked on a substrate and then electrically connected through wire bonding. The processing limit thickness of the existing substrate is 80 μm, which cannot meet the requirements of ultra-thin chip packaging, especially for applications in consumer electronics such as smart phones, smart watches, smart glasses, etc.
[0004] Therefore, there is an urgent need for a chip packaging method that can solve the above problems. Summary of the Invention
[0005] The object of the present invention is to provide a packaging method for stacking chips with misalignment on a redistribution layer, which can fabricate a packaging structure with a thin thickness, a simple and controllable packaging process, and a high yield.
[0006] To achieve the above object, the present invention provides a packaging method for stacking chips with misalignment on a redistribution layer, including: providing a carrier board, coating a temporary bonding adhesive layer on a first surface of the carrier board, fabricating a redistribution layer on the temporary bonding adhesive layer, the redistribution layer including metal pads and chip bonding areas; providing a plurality of chips, sequentially and misalignedly stacking and pasting the plurality of chips on the chip bonding areas, and exposing electrodes in electrode areas of each chip on an upper surface of the chip away from the redistribution layer; bonding wires between the electrode areas of the plurality of chips and the metal pads of the redistribution layer to electrically connect the electrodes of the chips and the metal pads; encapsulating the plurality of chips on the redistribution layer to form an encapsulation body; debonding the carrier board from the redistribution layer and removing the temporary bonding adhesive layer; fabricating solder balls electrically connected to the metal pads on a side of the redistribution layer away from the chips.
[0007] Preferably, sequentially stacking and pasting the plurality of chips on the chip bonding areas specifically includes: the chips include at least two first chips and at least two second chips, when sequentially stacking and pasting the at least two first chips on the carrier board, the upper layer of chips is misaligned by a preset distance along a first direction relative to the lower layer of chips, and when sequentially stacking and pasting the at least two second chips on the topmost first chip, the upper layer of chips is misaligned by a preset distance along a second direction relative to the lower layer of chips, and the first direction and the second direction are opposite directions.
[0008] Specifically, there are at least two of the metal pads, which are respectively arranged in the first direction and the second direction of the chip bonding area; bonding wires are bonded between the electrode areas of the chips and the metal pads of the redistribution layer to electrically connect the electrodes of the chips and the metal pads, which specifically includes: bonding wires are bonded between the electrode area of each first chip and the metal pad in the second direction; bonding wires are bonded between the electrode area of the second chip except the topmost one and the metal pad in the first direction; bonding wires are bonded between the electrode area of the topmost second chip and the metal pad in the first direction or the second direction.
[0009] Preferably, there are at least two of the metal pads, which are respectively arranged in the first direction and the second direction of the chip bonding area; bonding wires are bonded between the electrode areas of the chips and the metal pads of the redistribution layer to electrically connect the electrodes of the chips and the metal pads, which specifically includes: starting from the second layer of the first chips counted from bottom to top, bonding wires are bonded between the electrode areas of each first chip and the first chip of the next lower layer, and bonding wires are bonded between the electrode area of the first layer of the first chips and the metal pad in the second direction; starting from the second layer of the second chips counted from bottom to top, bonding wires are bonded between the electrode areas of each second chip and the second chip of the next lower layer, and bonding wires are bonded between the electrode area of the first layer of the second chips and the metal pad in the first direction.
[0010] Preferably, bonding wires are bonded between the electrode area of the first layer of the first chips and the metal pad in the second direction, there are two metal pads arranged at intervals in the second direction in the second direction of the chip bonding area, and bonding wires are bonded between the first chips and the topmost second chip and the metal pad in the second direction.
[0011] Preferably, the number of the first chips is 2 to 4, and the number of the second chips is 2 to 4.
[0012] Preferably, fabricating the redistribution layer on the temporary bonding adhesive layer specifically includes: performing photolithography, copper plating, and etching on the temporary bonding adhesive layer in sequence to form a layer of redistribution layer; coating an insulating adhesive on the redistribution layer, and then performing photolithography, developing, and curing to form an insulating layer; performing photolithography, copper plating, and etching again on the insulating layer and the redistribution layer to form another layer of redistribution layer, repeating the above steps until a preset number of layers of redistribution layer are formed, and the topmost redistribution layer is the redistribution layer with metal pads; coating an insulating adhesive on the redistribution layer with metal pads, and then performing photolithography, developing, and curing to form an insulating layer exposing the metal pads. The redistribution layer of the present invention is a multi-layer redistribution layer.
[0013] Preferably, the chips are sequentially stacked and pasted on the chip bonding area by glue pasting or adhesive film.
[0014] Preferably, a plurality of chips are provided, including: attaching a wafer to a BG film and thinning the substrate on the back surface of the wafer; transferring the thinned wafer to a DAF film and cutting it into a plurality of chips.
[0015] Preferably, the carrier plate and the redistribution layer are debonded by a mechanical method or a laser debonding method.
[0016] Preferably, the chip is a memory chip, and the package structure formed by the package method of stacking chips misaligned on the redistribution layer is a package structure of a memory chip.
[0017] Compared with the prior art, in the present invention, the package of stacked chips is on the redistribution layer. Compared with the existing circuit carrier plate, the thickness is thin, so that the thickness of the packaged structure is thin. Furthermore, in the present invention, the redistribution layer is directly grown on the temporary bonding adhesive layer, and then the chips are stacked and pasted on the carrier plate containing the redistribution layer and then encapsulated. On the one hand, there is no need to set up copper pillars for electrical connection, and only bonding wires are used to electrically connect the chips and the redistribution layer, with a thin thickness, low cost, and simple manufacturing process; on the other hand, the redistribution layer can be fabricated first and then the chips are pasted for electrical connection, ensuring the reliability of the electrical connection between the chips and the redistribution layer, and making the redistribution layer not only directly positioned together with the chips, with a stable structure, but also making the redistribution layer fabricated on a flat carrier plate, with a high yield. Description of the Drawings
[0018] Figure 1 is a partial flow chart of the package method of stacking chips misaligned on the redistribution layer of the present invention.
[0019] Figure 2 is another partial flow chart of the package method of stacking chips misaligned on the redistribution layer of the present invention.
[0020] Figure 3 is a misaligned stacked chip package structure formed by the package method of stacking chips misaligned on the redistribution layer in an embodiment of the present invention.
[0021] Figure 4 is a misaligned stacked chip package structure formed by the package method of stacking chips misaligned on the redistribution layer in another embodiment of the present invention.
[0022] Figure 5 is a misaligned stacked chip package structure formed by the package method of stacking chips misaligned on the redistribution layer in yet another embodiment of the present invention.
[0023] Figure 6 is a misaligned stacked chip package structure formed by the package method of stacking chips misaligned on the redistribution layer in still another embodiment of the present invention.
[0024] Figure 7 This is a misaligned stacked chip package structure fabricated by a packaging method for misaligned stacking of chips on a redistribution layer in another embodiment of the present invention. Detailed implementation manners
[0025] To describe in detail the technical content, structural features, achieved objectives, and effects of the present invention, the following will be described in detail in conjunction with the implementation manners and with reference to the drawings.
[0026] Refer to Figure 1 , the present invention discloses a packaging method for misaligned stacking of chips on a redistribution layer, including steps S1 to S7.
[0027] S1. Provide a carrier board 10, and coat a temporary bonding adhesive layer 11 on the first surface of the carrier board 10. The carrier board 10 can be a glass carrier board or a silicon board, etc.
[0028] Among them, the temporary bonding adhesive layer 11 is a mechanically debondable adhesive layer, a laser debondable adhesive layer, or a thermally debondable adhesive layer.
[0029] S2. Fabricate a redistribution layer 20 on the temporary bonding adhesive layer 11. The redistribution layer 20 includes metal pads and chip bonding areas.
[0030] Specifically, in S21, perform photolithography, copper plating, and etching on the temporary bonding adhesive layer 11 in sequence to form a layer of redistribution layer; in S22, coat an insulating adhesive on the redistribution layer, and then perform photolithography, development, and curing to form an insulating layer; in S23, perform photolithography, copper plating, and etching again on the insulating layer and the redistribution layer 20 to form another layer of redistribution layer. Repeat the above steps (repeat steps S22 to S23) until a preset number of layers of redistribution layers are formed, and the topmost redistribution layer is a redistribution layer with metal pads; coat an insulating adhesive on the redistribution layer with metal pads, and then perform photolithography, development, and curing to form an insulating layer that exposes the metal pads. Thus, a multi-layer redistribution layer 20 is fabricated.
[0031] Specifically, performing photolithography, copper plating, and etching to form a layer of redistribution layer specifically includes: coating a photoresist layer on the temporary bonding adhesive layer 11 to form a redistribution photolithography pattern; performing copper electroplating in the hollow area of the photoresist layer to form a copper plating layer; removing the photoresist and etching the copper plating layer to obtain a layer of redistribution layer.
[0032] S3. Provide a plurality of chips 30, and paste the plurality of chips 30 on the chip bonding areas in a misaligned stacked manner in sequence, and make the electrodes in the electrode areas of each chip 30 expose on the upper surface of the chip 30 away from the redistribution layer 20, and each electrode area is not blocked by the upper chip 30. The electrode areas are located at the misaligned exposed positions on the chip 30, generally near the edge of the chip 30.
[0033] Among them, the chip 30 is sequentially stacked and pasted on the chip pasting area by glue pasting or a glue film. The thickness of the glue layer formed by glue pasting or the glue film is 10 - 20 μm.
[0034] Among them, providing a number of chips 30 includes: attaching a wafer to a BG film (Back Grinding Tape), and thinning the substrate on the back of the wafer; transferring the thinned wafer to a DAF film (Die Attach Film) and cutting it into a number of chips 30.
[0035] The chip 30 of the present invention is preferably a thinned chip. Among them, the number of stacked layers of the chip 31 can be 2 layers, 3 layers... 8 layers, etc.
[0036] Specifically, referring to Figure 1 , the chip 30 includes at least two first chips 31 and at least two second chips 32. When the at least two first chips 31 are sequentially stacked and pasted on the carrier board 10, the upper layer of the chip 30 is displaced a preset distance along a first direction relative to the lower layer of the chip 30. When the at least two second chips 32 are sequentially stacked and pasted on the top - layer first chip 31, the upper layer of the chip 30 is displaced a preset distance along a second direction relative to the lower layer of the chip 30, and the first direction and the second direction are opposite directions. In this embodiment, the number of layers of the chip 31 is preferably 4 - 8 layers, and is not limited to 8 layers. For example Figure 6 There are a total of 6 layers of chips stacked in , among which four first chips 31 are sequentially displaced and stacked along the first direction, and two second chips 32 are sequentially displaced and stacked on the first chips 31 along the second direction.
[0037] Of course, different from this, the chip 30 can also only include the first chip 31. For example Figure 4 shown in , two chips 30 are displaced and stacked to form a two - layer chip stacking structure. Figure 5 It is disclosed that four chips 30 are sequentially displaced and stacked along the first direction to form a four - layer chip stacking structure.
[0038] S4. Bonding wires are bonded between the electrode regions of the several chips 30 and the metal pads of the redistribution layer 20 to electrically connect the electrodes of the chips 30 and the metal pads.
[0039] Among them, there are at least two metal pads, which are respectively arranged in the first direction and the second direction of the chip pasting area. In this embodiment, there are a metal pad 22 located in the first direction of the chip pasting area, metal pads 21 and 23 located in the second direction of the chip pasting area, and the metal pad 21 is in the first direction of the metal pad 23.
[0040] In step S4, bonding wires are respectively formed between the electrode regions of each of the first chips 31 and the metal pads 21 in the second direction to electrically connect the electrodes of the first chips 31 and the metal pads 21; bonding wires are formed between the electrode regions of the second chips 32 except the topmost one and the metal pads 22 in the first direction to electrically connect the electrodes of the second chips 32 and the metal pads 22; bonding wires are formed between the electrode regions of the topmost second chip 32 and the metal pads 23 in the second direction to electrically connect the electrodes of the second chip 32 and the metal pads 23. Of course, bonding wires can also be formed between the electrode regions of the topmost second chip 32 and the metal pads 22 in the first direction to electrically connect the electrodes of the second chip and the metal pads 22.
[0041] S5, encapsulating a plurality of chips 30 on the redistribution lines to form an encapsulation body 40.
[0042] S6, debonding the carrier board 10 from the redistribution layer 20 and removing the temporary bonding adhesive layer 11.
[0043] Wherein, the carrier board 10 is debonded from the redistribution layer 20 by a mechanical method or a laser debonding method.
[0044] S7, making solder balls 50 electrically connected to the metal pads 21, 22, 23 on a side of the redistribution layer 20 away from the chips 30.
[0045] Wherein, after forming the encapsulation body 40, there is also a step of thinning the encapsulation body 40. The step of thinning the encapsulation body 40 can be located between step S5 and step S6, or can be located after step S7.
[0046] Of course, different from the above embodiments, referring to Figure 7 , in another embodiment, starting from the second first chip 31 counted from the bottom up, bonding wires are formed between the electrode regions of each of the first chips 31 and the first chip 31 in the next lower layer to electrically connect the electrodes of the first chips 31 in adjacent layers, and bonding wires are formed between the electrode region of the first chip 31 in the first layer and the metal pads 21 in the second direction to electrically connect the electrodes of the first chip 31 and the metal pads 21; starting from the second second chip 32 counted from the bottom up, bonding wires are formed between the electrode regions of each of the second chips 32 and the second chip 32 in the next lower layer to electrically connect the electrodes of the adjacent second chips 32, and bonding wires are formed between the electrode region of the second chip 32 in the first layer and the metal pads 22 in the first direction to electrically connect the electrodes of the second chip 32 and the metal pads.
[0047] In this embodiment, the chip 30 is a storage chip, and the packaging structure made by the packaging method of stacking chips staggeredly on the redistribution layer is a storage chip packaging structure. Of course, the chip 30 can also be other chips, not limited to storage chips.
[0048] The above-disclosed are only the preferred embodiments of the present invention. Of course, the scope of the rights of the present invention cannot be limited thereby. Therefore, equivalent changes made according to the scope of the patent application of the present invention still fall within the scope covered by the present invention.
Claims
1. A packaging method for misaligned stacking of chips on a redistribution layer, characterized in that: Including: Providing a carrier substrate, forming a temporary bonding adhesive layer on the carrier substrate, and fabricating a redistribution layer on the temporary bonding adhesive layer, the redistribution layer including metal pads and a chip bonding area; Providing a plurality of chips, sequentially and staggeredly stacking and pasting the plurality of chips in the chip bonding area, and exposing the electrodes in the electrode area of each chip on the upper surface of the chip away from the redistribution layer; Bonding wires are bonded between the electrode areas of the plurality of chips and the metal pads of the redistribution layer to electrically connect the electrodes of the chips and the metal pads; Encapsulating the plurality of chips on the redistribution layer to form an encapsulation body; Debonding the carrier substrate from the redistribution layer and removing the temporary bonding adhesive layer; Fabricating solder balls electrically connected to the metal pads on the side of the redistribution layer away from the chips.
2. The packaging method for misaligned stacked chips on a redistribution layer according to claim 1, characterized in that: Sequentially stacking and pasting the plurality of chips in the chip bonding area specifically includes: the chips include at least two first chips and at least two second chips. When the at least two first chips are sequentially stacked and pasted on the carrier substrate, the upper layer of chips is displaced by a preset distance along a first direction relative to the lower layer of chips. When the at least two second chips are sequentially stacked and pasted on the topmost first chip, the upper layer of chips is displaced by a preset distance along a second direction relative to the lower layer of chips, and the first direction and the second direction are opposite directions.
3. The packaging method for misaligned stacked chips on a redistribution layer as claimed in claim 2, wherein: There are at least two metal pads, which are respectively arranged in the first direction and the second direction of the chip bonding area; Bonding wires are bonded between the electrode areas of the plurality of chips and the metal pads of the redistribution layer to electrically connect the electrodes of the chips and the metal pads specifically includes: Bonding wires are bonded between the electrode area of each first chip and the metal pad in the second direction; Bonding wires are bonded between the electrode areas of the second chips except the topmost one and the metal pads in the first direction; Bonding wires are bonded between the electrode area of the topmost second chip and the metal pad in the first direction or the second direction.
4. The packaging method for misaligned stacked chips on a redistribution layer according to claim 1, characterized in that: There are at least two metal pads, which are respectively arranged in the first direction and the second direction of the chip bonding area; Bonding wires are bonded between the electrode areas of the plurality of chips and the metal pads of the redistribution layer to electrically connect the electrodes of the chips and the metal pads specifically includes: Starting from the second layer of the first chips counted from bottom to top, bonding wires are bonded between the electrode areas of each first chip and the lower layer of first chips, and bonding wires are bonded between the electrode area of the first layer of first chips and the metal pads in the second direction; Starting from the second layer of the second chips counted from bottom to top, bonding wires are bonded between the electrode areas of each second chip and the lower layer of second chips, and bonding wires are bonded between the electrode area of the first layer of second chips and the metal pads in the first direction.
5. The packaging method for misaligned stacked chips on a redistribution layer according to claim 1, characterized in that: Bonding wires are bonded between the electrode area of the first layer of first chips and the metal pads in the second direction. There are two metal pads arranged at intervals along the second direction in the second direction of the chip bonding area. Bonding wires are bonded between the first chip and the topmost second chip and the metal pads in the second direction.
6. The packaging method for misaligned stacked chips on a redistribution layer according to claim 1, characterized in that: The number of the first chips is 2 to 4, and the number of the second chips is 2 to 4.
7. The packaging method for misaligned stacked chips on a redistribution layer as described in claim 1, characterized in that: Fabricating the redistribution layer on the temporary bonding adhesive layer specifically includes: Performing photolithography, copper plating, and etching on the temporary bonding adhesive layer in sequence to form a redistribution layer; Coating an insulating adhesive on the redistribution layer, and then performing photolithography, developing, and curing to form an insulating layer; Performing photolithography, copper plating, and etching again on the insulating layer and the redistribution layer to form another redistribution layer, repeating the above steps until a redistribution layer with a preset number of layers is formed, and the topmost redistribution layer is a redistribution layer with metal pads; Coating an insulating adhesive on the redistribution layer with metal pads, and then performing photolithography, developing, and curing to form an insulating layer exposing the metal pads.
8. The packaging method for misaligned stacked chips on a redistribution layer according to claim 1, wherein: The chips are stacked and pasted on the chip paste area in sequence by glue pasting or an adhesive film.
9. The packaging method for misaligned stacked chips on a redistribution layer according to claim 1, characterized in that: Providing a plurality of chips includes: attaching a wafer to a BG film, and thinning the substrate on the back surface of the wafer; Temporarily bonding and transferring the substrate surface of the thinned wafer to a DAF film, cutting the wafer into a plurality of chips, and fabricating electrodes of the chips.
10. The packaging method for misaligned stacked chips on a redistribution layer according to claim 1, characterized in that: Debonding the carrier plate from the redistribution layer by a mechanical method or a laser debonding method.
11. The packaging method for misaligned stacked chips on a redistribution layer according to claim 1, characterized in that: The chips are memory chips, and the package structure formed by the package method of stacking chips out of alignment on the redistribution layer is a memory chip package structure.