Semiconductor package and method of manufacturing the same

Abstract

A method for manufacturing a semiconductor device is provided. The method comprises the following steps: providing a packaging base part; attaching a first interposer on the package base via a solder bump; attaching a first semiconductor die on the package base and adjacent to the first interposer; a second interposer is attached over the first interposer via solder bumps to form an interposer stack, where the first interposer and the second interposer define a stepped structure, wherein the step structure comprises two step surfaces extending from the first interposer and the second interposer, respectively, at sides of the interposer stack; attaching a second semiconductor die over both the first semiconductor die and the first interposer; and forming a first encapsulant layer on the package base to encapsulate the first interposer, the second interposer, the first semiconductor die, and the second semiconductor die.

Description

Technical Field

[0001] The present application generally relates to semiconductor technology, and more particularly, to a semiconductor package and a method for manufacturing a semiconductor package. Background Art

[0002] Semiconductor devices are common in modern electronic products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, and generating visual images for video display. As electronic products continue to improve, it is desirable to integrate more and more semiconductor dies in a single package. For example, semiconductor dies can be stacked with through silicon vias (TSVs). However, for some packages, structures such as TSVs that pass through semiconductor dies may not be practical.

[0003] Therefore, there is a need for an improved packaging technology for semiconductor devices having multiple semiconductor dies. Summary of the Invention

[0004] An object of the present application is to provide a semiconductor package having multiple semiconductor dies with improved manufacturing efficiency and improved applicability.

[0005] According to one aspect of the present application, there is provided a method for manufacturing a semiconductor package. The method includes: providing a package base; attaching a first interposer to the package base via solder bumps; attaching a first semiconductor die to the package base and adjacent to the first interposer; attaching a second interposer to the first interposer via solder bumps to form an interposer stack, wherein the first interposer and the second interposer define a stepped structure at a side of the interposer stack adjacent to the first semiconductor die, the stepped structure including two stepped surfaces that extend from the first interposer and the second interposer respectively at the side of the interposer stack; attaching a second semiconductor die to both the first semiconductor die and the first interposer; and forming a first sealant layer on the package base to seal the first interposer, the second interposer, the first semiconductor die, and the second semiconductor die.

[0006] According to another aspect of the present application, a method for manufacturing a semiconductor package is provided. The method includes: providing a substrate and a plurality of semiconductor dies; forming an integrated interposer block including an interposer portion and a non-functional portion, the interposer portion having a multi-layer connection structure; removing the non-functional portion from the integrated interposer block to form an integrated interposer stack, the integrated interposer stack having a stepped structure at the side, wherein the integrated interposer stack includes a plurality of interposers, each interposer of the plurality of interposers having one connection structure of the multi-layer connection structure and an exposed stepped surface at the stepped structure; attaching the integrated interposer stack to the substrate; attaching the semiconductor dies to the substrate and adjacent to the integrated interposer stack; attaching at least two semiconductor dies to the integrated interposer stack, wherein each of the at least two semiconductor dies is partially attached to one of the exposed stepped surfaces; and forming a sealant layer on the substrate to seal the integrated interposer stack and the semiconductor dies.

[0007] According to yet another aspect of the present application, a method for manufacturing a semiconductor package is provided. The method includes: providing a plurality of semiconductor dies; forming an integrated interposer block including a substrate, an interposer portion, and a non-functional portion, the interposer portion having a multi-layer connection structure; removing the non-functional portion from the integrated interposer block to form an integrated interposer stack integrated with the substrate, wherein the integrated interposer stack has a stepped structure at the side, wherein the integrated interposer stack includes a plurality of interposers, each interposer of the plurality of interposers having one connection structure of the multi-layer connection structure and an exposed stepped surface at the stepped structure; attaching the semiconductor dies to the substrate and adjacent to the integrated interposer stack; attaching at least two semiconductor dies to the integrated interposer stack, wherein each of the at least two semiconductor dies is partially attached to one of the exposed stepped surfaces; and forming a sealant layer on the substrate to seal the integrated interposer stack and the semiconductor dies.

[0008] According to another aspect of the present application, a semiconductor package is provided. The semiconductor package includes: a substrate; an interposer stack formed on the substrate, wherein the interposer stack includes a plurality of interposers stacked together and defining a stepped structure at the side of the interposer stack, and wherein the stepped structure includes at least two stepped surfaces exposing corresponding interposers in the interposer stack; a plurality of semiconductor dies stacked together on the substrate and adjacent to the stepped structure of the interposer stack, wherein each semiconductor die of the plurality of semiconductor dies is partially attached to the substrate or attached to one of the stepped surfaces of the stepped structure; and a sealant layer formed on the substrate, wherein the sealant layer seals the interposer stack and the plurality of semiconductor dies.

[0009] It should be understood that the foregoing general description and the following detailed description are merely exemplary and explanatory, and not restrictive of the present invention. In addition, the accompanying drawings incorporated in and constituting a part of this specification illustrate embodiments of the present invention and, together with the specification, are used to explain the principles of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings cited herein constitute a part of the specification. The features shown in the drawings illustrate only some embodiments of the present application, rather than all embodiments of the present application, unless otherwise explicitly stated in the detailed description, and readers of the specification should not make an opposite inference.

[0011] Figure 1 Shows a semiconductor package according to an embodiment of the present application.

[0012] Figures 2A to 2G Shows steps of a method for manufacturing a Figure 1 semiconductor package according to an embodiment of the present application.

[0013] Figures 3A to 3F Shows steps of a method for manufacturing a Figure 1 semiconductor package according to another embodiment of the present application.

[0014] Figures 4A to 4C Shows different methods for attaching a Figure 1 higher semiconductor die of a semiconductor package according to some embodiments of the present application.

[0015] Figure 5 Shows a semiconductor package according to another embodiment of the present application.

[0016] Figure 6 Shows a semiconductor package according to another embodiment of the present application.

[0017] Figures 7A to 7F Shows the steps for manufacturing Figure 5 a semiconductor package according to an embodiment of the present application.

[0018] Figures 8A to 8E Shows the steps for manufacturing Figure 6 a semiconductor package according to an embodiment of the present application.

[0019] The same reference numerals will be used throughout the drawings to represent the same or similar parts. Detailed Description

[0020] The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings that form a part of the description. The drawings illustrate specific exemplary embodiments in which the present application may be practiced. The detailed description including the drawings describes these embodiments in sufficient detail to enable those skilled in the art to practice the present application. Those skilled in the art may further utilize other embodiments of the present application and make logical, mechanical, etc. changes without departing from the spirit or scope of the present application. Therefore, the reader of the following detailed description should not interpret the description in a restrictive manner, and the scope of the embodiments of the present application is defined only by the appended claims.

[0021] In the present application, unless otherwise clearly stated, the use of the singular includes the plural. In the present application, unless otherwise specified, the use of "or" means "and / or". In addition, the use of the term "comprising" and other forms such as "comprises" and "containing" is not restrictive. In addition, unless otherwise clearly stated, terms such as "element" or "component" cover elements and components including a single unit, as well as elements and components including more than one sub-unit. In addition, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0022] As used herein, spatially relative terms, such as "below", "beneath", "above", "over", "on", "under", "in front of", "behind", "left", "right", "vertical", "horizontal", "side", etc., may be used herein to facilitate the description of the relationship of one element or feature to another element or feature as shown in the drawings. In addition to the directions depicted in the figures, spatially relative terms are intended to cover different directions of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially related descriptors used herein may be interpreted accordingly. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.

[0023] To effectively utilize the space in a semiconductor package, multiple semiconductor dies can be vertically stacked in the package. Conventionally, electrical connections passing through the semiconductor dies, such as TSVs etc., can be formed to pass through one or more semiconductor dies for electrically connecting semiconductor dies at different heights. However, there are cases where such structures are not feasible. This application discloses a more generally applicable semiconductor package. This semiconductor package has multiple semiconductor dies stacked together via various interposers.

[0024] Figure 1 FIG. 1 shows a semiconductor package 100 according to an embodiment of the present application. The semiconductor package 100 includes a substrate 110 and an interposer stack 120, multiple semiconductor dies 130-1, 130-2, 130-3, and 130-4, and a sealant layer 140 formed on the substrate 110. Specifically, the interposer stack 120 and the multiple semiconductor dies 130-1 to 130-4 are formed adjacent to each other on the top surface 111 of the substrate 110. The interposer stack 120 provides a stepped structure for supporting the corresponding semiconductor dies 130-1 to 130-4 at different heights relative to the substrate 110 while maintaining the electrical connection of the semiconductor dies to the substrate 110, and preferably, also maintaining the electrical connection between these semiconductor dies 130-1 to 130-4. The sealant layer 140, also formed on the top surface 111, seals the interposer stack 120 and the semiconductor dies 130-1 to 130-4 for protection and electrical isolation.

[0025] The substrate 110 may include one or more insulating layers or passivation layers and one or more substrate interconnect structures formed in the insulating layer or passivation layer. Each substrate interconnect structure may include one or more conductive vias formed through the insulating layer or passivation layer, and one or more conductive layers formed on the top and / or bottom surfaces of the substrate 110. The substrate 110 may include one or more laminated layers of pre-impregnated polytetrafluoroethylene, FR-4, FR-1, CEM-1, or CEM-3, and a composition of phenolic cotton paper, epoxy resin, resin, glass fabric, frosted glass, polyester, or other reinforcing fibers or fabrics. The substrate 110 may also be a multi-layer flexible laminate, ceramic, copper-clad laminate, or glass. In some embodiments, the substrate interconnect structures or redistribution layers (RDLs) in the substrate 110 may be formed using sputtering, electroplating, electroless plating, or other suitable deposition processes. The conductive vias and layers may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable conductive materials.

[0026] Still referring to Figure 1, an interposer stack 120 is formed on the top surface 111 of a substrate 110. Preferably, the interposer stack 120 is attached to the substrate 110 via solder bumps 124. The interposer stack 120 includes a plurality of interposers 120-1, 120-2, and 120-3, which are preferably stacked together via solder bumps 125. It can also be understood that in other embodiments, the plurality of interposers can be connected together using other methods, such as by directly contacting the interposers. Each of the interposers 120-1, 120-2, and 120-3 may include conductive vias, which can provide paths for power supply, grounding, and data transmission sending and receiving of the electronic components attached thereto. For example, the interposer 120-1 may include a conductive pattern 126 on its exposed surface for electrical connection to a semiconductor die, and a connection structure 127 that extends and electrically passes through the interposer 120-1. The structures of the conductive pattern 126 and the connection structure 127 are not limited to the embodiments shown herein. For example, the materials and structures of the interposer may be similar to those of the substrate 110, which will not be repeated here.

[0027] Since the interposer stack 120 has different interposers that can be formed as the interposer stack 120, these different interposers can have different compositions and the solder bumps therebetween to meet the different requirements of the semiconductor dies they are connected to. For example, if two semiconductor dies need to exchange a large amount of current for power supply, a wider connection structure can be used for the interposer to connect the two semiconductor dies. For another example, if a large amount of data communication between two semiconductor dies is required, a more dense connection structure can be used for the interposer to connect the two semiconductor dies to provide more signal paths. Therefore, in some embodiments, it is not desirable for the connection structures of the interposers in the interposer stack to be vertically aligned with each other.

[0028] As Figure 1 shown, the plurality of interposers 120-1 to 120-3 can jointly define a stepped structure 121 on the side of the interposer stack 120. Generally speaking, the stepped structure 121 has a stepped cross-section like that of a staircase. The stepped structure 121 may include at least two stepped surfaces. For example, as Figure 1 shown, the stepped structure 121 may have three stepped surfaces 122-1, 122-2, and 122-3 that are respectively exposed from the interposers 120-1, 120-2, and 120-3. The stepped surfaces 122-1, 122-2, and 122-3 include conductive patterns, which are exposed as needed for electrical connection to the semiconductor dies thereon respectively.

[0029] Each of the interposer layers in the interposer stack 120 further includes a rise surface between its stepped surface and a lower (stepped) surface. Preferably, each interposer layer is formed as a cube or a cuboid, and its rise surface is perpendicular to its stepped surface. For example, the interposer 120-1 includes a rise surface 123-1 perpendicular to the stepped surface 122-1, the interposer 120-2 includes a rise surface 123-2 perpendicular to the stepped surface 122-2, and the interposer 120-3 includes a rise surface 123-3 perpendicular to the stepped surface 122-3. It can be understood that in other embodiments, the rise surface may be in other shapes and forms, such as a slope. As described below, preferably, the height of the interposer layer can be the same as the height of the semiconductor die located at the same horizontal height as the interposer layer, so as to standardize the manufacturing process. Preferably, the interposer layers in the interposer stack may have the same height and may be manufactured using the same process.

[0030] As Figure 1 shown, the stepped structure 121 of the interposer stack 120 is on the right side of the interposer stack 120. On the left side of the interposer stack 120, the interposer layers define a substantially vertical surface, preferably, the substantially vertical surface is flat. In other words, the left edges of the plurality of interposer layers are substantially in the same vertical plane, whether a gap is formed between the interposer layers or not. It can be understood that the two sides of the interposer stack 120 may take other forms to accommodate the electronic components in the semiconductor package 100.

[0031] Still referring to Figure 1, a plurality of semiconductor dies 130-1 to 130-4 are also stacked together on the top surface 111 of the substrate 110 and adjacent to the stepped structure 121. Preferably, the semiconductor die 130-1 is at least partially attached to the substrate 110 via solder bumps 131, and preferably, the semiconductor die 130-1 is completely attached to the substrate 110. The semiconductor die 130-2 is partially attached to the semiconductor die 130-1 and partially attached to the stepped surface 122-1 of the interposer 120-1. Similarly, the semiconductor die 130-3 is partially attached to the stepped surface 122-2 of the interposer 120-2, and the semiconductor die 130-4 is partially attached to the stepped surface 122-3 of the interposer 120-3. In some embodiments, the higher semiconductor die is attached to the lower semiconductor die via solder bumps. For example, the semiconductor die 130-2 is attached to the semiconductor die 130-1 via solder bumps 132. Depending on whether the conductive patterns are formed on both surfaces of the semiconductor die and / or the interposer, an electrical connection or path may or may not be formed between two components physically connected by solder bumps. For example, for the semiconductor die 130-2, a conductive pattern aligned with the top surface of the semiconductor die 130-1 is not formed on a part of its bottom surface, and therefore, the solder bumps there may not electrically connect the semiconductor die 130-2 to the semiconductor die 130-1. However, there may be a conductive pattern formed on another part of the bottom surface of the semiconductor die 130-2, and the conductive pattern is aligned with the top surface of the interposer 120-1, and therefore, the solder bumps there may electrically connect the semiconductor die 130-2 to the interposer 120-1.

[0032] As described above, in the semiconductor package 100, the semiconductor dies 130-1 to 130-4 can achieve electrical connection with each other and electrical connection to the substrate 110 via the interposer stack 120. Thus, wire bonding or TSV is not necessarily required between the plurality of semiconductor dies 130-1 to 130-4. Therefore, the manufacturing process of the semiconductor package 100 can be simplified.

[0033] To achieve a more stable structure, in semiconductor package 100, the heights of the interposer and the semiconductor die at the same horizontal height can be similar or the same to each other. For example, the heights of interposer 120-1 and semiconductor die 130-1 can be similar, and the heights of interposer 120-2 and semiconductor die 130-2 can be similar, and so on. It can be understood that the solder bumps used to attach the interposer and the semiconductor die can also have the same or similar heights and / or similar materials. In this case, the manufacturing process can be standardized and simplified. Additionally, during a bonding process such as a reflow process, for example, the solder bumps of the interposer stack and the multiple semiconductor dies can undergo similar changes, and the height difference between the interposer and the semiconductor die at the same horizontal height after the bonding process can be minimized, and it may even be possible to avoid the generation of the height difference.

[0034] Still referring to Figure 1 Semiconductor package 100 further includes a sealant layer 140 formed on substrate 110 and thus formed on the interposer stack 110 and the semiconductor dies. In some embodiments, the sealant layer 140 can be a polymer composite, such as epoxy resin, epoxy acrylate, or any suitable polymer with or without fillers. The sealant layer 140 can be non-conductive, provide structural support, and environmentally protect the electronic device from the external environment and contaminants. The sealant layer 140 can be formed in any shape as needed. The sealant layer 140 can be formed by depositing a sealant or a molding compound on substrate 110 using injection molding, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable processes.

[0035] In some embodiments, solder bumps 150 are mounted on the bottom surface of substrate 110 for electrically connecting semiconductor package 100 to an external device.

[0036] It can be understood that in other cases, the interposer stack 120, the multiple semiconductor dies 130-1 to 130-4, and the sealant layer 140 can be formed on various forms of bases. Figure 1The semiconductor package 100 shown in [Figure] is formed on a substrate 110 that serves as a package base. In other embodiments, a substrate with at least one electronic component mounted thereon may also serve as the package base, and the at least one electronic component may jointly define a flat surface for further accommodating and supporting components thereon. For example, the package base may be a substrate with a relatively large semiconductor die mounted thereon, or a substrate with a stack of multiple interposers and semiconductor dies mounted thereon. That is, there may be other components between the interposer stack and the multiple semiconductor dies and the substrate. For simplicity, the substrate is used as the package base in the following embodiments. The form of the package base is not limited to this.

[0037] Figures 2A to 2G Steps of a method for manufacturing Figure 1 the semiconductor package 100 according to an embodiment of the present application are shown. For simplicity, the connection structures of the substrate and the interposer are shown as blocks. It can be understood that the form of the connection structure in the substrate or the interposer and the form of the conductive pattern on the substrate or the interposer are not limited to this.

[0038] Refer to Figure 2A , a substrate 110 is provided as a package base for accommodating electronic components thereon. In some embodiments, the substrate 110 may include a printing area 112 for printing epoxy solder paste thereon, and the epoxy solder paste may be further attached to the non-functional bumps of the semiconductor die thereon. In some embodiments, pads may be formed on the printing area 112 of the substrate 110. The non-functional bumps of the semiconductor die may be connected to the pads to further strengthen the mechanical interconnection therebetween.

[0039] Refer to Figure 2B, the interposer 120-1 and the semiconductor die 130-1 are attached to the top surface 111 of the substrate 110. The semiconductor die 130-1 is adjacent to the interposer 120-1. In some embodiments, the interposer 120-1 is attached to the substrate 110 via solder bumps 124. The semiconductor die 130-1 may include dummy bumps 131-1 for attaching to the printed area 112 of the substrate 110. The dummy bumps 131-1 may not be electrically connected to the substrate 110, but only provide mechanical support for the components thereon. For example, the conductive pattern connected to the dummy bumps 131-1 may not be electrically connected to the connection structure in the substrate 110, or there may be no conductive pattern under the dummy bumps 131-1. In addition, the dummy bumps 131-1 may be the same or similar in material and shape as the solder bumps for electrical connection purposes. The semiconductor die 130-1 may further include solder bumps 131-2 that are electrically connected to the substrate 110 below. In some embodiments, the semiconductor die 130-1 may be a control circuit chip, such as a memory device. In some embodiments, all the bumps of the semiconductor die 130-1 are electrically connected to the substrate 110. Similar to the above embodiments, the substrate 110 may further include pads for attaching the semiconductor die 130-1. Preferably, the interposer 120-1 and the semiconductor die 130-1 may have the same height, and the solder bumps 124 below the interposer 120-1 and the solder bumps 131-2 and dummy bumps 131-1 below the semiconductor die 130-1 may have the same height and the same material. Therefore, during the reflow process, the bumps of the interposer 120-1 and the semiconductor die 130-1 may experience the same or similar height changes. Preferably, after placing the interposer and the semiconductor die at the same horizontal height on a lower base or layer, a bonding process may be performed to bond the interposer and the semiconductor die to the lower base or layer. In this way, the interposer and the semiconductor die supported on the lower base or layer have better stability and can thus be used as a base for further attaching additional layers of components and structures thereon. It can be understood that multiple interposers and semiconductor dies with different horizontal heights may be stacked together first, and then the bonding process may be performed on the multiple levels. Preferably, for the interposer and the semiconductor die at the bottom horizontal height, they may be attached to the substrate via laser-assisted bonding, while for the interposers and semiconductor dies at other horizontal heights higher than the bottom, they may be attached together using the reflow process for the solder bumps or similar structures formed between the higher horizontal heights. It can be understood that alternatively, the laser-assisted bonding process may be used to attach the interposers and semiconductor dies at all horizontal heights together.

[0040] Reference Figure 2C, a higher interposer 120-2 is attached to a relatively lower interposer 120-1 via solder bumps 125, and the two interposers 120-1 and 120-2 together form an interposer stack. The two interposers 120-1 and 120-2 together define a stepped structure 121 adjacent to the first semiconductor die 130-1 on the right side of the interposer stack. The stepped structure 121 includes two stepped surfaces 122-1 and 122-2 extending on the right sides of the first interposer 120-1 and the second interposer 120-2, respectively. As shown below, more interposers can be stacked above the substrate 110.

[0041] Still referring to Figure 2C , a higher semiconductor die 130-2 is attached to both a relatively lower semiconductor die 130-1 and a relatively lower interposer 120-1, preferably, the attachment is formed via solder bumps. It can be understood that the solder bumps 132-1 attached to the semiconductor die 130-2 can be non-functional bumps 132-1 that only provide mechanical support for the semiconductor die 130-2. In some embodiments, an epoxy resin is applied to the solder bumps 132-1 using a dipping process to assist the attachment between the solder bumps 132-1 and the underlying attached semiconductor die 130-1. The solder bumps 132-2 of the semiconductor die 130-2 can be attached to the exposed conductive patterns on the interposer 120-1 to achieve electrical connections with the interposer 120-1, with the substrate 110, and optionally with other electronic components such as the semiconductor die 130-1. Similar to Figure 2B the situation shown in Figures 4A to 4C , preferably, the height of the interposer 120-2 is similar to or the same as that of the semiconductor die 130-2. In some other embodiments, the attachment of the upper semiconductor die to the lower semiconductor die may include other techniques, such as bonding

[0042] Referring to Figure 2D , similar to Figure 2C , another higher interposer 120-3 is attached to a relatively lower interposer 120-2 via solder bumps, and another higher semiconductor die 130-3 is attached to both a relatively lower semiconductor die 130-2 and a relatively lower interposer 120-2, preferably, the attachment is formed via solder bumps. As shown in Figure 2D , the interposer 120-3 can form part of the interposer stack. Preferably, in the interposer stack, the interposers have a decreasing length or width from bottom to top. In this way, the top surface of the interposer can be at least partially exposed and can thus be used to attach components thereto.

[0043] Referring to Figure 2E, the interposer stack includes three interposers, and the interposer 120-3 farthest from the substrate 110 defines the top interposer. The semiconductor die 130-4 is attached to both the top interposer 120-3 and the semiconductor die 130-3. It can be understood that in some embodiments, other electronic components may be attached to the interposer 120-3 and the semiconductor die 130-3. For example, interposers and semiconductor dies of another layer may be attached.

[0044] Reference Figure 2F , a sealant layer 140 is formed on the substrate 110 to seal the interposers 120-1 to 120-3 and the semiconductor dies 130-1 to 130-4. The sealant layer 140 can be formed by depositing a sealant or a molding compound on the substrate 110 using injection molding, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable processes.

[0045] Reference Figure 2G , solder bumps 150 can be mounted on the bottom surface of the substrate 110. Thus, the electronic components on the substrate 110 can be electrically connected to external devices through the solder bumps 150.

[0046] Figures 2A to 2G The method shown simplifies the molding process for multiple layers. However, for the stability of the overall stack of multiple layers, the molding process can be performed several times rather than once. For example, first, a first sealant layer can be formed for the layers of several interposers and semiconductor dies stacked on the substrate. After that, additional interposers and semiconductor dies or multiple dies can be stacked thereon, and a second sealant layer can be formed on the first sealant layer, and so on.

[0047] Figures 3A to 3F Shows the steps of a method for forming a sealant layer multiple times according to an embodiment of the present application. When the sealant layer is formed multiple times, a relatively large number of layers can be stacked. Additionally, in some cases, due to defects in the components or height variations during the bonding process, the height of the components may change. Especially for the interposers and semiconductor dies of relatively high layers, the height error relative to the substrate may accumulate, and the interposers and semiconductor dies cannot be well aligned at the same horizontal height. For these cases, forming the sealant layer multiple times can help eliminate the accumulated height difference. Thus, for the interposers and semiconductor dies subsequently formed on the sealant layer, they can be unaffected by the accumulated height difference of the underlying layers. The steps of forming the sealant layer multiple times are shown below.

[0048] Reference Figure 3A , an interposer 120-1 and a semiconductor die 130-1 adjacent to the interposer 120-1 are formed on a substrate. In addition, an interposer 120-2 and a semiconductor die 130-2 are formed thereon. The formation of the components can be referred to Figures 2A to 2C for the description, which will not be repeated here. Different from the method shown above, in Figure 3A , a first sealant layer 140-1 is formed to seal the interposers 120-1, 120-2 and the semiconductor dies 130-1, 130-2.

[0049] Reference Figure 3B , an opening 141 is formed through the first sealant layer 140-1 to expose a conductive pattern on the top surface of the interposer 120-2. In some embodiments, the sealant layer 140-1 can completely seal the semiconductor die 130-2. That is, the top surface of the semiconductor die 130-2 is not exposed to the sealant layer 140-1. Preferably, as shown in Figure 3B , the top surface 133 of the semiconductor die 130-2 can be exposed. Processes such as film assisted molding, grinding, and / or plasma etching can be performed to remove the sealant material of the first sealant layer 140-1 above the semiconductor die 130-2 to expose the top surface 133 of the semiconductor die 130-2. Therefore, an electronic component can be directly attached to the top surface 133 of the semiconductor die 130-2, which is beneficial for heat dissipation because the semiconductor dies can be thermally connected together via non-functional bumps. In some embodiments, a thermal conductive layer can be formed on the top surface 133 of the semiconductor die 130-2 or on the first sealant layer 140-1 above the semiconductor die 130-2. The thermal conductive layer can be thermally connected but electrically isolated from the non-functional bumps that will be formed above the semiconductor die 130-2 later. The thermal conductive layer can extend to the side surface (e.g., the right side surface) of the first sealant layer 140-1 to provide a heat dissipation path from the inside to the outside of the semiconductor package. It can be understood that a similar thermal conductive layer such as a copper layer can be formed for other sealant layers or even other semiconductor dies. Preferably, laser ablation is used to form the opening.

[0050] Reference Figure 3C , an interposer 120-3 and a semiconductor die 130-3 are attached to the first sealant layer 140-1. Specifically, the interposer 120-3 is attached to a part of the conductive pattern exposed on the top surface of the interposer 120-2 through solder bumps 125 to be electrically connected to the interposer 120-2.

[0051] Still referring to Figure 3C, the semiconductor die 130-3 is attached to both the interposer 120-2 and the semiconductor die 130-2. Specifically, the semiconductor die 130-3 is attached to the encapsulant layer 140-1 through solder bumps to electrically connect the semiconductor die 130-3 at least partially to the conductive pattern exposed on the top surface of the interposer 120-2.

[0052] Reference Figure 3D , the semiconductor die 130-4 is attached to the interposer 120-3 and the semiconductor die 130-3.

[0053] Reference Figure 3E , the second encapsulant layer 140-2 is formed on the first encapsulant layer 140-1 to encapsulate the interposer 120-3, the semiconductor dies 130-3 and 130-4 on the first encapsulant layer 140-1. Reference Figure 3F , the solder bumps 150 can be mounted on the bottom surface of the substrate 110.

[0054] Figures 2A to 2G And Figures 3A to 3F illustrates two methods for manufacturing semiconductor packages such as the semiconductor package 100 shown in Figure 1 . In the above method for stacking semiconductor dies, when a higher semiconductor die is attached to a lower semiconductor die and a lower interposer, the attachment of the solder bumps of the higher semiconductor die can employ one or more of the methods shown in Figures 4A to 4C . Figures 4A to 4C Employ Figure 1 the semiconductor die 130-2 formed on both the interposer 120-1 and the semiconductor die 130-1 shown in

[0055] Reference Figure 4A , for the semiconductor die 130-2 attached with the solder bumps 132, a flux such as epoxy resin 160 is applied to the solder bumps 132 using a dipping process, and then the solder bumps 132 are attached to the underlying semiconductor die 130-1. Preferably, the solder bumps 132 applied with the epoxy resin 160 can be non-functional bumps that only provide mechanical support on the semiconductor die 130-1. This process is generally referred to as "epoxy flux dipping".

[0056] Reference Figure 4B, at least one dummy pad 170 is formed on the top surface of the lower semiconductor die 130-1, and the solder bumps 132 of the semiconductor die 130-2 can be attached to the dummy pad 170. In some embodiments, the dummy pad 170 can be formed by depositing and patterning a metallic material such as aluminum on the top surface of the semiconductor die 130-2. The dummy pad 170 can also be formed by sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), ink printing, etc. The dummy pad 170 can have a thickness significantly less than the height of the dummy bumps 132, which does not affect the horizontal alignment between the semiconductor die 130-2 and an interposer that is desired to be formed at the same horizontal height as the semiconductor die 130-2.

[0057] Reference Figure 4C , a pre-dot flux such as a pre-dot epoxy 180 can be dispensed on the semiconductor die 130-1. Preferably, the pre-dot epoxy 180 is dispensed at or near the periphery of the solder bumps 132. The pre-dot epoxy 180 has a predetermined height to maintain the separation distance between the lower semiconductor die 130-1 and the higher semiconductor die 130-2 during bonding and prevent interconnect defects.

[0058] The semiconductor package of the present application, such as Figure 1 the semiconductor 100 shown in Figure 5 and Figure 6 shown, can have other variations shown in Figure 5 . Specifically, as shown in Figure 6 , multiple interposers in the interposer stack can be integrally formed, or alternatively as shown in

[0059] Reference Figure 5 , the semiconductor package 200 includes a substrate 210, an interposer stack 220 formed on the substrate 210, and a plurality of semiconductor dies 230-1 to 230-4 stacked together on the substrate 210 and adjacent to the interposer stack 220. Similar to the above embodiments, the interposer stack 220 is mounted on the substrate 210 via solder bumps 224 and includes a plurality of interposers 220-1, 220-2, and 220-3. These interposers 220-1, 220-2, and 220-3 together define a stepped structure 221 on the side of the interposer stack 220. The interposers 220-1, 220-2, and 220-3 respectively include stepped surfaces 222-1, 222-2, and 222-3 that are exposed to the corresponding interposers for attachment to the corresponding semiconductor dies.

[0060] Still referring to Figure 5, a plurality of semiconductor dies 230-1 to 230-4 are preferably attached to the substrate 210 via solder bumps 231. Each semiconductor die may be partially attached to the substrate 210 or on one of the stepped surfaces 222-1, 222-2, and 222-3 of the stepped structure 221. A sealant layer 240 is also formed on the substrate 210, and the sealant layer seals the interposer stack 220 and the plurality of semiconductor dies 230-1 to 230-4. Preferably, the substrate 210 is mounted with solder bumps 250 for attaching the semiconductor package 200 to other electrical devices.

[0061] The semiconductor package 200 is different from Figure 1 the above-described semiconductor package 100 shown in Figures 7A to 7F . For illustrative purposes, in Figure 5 the interfaces between the layers are shown to distinguish different interposers.

[0062] Figure 6 FIG. shows a semiconductor package 300 according to another embodiment of the present application. As shown in Figure 6 FIG., the semiconductor package 300 is generally similar to Figure 5 the semiconductor package 200 shown in Figures 8A to 8E . Different from the semiconductor package 200, in the semiconductor package 300, the interposer stack 320 and the substrate 310 are integrally formed as a single piece. The method for forming the interposer stack 320 integrated with the substrate 310 can be referred to Figures 8A to 8E .

[0063] Figures 7A to 7F FIG. shows the steps for manufacturing Figure 5 the semiconductor package 200 with an integrated interposer stack shown in

[0064] Figures 2A to 2G Figures 2A to 2G To form the semiconductor package 200, similar to the method for manufacturing the semiconductor package 100 shown in Figures 2A to 2GThe steps of the method for manufacturing the semiconductor package 100 shown in the above can be referred to the above embodiments.

[0065] Figures 7A to 7E The formation of the integrated interposer stack is shown. Refer to Figure 7A , an interposer portion 420-1 of a layer with a connection structure is formed. The length of the interposer portion 420-1 can be Figure 5 twice the length of the interposer 220-1 shown in. The connection structure can include a set of die connection structures for further electrically coupling corresponding semiconductor dies on the stepped surface, and a set of interlayer connection structures extending through the layer of the connection structure. After forming the interposer portion 420-1, a barrier layer 422-1 is formed on the interposer portion 420-1. The barrier layer 422-1 helps to define the formation position of the stepped surface of the stepped structure of the interposer stack. Preferably, for the bottom interposer portion 420-1, the barrier layer 422-1 is formed at the central position along the extending direction X of the interposer portion 420-1, so that the interposer portion 420-1 can allow two interposer stacks symmetrical to each other to be manufactured at one time.

[0066] Specifically, the barrier layer 422-1 can have a material and composition similar to that of a non-functional layer. In some embodiments, the barrier layer 422-1 can include a release material, which can be any suitable material that allows the barrier layer 422-1 to be separated from the materials on both sides of the barrier layer 422-1 when sufficient force is applied. For example, the barrier layer 422-1 can be a silicone-based (silicon-based polymer) or a flaky material (such as talc). The barrier layer 422-1 can be formed using any suitable technique such as screenprinting. In some embodiments, the barrier layer 422-1 can be a metal layer, such as a copper layer serving as a laser drilling stop layer, which can absorb the thermal energy generated by the laser.

[0067] Refer to Figure 7B , an interposer portion 420-2 with a connection structure layer inside is further formed on the interposer portion 420-1. Specifically, the connection structure of the interposer portion 420-2 is formed at a position on the interposer portion 420-1 other than above the barrier layer 422-1, and a non-functional portion 423-1 is formed on the barrier layer 422-1.

[0068] Similar to Figure 7A the process shown in, in order to form the stepped structure, on the interposer portion 420-2 as shown in Figure 5A barrier layer 422-2 is further formed at the position of the stepped surface of the stepped structure shown in []. As described above, preferably, the method can form two integrated interposer stacks that are symmetric with each other at one time. Therefore, during each step of the method, the layout of the components on the substrate can be a generally symmetric layout, that is, a mirror layout. Specifically, the barrier layer 422-2 is formed symmetrically with respect to the center line C of the overall structure along the extending direction X. The barrier layer 422-2 is formed in the direction outward from the barrier layer 422-1. Specifically, along the direction X, a gap W is maintained between the adjacent edges of the barrier layer 422-2 and the barrier layer 422-1. As described below, the gap W is used to form an opening and remove non-functional parts. At the bottom of the opening, a corner of the stepped surface will be formed. Along the inner surface of the opening, an upright surface perpendicular to the stepped surface will also be formed. It can be understood that since the opening forms a corner for the stepped surface, the barrier layers 422-1 and 422-2 do not need to extend to the opening, that is, the corner of the lower stepped surface. Thus, the stepped surfaces other than the top stepped surface can be formed with corresponding barrier layers.

[0069] Reference Figure 7C , similar to Figure 7B in the process shown in [], an interposer part 420-3 is further formed on the interposer part 420-2, and a non-functional part 423-2 is further formed on the non-functional part 423-1 and the barrier layer 422-2. The non-functional parts 423-1 and 423-2 together constitute the non-functional part 423. Since no electrical connection is formed on the barrier layer, the areas on the barrier layers 422-1 and 422-2 define the non-functional part 423. The interposer parts 420-1 to 420-3 together constitute two interposer stacks 420. The interposer stack 420 and the non-functional part 423 together constitute an integrated interposer block 425. The integrated interposer block 425 is symmetric with respect to its center line C. Specifically, the two interposer stacks 420 are symmetric with respect to the non-functional part 423 therebetween.

[0070] Furthermore, a drilling process such as laser drilling is performed to form an opening 424 at the corner position of the lower stepped surface so as to expose the corner of the lower stepped surface. By forming the opening 424, an upright surface of the stepped structure of the interposer stack can be formed. In addition, the non-functional parts 423-1 and 423-2 can be easily removed because the side surfaces of the non-functional parts do not contact the interposer stack 420.

[0071] Reference Figure 7D, along the opening 424 and the barrier layers 422-1 and 422-2, the non-functional portion 423 is removed. As described above, the barrier layers 422-1 and 422-2 may use a release material having chemical and physical properties that allow the non-functional portion 423 to be removed from the barrier layers 422-1, 422-2 by applying mechanical force without deforming the interposer stack 420. Any suitable technique may be used to perform the removal of the non-functional portion 423 from the integrated interposer block 425. For example, a vacuum device may be used to remove the non-functional portion 423 and the interposer stack 420 from each other. Any suitable process may also be used to remove the barrier layers 422-1 and 422-2. After removing the barrier layers 422-1, 422-2 and the non-functional portion 423, two interposer stacks that are symmetric to each other are left, and the conductive patterns of the die connection structure are exposed to the corresponding stepped surfaces. Then a single split is performed at the center line C to split the two interposer stacks 420 from each other, with each piece being an interposer stack 420 as shown in Figure 7E as shown in the figure.

[0072] Refer to Figure 7F , the interposer stack 420 is attached to the top surface 411 of the substrate 410 via solder bumps 424. After attaching the interposer stack 420, a plurality of semiconductor dies may be sequentially stacked adjacent to the interposer stack 420, and a sealant layer may be formed on the substrate 410 to seal the components above, similar to Figures 2A to 2G as shown in the figure, to obtain Figure 5 the semiconductor package 200 as shown in the figure. The attachment of the plurality of semiconductor dies may refer to the above embodiments and will not be repeated here.

[0073] Different from Figures 2A to 2G the method shown in the figure, since the interposer stack 420 is integrally formed as a single piece, a plurality of semiconductor dies may be attached together at one time, and the higher semiconductor dies do not have to be attached after the bonding process for the lower semiconductor dies. This helps to simplify the manufacturing process and improve efficiency.

[0074] As described above in Figure 6 as shown in the figure, the interposer stack 320 and the substrate 310 may be formed together integrally. Figures 8A to 8E shows the steps for manufacturing a semiconductor package, where the interposer stack and the substrate are formed together integrally. The steps similar to those of the method for manufacturing the semiconductor package 200 shown in Figures 7A to 7F may refer to the above embodiments.

[0075] Refer to Figure 8A , a base substrate 510 is provided. The base substrate may have Figure 6Twice the length of the base of the semiconductor package 300 shown in []. A barrier layer 522-1 is formed on the top surface 511 of the base substrate 510. Preferably, the barrier layer 522-1 is located at the center along the extending direction X of the base substrate 510.

[0076] Reference Figure 8B , similar to Figure 7B and 7C In the process shown in [], a plurality of interposer layers are stacked at two opposite sides of the base substrate 510 to form two integrated interposer stacks 520. Barrier layers 522-2 and 522-3 are formed at the positions of the stepped surfaces, and a non-functional portion 523 is formed on the barrier layers 522-1, 522-2, and 522-3 between the two integrated interposer stacks 520. Thus, the base substrate 510, the two interposer stacks 520, and the non-functional portion 523 constitute an integrated interposer block 525.

[0077] Reference Figure 8C , openings 524 are formed at the edges of the barrier layers 522-1, 522-2, and 522-3 for removing the non-functional portion 523. Then, as Figure 8D shown in [], two integrated interposer stacks 520 integrated with the underlying base substrate 510 can be obtained. A singulation process is performed at the center line C on the base substrate 510 to singulate the base substrate 510 and the components thereon into two pieces, each piece being an integrated interposer stack 520 integrated with half of the base substrate 510, as Figure 8E shown. Here, each half of the base substrate 510 constitutes a substrate 510 integrated with the corresponding interposer stack 520.

[0078] After forming the integrated interposer stacks 520 and the substrate 510, a plurality of semiconductor dies can be stacked thereon. Other steps for manufacturing the semiconductor package can refer to the above embodiments.

[0079] In the method for manufacturing the semiconductor packages 200 and 300 shown respectively in Figure 5 and 6 [], since the interposer stack is integrally formed as a single piece, the height for attaching the corresponding semiconductor die is predetermined and does not change during the bonding process. The semiconductor dies can be stacked together first, and then only undergo one bonding process, which can greatly reduce the number of bonding processes and simplify the attachment process of the semiconductor dies.

[0080] The discussion herein includes a number of illustrative figures that show multiple steps of a method for manufacturing multiple semiconductor packages. For clarity of illustration, these figures do not show all aspects of every example component. Any example component and / or method provided herein may share any or all features with any or all other components and / or methods provided herein.

[0081] The various embodiments have been described with reference to the accompanying figures. However, it will be apparent that various modifications and changes can be made thereto, and additional embodiments can be implemented, without departing from the broader scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art by considering the specification and practice of one or more embodiments of the invention disclosed herein. Accordingly, the application and the embodiments herein are intended to be considered only as exemplary, with the true scope and spirit of the invention being indicated by the list of appended exemplary claims.

Claims

1. A method for manufacturing a semiconductor package, characterized in that, The method includes: Providing a package base; Attaching a first interposer to the package base via solder bumps; Attaching a first semiconductor die to the package base and adjacent to the first interposer; Attaching a second interposer to the first interposer via solder bumps to form an interposer stack, wherein the first interposer and the second interposer define a stepped structure at a side of the interposer stack adjacent to the first semiconductor die, and the stepped structure includes two stepped surfaces that extend from the first interposer and the second interposer respectively at the side of the interposer stack; Attaching a second semiconductor die to both the first semiconductor die and the first interposer; and Forming a first sealant layer on the package base to seal the first interposer, the second interposer, the first semiconductor die, and the second semiconductor die.

2. The method according to claim 1, characterized in that Providing a package base includes: Providing a substrate as the package base; or Providing a substrate having at least one electronic component mounted thereon as the package base, wherein the at least one electronic component together defines a flat surface.

3. The method according to claim 1, characterized in that Attaching a second semiconductor die to both the first semiconductor die and the first interposer includes: Applying a flux on solder bumps attached to the second semiconductor die using a dipping process; Attaching non-functional bumps of the second semiconductor die to non-functional pads of the first semiconductor die; and / or Dispensing a pre-applied flux on the first semiconductor die.

4. The method according to claim 1, wherein The method further includes: Forming an opening through the first sealant layer to expose a conductive pattern on a top surface of the second interposer.

5. The method according to claim 4, wherein The method further includes: Attaching a third semiconductor die to the first sealant layer via solder bumps to at least partially electrically connect the third semiconductor die to the exposed conductive pattern on the top surface of the second interposer.

6. The method according to claim 5, characterized in that The method further includes: Forming a second sealant layer to seal the first sealant layer and the third semiconductor die.

7. The method according to claim 4, characterized in that The method further includes: Attaching a third interposer to the first sealant layer via solder bumps to electrically connect a part of the third interposer to the exposed conductive pattern on the top surface of the second interposer.

8. The method according to claim 7, wherein The method further includes: Forming a second sealant layer to seal the first sealant layer and the third interposer.

9. The method according to claim 4, wherein Before forming the opening through the first sealant layer, the method further includes: Removing a sealant material of the first sealant layer above the second semiconductor die to expose a top surface of the second semiconductor die.

10. A method of manufacturing a semiconductor package, characterized in that, The method includes: Providing a substrate and a plurality of semiconductor dies; Forming an integrated interposer block that includes an interposer portion and a non-functional portion, and the interposer portion has a multi-layer connection structure; Remove the non-functional portion from the integrated interposer block to form an integrated interposer stack having a stepped structure on its side, wherein the integrated interposer stack includes a plurality of interposer layers, each of the plurality of interposer layers having one of the connection structures of the multi-layer connection structure and an exposed stepped surface at the stepped structure; Attach the integrated interposer stack to the substrate; Attach semiconductor dies to the substrate and adjacent to the integrated interposer stack; Attach at least two semiconductor dies to the integrated interposer stack, wherein each of the at least two semiconductor dies is partially attached on one of the exposed stepped surfaces; and Form a sealant layer on the substrate to seal the integrated interposer stack and the semiconductor dies.

11. The method according to claim 10, wherein Forming the integrated interposer block includes: Form the integrated interposer block including two interposer portions and a non-functional portion between the two interposer portions, wherein the two interposer portions are symmetric with respect to the non-functional portion; and wherein removing the non-functional portion from the integrated interposer block to form an integrated interposer stack having a stepped structure on its side includes: Remove the non-functional portion from the integrated interposer block; and Separate the two interposer portions into two pieces to obtain an integrated interposer stack having the stepped structure.

12. The method according to claim 10, wherein Forming the integrated interposer block includes: Form a multi-layer connection structure, wherein each layer's connection structure includes a set of die connection structures and a set of interlayer connection structures, and the set of interlayer connection structures extends through the connection structure of the layer; Form a barrier layer at the position of the lower stepped surface on the connection structure of the lower layer, wherein the corners of the lower stepped surface are not formed with the barrier layer, and the area on the barrier layer defines the non-functional portion of the integrated interposer block; Perform laser drilling at the corners of the lower stepped surface to expose the corners of the lower stepped surface; Remove the barrier layer and the non-functional portion from the integrated interposer block; and wherein After removing the non-functional portion from the integrated interposer block, the conductive patterns of the set of die connection structures are exposed at the corresponding stepped surfaces of the interposer layer for electrically coupling the corresponding semiconductor dies on the stepped surfaces.

13. The method according to claim 10, wherein Removing the non-functional portion from the integrated interposer block includes laser drilling the non-functional portion.

14. The method according to claim 10, wherein Attaching at least two semiconductor dies to the integrated interposer stack includes: Apply a flux on the solder bumps attached to one of the at least two semiconductor dies using a dipping process; Attach the non-functional bumps of one of the at least two semiconductor dies to the non-functional pads of the semiconductor die below the one semiconductor die; and / or Dispense a pre-dot flux on the at least two semiconductor dies and one of the semiconductor dies attached to the substrate.

15. A method of manufacturing a semiconductor package, characterized in that, The method includes: Provide a plurality of semiconductor dies; Form an integrated interposer block, the integrated interposer block including a substrate, an interposer portion, and a non-functional portion, the interposer portion having a multi-layer connection structure; Remove the non-functional portion from the integrated interposer block to form an integrated interposer stack integrated with the substrate, wherein the integrated interposer stack has a stepped structure on the side, wherein the integrated interposer stack includes a plurality of interposers, and each interposer of the plurality of interposers has one layer of the connection structure in the multi-layer connection structure and an exposed stepped surface at the stepped structure; Attach a semiconductor die on the substrate and adjacent to the integrated interposer stack; Attach at least two semiconductor dies to the integrated interposer stack, wherein each of the at least two semiconductor dies is partially attached on one of the exposed stepped surfaces; and Form a sealant layer on the substrate to seal the integrated interposer stack and the semiconductor die.

16. The method according to claim 15, characterized in that, Forming the integrated interposer block includes: Form the integrated interposer block, the integrated interposer block including two interposer portions on two substrates and an integrated interposer block between the two interposer portions, wherein the two interposer portions are symmetric to each other with respect to the non-functional portion; and wherein removing the non-functional portion from the integrated interposer block to form an integrated interposer stack integrated with the substrate includes: Remove the non-functional portion from the integrated interposer block; and Separate the two interposer portions and the two substrates into two pieces to obtain an integrated interposer stack integrated with the substrate.

17. The method according to claim 15, wherein Forming the integrated interposer block includes: Form a multi-layer connection structure on the substrate, wherein each layer of the connection structure includes a set of die connection structures and a set of interlayer connection structures, and the set of interlayer connection structures extends through the connection structure of the layer; Form a barrier layer at the position of the lower stepped surface on the lower layer of the connection structure, wherein the corner of the lower stepped surface is not formed with the barrier layer, and wherein the area on the barrier layer defines the non-functional portion of the integrated interposer block; Perform laser drilling at the corner of the lower stepped surface to expose the corner of the lower stepped surface; Remove the barrier layer and the non-functional portion from the integrated interposer block; and wherein After removing the non-functional portion from the integrated interposer block, the conductive pattern of the set of die connection structures is exposed at the corresponding stepped surface at the interposer for electrically coupling the corresponding semiconductor die on the stepped surface.

18. The method according to claim 15, wherein Removing the non-functional portion from the integrated interposer block includes laser drilling the non-functional portion.

19. The method according to claim 15, characterized in that, Attaching at least two semiconductor dies to the integrated interposer stack includes: Applying a flux on the solder bumps attached to one of the at least two semiconductor dies using a dipping process; Attach the non-functional bumps of one of the at least two semiconductor dies to the non-functional pads of the semiconductor die under the one semiconductor die; and / or Apply a pre - dot flux on at least two of the semiconductor dies and one of the semiconductor dies attached to the substrate.

20. A semiconductor package, characterized in that, The semiconductor package includes: A substrate; An interposer stack formed on the substrate, wherein the interposer stack includes a plurality of interposers stacked together and defining a stepped structure at the side of the interposer stack, and wherein the stepped structure includes at least two stepped surfaces exposing corresponding interposers in the interposer stack; A plurality of semiconductor dies stacked together on the substrate and adjacent to the stepped structure of the interposer stack, wherein each of the plurality of semiconductor dies is partially attached to the substrate or attached to one of the stepped surfaces of the stepped structure; and A sealant layer formed on the substrate, wherein the sealant layer seals the interposer stack and the plurality of semiconductor dies.

21. The semiconductor package according to claim 20, wherein The interposer stack is integrally formed together and mounted on the substrate via solder bumps.

22. The semiconductor package according to claim 20, wherein, The interposer stack and the substrate are integrally formed.

23. The semiconductor package according to claim 20, wherein, The plurality of interposers in the interposer stack are stacked on top of each other via solder bumps.

24. The semiconductor package according to claim 20, wherein, The lower semiconductor die of the plurality of semiconductor dies includes at least one non - functional pad on the top surface of the lower semiconductor die.

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