Semiconductor package

Abstract

A semiconductor package includes: a first semiconductor chip including a semiconductor substrate and an upper bonding pad disposed on an upper surface of the semiconductor substrate; and a bridge die disposed on the first semiconductor chip and including a bridge substrate and a first underpad. The bridging substrate includes a first bridging portion and a second bridging portion. The first lower pads are disposed on a first lower surface of the first bridge portion of the bridge substrate, and contact the upper bonding pads of the first semiconductor chip, respectively. When viewed in a plan view, the first bridge overlaps an edge portion of the first semiconductor chip, and the second bridge extends beyond a side of the first semiconductor chip in a direction away from the edge portion of the first semiconductor chip. The bridge die and the first semiconductor chip are different types of semiconductor devices.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0001457, filed with the Korean Intellectual Property Office on Jan. 4, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present inventive concept relates to a semiconductor package. Background Art

[0003] With the development of the electronics industry and user demands, electronic devices have become smaller and lighter, and there is a desire for semiconductor packages used in electronic devices to have high performance and high capacity, as well as miniaturization and weight reduction of the semiconductor packages. To achieve high performance and high capacity of semiconductor packages, as well as miniaturization and weight reduction of semiconductor packages, research and development of semiconductor chips including through-silicon vias (TSVs) and semiconductor packages in which semiconductor chips are stacked therein are continuously underway. Since the interconnection between multiple semiconductor chips may not be guaranteed by a printed circuit board, multiple semiconductor chips may be connected through a separate interposer. Summary of the Invention

[0004] One aspect of the present inventive concept is to provide a semiconductor package including stacked semiconductor chips having improved structural reliability.

[0005] According to an aspect of the present disclosure, a semiconductor package includes: a first semiconductor chip including a semiconductor substrate and a plurality of upper bonding pads disposed on an upper surface of the semiconductor substrate; and a bridge die disposed on the first semiconductor chip and including a bridge substrate and a plurality of first lower pads. The bridge substrate includes a first bridge portion and a second bridge portion. The plurality of first lower pads are disposed on a first lower surface of the first bridge portion of the bridge substrate and respectively contact the plurality of upper bonding pads of the first semiconductor chip. When viewed in a plan view, the first bridge portion overlaps an edge portion of the first semiconductor chip, and the second bridge portion extends beyond one side of the first semiconductor chip in a direction away from the edge portion of the first semiconductor chip. The bridge die and the first semiconductor chip are different types of semiconductor devices.

[0006] According to one aspect of the present disclosure, a semiconductor package includes: a redistribution structure including an insulating layer and an interconnect layer disposed within the insulating layer, and including a plurality of first upper contact pads and a plurality of second upper contact pads disposed on an upper surface of the insulating layer; a first semiconductor chip disposed on the redistribution structure and having a semiconductor substrate and a plurality of upper bonding pads disposed on an upper surface of the semiconductor substrate; at least one second semiconductor chip disposed around the first semiconductor chip on the redistribution structure; a bridging die disposed on the first semiconductor chip and including a bridging substrate and a plurality of first lower pads and a plurality of second lower pads disposed on a lower surface of the bridging substrate, wherein the bridging substrate includes a first bridging portion and a second bridging portion, wherein the plurality of first lower pads are disposed on a first lower surface of the first bridging portion of the bridging substrate and respectively contact the plurality of upper bonding pads, wherein the plurality of second lower pads are disposed on a second lower surface of the second bridging portion of the bridging substrate, wherein the first lower surface of the first bridging portion and the second lower surface of the second bridging portion are included in the lower surface of the bridging substrate, and wherein, when viewed in a plan view, the first bridging portion overlaps an edge portion of the first semiconductor chip and the second bridging portion extends beyond one side of the first semiconductor chip in a direction away from the edge portion of the first semiconductor chip; and a plurality of vertical conductive structures respectively connecting the plurality of second lower pads of the bridging die to the plurality of second upper contact pads of the redistribution structure.

[0007] According to one aspect of the present disclosure, a semiconductor package includes: a redistribution structure; a first semiconductor chip disposed on the redistribution structure; a plurality of second semiconductor chips disposed around the first semiconductor chip on the redistribution structure; a first type of bridging die partially overlapping the first semiconductor chip; a second type of bridging die partially overlapping the first semiconductor chip, wherein the area of the first type of bridging die is larger than the area of the second type of bridging die; and a plurality of vertical conductive structures connecting each of the first type of bridging die and the second type of bridging die to the redistribution structure. The first type of bridging die is electrically connected to M semiconductor chips among the plurality of second semiconductor chips. The second type of bridging die is electrically connected to N semiconductor chips among the plurality of second semiconductor chips. The first type of bridging die includes M memory controllers and a first cache memory. The second type of bridging die includes N memory controllers and a second cache memory. M is an integer equal to or greater than 2, N is an integer equal to or greater than 1, and M is greater than N. The memory capacity of the first cache memory is larger than the memory capacity of the second cache memory. Description of the Drawings

[0008] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings. Figure 1is a view showing a semiconductor package according to an exemplary embodiment of the inventive concept; Figure 2 is a schematic cross-sectional view taken along line I-I' of an exemplary embodiment; Figure 1 taken along line I-I' of an exemplary embodiment; Figure 3 is a plan view of the semiconductor package taken along line II-II'; Figure 1 of the semiconductor package taken along line II-II'; Figure 4 is Figure 2 an enlarged cross-sectional view of region “A” of the semiconductor package; Figure 5 and Figure 6 is an enlarged cross-sectional view showing a semiconductor package according to another exemplary embodiment of the inventive concept; Figures 7 to 9 is a plan view showing a semiconductor package according to an exemplary embodiment of the inventive concept; Figure 10 is a cross-sectional view of the semiconductor package taken along line III-III'; Figure 9 taken along line III-III'; and Figures 11 to 13 is a plan view showing a semiconductor package according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0009] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0010] Figure 1 is a view showing a semiconductor package according to an exemplary embodiment of the inventive concept, Figure 2 is a schematic cross-sectional view taken along line I-I' of an exemplary embodiment, Figure 1 taken along line I-I' of an exemplary embodiment, Figure 3 is a plan view of the semiconductor package taken along line II-II', and Figure 1 is Figure 4 is Figure 2 an enlarged cross-sectional view of region “A” of the semiconductor package.

[0011] Referring to Figures 1 to 4, the semiconductor package 300 may include a package substrate 311, an interposer 100, and a plurality of semiconductor chips 210, 220, and 250. In one example, the semiconductor package 300 may further include a first semiconductor chip (e.g., a logic chip or a processor chip) 210 disposed on the interposer 100 adjacent to at least one second semiconductor chip (e.g., a memory semiconductor chip) 220, and at least one bridging die 250 disposed on the processor chip 210. In one embodiment, the bridging die 250 and the first semiconductor chip 210 may be different types of semiconductor devices. In one embodiment, the bridging die 250 may be repeatedly placed on the upper surface of the first semiconductor chip 210 to form a plurality of bridging dies.

[0012] In one exemplary embodiment, the package substrate 311 may include a substrate body, an upper pad (or upper solder pad) 324 disposed on the upper surface of the substrate body, a lower pad 322 disposed on the lower surface of the substrate body, and a redistribution circuit 330 that electrically connects the upper pad 324 and the lower pad 322 to each other. In one example, the package substrate 311 may be a support substrate on which the interposer 100, the processor chip 210, the bridging die 250, and the memory semiconductor chip 220 are mounted, and may be a substrate for a semiconductor package including a printed circuit board (PCB), a ceramic substrate, a glass substrate, or a tape wiring substrate.

[0013] In an example embodiment, the body of the encapsulation substrate 311 may include different materials depending on the type of the substrate. For example, when the encapsulation substrate 311 is a printed circuit board, the encapsulation substrate 311 may have a form of "an interconnect layer additionally stacked on one side or opposite sides of a body copper-clad laminate or a copper-clad laminate". In one example, a solder mask layer may be formed on the lower surface and the upper surface of the encapsulation substrate 311. The upper pad 324, the lower pad 322, and the redistribution circuit 330 may form a circuit path between the upper surface and the lower surface of the encapsulation substrate 311. The upper pad 324, the lower pad 322, and the redistribution circuit 330 may include a metal material or may be formed of a metal material. The upper pad 324, the lower pad 322, and the redistribution circuit 330 may include at least one metal (such as copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), carbon (C), and alloys including two or more of these metals) or may be formed of at least one metal (such as copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), carbon (C), and alloys including two or more of these metals). In one example, the redistribution circuit 330 may include a multi-layer redistribution layer and vias connecting the multi-layer redistribution layers. The external connection terminal 380 connected to the lower pad 322 may be provided on the lower surface of the encapsulation substrate 311. In one example, the external connection terminal 380 may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or their alloys, or may be formed of tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or their alloys.

[0014] In an exemplary embodiment, the interposer 100 may include a substrate 110, a lower protective layer 120, an underfill 130, bumps 140, through electrodes 150, and an interconnect structure 170 (i.e., a redistribution structure). In one example, a plurality of semiconductor chips 210, 220, and 250 may be stacked on a package substrate 311 via the interposer 100. In one example, the interposer 100 may electrically connect the plurality of semiconductor chips 210, 220, and 250 to each other. In one example, the substrate 110 may be formed of any one of a silicon substrate, an organic substrate, a plastic substrate, and a glass substrate. When the substrate 110 is a silicon substrate, the interposer 100 may be referred to as a silicon interposer 100. When the substrate 110 is an organic substrate, the interposer 100 may be referred to as a panel interposer 100. In one example, the lower protective layer 120 may be disposed on the lower surface of the substrate 110, and the underfill 130 may be disposed below the lower protective layer 120. The underfill 130 may be connected to the through electrodes 150. The plurality of semiconductor chips 210, 220, and 250 and the package substrate 311 may be electrically connected to the bumps 140 disposed below the underfill 130.

[0015] In an exemplary embodiment, the interconnect structure 170 may be disposed on the upper surface of the substrate 110 and may include an insulating layer 171 and a single or multiple interconnect layers 172. When the interconnect structure 170 has a multi-layer wiring structure, the wirings in different layers may be connected to each other through vertical contacts.

[0016] In an exemplary embodiment, the through electrodes 150 may extend from the upper surface of the substrate 110 to the lower surface of the substrate 110 and penetrate the substrate 110. The through electrodes 150 may extend into the interior of the interconnect structure 170 and be electrically connected to the interconnect layers of the interconnect structure 170. The present disclosure is not limited thereto. The through electrodes 150 may extend up to the upper surface of the substrate 110 to contact the lower surface of the insulating layer 171. In one example, when the substrate 110 is a silicon substrate, the through electrodes 150 may be referred to as through-silicon vias (TSVs, or silicon through vias). In one example, the interposer 100 may include only the interconnect layers 172 in the interposer 100 without the through electrodes 150.

[0017] In an exemplary embodiment, the interposer 100 may be used to convert or transfer input electrical signals between the package substrate 311 and the plurality of semiconductor chips 210, 220, and 250. That is, the interposer 100 may not include elements such as active elements (such as transistors) or passive elements (such as capacitors and resistors).

[0018] In an exemplary embodiment, the interconnect structure 170 may be disposed above the through electrodes 150. For example, the setting relationship between the interconnect structure 170 and the through electrodes 150 may be relative.

[0019] In an example embodiment, the bumps 140 may be disposed on the lower surface of the interposer 100 and may be electrically connected to the wiring of the interconnect structure 170. The interposer 100 may be stacked on the package substrate 311 via the bumps 140. The bumps 140 may be connected to the interconnect layer 172 of the interconnect structure 170 through the vias 150 and the lower pads 130. In one example, the bumps 140 may be repeatedly placed to form a plurality of bumps 140, and the lower pads 130 may be repeatedly placed to form a plurality of lower pads 130. Some of the pads for power or ground in the lower pads 130 may be integrated and connected together to the corresponding bumps in the bumps 140, such that the number of the lower pads 130 may be greater than the number of the bumps 140.

[0020] In an example embodiment, the interposer 100 may further include upper pads 160 (i.e., upper contact pads) on the insulating layer 171 of the interconnect structure 170. For example, the interconnect structure 170 may include the upper pads 160.

[0021] Referring to Figure 3 and Figure 1 , the upper pads 160 may be disposed on the insulating layer 171 of the interconnect structure 170 of the interposer 100 and may include a first upper pad 160a (i.e., first upper contact pad) disposed under the semiconductor chips 210 and 220 and a second upper pad 160b (i.e., second upper contact pad) connected to the bridge die 250. In one embodiment, when viewed in a plan view, a plurality of bridge dies 250 may define a central region of the first semiconductor chip 210 and may be arranged symmetrically with respect to the central region of the first semiconductor chip 210.

[0022] According to the plurality of semiconductor chips 210 and 220 disposed on the upper surface of the interposer 100, the upper pads 160 disposed on the upper surface of the interposer 100 may be assigned to each of the processor chip region 210A, the memory structure region 220A, and the bridge die region 250A. Specifically, the first upper pad 160a attached to the connection bumps 216 of the first semiconductor chip 210 may be disposed in the processor chip region 210A where the first semiconductor chip 210 serving as a processor is disposed. The first upper pad 160a may also be disposed in the memory structure region 220A where the second semiconductor chip 220 serving as a memory structure is disposed. The first upper pads 160a disposed in each of the processor chip region 210A and the memory structure region 220A may have substantially the same area and may have a circular or square planar shape. Terms such as "same", "equal", "planar", or "coplanar" as used herein encompass near sameness including variations that may occur, for example, due to manufacturing processes. Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize such meaning.

[0023] Meanwhile, a bridging die 250 is disposed outside the first semiconductor chip 210, and a protruding area above the first semiconductor chip 210 can be defined as a bridging die area 250A, and the bridging die area 250A can be disposed in a continuous position without overlapping with the processor chip area 210A.

[0024] The second upper pad 160b can be disposed within the bridging die area 250A. The vertical bump 240 can be disposed on the second upper pad 160b to contact the second lower pad 253b of the bridging die 250 in the Z direction perpendicular to the upper surface of the package substrate 311. For example, the vertical bump 240 can connect the second upper pad 160b to the second lower pad 253b of the bridging die 250 respectively. In one embodiment, the vertical conductive structure for electrically connecting the bridging die 250 to the interconnect structure 170 outside the first semiconductor chip 210 can include the vertical bump 240 longitudinally extending in the Z direction.

[0025] In one embodiment, each first upper pad 160a can have a first width W1 and a first area, and each second upper pad 160b can have a second width W2 and a second area. The second width W2 can be greater than the first width W1. The second area can be greater than the first area. Additionally, the second upper pad 160b can have the same shape as the first upper pad 160a (e.g., circular shape), but can have a prism shape according to the embodiment. When the second upper pad 160b has a circular or prism shape, the second area of the second upper pad 160b can be greater than the first area of the first upper pad 160a.

[0026] The second upper pads 160b disposed in the bridging die area 250A can be spaced apart from each other by a separation distance equal to or greater than the minimum separation distance. The minimum separation distance can be a separation distance in the range of 10 μm to 100 μm. In one embodiment, the minimum separation distance of the second upper pads 160b can be greater than the separation distance between the first upper pads 160a.

[0027] The semiconductor package 300 according to this embodiment can include a bridging die 250, a first semiconductor chip 210, and a second semiconductor chip 220 mounted on the interposer 100. In one embodiment, the bridging die 250 can be repeatedly placed to form four bridging dies. The number of bridging dies can have a number different from four. The first semiconductor chip 210 can be disposed to partially overlap each bridging die 250, and complex signal lines in the physical layer (PHY) area can be connected to each other through the bridging die 250. When the semiconductor package 300 is intercepted in a plan view (see Figure 1 and Figure 3), a part of the functional blocks in the first semiconductor chip 210 is formed and configured as a separate chip structure (chipletz) of the bridge die 250, so that the area occupied by the first semiconductor chip 210 in the semiconductor package 300 can be reduced, and the area occupied by the memory semiconductor chip 220 can be ensured. Additionally, a part of the functional blocks included in the first semiconductor chip 210 (e.g., semiconductor structures such as cache memories) and the functional blocks directly connected to the second semiconductor chip 220 (such as memory controllers) can be mounted on the bridge die 250 as separate chip structures. By forming the functional blocks of the first semiconductor chip 210 as separate chip structures and arranging the separate chip structures to be stacked with the first semiconductor chip 210, the area of the first semiconductor chip 210 can be reduced and more memory chips can be mounted.

[0028] The second semiconductor chip 220 adopted in this embodiment may include high-bandwidth memory chips. The second semiconductor chip 220 may include a plurality of (e.g., four) memory chips stacked and connected to each other. The plurality of memory chips may respectively include a semiconductor substrate having an active surface and an inactive surface opposite to each other, a through electrode penetrating the semiconductor substrate, an upper pad, and a lower pad. The upper pad of one memory chip may be connected to the lower pad of an adjacent memory chip. The lower pad of the memory chip disposed at the bottom may be connected to the redistribution pattern through a connection bump.

[0029] In a system where a plurality of independent semiconductor chips are packaged into one package, the number of memory dies included in the second semiconductor chip 220 may vary according to the purpose of the semiconductor package 300. That is to say, the number of memory dies included in the second semiconductor chip 220 is not limited to the number shown in the drawings. Each memory die in the second semiconductor chip 220 may be bonded to another adjacent memory die through a bonding member (not shown), and the memory dies may be stacked on each other. The bonding member may be a non-conductive film.

[0030] In one exemplary embodiment, the space between the second semiconductor chip 220 and the interconnect structure 170 and the space between the plurality of memory dies in the second semiconductor chip 220 may be filled with a bonding material layer, and the side surfaces of the plurality of memory dies in the second semiconductor chip 220 may be surrounded. In one example, the bonding material layer may include an epoxy resin material or may be formed of an epoxy resin material. For example, the bonding material layer may be a non-conductive film (NCF), and the exemplary embodiments of the bonding material layer are not limited to such materials.

[0031] In an example embodiment, the molding layer 270 may be provided to cover the second semiconductor chip 220 and the adhesive material layer, and protect the second semiconductor chip 220 and the adhesive material layer from the external environment. In one example, the molding layer 270 may include an insulating material containing a resin material (such as, epoxy molding compound (EMC)) or may be formed of an insulating material containing a resin material (such as, epoxy molding compound (EMC)).

[0032] In some example embodiments, the second semiconductor chip 220 may include a volatile memory die and / or a non-volatile memory die. The volatile memory die may be, for example, a dynamic random access memory (RAM) (DRAM), a static RAM (SRAM), a thyristor RAM (TRAM), a zero-capacitor RAM (ZRAM), or a two-transistor RAM (TTRAM). Additionally, the non-volatile memory die may be, for example, a flash memory, a magnetic RAM (MRAM), a spin-transfer torque MRAM (STT-MRAM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a resistive RAM (RRAM), a nanotube RRAM, a polymer RAM, or an insulator resistance change memory. The second semiconductor chip 220 may include a substrate at the bottom of the second semiconductor chip 220, and may include lower bonding pads 224 under the substrate. The lower bonding pads 224 may be connected to the first upper pads 160a through connection bumps 225, and the lower bonding pads 224 and the connection bumps 225 may be protected by an underfill 235. For example, the underfill 235 may fill the space between the second semiconductor chip 220 and the interconnect structure 170 and surround each connection bump 225. The molding layer 270 may cover and contact the exposed surface of the underfill 235 between the second semiconductor chip 220 and the interconnect structure 170.

[0033] In an example embodiment, the first semiconductor chip 210 is a processor chip, and may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, a chipset, an audio codec, a video codec, an application processor, a system-on-chip, or an application specific integrated circuit (ASIC). Depending on the type of elements included in the first semiconductor chip 210, the semiconductor package 300 may be classified as a server-oriented semiconductor package or a mobile-oriented semiconductor package.

[0034] The first semiconductor chip 210 may include a semiconductor substrate 211 having an active surface and an inactive surface opposite to each other, and a lower bonding pad 215 on the lower surface of the semiconductor substrate 211. The lower bonding pad 215 may be connected to the first upper pad 160a through a connection bump 216. The lower bonding pad 215 may include a surface treatment layer formed to act as a pad. The surface treatment layer is not specifically limited as long as it is known in the art, and may be formed by, for example, electrolytic gold plating, chemical gold plating, organic solderability preservative (OSP), electroless tin plating, electroless silver plating, electroless nickel / immersion gold plating, direct immersion gold (DIG), or hot air solder leveling (HASL), but the exemplary embodiments thereof are not limited thereto. In this embodiment, the first semiconductor chip 210 may further include a dielectric layer 212 (i.e., an upper insulating layer) on the upper surface of the semiconductor substrate 211 and an upper bonding pad 213 formed on the dielectric layer 212. The upper bonding pad 213 of the first semiconductor chip 210 may contact a first lower pad 253a provided on the lower surface of the bridging die 250. In one embodiment, the first lower pad 253a of the bridging die 250 may be used as a bonding pad for contacting the upper bonding pad 213 to form a metal indirect bond DB1, which will be described later.

[0035] Underfill 231 around the connection bump 216 and underfill 235 around the connection bump 225 may be formed between the first semiconductor chip 210 and the second semiconductor chip 220 and the interconnect structure 170. The underfills 231 and 235 may stably fix the first semiconductor chip 210 and the second semiconductor chip 220 to the interposer 100. For example, the underfills 231 and 235 may be formed of a curable resin (such as an epoxy resin).

[0036] Referring to Figure 1 and Figure 3 , in the semiconductor package 300 according to this embodiment, the first semiconductor chip 210 may be disposed in the central region on the upper surface of the interposer 100, and the second semiconductor chip 220 may be adjacent to the first semiconductor chip 210. The number of the second semiconductor chips 220 may be set differently, and in Figures 1 to 4 , four second semiconductor chips 220 may be disposed such that two of the second semiconductor chips may be disposed on the left side of the first semiconductor chip 210, and the other second semiconductor chips may be disposed on the right side of the first semiconductor chip 210.

[0037] The two second semiconductor chips 220 disposed on one side of the first semiconductor chip 210 may be disposed side by side in the Y direction and may be disposed to have a first separation distance I1 from the first semiconductor chip 210.

[0038] At least one bridging die 250 may be disposed on the first semiconductor chip 210. As described above, the bridging die 250 may be formed by forming some of the functional blocks of the first semiconductor chip 210 into separate chip structures, and may include Figures 1 to 4 the memory controller and cache memory in

[0039] The memory controller may be a functional block connected to each second semiconductor chip 220, and may write data to the second semiconductor chip or read data stored in the second semiconductor chip by transmitting and receiving signals. Accordingly, one memory controller may be disposed on each second semiconductor chip 220. Multiple cache memories may be applied to the processor, and the cache memory is a buffer memory between the first semiconductor chip 210 as a fast memory semiconductor chip and the second semiconductor chip as a slow memory semiconductor chip. The cache memory may be defined as a general-purpose memory that compensates for the speed difference for storing data in the second semiconductor chip 220 and using the data for the operation of the first semiconductor chip 210. As the functions of the processor improve, it is desired that this type of cache memory has a higher memory storage capacity. The higher the capacity of the cache memory, the better the performance of the semiconductor package 300. The cache memory may be classified into an L1 cache memory, an L2 cache memory, and an L3 cache memory, and the L1 cache memory may be a memory that is generally built in the first semiconductor chip 210 and is first used for data usage and reference. The L2 cache memory performs a similar function to the L1 cache memory, but when the L1 cache memory is first used and the desired data does not exist in the L1 cache memory, the processor may search the L2 cache memory. The L2 cache memory may be slower than the L1 cache memory, but faster than the general-purpose memory (RAM).

[0040] The L3 cache memory may perform a similar function to the L1 cache memory and the L2 cache memory, and may act as a memory for finding data not covered by the L2 cache memory. Accordingly, when searching for data in the first semiconductor chip 210, access may be performed in the order of the L1-L2-L3 cache memories, and the higher the capacity of the L3 cache memory, the better the performance of the semiconductor package may be considered. Accordingly, there is a continuous need for an expansion of the capacity of the L3 cache memory, which may lead to an increase in the size of the first semiconductor chip 210. An increase in the size of the first semiconductor chip 210 on the semiconductor package 300 (i.e., the interposer 100) having a predetermined area may reduce the number of second semiconductor chips 220, which may lead to an increase in the vertical stacking of the second semiconductor chips 220, which may lead to an increase in the process burden and an increase in the total height of the package.

[0041] In an exemplary embodiment of the inventive concept, among some functional blocks of the first semiconductor chip 210, a memory controller and an L3 cache memory, which are most closely related to the second semiconductor chip 220, are separate chip structures, and such chip structures may be provided as bridge dies 250 on the first semiconductor chip 210.

[0042] At least one bridge die 250 may be provided on the first semiconductor chip 210, and as Figures 1 to 4 shown, the bridge die 250 may be provided in one-to-one correspondence with each second semiconductor chip 220. Accordingly, when four second semiconductor chips 220 are provided around one first semiconductor chip 210, four bridge dies 250 may be provided on the first semiconductor chip 210.

[0043] Each bridge die 250 may have the same area and the same shape, and may protrude from the first semiconductor chip 210 toward each corresponding second semiconductor chip 220. Specifically, in the X-Y plane, the bridge die 250 may include a first region 250a (i.e., a first bridge portion) located on the first semiconductor chip 210 and a second region 250b (i.e., a second bridge portion) protruding outside the first semiconductor chip 210. The area of the first region 250a may be larger than the area of the second region 250b, but exemplary embodiments thereof are not limited thereto.

[0044] When a plurality of bridge dies 250 are provided on the first semiconductor chip 210, the plurality of bridge dies 250 may not be provided in the central region of the first semiconductor chip 210, but may be restrictedly provided in each corner region or edge region of the first semiconductor chip 210. A large amount of heat may be generated in the central region of the first semiconductor chip 210, and thus a device layer may not be provided, and a heat dissipation chip or a heat dissipation layer may be provided on the central region, but exemplary embodiments thereof are not limited thereto. The plurality of bridge dies 250 may be spaced apart from each other on the first semiconductor chip 210, and may be provided such that the second region 250b overlaps with a separation space between the first semiconductor chip 210 and the second semiconductor chip 220. In this case, the second region 250b may not overlap with the second semiconductor chip 220 in the Z direction, and may satisfy a separation distance I2 to be spaced apart from each other. For example, the bridge die 250 may be spaced apart from the second semiconductor chip 220 adjacent to the bridge die 250 by the separation distance I2. Each bridge die 250 may be provided such that the first region 250a contacts the upper surface of the first semiconductor chip 210. For example, each bridge die 250 may be partially overlapped with the upper surface of the first semiconductor chip 210. Refer to Figure 1 and Figure 4 for a description of each bridge die 250.

[0045] The bridging die 250 may have a first region 250a attached to the first semiconductor chip 210 and a second region 250b protruding outside the first semiconductor chip 210 to overlap with the partition space. The bridging die 250 can be used to connect the first semiconductor chip 210 and the second semiconductor chip 220 to each other.

[0046] Referring Figure 4 , the bridging die 250 adopted in this embodiment includes a semiconductor block 251 (i.e., a bridging substrate), a dielectric layer (as a lower insulating layer) 252 provided on the lower surface of the semiconductor block 251, and an interconnect layer 254 formed in the dielectric layer 252. In this specification, the bridging die 250 is referred to as a "semiconductor bridge". The interconnect layer 254 may include lower pads 253 provided on the lower surface of the bridging die 250. The semiconductor block 251 may be, for example, a silicon (Si) block. The interconnect layer 254 may include conductive patterns and vias connecting the conductive patterns. The conductive patterns and vias can be formed into a fine structure using semiconductor processes. The conductive patterns of the interconnect layer 254 may have a small width. For example, the width and pitch of the conductive patterns may be 1 μm or less, respectively.

[0047] The lower pads 253 may include a first lower pad 253a provided in the first region 250a and a second lower pad 253b provided in the second region 250b.

[0048] The first lower pad 253a may contact the upper bonding pad 213 of the first semiconductor chip 210 to form a physical / electrical connection, and the second lower pad 253b may be connected to the vertical bump 240 to connect to the second upper pad 160b of the interposer 100. For example, the first lower pad 253a of the bridging die 250 can be used as a bonding pad that contacts the upper bonding pad 213 of the first semiconductor chip 210, and the second lower pad 253b of the bridging die 250 can be used as a contact pad that connects to the vertical bump 240.

[0049] The second lower pad 253b may be stacked with the second upper pad 160b of the interposer 100 in the Z direction and may be electrically / physically connected to the second upper pad 160b through the vertical bump 240, and the vertical bump 240 extends longitudinally along a straight line extending in the Z direction.

[0050] In one embodiment, each first underpad 253a of the bridging die 250 may have a third width W3 and a third area, and each second underpad 253b of the bridging die 250 may have a fourth width W4 greater than the third width W3 and a fourth area greater than the third area. The shapes of the second underpad 253b and the first underpad 253a may be different from each other. For example, the first underpad 253a may have a circular or square shape (such as a shape similar to that of the first upper pad 160a of the interposer 100), and the second underpad 253b may have a circular or square shape. In one embodiment, the lower surfaces of the first underpad 253a and the second underpad 253b may be at the same height.

[0051] The bridging die 250 and the first semiconductor chip 210 may be connected by hybrid bonding, which is a connection process between semiconductor chips. Specifically, the first underpad 253a of the bridging die 250 may be directly bonded to the upper bonding pad 213 of the first semiconductor chip 210 to form a metal indirect bond DB1. The metal indirect bond DB1 may bond the bridging die 250 to the first semiconductor chip 210 and at the same time ensure electrical connectivity between the bridging die 250 and the first semiconductor chip 210. The dielectric layer 252 may be formed on the lower surface of the semiconductor block 251. The dielectric layer 252 may have a substantially flat lower surface flush with the first underpad 253a. For example, the first underpad 253a may be exposed on the lower surface of the dielectric layer 252. The dielectric layer 212 of the first semiconductor chip 210 and the lower bonding insulating layer (e.g., the dielectric layer 252) of the bridging die 250 may be directly bonded to form a dielectric indirect bond DB2. There may be no adhesive layer at the metal indirect bond DB1 and the dielectric indirect bond DB2. In one embodiment, contacts 214 may also be provided in the dielectric layer 212.

[0052] In this embodiment, the vertical bump 240 employed is a conductive pillar and can be set as a path for vertically connecting the interposer 100 and the bridging die 250 to each other. The vertical bump 240 can be formed through multiple electroplating processes (e.g., once) to form the desired height of the vertical bump 240. The present disclosure is not limited thereto. In one embodiment, the vertical bump 240 can be an integrated pillar formed of a single layer. The vertical bump 240 can be implemented as an alloy including a conductive material (such as copper), but the exemplary embodiments thereof are not limited thereto. The vertical bump 240 can connect the second upper pad 160b of the interposer 100 and the second lower pad 253b of the bridging die 250. The second upper pad 160b of the interposer 100 can have an area larger than that of the first upper pad 160a of the interposer 100. The second lower pad 253b of the bridging die 250 can have an area larger than that of the first lower pad 253a. Additionally, the vertical bump 240 can be set to be spaced apart from adjacent vertical bumps 240 to have a predetermined separation distance. The predetermined separation distance can be a separation distance in the range of 200 μm to 400 μm. In one embodiment, the predetermined separation distance can be in the range of 250 μm to 350 μm. In one embodiment, the predetermined separation distance can be in the range of 200 μm to 300 μm. In one embodiment, the vertical bump 240 can have a fifth width W5 smaller than the width of the second upper pad 160b (e.g., the second width W2) and the width of the second lower pad 253b (e.g., the fourth width W4). The fifth width W5 can have a value in the range of 150 μm to 250 μm.

[0053] The molding layer 270 can seal the upper surfaces of the first semiconductor chip 210, the second semiconductor chip 220, and the bridging die 250 to protect the first semiconductor chip 210, the second semiconductor chip 220, and the bridging die 250 from the external environment. In the molding layer 270, an appropriate amount of molding resin can be injected into the upper surface of the interposer 100, and the exterior of the semiconductor package 300 can be formed through a curing process. In some exemplary embodiments, the molding resin can include an epoxy group molding resin or a polyimide group molding resin. The molding layer 270 can be used to protect the first semiconductor chip 210 and the second semiconductor chip 220 from external influences (such as collision, etc.). In some exemplary embodiments, the molding layer 270 can be formed to surround the upper surfaces of the first semiconductor chip 210 and the second semiconductor chip 220. In other exemplary embodiments, the molding layer 270 can be formed to expose the upper surfaces of the first semiconductor chip 210 and the second semiconductor chip 220 to the outside.

[0054] The semiconductor package 300 employed in this embodiment may further include a heat dissipation member 390. The heat dissipation member 390 may be, for example, a heat sink or a radiator. The heat dissipation member 390 may be in contact with the upper surface of the package substrate 311 and may be disposed to surround the semiconductor package 300. The heat dissipation member 390 may directly contact the upper surfaces of the first semiconductor chip 210 and the second semiconductor chip 220, but the exemplary embodiments are not limited thereto. Unless the context otherwise indicates, the term "contact" or "in contact with" as used herein refers to direct connection (i.e., physical touch).

[0055] In some exemplary embodiments, a thermal interface material (TIM) layer may be disposed between the heat dissipation member 390 and the upper surfaces of the first semiconductor chip 210 and the second semiconductor chip 220. In some exemplary embodiments, the heat dissipation member 390 may be formed with an electromagnetic interference (EMI) shielding layer, and the electromagnetic interference (EMI) shielding layer may be electrically connected to the ground layer of the package substrate 311.

[0056] Figure 5 and Figure 6 are enlarged cross-sectional views showing a semiconductor package according to an embodiment of the inventive concept. Figure 5 and Figure 6 is Figure 2 an enlarged cross-sectional view of region "A" in (corresponding to Figure 4 ).

[0057] Referring to Figure 5 , except that the first semiconductor chip 210 having a different structure is employed, the semiconductor package 300a according to this embodiment is similar to the semiconductor package 300 described with reference to Figures 1 to 4 . Unless otherwise stated, the description of the components of this embodiment may refer to the description of the same or similar components of the semiconductor package 300 as shown in Figures 1 to 4 .

[0058] Figure 5The semiconductor package 300a may include a through electrode 217 (i.e., a first through electrode) that penetrates the first semiconductor chip 210 and connects the upper bonding pad 213 of the first semiconductor chip 210 and the interconnect layer 232 to each other. The through electrode 217 may extend from the upper surface of the semiconductor substrate 211 to the lower surface and penetrate the semiconductor substrate 211. The through electrode 217 may extend to the interconnect structure 230 and may be electrically connected to the interconnect layer 232 through the wiring pad 233 of the interconnect structure 230. For example, the upper bonding pad 213 and the wiring pad 233 of the interconnect structure 230 may be stacked in the Z direction, and the through electrode 217 extending along a straight line extending in the Z direction may connect the upper bonding pad 213 and the wiring pad 233. In one example, when the semiconductor substrate 211 is formed of silicon, the through electrode 217 may be referred to as a through-silicon via (TSV).

[0059] Referring to Figure 6 , except for the first semiconductor chip 210 and the bridging die 250 having different structures, the semiconductor package 300b according to this embodiment is similar to the semiconductor package 300 as referred to in Figures 1 to 4 . Unless otherwise stated, the description of the components of this embodiment may refer to the description of the same or similar components of the semiconductor package 300 as shown in Figures 1 to 4 .

[0060] Figure 6 The semiconductor package 300b may include a through electrode 217 that penetrates the first semiconductor chip 210 and connects the upper bonding pad 213 and the lower interconnect layer 232 to each other, and the bridging die 250 may include a through electrode 255 (i.e., a second through electrode) that penetrates the semiconductor block 251. The through electrode 217 of the first semiconductor chip 210 may be the same as the through electrode 217 described in Figure 5 . The bridging die 250 may further include a redistribution structure under the semiconductor block 251. The redistribution structure of the bridging die 250 may include a dielectric layer 252 and an interconnect layer 254. It can be understood that the interconnect layer 254 includes a first lower pad 253a and a second lower pad 253b.

[0061] The through electrode 255 of the bridging die 250 may extend from the upper surface of the semiconductor block 251 to the lower surface to penetrate the semiconductor block 251. The through electrode 255 may penetrate the semiconductor block 251 and may be electrically connected to the interconnect layer 254 through the interconnect upper pad 256 of the interconnect layer 254. The interconnect upper pad 256 may be disposed on the upper surface of the dielectric layer 252. In one example, when the semiconductor block 251 is formed of silicon, the through electrode 255 may be referred to as a through-silicon via (TSV).

[0062] The bridging die 250 may further include an upper pad 258 that is connected to the vias 255 and disposed on the upper surface of the semiconductor block 251 of the bridging die 250.

[0063] Hereinafter, with reference to Figures 7 to 13 FIGS., various examples of the arrangement and relationship of electrical connections of semiconductor packages according to various exemplary embodiments of the inventive concept will be described.

[0064] Figure 7 Shown Figures 1 to 6 are the electrical connections in the semiconductor packages 300, 300a, and 300b.

[0065] With reference to Figure 7 FIG., in the semiconductor package 300c according to the exemplary embodiment, an electrical signal from the first semiconductor chip 210(C) as a processor may be sent to the bridging die 250(B1 to B4) through the upper bonding pads 213 of the first semiconductor chip 210(C) and the first lower pads 253a of the bridging die 250(B1 to B4) that are in contact with each other via the hybrid bonding C1. When the bridging die 250(B1 to B4) includes memory controllers MC1 to MC4 and L3 cache memories L31 to L34 in the bridging die 250(B1 to B4), the memory controller MC may operate according to the corresponding electrical signal, and the electrical signal may be sent to the second semiconductor chip 220 via an electrical connection "including the connection between the second lower pad 253b and the vertical bump 240 and the pad connection C3 between the interconnect layer 172 of the interposer 100 and the second semiconductor chip 220". The electrical signal from the second semiconductor chip 220 may also be sent through the memory controller MC via the connection C2 between the memory controller MC and the L3 cache memory and stored in the L3 cache memory. For example, the electrical signal from the second semiconductor chip 220 may be sent to the bridging die 250 via the pad connection C3 including the interconnect layer 172 of the interposer 100 and the vertical bump 240, and the electrical signal from the bridging die 250 may be sent to the first semiconductor chip 210 through the hybrid bonding C1.

[0066] As described above, the functional blocks within the first semiconductor chip 210 may be formed as separate chip structures, and the separate chip structures may be provided on the first semiconductor chip 210 as the bridging die 250(B1 to B4). The functional blocks of the bridging die 250 may be connected to the first semiconductor chip 210 through hybrid bonding. One side (B1 to B4) of the bridging die 250 may be configured to protrude to overlap with the interposer 100, thereby forming a circuit path connected to the interposer 100 through the separate vertical bumps 240.

[0067] Accordingly, the area of the first semiconductor chip 210 can be significantly reduced by vertically stacking the bridge die 250 and the first semiconductor chip 210, and more space can be allocated to the second semiconductor chip 220 serving as a memory block. The area of the semiconductor package 300 can be significantly reduced, and the memory capacity (such as the capacity of a cache memory, etc.) can be significantly increased.

[0068] Referring to Figure 8 , in the semiconductor package 300d according to this embodiment, the first semiconductor chip 210 (C) can be disposed in the central region of the upper surface of the interposer 100 on the upper surface of the interposer 100, and a plurality of second semiconductor chips 220 (M1 to M4) can be disposed on opposite sides of the first semiconductor chip 210. The number of the second semiconductor chips 220 can be set differently, and in Figure 8 , what is the same as in Figures 1 to 7 is that four second semiconductor chips 220 are provided. Two of the four second semiconductor chips 220 can be disposed on the left side of the first semiconductor chip 210, and the other second semiconductor chips 220 can be disposed on the right side of the first semiconductor chip 210.

[0069] Two bridge dies 250 (B R and B L ) can be disposed above the first semiconductor chip 210. The bridge die 250 can include a right bridge die 250 (B R ) disposed on the right side and a left bridge die 250 (B L ) disposed on the left side. The bridge dies 250 can have the same structure and size and can be symmetrically disposed on the first semiconductor chip 210. As described above, the bridge die 250 can be formed by forming some of the functional blocks of the first semiconductor chip 210 into separate chip structures, and each of the bridge dies (B R and B L ) can include a memory controller and a cache memory.

[0070] The memory controllers MC1 to MC4 can be connected to the first semiconductor chip 210 and can be functional blocks that can write data to the second semiconductor chips 220 (M1 to M4) or read data stored in the second semiconductor chips 220 (M1 to M4) by transmitting and receiving signals. Accordingly, the memory controllers (MC1 to MC4) can respectively correspond to the second semiconductor chips 220 (M1 to M4). The first memory controller MC1 and the second memory controller MC2 can be disposed within the right bridge die 250 (B R ) and can be electrically connected to share the right L3 cache memory (L3 R). The third memory controller MC3 and the fourth memory controller MC4 may be disposed within the left bridging die 250 (B L ), and may be electrically connected to share the left L3 cache memory (L3 L ).

[0071] Accordingly, an electrical signal from the first semiconductor chip 210 may be transmitted to the bridging die 250 through the "upper bonding pads 213 of the first semiconductor chip 210 and the first lower pads 253a of the left bridging die 250 and the right bridging die 250 (B R and B L ) that are in contact with each other to form the hybrid bond C1". The bridging die 250 may perform operations on specific memory controllers (MC1 to MC4) using the corresponding electrical signals, and the electrical signals may be transmitted to the second semiconductor chip 220 via the electrical connection "including the connection between the second lower pad 253b and the vertical bump 240 and the pad connection C3 between the interconnect layer 172 of the interposer 100 and the second semiconductor chip 220". Electrical signals from the second semiconductor chip 220 may also be stored in the cache memory (L3 R , L3 L ) through the interconnect layer 172 of the interposer 100, the vertical bump 240, and the memory controllers MC1 to MC4 of the bridging die 250, and may also be transmitted to the first semiconductor chip 210 through the hybrid bond C1. Accordingly, the L3 cache memory (L3 R , L3 L ) for storing data of the plurality of second semiconductor chips 220 may be shared in each bridging die 250, and even when two bridging dies 250 are provided, separate dies may not be provided in the central region of the first semiconductor chip 210 and may be provided to be exposed to the outside (i.e., may extend beyond one side of the first semiconductor chip 210 in a direction away from the first semiconductor chip 210).

[0072] Figure 9 and Figure 10 show a semiconductor package according to an embodiment of the inventive concept. Figure 9 shows the arrangement of the semiconductor package in the embodiment, and Figure 10 is a cross-sectional view of the semiconductor package taken along line III-III'. Figure 9 of the semiconductor package.

[0073] Referring to Figure 9 and Figure 10 , the semiconductor package 300e according to the present embodiment is the same as that shown in Figures 1 to 7The similarities of the semiconductor package shown in the figure are as follows: The first semiconductor chip 210 is disposed in the central region of the upper surface of the interposer 100 on the upper surface of the interposer 100, and the four second semiconductor chips 220 M1 to M4 are disposed while surrounding the first semiconductor chip 210 (C).

[0074] A bridging die 250 (B) may be disposed on the first semiconductor chip 210. The bridging die 250 (B) may cover the entire upper surface of the first semiconductor chip 210 and may include a first region 250a that overlaps the first semiconductor chip 210 and a second region 250b that protrudes outward from the first semiconductor chip 210 (i.e., extends beyond one side of the first semiconductor chip 210 in a direction away from the first semiconductor chip 210). As described above, in the bridging die 250, a part of the functional blocks of the first semiconductor chip 210 may be formed as a separate chip structure, and the bridging die 250 may include memory controllers MC1 to MC4 and a cache memory L3. The memory controllers MC1 to MC4 may be respectively connected to the second semiconductor chips M1 to M4. In this case, a plurality of memory controllers MC1 to MC4 may be disposed within the bridging die 250 and may be electrically connected to share one L3 cache memory (L3).

[0075] In this case, as Figure 10 shown in the figure, a heat dissipation portion 260 may be disposed in the central region of the bridging die 250 (i.e., the central region of the first semiconductor chip 210). The heat dissipation portion 260 may not be formed as a device, but may be buried with a material having a high thermal conductivity (such as bulk silicon). Therefore, the heat generated in the central region of the first semiconductor chip 210 may be conducted and discharged to the outside.

[0076] The bridging die 250 may include a dielectric layer 252 and a first lower pad 253a disposed below the heat dissipation part 260. The first lower pad 253a may include copper or the like having high conductivity and may effectively conduct heat. When one bridging die 250 is disposed on the first semiconductor chip 210, a second region 250b protruding to be adjacent to each second semiconductor chip 220 may be provided. Accordingly, the area of the bridging die 250 may be larger than the area of the first semiconductor chip 210. In addition, the width of the second region 250b protruding into the separation space may be larger than the width of the region protruding to the side where the second semiconductor chip 220 is not provided. Even when the heat dissipation part 260 is disposed in the central region of the bridging die 250, the upper surface of the bridging die 250 may be formed such that the heat dissipation part 260 and the semiconductor block 251 are coplanar. The structure for signal connection between the first semiconductor chip 210, the bridging die 250, the interposer 100, and the second semiconductor chip 220 is the same as described above, and one cache memory may be shared. In one example, a heat dissipation pad 261 may be disposed on the lower surface of the heat dissipation part 260.

[0077] Referring to Figure 11 , in the semiconductor package 300f according to this embodiment, the first semiconductor chip 210 (C) may be disposed on the upper surface of the interposer 100, and the second semiconductor chips 220 (M1 to M8) may surround the first semiconductor chip 210 (C). The second semiconductor chips 220 (M1 to M8) may be differently disposed, and in Figure 11 , eight second semiconductor chips 220 (M1 to M8) are disposed on four sides of the first semiconductor chip 210. For example, two second semiconductor chips may be adjacent to each side of the first semiconductor chip 210.

[0078] Four bridging dies 250 (B1 to B4) may be disposed above the first semiconductor chip 210. When the four bridging dies 250 (B1 to B4) have a square shape, one vertex of each of the four bridging dies 250 (B1 to B4) may be disposed on the first semiconductor chip 210, and the remaining three vertices of each of the four bridging dies 250 (B1 to B4) may be disposed to protrude from the first semiconductor chip 210. The four bridging dies 250 (B1 to B4) may be interconnected to the interposer 100 through vertical bumps 240 below the protruding second region 250b.

[0079] The configurations and dimensions of each of the bridging dies 250 (B1 to B4) may all be the same and may be symmetrically disposed on the first semiconductor chip 210. As described above, the bridging dies 250 (B1 to B4) are formed by forming a part of the functional blocks of the first semiconductor chip 210 into separate chip structures, and the bridging dies 250 (B1 to B4) may include memory controllers MC1 to MC8 and cache memories L31 to L34. Each bridging die 250 (B1 to B4) includes two memory controllers (for example, the bridging die 250 (B1) includes two memory controllers MC1 and MC2, wherein one bridging die is connected to two adjacent second semiconductor chips 220 (M1, M2), and the two memory controllers MC1 and MC2 may be electrically connected to share the L3 cache memory L31).

[0080] Accordingly, an electrical signal from the first semiconductor chip 210 may be sent to the bridging die 250 through the hybrid bonding C1, and the bridging die 250 may perform operations on a specific memory controller (MC1 to MC8) using the corresponding electrical signal, and the electrical signal may be sent to the second semiconductor chip 220 through the electrical connection "including the connection between the second under bump 253b and the vertical bump 240 and the pad connection C3 between the interconnect layer 172 of the interposer 100 and the second semiconductor chip 220". An electrical signal from the second semiconductor chip 220 may also be stored in the cache memory (L3) through the interconnect layer 172 of the interposer 100, the vertical bump 240, and the bridging die 250 via the memory controller MC, and may also be sent to the first semiconductor chip 210 through the hybrid bonding C1. Accordingly, the L3 cache memory (L3) for storing data of the plurality of second semiconductor chips 220 may be shared in each bridging die 250, and even when four bridging dies 250 (B1 to B4) are provided, a separate die may not be provided in the central region of the first semiconductor chip 210 and may be provided to be exposed to the outside (i.e., may extend beyond one side of the first semiconductor chip 210 in a direction away from the first semiconductor chip 210).

[0081] Referring to Figure 12 , in the semiconductor package 300g according to this embodiment, the first semiconductor chip 210 may be disposed in the central region of the semiconductor package 300g. The first semiconductor chip 210 may be disposed on the upper surface of the interposer 100, and the second semiconductor chips 220 (M1 to M10) may be disposed on the upper surface of the interposer 100 and surround the first semiconductor chip 210. The number of the second semiconductor chips 220 (M1 to M10) may be set differently, and in Figure 12In this case, ten second semiconductor chips 220 (M1 to M10) can surround the first semiconductor chip 210. Two of the second semiconductor chips 220 (M1 to M10) can be disposed on each of the left and right sides of the first semiconductor chip 210, and three of the second semiconductor chips 220 (M1 to M10) can be disposed on each of the upper and lower sides of the first semiconductor chip 210.

[0082] Therefore, different from the semiconductor package 300f of Figure 11 , the semiconductor package 300g can further include a second semiconductor chip M5 adjacent to the lower side of the first semiconductor chip 210 and a second semiconductor chip M10 adjacent to the upper side of the first semiconductor chip 210, and the semiconductor package 300g can further include bridging dies 250 (B3 and B6) corresponding to the second semiconductor chip M5 and the second semiconductor chip M10, and Figure 12 the semiconductor package 300g of

[0083] can include a total of six bridging dies 250 (B1 to B6).

[0084] The first type of bridging die 250 (B1, B2, B4, B5) may occupy a larger area than the second type of bridging die 250 (B3, B6), may include two memory controllers therein, and the L3 cache memory of the first type of bridging die 250 (B1, B2, B4, B5) may also have a higher capacity. By disposing the second type of bridging die 250 (B3 and B6) with a small area between the first type of bridging die 250 (B1, B2, B4, B5), additional bridging dies may be attached according to an increase in the number of semiconductor chips 220, such that the bridging die 250 and the second semiconductor chip 220 may be selectively attached according to a required memory capacity without changing the design of the entire semiconductor package. In one example, the first type of bridging die 250 may be electrically connected to M semiconductor chips among a plurality of second semiconductor chips 220, the second type of bridging die 250 may be electrically connected to N semiconductor chips among the plurality of second semiconductor chips 220, the first type of bridging die 250 may include M memory controllers, and the second type of bridging die 250 may include N memory controllers, where M may be an integer equal to or greater than 2, N may be an integer equal to or greater than 1, and M is greater than N.

[0085] As described above, the bridging die 250 may be formed by forming some of the functional blocks of the first semiconductor chip 210 into a separate chip structure, and the bridging die 250 may include a memory controller MC and a cache memory L3.

[0086] Accordingly, an electrical signal from the first semiconductor chip 210 may be sent to the bridging die 250 through the hybrid bond C1. In the bridging die 250, the electrical signal may be sent to the second semiconductor chip 220 through an electrical connection "including a connection between the second underpad 253b and the vertical bump 240 and a pad connection C3 between the interconnect layer 172 of the interposer 100 and the second semiconductor chip 220". An electrical signal from the second semiconductor chip 220 may also be sent to the bridging die 250 through the vertical bump 240, and an electrical signal from the bridging die 250 may be sent to the first semiconductor chip 210 through the hybrid bond C1. Accordingly, the cache memory L3 for storing data of the plurality of second semiconductor chips 220 may be shared in each bridging die 250, and even when six bridging dies 250 (B1 to B6) are provided, separate dies may not be provided in the central region of the first semiconductor chip 210 but may be provided to be exposed to the outside.

[0087] Refer to Figure 13, in the semiconductor package 300h according to this embodiment, the first semiconductor chip 210 may be in the central region on the upper surface of the interposer 100, and the second semiconductor chips 220 (M1 to M10) may be arranged while surrounding the first semiconductor chip 210. The number of the second semiconductor chips 220 (M1 to M10) may be set in various ways, and in Figure 8 , ten second semiconductor chips 220 (M1 to M10) may be centered on the first semiconductor chip 210, two of the second semiconductor chips 220 (M1 to M10) may be arranged on each of the left and right sides of the first semiconductor chip 210, and three of the second semiconductor chips 220 (M1 to M10) may be arranged on each of the upper and lower sides of the first semiconductor chip 210.

[0088] Unlike Figure 11 the semiconductor package 300f, the semiconductor package 300h may further include second semiconductor chips (M5 and M10) (each of the second semiconductor chips (M5 and M10) is located above and below the first semiconductor chip 210), and may include two bridging dies 250 (B1 and B2).

[0089] That is, the first bridging die 250 (B1) may be arranged above the first semiconductor chip 210 and may be connected through the vertical bumps 240 and the interposer 100 to connect to five second semiconductor chips M1, M2, M8 to M10 above the central region of the first semiconductor chip 210.

[0090] The second bridging die 250 (B2) may be arranged below the first semiconductor chip 210 and may be connected through the vertical bumps 240 and the interposer 100 to connect to five second semiconductor chips M3 to M7 below the central region of the first semiconductor chip 210.

[0091] The shapes and structures of the first bridging die 250 and the second bridging die 250 (B1 and B2) may be the same, and a separate die may not be arranged in the central region of the first semiconductor chip 210 but may be arranged to be exposed to the outside. The first bridging die and the second bridging die 250 (B1 and B2) may include memory controllers (MC1 to MC10) connected to each memory and may be connected to share the L3 cache memories (L31 and L32).

[0092] In this case, when ten second semiconductor chips (M1 to M10) are provided, there are separation spaces between the second semiconductor chips (M1 to M10) (specifically, regions where there are no second semiconductor chips (M1 to M10) in each corner region of the semiconductor package 300h), and dummy chip DM 280 may also be included to prevent corner region collapse.

[0093] In Figure 13 when multiple second semiconductor chips (M1 to M10) are provided in the semiconductor package 300h, in order to prevent collapse in the interval regions where the second semiconductor chips M1 to M10 are not provided, a three-dimensional structure having a density similar to that of the second semiconductor chips (M1 to M10) may be provided to prevent substrate warping. The dummy chip DM 280 may include materials having a thermal conductivity and density similar to those of the second semiconductor chips (M1 to M10), and may include materials for expanding the heat dissipation function (such as bulk silicon, etc.).

[0094] As described above, according to the above embodiments, by forming some functional blocks of the logic chip into independent chips and attaching the separate chips as bridge dies (e.g., semiconductor bridges) to the logic chip, the area of the logic chip can be reduced on the package.

[0095] Specifically, the memory controller directly connected to multiple memory chips and the cache memory that occupies a large area together with the memory controller can be separated into a separate bridge die and the separate bridge die can be vertically provided to further expand the size of the cache memory.

[0096] Specifically, by implementing various numbers of bridge dies provided above the logic chip, it is feasible to implement bridge dies having an optimal number and an optimal shape according to the number of memory chips.

[0097] Various and advantageous advantages and effects of the inventive concept are not limited to the above description, and can be more easily understood during the process of describing specific embodiments of the inventive concept. Although example embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

[0098] Although example embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor package, comprising: A first semiconductor chip, comprising a semiconductor substrate and a plurality of upper bonding pads disposed on an upper surface of the semiconductor substrate; And A bridge die, disposed on the first semiconductor chip, and comprising a bridge substrate and a plurality of first lower pads, Wherein, the bridge substrate comprises a first bridge portion and a second bridge portion, Wherein, the plurality of first lower pads are disposed on a first lower surface of the first bridge portion of the bridge substrate and respectively contact the plurality of upper bonding pads of the first semiconductor chip, Wherein, when viewed in a plan view, the first bridge portion overlaps with an edge portion of the first semiconductor chip, and the second bridge portion extends beyond one side of the first semiconductor chip in a direction away from the edge portion of the first semiconductor chip, and Wherein, the bridge die and the first semiconductor chip are different types of semiconductor devices.

2. The semiconductor package according to claim 1, Among them, The bridge die further comprises a plurality of second lower pads, Wherein, the plurality of second lower pads are coplanar with the plurality of first lower pads, Wherein, the plurality of second lower pads are disposed on a second lower surface of the second bridge portion of the bridge substrate, and Wherein, the first lower surface of the first bridge portion and the second lower surface of the second bridge portion are included in a lower surface of the bridge substrate.

3. The semiconductor package according to claim 2, Among them, The bridge die further comprises: a lower insulating layer, disposed under the bridge substrate and exposing each of the plurality of first lower pads, Wherein, the first semiconductor chip further comprises: an upper insulating layer, disposed on an upper surface of the semiconductor substrate and exposing each of the plurality of upper bonding pads, and Wherein, the lower insulating layer and the upper insulating layer are in contact with each other, and each of the plurality of first lower pads and a corresponding one of the plurality of upper bonding pads are in contact with each other to form a hybrid bond.

4. The semiconductor package according to claim 2, Among them, Each of the plurality of first lower pads has a first width, Wherein, each of the plurality of second lower pads has a second width, and Wherein, the second width is greater than the first width.

5. The semiconductor package according to claim 2, Among them, The semiconductor package further comprises: a redistribution structure, disposed under the first semiconductor chip, and comprising an insulating layer and an interconnect layer disposed in the insulating layer, Wherein, the redistribution structure further comprises: a plurality of first upper contact pads, disposed on an upper surface of the insulating layer and respectively connected to a plurality of lower bonding pads of the first semiconductor chip.

6. The semiconductor package according to claim 5, Among them, The redistribution structure further comprises: a second upper contact pad, on the upper surface of the insulating layer, Wherein, the semiconductor package further comprises: a plurality of vertical conductive structures, respectively connecting the plurality of second lower pads of the bridge die and the plurality of second upper contact pads of the redistribution structure to each other, and Wherein, when viewed in a plan view, the plurality of vertical conductive structures are disposed outside the first semiconductor chip.

7. The semiconductor package according to claim 6, Among them, Each of the plurality of vertical conductive structures has a width in the range of 150 μm to 250 μm.

8. The semiconductor package according to claim 7, Among them, The plurality of vertical conductive structures are spaced apart from each other by a separation distance in the range of 200 μm to 300 μm.

9. The semiconductor package according to any one of claims 1 to 8, Among them, The first semiconductor chip further includes: a plurality of first vias, connected to the plurality of upper bonding pads and penetrating the semiconductor substrate.

10. The semiconductor package according to claim 9, Among them, The bridging die further includes: a plurality of second vias, connected to the plurality of first lower pads of the bridging die and penetrating the bridging substrate.

11. The semiconductor package according to claim 1, Among them, The first semiconductor chip is a processor, and wherein the bridging die includes a cache memory of the processor.

12. A semiconductor package, comprising: A redistribution structure, including an insulating layer and an interconnect layer disposed within the insulating layer, and including a plurality of first upper contact pads and a plurality of second upper contact pads disposed on an upper surface of the insulating layer; A first semiconductor chip, disposed on the redistribution structure and having a semiconductor substrate and a plurality of upper bonding pads disposed on an upper surface of the semiconductor substrate; At least one second semiconductor chip, disposed around the first semiconductor chip on the redistribution structure; A bridging die, disposed on the first semiconductor chip and including a bridging substrate and a plurality of first lower pads and a plurality of second lower pads disposed on a lower surface of the bridging substrate; And A plurality of vertical conductive structures, respectively connecting the plurality of second lower pads of the bridging die to the plurality of second upper contact pads of the redistribution structure, wherein the bridging substrate includes a first bridging portion and a second bridging portion, wherein the plurality of first lower pads are disposed on a first lower surface of the first bridging portion of the bridging substrate and respectively contact the plurality of upper bonding pads, wherein the plurality of second lower pads are disposed on a second lower surface of the second bridging portion of the bridging substrate, wherein the first lower surface of the first bridging portion and the second lower surface of the second bridging portion are included in the lower surface of the bridging substrate, and wherein when viewed in a plan view, the first bridging portion overlaps an edge portion of the first semiconductor chip, and the second bridging portion extends beyond one side of the first semiconductor chip in a direction away from the edge portion of the first semiconductor chip.

13. The semiconductor package according to claim 12, Among them, The plurality of first upper contact pads are disposed below the first semiconductor chip and the at least one second semiconductor chip.

14. The semiconductor package according to claim 13, Among them, The plurality of vertical conductive structures include: a plurality of bumps, vertically connecting the plurality of second upper contact pads of the redistribution structure and the plurality of second lower pads of the bridging die.

15. The semiconductor package according to claim 12, Among them, The second bridging portion of the bridging die extends into a separation space between the first semiconductor chip and the at least one second semiconductor chip.

16. The semiconductor package according to claim 12, Among them, The at least one second semiconductor chip is electrically connected to the plurality of vertical conductive structures through an interconnect layer of the redistribution structure.

17. The semiconductor package according to claim 12, Among them, The bridging die is repeatedly placed on an upper surface of the first semiconductor chip to form a plurality of bridging dies. Among them, the multiple bridging dies are stacked on an edge portion of the first semiconductor chip and, when viewed in a plan view, define a central region of the first semiconductor chip, and among them, the multiple bridging dies are symmetrically arranged with respect to the central region.

18. The semiconductor package according to claim 12, Among them, when viewed in a plan view, the bridging die also overlaps with the central region of the first semiconductor chip, wherein the bridging die includes a heat dissipation portion above the central region of the first semiconductor chip, and wherein the area of the bridging die is larger than the area of the first semiconductor chip.

19. The semiconductor package according to any one of claims 12 to 18, Among them, the first semiconductor chip is a processor, wherein the at least one second semiconductor chip is a memory structure including a plurality of memory chips stacked on each other, and wherein the bridging die includes a cache memory of the first semiconductor chip and a memory controller for controlling the memory structure.

20. A semiconductor package, comprising: a redistribution structure; a first semiconductor chip disposed on the redistribution structure; a plurality of second semiconductor chips disposed around the first semiconductor chip on the redistribution structure; a first type of bridging die partially overlapping with the first semiconductor chip; a second type of bridging die partially overlapping with the first semiconductor chip; and a plurality of vertical conductive structures connecting each of the first type of bridging die and the second type of bridging die to the redistribution structure, wherein the area of the first type of bridging die is larger than the area of the second type of bridging die, wherein the first type of bridging die is electrically connected to M semiconductor chips among the plurality of second semiconductor chips, wherein the second type of bridging die is electrically connected to N semiconductor chips among the plurality of second semiconductor chips, wherein the first type of bridging die includes M memory controllers and a first cache memory, wherein the second type of bridging die includes N memory controllers and a second cache memory, wherein M is an integer equal to or greater than 2, N is an integer equal to or greater than 1, and M is greater than N, and wherein the memory capacity of the first cache memory is larger than the memory capacity of the second cache memory.

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