Control method and control system of flyback switching power supply

Abstract

The invention discloses a control method and a control system of a flyback switching power supply, and belongs to the field of switching power supplies. The control method of the flyback switching power supply comprises the following steps: counting the number of times that the drain terminal voltage of a switching tube in a primary side control module or a secondary side control module is greater than a target voltage, and when the number of times reaches a target threshold value, on the basis of the wave sending condition of the gate driving voltage of the switching tube, controlling the switching tube to be switched on; determining the working state of the flyback switching power supply at the current moment; determining a target reset signal and a target sampling signal based on the working state; and based on the target reset signal, resetting a first capacitor and a second capacitor in the peak sampling hold circuit, and sampling a platform voltage of the drain terminal voltage based on the target sampling signal. According to the control method of the flyback switching power supply, the real-time performance, the restorability and the accuracy of platform voltage sampling can be improved, and then the stability and the reliability of the switching power supply are enhanced.

Description

Technical Field

[0001] This application belongs to the field of switching power supplies, and particularly relates to a control method and a control system for a flyback switching power supply. Background Art

[0002] Due to its simple circuit structure, low electromagnetic interference, low cost and other characteristics, the flyback switching power supply has been widely used in consumer electronics fields such as mobile phone chargers and televisions. The normal operation and performance of the flyback converter are affected by the magnitude of the AC line voltage. For example, too high an AC line voltage may cause chip damage, and the drain voltage VD (the drain voltage of the primary-side switching MOS transistor or the drain voltage of the secondary-side SR transistor) contains information about the line voltage VBULK. The VD platform voltage changes with VBULK and Vo (the output voltage of the flyback switching power supply). The conduction logic of some control chips depends on the detection of the VD platform voltage. Therefore, the detection of the VD platform voltage is crucial for the operating performance of the switching power supply. In the related art, the peak sampling and holding technology can track the VD platform voltage and memorize its maximum peak value, but it cannot track and record the peak voltage when the VD platform voltage drops, and the recoverability of the flyback switching power supply under abnormal operating conditions (such as the switching MOS transistor not generating waves for a long time) is relatively low, resulting in poor real-time performance and accuracy of the VD platform voltage sampling. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems existing in the related art. For this purpose, this application provides a control method and a control system for a flyback switching power supply, which can improve the real-time performance, recoverability and accuracy of the platform voltage sampling, and further enhance the stability and reliability of the switching power supply.

[0004] In a first aspect, this application provides a control method for a flyback switching power supply, the method comprising:

[0005] Count the number of times that the drain voltage of the switching transistor in the primary control module or the secondary control module is greater than the target voltage. When the number reaches the target threshold, determine the operating state of the flyback switching power supply at the current moment based on the wave generation situation of the gate drive voltage of the switching transistor; the operating state includes a first state and a second state; the target voltage includes the output sampling voltage or the fixed voltage of the output capacitor in the secondary control module;

[0006] Determine a target reset signal and a target sampling signal based on the operating state;

[0007] Reset the first capacitor and the second capacitor in the peak sampling and holding circuit based on the target reset signal, and sample the platform voltage of the drain voltage based on the target sampling signal.

[0008] According to the control method of the flyback switching power supply of the present application, when the counting period is reached, based on the waveform of the gate drive voltage of the switching transistor, and when the gate drive voltage has no waveform, based on the startup situation of the switching power supply chip and whether the light load mode is exited, it is determined whether the flyback switching power supply is in a normal state or in a working state where the chip is started, the light load mode is exited, and the gate drive voltage has no waveform at the current moment. Based on the target reset signal corresponding to the working state, the first capacitor and the second capacitor in the peak sampling and holding circuit are reset, and after the first capacitor is recharged to a new peak voltage and the second capacitor is charged until the voltage of the second capacitor reaches the peak voltage, the sampling of the platform voltage is performed based on the target sampling signal corresponding to the working state. It can be realized that regardless of whether the peak voltage rises or falls and whether the gate drive voltage of the flyback switching power supply has a waveform, the sampling of the platform voltage can be completed, improving the real-time performance, recoverability, and accuracy of the platform voltage sampling, and further enhancing the stability and reliability of the switching power supply.

[0009] According to an embodiment of the present application, based on the waveform of the gate drive voltage of the switching transistor, the working state of the flyback switching power supply at the current moment is determined; based on the working state, the target reset signal and the target sampling signal are determined, including:

[0010] When the waveform of the gate drive voltage is not detected and the chip of the flyback switching power supply is started and the light load mode is exited, it is determined that the working state of the flyback switching power supply is the first state. When the working state is the first state, the target reset signal is determined as the first reset signal, and the target sampling signal is determined as the first sampling signal; the first reset signal and the first sampling signal are generated based on the drain voltage and the target voltage;

[0011] When the waveform of the gate drive voltage is detected, it is determined that the working state of the flyback switching power supply is the second state. When the working state is the second state, the target reset signal is determined as the second reset signal and the third reset signal, and the target sampling signal is determined as the second sampling signal; the second reset signal is generated based on the drain voltage and the decay voltage of the platform voltage, or based on the drain voltage and the target voltage, and the third reset signal and the second sampling signal are generated based on the gate drive voltage; the decay voltage is less than the platform voltage, and the target voltage is less than the decay voltage.

[0012] According to an embodiment of the present application, the first reset signal and the first sampling signal are generated based on the drain voltage and the target voltage, including:

[0013] At the moment when it is detected that the leakage terminal voltage is greater than the target voltage, perform a first replacement of the high and low levels of the first reset signal, and after a first duration, perform a second replacement of the high and low levels of the first reset signal; wherein, the moment of the first replacement of the high and low levels of the first reset signal is the moment to reset the first capacitor and the second capacitor;

[0014] After a second duration after the second replacement of the high and low levels of the first reset signal, perform a replacement of the high and low levels of the first sampling signal, and after a third duration, perform a second replacement of the high and low levels of the first sampling signal; wherein, the moment of the first replacement of the high and low levels of the first sampling signal is the moment to sample the plateau voltage of the leakage terminal voltage.

[0015] According to an embodiment of the present application, the second reset signal is generated based on the decay voltage of the leakage terminal voltage and the plateau voltage, and the third reset signal and the second sampling signal are generated based on the gate drive voltage, including:

[0016] At the moment when it is detected that the leakage terminal voltage is greater than the decay voltage, perform a first replacement of the high and low levels of the second reset signal, and after a fourth duration, perform a second replacement of the high and low levels of the second reset signal; wherein, the moment of the first replacement of the high and low levels of the second reset signal is the moment to reset the first capacitor;

[0017] At the rising edge moment of the gate drive voltage, perform a first replacement of the high and low levels of the third reset signal, and after a fifth duration, perform a second replacement of the high and low levels of the third reset signal; wherein, the moment of the first replacement of the high and low levels of the third reset signal is the moment to reset the second capacitor;

[0018] After a sixth duration after the second replacement of the high and low levels of the third reset signal, perform a first replacement of the high and low levels of the second sampling signal, and after a seventh duration, perform a second replacement of the high and low levels of the second sampling signal; wherein, the moment of the first replacement of the high and low levels of the second sampling signal is the moment to sample the plateau voltage of the leakage terminal voltage.

[0019] According to an embodiment of the present application, reset the first capacitor and the second capacitor in the peak sampling and holding circuit based on the target reset signal, and sample the plateau voltage of the leakage terminal voltage based on the target sampling signal, including:

[0020] When the target reset signal is the first reset signal and the target sampling signal is the first sampling signal, at the rising edge of the first reset signal, reset the first capacitor and the second capacitor in the peak sampling and holding circuit, and at the rising edge of the first sampling signal, sample the plateau voltage of the drain voltage;

[0021] When the target reset signals are the second reset signal and the third reset signal and the target sampling signal is the second sampling signal, at the rising edges of the second reset signal and the third reset signal, reset the first capacitor and the second capacitor respectively, and at the rising edge of the second sampling signal, sample the plateau voltage;

[0022] Among them, resetting the first capacitor is used to reset the voltage of the first capacitor to zero voltage, so that after the reset of the first capacitor ends, the first capacitor starts to charge from zero voltage to the peak voltage of the drain voltage; resetting the second capacitor is used to reset the voltage of the second capacitor to the first voltage, so that at the rising edge of the second sampling signal, charge the second capacitor based on the voltage of the first capacitor, so that the voltage of the second capacitor starts to charge from the first voltage to the plateau voltage; the first voltage includes zero voltage or the second voltage; the second voltage is determined based on the switching period of the flyback switching power supply and the change rate of the plateau voltage.

[0023] In a second aspect, the present application provides a control system based on the control method of the flyback switching power supply as described in the first aspect. The system includes:

[0024] A first comparator;

[0025] A forced refresh circuit, the input end of the forced refresh circuit is connected to the output end of the first comparator;

[0026] A refresh control circuit, the input end of the refresh control circuit is connected to the output end of the first comparator;

[0027] A reset and sampling control circuit, the input end of the reset and sampling control circuit is connected to the output end of the refresh control circuit;

[0028] A peak voltage sampling and holding circuit, the input end of the peak voltage sampling and holding circuit is respectively connected to the output end of the reset and sampling holding circuit and the output end of the peak voltage sampling and holding circuit, and the peak voltage sampling and holding circuit is used to sample the plateau voltage of the drain voltage.

[0029] According to the control system of the present application, based on a control system provided with a first comparator, a forced refresh circuit, a refresh control circuit, a reset and sampling control circuit, and a peak voltage sampling and holding circuit, it can be realized that when the counting period is reached, based on the waveform of the gate drive voltage of the switching transistor, and when the gate drive voltage does not have a waveform, based on the startup situation of the switching power supply chip and whether to exit the light load mode, it is determined whether the flyback switching power supply is in a normal working state or in a working state where the chip is started, the light load mode is exited, and the gate drive voltage does not have a waveform, so as to reset the first capacitor and the second capacitor in the peak sampling and holding circuit based on the target reset signal corresponding to the working state, and after the first capacitor is recharged to a new peak voltage and the second capacitor is charged until the voltage of the second capacitor reaches the peak voltage, then sample the platform voltage based on the target sampling signal corresponding to the working state, thereby realizing that regardless of whether the peak voltage rises or falls and whether the gate drive voltage of the flyback switching power supply has a waveform, the sampling of the platform voltage can be completed, improving the real-time performance, recoverability, and accuracy of the platform voltage sampling, and further enhancing the stability and reliability of the switching power supply.

[0030] According to an embodiment of the present application, the forced refresh circuit includes:

[0031] A counting circuit, the seventh input end of the counting circuit is connected to the output end of the first comparator, and the third output end of the counting circuit is used to output a first narrow pulse signal; the short-time high-level signal of the first narrow pulse signal is used to represent entering a new counting period;

[0032] A first flip-flop; the eighth input end of the first flip-flop is connected to the third output end, the ninth input end is used to receive the gate drive voltage, and the fourth output end of the first flip-flop is used to output a first control signal; within each counting period, the rising edge moment of the first control signal is consistent with the first rising edge moment of the gate drive voltage, and the falling edge moment of the first control signal is consistent with the rising edge moment of the first narrow pulse signal;

[0033] A falling edge delay circuit, the tenth input end of the falling edge delay circuit is connected to the fourth output end of the first flip-flop;

[0034] A second flip-flop, the eleventh input end of the second flip-flop is connected to the fifth output end of the falling edge delay circuit, the twelfth input end is connected to the third output end, the thirteenth input end is used to receive an enable signal, and the sixth output end of the second flip-flop is used to output a second control signal; the enable signal is used to represent whether the control chip of the flyback switching power supply is enabled; the second control signal is used to represent whether the gate drive voltage has a waveform within the current counting period;

[0035] A logical NOR operator, wherein the fourteenth input terminal of the logical NOR operator is connected to the sixth output terminal, the fifteenth input terminal is connected to the third output terminal, and the seventh output terminal of the logical NOR operator is used to output a target refresh signal; the high and low levels of the target refresh signal are used to participate in characterizing the working state.

[0036] According to an embodiment of the present application, the refresh control circuit includes:

[0037] An exception judgment module, wherein three input terminals of the exception judgment module are respectively used to receive an enable signal, a signal for exiting the light load mode, and a target refresh signal, and the eighth output terminal of the exception judgment module is used to output a fourth reset signal; the fourth reset signal is used to determine the target reset signal and the target sampling signal based on the working state; the signal for exiting the light load mode is used to characterize whether the chip of the flyback switching power supply exits the light load mode;

[0038] A third flip-flop, wherein the sixteenth input terminal of the third flip-flop is connected to the output terminal of the first comparator, and the seventeenth input terminal is connected to the eighth output terminal;

[0039] A fourth flip-flop, wherein the eighteenth input terminal of the fourth flip-flop is connected to the output terminal of the first comparator, and the nineteenth input terminal is connected to the eighth output terminal;

[0040] A logical AND operator; the twentieth input terminal and the twenty-first input terminal of the logical AND operator are respectively connected to the ninth output terminal of the third flip-flop and the tenth output terminal of the fourth flip-flop, and the eleventh output terminal of the logical AND operator is used to output a first pulse signal; the rising edge moment of the first pulse signal is used to characterize the moment when the drain voltage is first detected to be greater than the target voltage when the working state in the counting period is the first state;

[0041] A first ost circuit; the twenty-second input terminal of the first ost circuit is connected to the eleventh output terminal, and the twelfth output terminal of the first ost circuit is used to output a first reset signal;

[0042] A first rising edge delay circuit; the twenty-third input terminal of the first rising edge delay circuit is connected to the eleventh output terminal, and the thirteenth output terminal of the first rising edge delay circuit is used to output a first sampling signal.

[0043] According to an embodiment of the present application, the reset and sampling control circuit includes:

[0044] A second comparator, wherein a fortieth input terminal of the second comparator is configured to receive the drain voltage, a forty-first input terminal is configured to receive an attenuated voltage of the platform voltage, and an eighteenth output terminal of the second comparator is configured to output a second square wave signal; a rising edge moment of the second square wave signal is used to represent a moment when the drain voltage is detected to be greater than the attenuated voltage each time in the case that the working state in the counting period is the second state;

[0045] A second ost circuit, wherein a forty-second input terminal of the second ost circuit is connected to the eighteenth output terminal, and a nineteenth output terminal of the second ost circuit is configured to output a second reset signal;

[0046] A third ost circuit, wherein a forty-third input terminal of the third ost circuit is configured to receive the gate drive voltage, and a twentieth output terminal of the third ost circuit is configured to output a third reset signal;

[0047] A second rising edge delay circuit, wherein a forty-fourth input terminal of the second rising edge delay circuit is configured to receive the gate drive voltage;

[0048] A fourth ost circuit, wherein a forty-fifth input terminal of the fourth ost circuit is connected to a twenty-first output terminal of the second rising edge delay circuit, and a twenty-second output terminal of the fourth ost circuit is configured to output a second sampling signal;

[0049] A first two-way one-select data selector, wherein a forty-sixth input terminal of the first two-way one-select data selector is configured to receive a first reset signal, a forty-seventh input terminal is connected to the nineteenth output terminal, a forty-eighth input terminal is configured to receive a first pulse signal, and a twenty-third output terminal of the first two-way one-select data selector is configured to output a first target reset signal; the first target reset signal includes the first reset signal or the second reset signal;

[0050] A second two-way one-select data selector, wherein a forty-ninth input terminal of the second two-way one-select data selector is configured to receive the first reset signal, a fiftieth input terminal is connected to the twentieth output terminal, a fifty-first input terminal is configured to receive a first pulse signal, and a twenty-fourth output terminal of the second two-way one-select data selector is configured to output a second target reset signal; the second target reset signal includes the first reset signal or the third reset signal;

[0051] A third two-way one-select data selector, wherein a fifty-second input terminal of the third two-way one-select data selector is configured to receive the first reset signal, a fifty-third input terminal is connected to the twenty-second output terminal, a fifty-fourth input terminal is configured to receive a first pulse signal, and a twenty-fifth output terminal of the third two-way one-select data selector is configured to output a target sampling signal; the target sampling signal includes the first sampling signal or the second sampling signal.

[0052] According to an embodiment of the present application, the peak voltage sampling and holding circuit includes:

[0053] An operational amplifier, the thirty-ninth input terminal of which is used to receive the drain voltage;

[0054] A triode, the base of which is connected to the seventeenth output terminal of the operational amplifier, and the collector of which is connected to the low-voltage power supply of the chip of the flyback switching power supply;

[0055] A sampling capacitor, which is connected to the seventeenth output terminal of the operational amplifier and the emitter of the triode;

[0056] A first reset switch, which is in parallel with the sampling capacitor, and the first terminal of the first reset switch is connected to the grounded side of the sampling capacitor, and the second terminal is connected to the non-grounded side of the sampling capacitor; the opening and closing state of the first reset switch is controlled based on a first target reset signal;

[0057] A sampling switch, the first terminal of which is connected to the second terminal of the first reset switch; the opening and closing state of the sampling switch is controlled based on the target sampling signal;

[0058] A holding capacitor, the non-grounded side of which is connected to the second terminal of the sampling switch;

[0059] A current-limiting resistor;

[0060] A first current-limiting switch;

[0061] A second reset switch, the current-limiting resistor is connected in series with the second reset switch and is in parallel with the holding capacitor, and the first current-limiting switch is in parallel with the current-limiting resistor;

[0062] The opening and closing state of the second reset switch is controlled based on a second target reset signal, and the opening and closing state of the first current-limiting switch is controlled based on the first reset signal.

[0063] According to an embodiment of the present application, the peak voltage sampling and holding circuit includes:

[0064] A third reset switch;

[0065] A current mirror circuit, the current mirror circuit includes a second current limiting switch and a third current limiting switch, the second current limiting switch is in series with the third reset switch, and the third current limiting switch is in parallel with the second current limiting switch; the opening and closing state of the third reset switch is controlled based on a second target reset signal, the opening and closing state of the second current limiting switch is controlled based on a first reset signal, and the opening and closing state of the third current limiting switch is controlled based on the inverted signal of the first reset signal.

[0066] In a third aspect, the present application provides a control device for a flyback switch power supply, the device includes:

[0067] A first processing module, configured to count the number of times that the drain voltage of the switching tube in the primary control module or the secondary control module is greater than a target voltage, and based on the waveform of the gate drive voltage of the switching tube, determine the operating state of the flyback switch power supply at the current moment when the number reaches a target threshold; the operating state includes a first state and a second state; the target voltage includes the output sampling voltage or a fixed voltage of the output capacitor in the secondary control module;

[0068] A second processing module, configured to determine a target reset signal and a target sampling signal based on the operating state;

[0069] A third processing module, configured to reset a first capacitor and a second capacitor in the peak sampling and holding circuit based on the target reset signal, and sample the platform voltage of the drain voltage based on the target sampling signal.

[0070] In a fourth aspect, the present application provides a chip, the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run programs or instructions to implement the control method of the flyback switch power supply as described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The above and / or additional aspects and advantages of the present application will become apparent and easy to understand from the description of the embodiments in conjunction with the following drawings, where:

[0072] Figure 1 is a schematic flow chart of the control method of the flyback switch power supply provided by the embodiment of the present application;

[0073] Figure 2 is an important waveform schematic diagram of the flyback switch power supply provided by the embodiment of the present application;

[0074] Figure 3 is a schematic structural diagram of the primary control module of the flyback switch power supply provided by the embodiment of the present application;

[0075] Figure 4It is a schematic structural diagram of the secondary side control module of the flyback switching power supply provided by the embodiments of the present application;

[0076] Figure 5 It is one of the schematic structural diagrams of the control system of the control method based on the flyback switching power supply provided by the embodiments of the present application;

[0077] Figure 6 It is another schematic structural diagram of the control system of the control method based on the flyback switching power supply provided by the embodiments of the present application;

[0078] Figure 7 It is an important waveform schematic diagram of the forced refresh circuit in the flyback switching power supply provided by the embodiments of the present application;

[0079] Figure 8 It is a schematic structural diagram of the reset and sampling control circuit provided by the embodiments of the present application;

[0080] Figure 9 It is a schematic structural diagram of the peak voltage sampling and holding circuit provided by the embodiments of the present application;

[0081] Figure 10 It is an important waveform schematic diagram of the peak voltage sampling and holding (taking the secondary side control chip as an example) in the flyback switching power supply provided by the embodiments of the present application;

[0082] Figure 11 It is another flow schematic diagram of the control method of the flyback switching power supply provided by the embodiments of the present application;

[0083] Figure 12 It is a schematic structural diagram of another reset and sampling control circuit provided by the embodiments of the present application;

[0084] Figure 13 It is an important waveform schematic diagram of the peak voltage sampling and holding (taking the secondary side control chip as an example) in the flyback switching power supply provided by the embodiments of the present application;

[0085] Figure 14 It is a schematic structural diagram of another peak voltage sampling and holding circuit provided by the embodiments of the present application;

[0086] Figure 15 It is a schematic structural diagram of the control device of the flyback switching power supply provided by the embodiments of the present application;

[0087] Figure 16 It is a schematic structural diagram of the electronic device provided by the embodiments of the present application. Specific embodiments

[0088] The following will clearly describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0089] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and do not limit the number of objects. For example, the first object can be one or multiple. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / ", generally represents an "or" relationship between the associated objects before and after.

[0090] The following will, in conjunction with the accompanying drawings, elaborate in detail on the control method for a flyback switching power supply, the control device for a flyback switching power supply, the control system, the electronic device, and the readable storage medium provided in the embodiments of the present application through specific embodiments and their application scenarios.

[0091] Among them, the control method for a flyback switching power supply can be applied to a terminal, and specifically can be executed by hardware or software in the terminal.

[0092] The terminal includes but is not limited to portable communication devices such as mobile phones or tablets. It should also be understood that in some embodiments, the terminal may not be a portable communication device, but a desktop computer.

[0093] For the control method for a flyback switching power supply provided in the embodiments of the present application, the execution subject of the control method for the flyback switching power supply can be an electronic device or a functional module or functional entity in the electronic device that can implement the control method for the flyback switching power supply. The electronic devices mentioned in the embodiments of the present application include but are not limited to mobile phones, tablets, computers, cameras, and wearable devices, etc. The following will take the electronic device as the execution subject to illustrate the control method for the flyback switching power supply provided in the embodiments of the present application.

[0094] As Figure 1 shown, the control method for the flyback switching power supply includes: step 110, step 120, and step 130.

[0095] The flyback switching power supply is an isolated AC-DC converter, and the flyback switching power supply may include: a primary control module, a transformer, and a secondary control module.

[0096] The output of the primary control module is coupled to the secondary control module on the secondary side of the transformer based on the primary side of the transformer; the primary control module is used to receive the input voltage of the input power supply and convert it into magnetic energy stored in the magnetic core of the transformer, and the secondary control module is used to convert the energy stored in the transformer into output voltage and current for supplying the load.

[0097] Among them, as Figure 3 shown, the primary control module may include: a switching MOS transistor Q1 and a primary control chip, where the primary control chip is connected to the drain and gate of the switching MOS transistor Q1, the switching MOS transistor Q1 is connected to the input voltage VBULK through a transformer, and the function of the primary control chip is to control the conduction and cut-off of the switching MOS transistor Q1.

[0098] As Figure 4 shown, the secondary control module may include: a secondary control chip, a synchronous rectification (SR) transistor, and an output capacitor Cout, where the secondary control chip is connected to the drain and gate of the SR transistor, at the same time the drain of the SR transistor is connected to the transformer, the source of the SR transistor is connected to the ground, the output voltage Vo is connected to the other end of the transformer and the output capacitor Cout, and the function of the secondary control chip is to control the conduction and cut-off of the synchronous rectification SR transistor.

[0099] During the actual execution process, the important waveforms of the flyback converter are as Figure 2 shown, where VD_P is the drain voltage of the primary switching MOS transistor, DRV_P is the gate drive voltage of the primary switching MOS transistor, VD_S is the drain voltage of the secondary SR transistor, DRV_S is the gate drive voltage of the secondary SR transistor. It can be seen from the waveforms that VD_P oscillates around the input voltage VBULK during the resonance stage, and VD_S oscillates around the output voltage Vo during the resonance stage. Then the expressions for the platform voltages of VD_P and VD_S are: VD_Ph = VBULK + Nps * Vo, VD_Sh = Vo + VBULK / Nps, where Nps is the turns ratio of the primary and secondary sides of the transformer. From the above expressions, it can be obtained that the VD platform voltage (which can be the VD_Ph platform voltage or the VD_Sh platform voltage) changes with the changes of VBULK and Vo, that is, when VBULK and Vo increase / decrease, the VD platform voltage also increases / decreases accordingly.

[0100] The VD platform voltage can be obtained based on the peak voltage sampling and holding technique.

[0101] The peak voltage sampling and holding technique is a technique for detecting and holding the peak voltage of a signal.

[0102] In the actual implementation process, the peak voltage sample-and-hold circuit can be controlled based on a reset signal and a sampling signal, so as to sample the VD platform voltage based on the peak voltage sample-and-hold technology. Among them, the reset signal can be used to reset the voltage of the capacitor in the peak voltage sample-and-hold circuit when needed, so that the sampling capacitor can be charged to the peak voltage (VD platform voltage) of the current cycle every cycle, and the sampling signal is used to hold and sample the peak voltage (VD platform voltage) of the capacitor in the peak voltage sample-and-hold circuit.

[0103] However, the peak sample-and-hold technology cannot sample the normal platform voltage when the flyback switching power supply is starting up, exiting the light load mode, and the switching MOS transistor does not generate waves for a long time; and when the switching MOS transistor in the flyback switching power supply generates waves normally, after the voltage of the capacitor in the peak voltage sample-and-hold circuit reaches a peak voltage once, it will remain at the peak voltage until the next peak voltage with a higher voltage value arrives. Then, it is impossible to sample the peak voltage when the voltage value drops.

[0104] In this application, improvements are made to the above problems.

[0105] Step 110: Count the number of times that the drain voltage of the switching transistor in the primary control module or the secondary control module is greater than the target voltage. When the number of times reaches the target threshold, determine the working state of the flyback switching power supply at the current moment based on the wave generation situation of the gate drive voltage of the switching transistor.

[0106] In this step, the switching transistor can be the switching MOS transistor in the primary control module, or it can also be the SR transistor in the secondary control module.

[0107] It can be understood that the drain voltage can be the sampled voltage of the drain voltage of the switching MOS transistor, or it can also be the sampled voltage of the drain voltage of the SR transistor.

[0108] The target voltage includes the output sampled voltage of the output capacitor in the secondary control module or a fixed voltage.

[0109] Among them, the output sampled voltage is the sampled voltage of the output voltage of the output capacitor in the secondary control module, that is, the output voltage supplied by the flyback converter to the load.

[0110] The fixed voltage is greater than 0 and less than or equal to the output sampled voltage.

[0111] In the actual implementation process, the fixed voltage can be set to any effective voltage within the range greater than 0 and less than or equal to the output sampled voltage. Among them, effective means that in the subsequent embodiments, a first reset signal can be generated based on the drain voltage and the fixed voltage.

[0112] The target threshold is used to count the number of times the drain voltage is greater than the target voltage, and is the threshold for determining whether to determine the operating state of the flyback switching power supply.

[0113] In the actual execution process, start counting from zero the number of times the drain voltage of the switching transistor in the primary control module or the secondary control module is greater than the target voltage. When this number reaches the target threshold, then based on the waveform of the gate drive voltage of the switching transistor, determine the operating state of the flyback switching power supply at the current moment.

[0114] Among them, start counting from zero the number of times the drain voltage is greater than the target voltage, and the time range when the number reaches the target threshold is one counting cycle.

[0115] In some embodiments, the target threshold can be set based on user-defined settings. For example, the target threshold can be set to 1, 2, 3, or 4, etc., and can be specifically determined based on actual needs, which is not limited here.

[0116] The gate drive voltage can be the gate drive voltage of the switching MOS transistor, or can also be the gate drive voltage of the SR transistor.

[0117] It should be noted that when the drain voltage is the sampled voltage of the drain voltage of the switching MOS transistor, the gate drive voltage is the gate drive voltage of the switching MOS transistor; when the drain voltage is the sampled voltage of the drain voltage of the SR transistor, the gate drive voltage is the gate drive voltage of the SR transistor.

[0118] The operating state includes a first state and a second state.

[0119] Among them, the first state can be the operating state where the switching power supply chip starts, the switching power supply chip exits the light load mode and the gate drive voltage does not generate a waveform.

[0120] The second state is the normal operating state.

[0121] In the actual execution process, when the gate drive voltage of the switching transistor does not generate a waveform, it can be determined that the flyback switching power supply at the current moment is in the first state; when the switching power supply chip is turned on, exits the light load mode, and the gate drive voltage of the switching transistor generates a waveform, it can be determined that the flyback switching power supply at the current moment is in the second state.

[0122] Among them, the light load mode means that in the case of extremely light load or no load, the flyback switching power supply may enter an intermittent operating mode, which is suitable for occasions with a small load current and effectively improves the efficiency of the power supply.

[0123] Step 120: Determine the target reset signal and the target sampling signal based on the operating state;

[0124] In this step, the target reset signal is a signal used to reset the voltage of the capacitor in the peak voltage sampling and holding circuit.

[0125] The target sampling signal is a signal used to sample the plateau voltage of the peak voltage, i.e., the drain voltage.

[0126] The target reset signal may include a first reset signal, a second reset signal, and a third reset signal.

[0127] The target sampling signal may include a first sampling signal and a second sampling signal.

[0128] In the actual execution process, the working states of the flyback switching power supply are different, and the corresponding target reset signal and target sampling signal are different. That is, the target reset signal and target sampling signal are different based on the waveform of the gate drive voltage. This mainly depends on whether there is a control signal that can be used to generate the target reset signal and target sampling signal when the gate drive voltage is in a waveform or not. This will be specifically described in the following embodiments and will not be elaborated here for the time being.

[0129] Step 130: Based on the target reset signal, reset the first capacitor and the second capacitor in the peak sampling and holding circuit, and sample the plateau voltage of the drain voltage based on the target sampling signal.

[0130] In this step, resetting the first capacitor and the second capacitor in the peak sampling and holding circuit means controlling the generation of a reset current based on the target reset signal to reset the voltages of the first capacitor and the second capacitor.

[0131] Among them, the first capacitor is the sampling capacitor in the peak sampling and holding circuit, and the second capacitor is the holding capacitor in the peak sampling and holding circuit. The first capacitor is used to charge the second capacitor so that the voltage of the second capacitor reaches the peak voltage, i.e., the plateau voltage of the drain voltage.

[0132] In the actual execution process, after resetting the voltage of the first capacitor, the first capacitor can be charged based on the low-voltage power supply in the peak sampling and holding circuit until the voltage of the first capacitor reaches the plateau voltage of the drain voltage, then the charging stops. Then, the voltage of the second capacitor is reset, and after resetting the voltage of the second capacitor, the first capacitor is controlled to charge the second capacitor based on the target sampling signal until the voltage of the second capacitor reaches the plateau voltage of the drain voltage, completing the sampling of the plateau voltage.

[0133] During the R & D process, the inventor found that when the switching MOS transistor in the flyback switching power supply does not generate waveforms for a long time, the normal sampling of the platform voltage cannot be carried out based on the peak voltage sampling and holding technology in the related art; and in the related art, when the switching MOS transistor in the flyback switching power supply generates waveforms normally, after the voltage of the capacitor in the peak voltage sampling and holding circuit reaches a peak voltage once, it will maintain the peak voltage unchanged until a peak voltage with a higher voltage value arrives next time. Then, it is impossible to sample the peak voltage when the voltage value drops, reducing the real-time performance of sampling the peak voltage.

[0134] In this application, when the counting cycle is reached and the gate drive voltage of the switching transistor generates waveforms, it is determined that the flyback switching power supply is in the normal working state, that is, the second state, at the current moment. When the switching power supply chip is turned on and exits the light load mode, and the gate drive voltage does not generate waveforms, it is determined that the flyback switching power supply is in the working state of the chip being turned on, exiting the light load mode, and the gate drive voltage not generating waveforms, that is, the first state, and the target reset signal and the target sampling signal corresponding to the working state are determined. Based on the determined target reset signal, the first capacitor and the second capacitor in the peak sampling and holding circuit are reset, so that the reset first capacitor is recharged based on the new peak voltage, and after the charging is completed, the second capacitor can be charged with the new peak voltage, so that the voltage of the second capacitor reaches the new peak voltage, that is, the platform voltage of the drain voltage. Then, the platform voltage is sampled based on the target sampling signal. That is, regardless of whether the peak voltage rises or falls, the sampling of the peak voltage can be realized based on the above process, improving the accuracy and real-time performance of the platform voltage sampling; and regardless of which working state the flyback switching power supply is in, the real-time sampling of the platform voltage can be realized based on the above process, improving the recoverability and adaptability of the platform voltage sampling, and further enhancing the stability and reliability of the switching power supply.

[0135] According to the control method of the flyback switching power supply provided by the embodiments of the present application, when the counting period is reached, based on the waveform of the gate drive voltage of the switching transistor, and when the gate drive voltage does not have a waveform, based on the startup situation of the switching power supply chip and whether the light load mode is exited, it is determined whether the flyback switching power supply is in the normal working state or in the working state where the chip is started, the light load mode is exited, and the gate drive voltage does not have a waveform at the current moment, so as to reset the first capacitor and the second capacitor in the peak sampling and holding circuit based on the target reset signal corresponding to the working state, and after the first capacitor is recharged to a new peak voltage and the second capacitor is charged until the voltage of the second capacitor reaches the peak voltage, then sample the platform voltage based on the target sampling signal corresponding to the working state. It can be realized that regardless of whether the peak voltage rises or falls and whether the gate drive voltage in the flyback switching power supply has a waveform, the sampling of the platform voltage can be completed, improving the real-time performance, recoverability and accuracy of the platform voltage sampling, and further enhancing the stability and reliability of the switching power supply.

[0136] In some embodiments, based on the waveform of the gate drive voltage of the switching transistor, determining the working state of the flyback switching power supply at the current moment, and based on the working state, determining the target reset signal and the target sampling signal may include:

[0137] When the waveform of the gate drive voltage is not detected and the chip of the flyback switching power supply is started and the light load mode is exited, it is determined that the working state of the flyback switching power supply is the first state. When the working state is the first state, the target reset signal is determined as the first reset signal, and the target sampling signal is determined as the first sampling signal; the first reset signal and the first sampling signal are generated based on the drain voltage and the target voltage;

[0138] When the waveform of the gate drive voltage is detected, it is determined that the working state of the flyback switching power supply is the second state. When the working state is the second state, the target reset signal is determined as the second reset signal and the third reset signal, and the target sampling signal is determined as the second sampling signal; the second reset signal is generated based on the drain voltage and the decay voltage of the platform voltage, or based on the drain voltage and the target voltage, the third reset signal and the second sampling signal are generated based on the gate drive voltage; the decay voltage is less than the platform voltage, and the target voltage is less than the decay voltage.

[0139] In this embodiment, when the waveform of the gate drive voltage is detected, it is determined that the gate drive voltage has a waveform, then it is determined that the working state of the flyback switching power supply is the second state; when the waveform of the gate drive voltage is not detected, it is determined that the gate drive voltage does not have a waveform, then when the chip of the flyback switching power supply is started and the light load mode is exited, it is determined that the working state of the flyback switching power supply is the first state.

[0140] In some embodiments, detecting the waveform of the gate drive voltage may be detecting the rising edge or the falling edge of the gate drive voltage. That is, when the rising edge or the falling edge of the gate drive voltage is detected, it is determined that the gate drive voltage generates a wave.

[0141] The following takes the process of determining whether the gate drive voltage generates a wave by detecting whether the rising edge of the gate drive voltage is detected as an example to illustrate the above judgment process:

[0142] In some embodiments, it is possible to detect whether there is a situation where the gate drive voltage is not 0V based on a software program method, so as to determine whether there is a rising edge of the gate drive voltage. It can be understood that when there is a voltage value other than 0V for the gate drive voltage, it is determined that there is a rising edge of the gate drive voltage, that is, the gate drive voltage generates a wave, otherwise it is determined that the gate drive voltage does not generate a wave.

[0143] In some embodiments, it is also possible to detect whether there is a high level of the gate drive voltage based on a hardware circuit method, such as detecting the high level of the gate drive voltage based on a flip-flop, etc. It should be noted that when detecting the gate drive voltage based on the hardware circuit method, since when entering the current counting cycle, it is necessary to determine the working state of the flyback switching power supply within the current counting cycle for the subsequent circuit to generate a reset signal and a sampling signal corresponding to the working state in a timely manner, then it is necessary to determine the working state of the flyback switching power supply within the current counting cycle based on the wave generation situation of the gate drive voltage in the previous counting cycle.

[0144] The first reset signal and the first sampling signal are respectively the reset signal and the sampling signal when the flyback switching power supply is in the first state.

[0145] Among them, the first reset signal and the first sampling signal are square wave signals with different high potential times, that is, the high level time of the first reset signal does not coincide with the high level time of the first sampling signal, and within the same switching cycle, the high level time of the first reset signal is before the high level time of the first sampling signal.

[0146] Among them, one switching cycle is from the turn-off of the primary switching transistor of the flyback switching power supply to the next turn-off.

[0147] In the actual execution process, it is possible to control the reset of the first capacitor and the second capacitor in the peak sampling and holding circuit when the flyback switching power supply is in the first state based on the first reset signal, and sample the peak voltage when the flyback switching power supply is in the first state based on the first sampling signal, that is, sample the platform voltage of the drain voltage.

[0148] When the flyback switching power supply is in the first state, since the gate drive voltage does not generate a waveform, the first reset signal and the first sampling signal can be generated based on the drain voltage and the target voltage.

[0149] During the actual execution process, the rising edge moments of the first reset signal and the first sampling signal within the current counting period are determined based on the moment when the drain voltage within the current counting period is greater than the target voltage.

[0150] In some embodiments, based on the software program method, the rising edge moments of the first reset signal and the first sampling signal can be determined based on the moment when the drain voltage within the current counting period is greater than the target voltage. For example, based on the software program, detect the moment when the drain voltage is greater than the target voltage, and at this moment, control the first reset signal from low level to high level, and after a certain duration, control the second sampling signal from low level to high level.

[0151] In some embodiments, based on the hardware circuit method, the rising edge moments of the first reset signal and the first sampling signal can also be determined based on the moment when the drain voltage within the current counting period is greater than the target voltage. Specific details will be described in the following embodiments and will not be elaborated here for the time being.

[0152] The second reset signal and the third reset signal are both reset signals when the flyback switching power supply is in the second state, and the second sampling signal is the sampling signal when the flyback switching power supply is in the second state.

[0153] Among them, the second reset signal, the third reset signal, and the second sampling signal are square wave signals with different high-potential times. The high-level time of the second reset signal, the high-level time of the third reset signal, and the high-level time of the second sampling signal do not overlap, and within the same cycle, the high-level time of the second reset signal is before the high-level time of the third reset signal, and the high-level time of the third reset signal is before the high-level time of the second sampling signal.

[0154] It can be understood that based on the second reset signal and the third reset signal, the reset of the first capacitor and the second capacitor in the peak sampling and holding circuit when the flyback switching power supply is in the second state can be achieved, and based on the second sampling signal, the sampling of the peak voltage when the flyback switching power supply is in the second state can be achieved.

[0155] When the operating state of the switching power supply is the second state, the second reset signal can be generated based on the decay voltage of the drain voltage and the platform voltage, or based on the drain voltage and the target voltage, and since the gate drive voltage normally generates a waveform, the third reset signal and the second sampling signal can be generated based on the gate drive voltage.

[0156] Among them, the decay voltage of the platform voltage can be the product of the decay coefficient and the platform voltage.

[0157] The decay coefficient can be any value within the range greater than 0.5 and less than 1.

[0158] It can be understood that the decay voltage is less than the platform voltage, and the target voltage is less than the decay voltage.

[0159] In the actual execution process, similar to the above method for generating the first reset signal and the first sampling signal, in some embodiments, the rising edge time of the second reset signal can be determined based on the software program method at the moment when the drain voltage is greater than the decay voltage of the platform voltage, or based on the moment when the drain voltage is greater than the target voltage, and the rising edge times of the third reset signal and the second sampling signal can be determined based on the rising edge time of the gate drive voltage; of course, in some embodiments, the above process can also be implemented based on the hardware circuit method, which will be specifically described in the following embodiments and will not be elaborated here for the time being.

[0160] According to the control method of the flyback switching power supply provided by the embodiments of the present application, by determining the target reset signal as the first reset signal and the target sampling signal as the first sampling signal when the working state is the first state, and determining the target reset signal as the second reset signal and the third reset signal and the target sampling signal as the second sampling signal when the working state is the second state, it is possible to determine the corresponding effective target reset signal and target sampling signal based on the waveform of the gate drive voltage, so as to realize the reset of the first capacitor and the second capacitor in the peak voltage sampling and holding circuit and the smooth progress of the peak voltage sampling in each working state, and improve the accuracy and reliability of the target reset signal and the target sampling signal.

[0161] In some embodiments, the first reset signal and the first sampling signal are generated based on the drain voltage and the target voltage, and may include:

[0162] At the moment when it is detected that the drain voltage is greater than the target voltage, the high and low levels of the first reset signal are replaced for the first time, and after the first time period, the high and low levels of the first reset signal are replaced for the second time;

[0163] After the second time period after the high and low levels of the first reset signal are replaced for the second time, the high and low levels of the first sampling signal are replaced, and after the third time period, the high and low levels of the first sampling signal are replaced for the second time.

[0164] In this embodiment, replacing the high and low levels means converting the low level to the high level or converting the high level to the low level.

[0165] Among them, the moment when the high and low levels of the first reset signal are replaced for the first time is the moment to reset the first capacitor and the second capacitor.

[0166] The moment when the high and low levels of the first sampling signal are replaced for the first time is the moment to sample the plateau voltage of the drain terminal voltage.

[0167] The following takes the hardware circuit method and the levels of each signal before the first replacement of the high and low levels being low levels as an example to illustrate this embodiment.

[0168] During the actual execution process, within the current counting cycle, the moment when the drain terminal voltage is detected to be greater than the target voltage can generate the rising edge of the first square wave signal. Among them, the first square wave signal is a square wave signal obtained based on the comparison result of the magnitudes of the drain terminal voltage and the target voltage. Among them, the high-level time of the first square wave signal is the time when the drain terminal voltage is greater than the target voltage, and the low-level time of the first square wave signal is the time when the drain terminal voltage is less than the target voltage.

[0169] Then, in the case where the rising edge of the first square wave signal is detected, the rising edge of the first reset signal is generated based on the first square wave signal, that is, the first reset signal is replaced from the low level to the high level, and after the first duration, the first reset signal is then replaced from the high level to the low level, that is, the falling edge of the first reset signal is generated.

[0170] Within the current counting cycle, after the second duration after the falling edge of the first reset signal is generated, that is, after delaying the rising edge of the first square wave signal by the second duration, the rising edge of the first sampling signal is generated, that is, the first sampling signal is replaced from the low level to the high level, that is, the rising edge of the first sampling signal is generated, and after the third duration, the first sampling signal is then replaced from the high level to the low level, that is, the falling edge of the first sampling signal is generated.

[0171] Among them, the first duration and the third duration can be the same or different, and both the first duration and the third duration can be user-defined and set, which is not limited here.

[0172] It should be noted that the second duration is not zero, and the second duration can be user-defined and set.

[0173] It can be understood that the moment of the falling edge of the first reset signal does not coincide with the moment of the rising edge of the first sampling signal, so as to make the subsequent processes of resetting the capacitor voltage and sampling the peak voltage not conflict.

[0174] According to the control method of the flyback switching power supply provided by the embodiments of the present application, by replacing the high and low levels of the first reset signal for the first time at the moment when the drain voltage is detected to be greater than the target voltage, replacing the high and low levels of the first reset signal for the second time after the first duration, replacing the high and low levels of the first sampling signal after the second duration after replacing the high and low levels of the first reset signal for the second time, and replacing the high and low levels of the first sampling signal for the second time after the third duration, it is possible to generate a first reset signal and a first sampling signal with a time sequence of high-level time based on the first square wave signal when the working state is the first state. Thus, it is possible to achieve an orderly sampling process of the peak voltage sampling and holding circuit when the working state of the flyback switching power supply is the first state, reduce circuit conflicts, and improve the reliability of the control method.

[0175] In some embodiments, the second reset signal is generated based on the decay voltage of the drain voltage and the platform voltage, and the third reset signal and the second sampling signal are generated based on the gate drive voltage, which may include:

[0176] At the moment when the drain voltage is detected to be greater than the decay voltage, replacing the high and low levels of the second reset signal for the first time, and replacing the high and low levels of the second reset signal for the second time after the fourth duration;

[0177] At the rising edge moment of the gate drive voltage, replacing the high and low levels of the third reset signal for the first time, and replacing the high and low levels of the third reset signal for the second time after the fifth duration;

[0178] After the sixth duration after replacing the high and low levels of the third reset signal for the second time, replacing the high and low levels of the second sampling signal for the first time, and replacing the high and low levels of the second sampling signal for the second time after the seventh duration.

[0179] In this embodiment, the moment of replacing the high and low levels of the second reset signal for the first time is the moment of resetting the first capacitor.

[0180] The moment of replacing the high and low levels of the third reset signal for the first time is the moment of resetting the second capacitor.

[0181] The moment of replacing the high and low levels of the second sampling signal for the first time is the moment of sampling the platform voltage of the drain voltage.

[0182] Next, continue to illustrate this embodiment by taking the hardware circuit method and the levels of each signal before the first replacement of the high and low levels as low levels as an example.

[0183] During the actual execution process, within the current counting cycle, the rising edge moment of the second square wave signal can be generated at the moment when the drain terminal voltage is detected to be greater than the attenuation voltage. Here, the second square wave signal is a square wave signal obtained based on the comparison result of the magnitudes of the drain terminal voltage and the attenuation voltage of the platform voltage. Among them, the high-level time of the second square wave signal is the time when the drain terminal voltage is greater than the attenuation voltage of the platform voltage, and the low-level time of the first square wave signal is the time when the drain terminal voltage is less than the attenuation voltage of the platform voltage.

[0184] Then, in the case where the rising edge of the second square wave signal is detected, the rising edge of the second reset signal can be generated based on the second square wave signal, that is, the second reset signal is replaced from the low level to the high level, and after the fourth duration, the second reset signal is replaced from the high level to the low level again, that is, the falling edge of the second reset signal is generated.

[0185] During the actual execution process, within the current counting cycle, the rising edge moment of the gate drive voltage is after the falling edge moment of the second reset signal.

[0186] Then, within the current counting cycle, in the case where the rising edge of the gate drive voltage is detected, the rising edge of the third reset signal can be generated based on the gate drive voltage, that is, the third reset signal is replaced from the low level to the high level, and after the fifth duration, the third reset signal is replaced from the high level to the low level again, that is, the falling edge of the third reset signal is generated.

[0187] And after the sixth duration after the falling edge moment of the third reset signal is generated, that is, after delaying the rising edge of the gate drive voltage by the sixth duration, the rising edge of the second sampling signal is generated, that is, the second sampling signal is replaced from the low level to the high level, that is, the rising edge of the second sampling signal is generated, and after the seventh duration, the second sampling signal is replaced from the high level to the low level again, that is, the falling edge of the second sampling signal is generated.

[0188] Among them, the fourth duration, the fifth duration, and the seventh duration can be the same or different, and can all be user-defined settings, which are not limited here.

[0189] It should be noted that the sixth duration is not zero. The sixth duration can be the same as or different from the second duration, and can be specifically user-defined settings, which are not limited here.

[0190] It can be understood that the falling edge moment of the second reset signal, the falling edge moment of the third reset signal, and the rising edge moment of the first sampling signal do not coincide, so that the subsequent processes of resetting the first capacitor and the second capacitor and sampling the peak voltage do not conflict.

[0191] According to the control method of the flyback switching power supply provided by the embodiments of the present application, by performing the first replacement of the high and low levels of the second reset signal at the moment when the drain voltage is detected to be greater than the attenuation voltage, performing the second replacement of the high and low levels of the second reset signal after the fourth duration, performing the first replacement of the high and low levels of the third reset signal at the rising edge of the gate drive voltage, performing the second replacement of the high and low levels of the third reset signal after the fifth duration, and performing the first replacement of the high and low levels of the second sampling signal after the sixth duration after the second replacement of the high and low levels of the third reset signal, and performing the second replacement of the high and low levels of the second sampling signal after the seventh duration, it is possible to generate the second reset signal, the third reset signal, and the second sampling signal with a time sequence of high-level times based on the second square wave signal in the case where the working state is the second state, so that it is possible to realize the orderly sampling process of the peak voltage sampling and holding circuit in the case where the working state of the flyback switching power supply is the second state, reduce circuit conflicts, and improve the reliability of the control method.

[0192] In some embodiments, the rising edge of the second reset signal can also be generated based on the rising edge of the first square wave signal. The difference from being generated based on the second square wave signal is that in the case where the flyback switching power supply is in the second state, within the counting period, there are multiple high-level times in the first square wave signal, that is, there are multiple rising edges in the generated second reset signal. Then, in the subsequent case of controlling the reset of the first capacitor based on the second reset signal, the voltage of the first capacitor has multiple reset phenomena within the counting period.

[0193] According to the control method of the flyback switching power supply provided by the embodiments of the present application, the second reset signal can also be generated based on the first square wave signal, so that multiple generation methods of the second reset signal can be provided, and the flexibility and adaptability of the generation method of the second reset signal can be provided.

[0194] In some embodiments, resetting the first capacitor and the second capacitor in the peak sampling and holding circuit based on the target reset signal, and sampling the platform voltage of the drain voltage based on the target sampling signal may include:

[0195] In the case where the target reset signal is the first reset signal and the target sampling signal is the first sampling signal, at the rising edge of the first reset signal, reset the first capacitor and the second capacitor in the peak sampling and holding circuit, and at the rising edge of the first sampling signal, sample the platform voltage of the drain voltage;

[0196] In the case where the target reset signal is the second reset signal and the third reset signal, and the target sampling signal is the second sampling signal, at the rising edges of the second reset signal and the third reset signal, reset the first capacitor and the second capacitor respectively, and at the rising edge of the second sampling signal, sample the platform voltage.

[0197] In this embodiment, the first reset capacitor is used to reset the voltage of the first capacitor to zero voltage, so that after the reset of the first capacitor ends, the first capacitor starts charging from zero voltage to the peak voltage of the drain voltage.

[0198] The second reset capacitor is used to reset the voltage of the second capacitor to the first voltage, so that at the rising edge of the second sampling signal, the second capacitor is charged based on the voltage of the first capacitor, and the voltage of the second capacitor starts charging from the first voltage to the plateau voltage.

[0199] The first voltage includes zero voltage or the second voltage.

[0200] The second voltage is determined based on the switching period of the flyback switching power supply and the change rate of the plateau voltage.

[0201] In some embodiments, the second voltage can be obtained based on the following formula:

[0202] vdpk rst = vdpk - ΔV

[0203] Where, vdpk rst is the second voltage, vdpk is the voltage of the second capacitor, and ΔV is the voltage change amount; where, ΔV can be obtained based on the following formula:

[0204] ΔV = (vdpk * td4) / (R1 * C2)

[0205] Where, ΔV is the voltage change amount, vdpk is the voltage of the second capacitor, td4 is the pulse width (high-level duration) of the reset signal corresponding to the second capacitor, R1 is the current-limiting resistor, and C2 is the second capacitor.

[0206] Next, the working process of controlling the peak voltage sampling and holding circuit based on the control method in this embodiment will be described.

[0207] First, the case of the working state being the first state

[0208] In the actual execution process, when the target reset signal is the first reset signal and the target sampling signal is the first sampling signal, the first reset signal controls the first reset switch, the second reset switch, and the fourth current-limiting switch in the peak voltage sampling and holding circuit, and the first sampling signal controls the third sampling switch in the peak sampling and holding circuit.

[0209] Among them, each switch is closed during the high-level time of the corresponding control signal and opened during the low-level time.

[0210] When the first reset switch is closed and the third sampling switch is open, the reset of the first capacitor can be achieved. When the second reset switch is closed and the third sampling switch is open, the reset of the second capacitor can be achieved. When the second reset switch and the fourth current-limiting switch are closed and the third sampling switch is open, the voltage of the first capacitor can be reset to 0. When the second reset switch is closed, the fourth current-limiting switch is open and the third sampling switch is open, the current-limiting resistor can be connected in series to the circuit where the second capacitor is located, and the voltage of the second capacitor can be reset to the second voltage. When the third sampling switch is closed and the rest of the switches are open, the charging of the second capacitor based on the first capacitor can be achieved, so that the voltage of the second capacitor climbs to the platform voltage within this counting period for platform voltage sampling.

[0211] Then it can be understood that at the rising edge of the first reset signal, control the first reset switch, the second reset switch and the fourth current-limiting switch to close, and at the falling edge of the first reset signal, control the first reset switch, the second reset switch and the fourth current-limiting switch to turn off, that is, the voltages of the first capacitor and the second capacitor can be reset to zero voltage. Then at the rising edge of the first sampling signal, control the third sampling switch to close, and at the falling edge of the first sampling signal, control the third sampling switch to turn off, and the sampling of the platform voltage of the drain voltage in the case where the working state is the first state within the counting period can be achieved.

[0212] It should be noted that when the second reset switch and the fourth current-limiting switch are closed and the third sampling switch is open, and the voltage of the second capacitor is reset to 0, the reset of the second capacitor can be achieved when the gate drive voltage in the flyback switch power supply does not generate a waveform, which is convenient for subsequent charging of the second capacitor based on the first capacitor when the other switches are open, so that the voltage of the second capacitor gradually climbs again from 0 until the voltage of the first capacitor is equal to the platform voltage within this counting period, to achieve the acquisition of the platform voltage when the gate drive voltage in the flyback switch power supply does not generate a waveform.

[0213] Second, the case where the working state is the second state

[0214] During the actual execution process, when the target reset signals are the second reset signal and the third reset signal, and the target sampling signal is the second sampling signal, the second reset signal controls the first reset switch in the peak voltage sampling and holding circuit, the third reset signal controls the second reset switch in the peak voltage sampling and holding circuit, and the second sampling signal controls the third sampling switch in the peak sampling and holding circuit.

[0215] Among them, each switch is closed during the high-level time of the corresponding control signal and open during the low-level time.

[0216] Then it can be understood that at the rising edge of the second reset signal, the first reset switch is controlled to close, and at the falling edge of the first reset signal, the first reset switch is controlled to turn off, so that the voltage of the first capacitor can be reset to zero voltage.

[0217] It should be noted that when the flyback switching power supply is in the second state, the first reset signal is at a low level, that is, when the voltage of the second capacitor is reset, the fourth current limiting switch does not close; then at the rising edge of the third reset signal, the second reset switch is controlled to close, and at the falling edge of the third reset signal, the second reset switch is controlled to turn off, so that the current limiting resistor can be connected in series to the circuit where the second capacitor is located, and the voltage of the second capacitor is reset to the second voltage.

[0218] At the rising edge of the second sampling signal, the third sampling switch is controlled to close, and at the falling edge of the second sampling signal, the third sampling switch is controlled to turn off, so as to sample the platform voltage of the drain voltage when the working state is in the second state within the counting period.

[0219] According to the control method of the flyback switching power supply provided by the embodiments of the present application, when the target reset signal is the first reset signal and the target sampling signal is the first sampling signal, at the rising edge of the first reset signal, the first capacitor and the second capacitor in the peak sampling and holding circuit are reset, and at the rising edge of the first sampling signal, the platform voltage of the drain voltage is sampled. When the target reset signals are the second reset signal and the third reset signal, and the target sampling signal is the second sampling signal, at the rising edges of the second reset signal and the third reset signal, the first capacitor and the second capacitor are respectively reset, and at the rising edge of the second sampling signal, the platform voltage is sampled. It can be realized that within each counting period of the flyback switching power supply, regardless of whether the flyback switching power supply is in the first state or the second state, and regardless of whether the platform voltage in each counting period rises or falls compared with the platform voltage in the previous counting period, the platform voltage can be sampled, improving the reliability and applicability of the control method of the flyback switching power supply.

[0220] The present application also provides a control system based on the control method of the flyback switching power supply described in any of the above embodiments, as Figure 5 shown, the control system includes:

[0221] A first comparator;

[0222] A forced refresh circuit, the input end of the forced refresh circuit is connected to the output end of the first comparator;

[0223] A refresh control circuit, the input end of the refresh control circuit is connected to the output end of the first comparator;

[0224] A reset and sampling control circuit, the input end of the reset and sampling control circuit is connected to the output end of the refresh control circuit;

[0225] A peak voltage sampling and holding circuit, the input end of the peak voltage sampling and holding circuit is respectively connected to the output end of the reset and sampling holding circuit and the output end of the peak voltage sampling and holding circuit, and the peak voltage sampling and holding circuit is used to sample the plateau voltage of the drain voltage.

[0226] In this embodiment, the first comparator is used to receive the drain voltage and the target voltage of the switching transistor in the primary control module or the secondary control module, and output a first square wave signal. Wherein, when the drain voltage is greater than the target voltage, the first square wave signal is set to a high level, and the number of high-level times of the first square wave signal is counted to divide the counting period.

[0227] The first input end of the forced refresh circuit is connected to the output end of the first comparator, the second input end of the forced refresh circuit is used to receive the gate drive voltage, and the first output end of the forced refresh circuit is used to output a target refresh signal.

[0228] The high and low levels of the target refresh signal are used to participate in characterizing the working state.

[0229] The third input end of the refresh control circuit is connected to the output end of the first comparator, the fourth input end is used to receive the enable signal, the fifth input end is used to receive the signal to exit the light load mode, the sixth input end is used to receive the target refresh signal, and the second output end of the refresh control circuit is used to output a first pulse signal.

[0230] Wherein, the enable signal being at a high level indicates that the control chip of the flyback switching power supply is enabled, and the signal to exit the light load mode being at a low level indicates that the chip exits the light load mode.

[0231] The light load mode means that in the case of extremely light load or no load, the flyback switching power supply may enter an intermittent working mode, which is applicable to occasions with a small load current and effectively improves the efficiency of the power supply.

[0232] It should be noted that when the drain voltage is the sampled voltage of the drain voltage of the switching MOS transistor, the enable signal is used to indicate whether the chip in the primary control module is enabled, and the signal to exit the light load mode is used to indicate whether the chip in the primary control module exits the light load mode; when the drain voltage is the sampled voltage of the drain voltage of the SR transistor, the enable signal is used to indicate whether the chip in the secondary control module is enabled, and the signal to exit the light load mode is used to indicate whether the chip in the secondary control module exits the light load mode.

[0233] The rising edge moment of the first pulse signal is used to indicate the moment when the drain voltage is first detected to be greater than the target voltage when the working state in the counting period is the first state.

[0234] Taking the output sampling voltage as the target voltage as an example, the first comparator will be described as follows: As Figure 6 shown, the drain voltage vd_sen is connected to the positive input terminal of the first comparator comp, and the output sampling voltage vo_sen is connected to the negative input terminal of the first comparator comp. After being compared by the first comparator comp, a first square wave signal vd_ring of the drain sampling voltage crossing the output voltage Vo of the flyback switching power supply is obtained. Among them, the waveform of vd_ring is as Figure 7 shown.

[0235] Among them, when vd_sen > vo_sen, the output signal vd_ring of comp is at a high level; when vd_sen < vo_sen, the output signal vd_ring of comp is at a low level, and the square wave signal vd_ring is obtained periodically.

[0236] In some embodiments, the reference voltage connected to the negative input terminal of the first comparator comp can also be a certain fixed voltage vref (0 < vref ≤ vo_sen), and this fixed voltage only needs to satisfy that the first square wave signal vd_ring of vd_sen crossing this fixed voltage can be correctly detected.

[0237] The forced refresh control circuit can receive the first square wave signal vd_ring output by the first comparator and receive the gate drive voltage DRV, so as to implement the control method of the above flyback switching power supply. Based on the first square wave signal vd_ring, the gate drive voltage DRV and the target voltage, a target refresh signal flash is generated and output. Among them, the waveforms of the gate drive voltage DRV and flash are as Figure 7 shown.

[0238] The refresh control circuit can receive the enable signal, the signal to exit the light load mode, the target refresh signal flash output by the forced refresh circuit, and the first square wave signal vd_ring output by the first comparator, and implement the generation and output of the first pulse signal vd_sel in the control method of the above flyback switching power supply. Among them, the waveform of the first pulse signal vd_sel is as Figure 10 shown.

[0239] The reset and sampling control circuit can receive the drain voltage, the attenuated voltage of the platform voltage, and the gate drive voltage, obtain the second reset signal, the third reset signal, and the second sampling signal of the flyback switching power supply in the second state, and can receive the first pulse signal vd_sel, as well as the first reset signal and the first sampling signal of the flyback switching power supply in the first state. Thus, based on the level of the first pulse signal vd_sel, it can determine whether the flyback switching power supply is in the second state or the first state, and select the corresponding reset signal and sampling signal to generate the first target reset signal, the second target reset signal, and the target sampling signal for controlling each switch in the subsequent peak voltage sample and hold circuit.

[0240] The peak voltage sample and hold circuit can receive the drain voltage, the low-voltage power supply of the chip in the primary control module or the secondary control module, the first target reset signal, the second target reset signal, the target sampling signal, and the first reset signal, and can obtain the first target current limiting signal based on the first reset signal, thereby controlling the reset of the capacitor voltage and the sampling of the platform voltage in an orderly manner based on each signal.

[0241] According to the control system provided by the embodiments of the present application, based on the control system provided with the first comparator, the forced refresh circuit, the forced refresh circuit, the reset and sampling control circuit, and the peak voltage sample and hold circuit, it can be realized that when the counting period is reached, based on the waveform of the gate drive voltage of the switching transistor, and when the gate drive voltage does not generate a waveform, based on the startup situation of the switching power supply chip and whether it exits the light load mode, it is determined whether the flyback switching power supply is in the normal working state or in the working state where the chip is started, exits the light load mode, and the gate drive voltage does not generate a waveform. Based on the target reset signal corresponding to the working state, the first capacitor and the second capacitor in the peak sample and hold circuit are reset, and after the first capacitor is recharged to a new peak voltage and the second capacitor is charged until the voltage of the second capacitor reaches the peak voltage, the platform voltage is sampled based on the target sampling signal corresponding to the working state. Thus, regardless of whether the peak voltage rises or falls and whether the gate drive voltage of the flyback switching power supply generates a waveform, the sampling of the platform voltage can be completed, improving the real-time performance, recoverability, and accuracy of the platform voltage sampling, and further enhancing the stability and reliability of the switching power supply.

[0242] In some embodiments, the forced refresh circuit may include:

[0243] A counting circuit, the seventh input terminal of the counting circuit is connected to the output terminal of the first comparator, and the third output terminal of the counting circuit is used to output a first narrow pulse signal; the short-term high-level signal of the first narrow pulse signal is used to represent entering a new counting period;

[0244] The first flip - flop; the eighth input terminal of the first flip - flop is connected to the third output terminal, the ninth input terminal is used to receive the gate drive voltage, and the fourth output terminal of the first flip - flop is used to output the first control signal; within each counting cycle, the rising - edge moment of the first control signal is consistent with the first rising - edge moment of the gate drive voltage, and the falling - edge moment of the first control signal is consistent with the rising - edge moment of the first narrow - pulse signal;

[0245] The falling - edge delay circuit, the tenth input terminal of the falling - edge delay circuit is connected to the fourth output terminal of the first flip - flop;

[0246] The second flip - flop, the eleventh input terminal of the second flip - flop is connected to the fifth output terminal of the falling - edge delay circuit, the twelfth input terminal is connected to the third output terminal, the thirteenth input terminal is used to receive the enable signal, and the sixth output terminal of the second flip - flop is used to output the second control signal; the enable signal is used to indicate whether the control chip of the flyback switching power supply is enabled; the second control signal is used to indicate whether the gate drive voltage generates a waveform within the current counting cycle;

[0247] The logical NOR operator, the fourteenth input terminal of the logical NOR operator is connected to the sixth output terminal of the second flip - flop, the fifteenth input terminal is connected to the third output terminal, and the seventh output terminal of the logical NOR operator is used to output the target refresh signal; the high and low levels of the target refresh signal are used to participate in indicating the working state.

[0248] In this embodiment, the first flip - flop can be an RS flip - flop.

[0249] The second flip - flop can be a D flip - flop.

[0250] The falling - edge delay circuit is used to extend the falling - edge moment of the first control signal.

[0251] As Figure 6 shown, during the actual execution process, the first square - wave signal vd_ring can be sent into the counting circuit. Whenever the number of consecutive high - level times counted reaches the first threshold, a first narrow - pulse signal is output and sent to the reset terminal of the RS flip - flop 1 (the first flip - flop), the gate drive voltage DRV serves as the set terminal of the RS flip - flop 1, the output terminal of the RS flip - flop 1 is sent to the data terminal of the D flip - flop 3 (the second flip - flop) after passing through the falling - edge delay circuit, the first narrow - pulse signal output by the counting circuit is sent to the rising - edge trigger terminal of the clock of the D flip - flop 3, the enable signal of the chip serves as the reset terminal of the D flip - flop 3, and the output terminal of the D flip - flop 3 and the first narrow - pulse signal pass through the logical NOR operator (NOR gate) NOR1 to obtain the forced refresh signal flash.

[0252] Among them, the counting circuit counts the number of pulse signals (the number of continuously appearing high levels) of the first square wave signal vd_ring, and outputs a first narrow pulse signal every time the first threshold is reached. The first narrow pulse signal is sent to the reset (R) terminal of the RS flip-flop 1. When the first narrow pulse signal is at a high level, the output terminal Q1 of the RS flip-flop 1 is at a low level; the gate drive voltage DRV is sent to the set (S) terminal of the RS flip-flop 1. When the gate drive voltage DRV is at a high level, the output terminal Q1 of the RS flip-flop 1 is at a high level.

[0253] It can be understood that every N pulse signals of the first square wave signal vd_ring, the RS flip-flop 1 detects whether the gate drive voltage DRV generates a wave (square wave signal, high level valid). If the gate drive voltage DRV generates a wave at any time during the N pulse signals of the first square wave signal vd_ring, the output Q of the RS flip-flop 1 outputs a high level during this period, otherwise it outputs a low level.

[0254] Among them, in order to process the read data moment of the D flip-flop 3, the output signal Q1 of the RS flip-flop 1 passes through a falling-edge delay circuit to obtain the input signal D2 of the D flip-flop 3. The rising-edge moments of the signal D2 and Q1 are the same, and the falling-edge moment of the signal D2 is after the falling-edge of the signal Q1.

[0255] The D flip-flop 3 is triggered by the rising edge. Every N pulse signals of the first square wave signal vd_ring, the data terminal D2 is detected at the rising edge of the first narrow pulse signal. If the gate drive voltage DRV generates a wave, the output signal Q2 of the D flip-flop 3 is at a high level, and flash is at a low level after being operated by the logical NOR gate NOR1; if the gate drive voltage DRV does not generate a wave, D2 is at a low level, then the output signal Q2 of the D flip-flop 3 is at a low level, and flash is at a high level after being operated by the logical NOR gate NOR1; The important waveforms of the forced refresh circuit are as Figure 7 shown.

[0256] According to the control system provided by the embodiments of the present application, based on a forced refresh circuit including a counting circuit, a first flip-flop, a falling-edge delay circuit, a second flip-flop, and a logical NOR gate, it is possible to obtain a first narrow pulse signal based on the first square wave signal, and based on the rising-edge moment of the gate drive voltage and the rising-edge moment of the first narrow pulse signal, determine the high-level duration of the first control signal. Thus, based on the second control signal and the first narrow pulse signal, that is, based on the wave generation situation of the gate drive voltage in the previous cycle of each cycle, a target refresh signal with different high and low level transformation situations within each cycle is generated, so as to participate in subsequent characterization of the second state or the first state of the flyback switch power supply based on the target refresh signal, so as to facilitate the realization of such as Figure 11Subsequently, for different operating states (the second state or the first state) of the flyback switching power supply shown, based on different reset and sampling signals, the platform voltage of the sampled drain voltage is controlled.

[0257] In some embodiments, the refresh control circuit may include:

[0258] An anomaly judgment module, the three input terminals of the anomaly judgment module are respectively used for receiving an enable signal, a signal for exiting the light load mode, and a target refresh signal, and the eighth output terminal of the anomaly judgment module is used for outputting a fourth reset signal; the fourth reset signal is used for determining a target reset signal and a target sampling signal based on the operating state; the signal for exiting the light load mode is used to indicate whether the chip of the flyback switching power supply exits the light load mode;

[0259] A third flip-flop, the sixteenth input terminal of the third flip-flop is connected to the output terminal of the first comparator, and the seventeenth input terminal is connected to the eighth output terminal;

[0260] A fourth flip-flop, the eighteenth input terminal of the fourth flip-flop is connected to the output terminal of the first comparator, and the nineteenth input terminal is connected to the eighth output terminal;

[0261] A logical AND operation unit; the twentieth input terminal and the twenty-first input terminal of the logical AND operation unit are respectively connected to the ninth output terminal of the third flip-flop and the tenth output terminal of the fourth flip-flop, and the eleventh output terminal of the logical AND operation unit is used for outputting a first pulse signal; the rising edge moment of the first pulse signal is used to indicate the moment when the drain voltage is first detected to be greater than the target voltage when the operating state within the counting period is the first state;

[0262] A first ost circuit; the twenty-second input terminal of the first ost circuit is connected to the eleventh output terminal, and the twelfth output terminal of the first ost circuit is used for outputting a first reset signal;

[0263] A first rising edge delay circuit; the twenty-third input terminal of the first rising edge delay circuit is connected to the eleventh output terminal, and the thirteenth output terminal of the first rising edge delay circuit is used for outputting a first sampling signal.

[0264] In this embodiment, both the third flip-flop and the fourth flip-flop can be D flip-flops.

[0265] Among them, the third flip-flop is triggered by the rising edge, the fourth flip-flop is triggered by the falling edge, and the reset terminals of the third flip-flop and the fourth flip-flop are both active low.

[0266] Such as Figure 6As shown, during the actual execution process, the exception determination module may include a logical NOT operator INV1 and a logical AND operator AND1. Among them, the output terminal of the logical NOT operator INV1 is connected to one input terminal of the logical AND operator AND1. The logical NOT operator INV1 is used to receive the signal burst for the chip to exit the light load mode, and the other two input terminals of the logical AND operator AND1 are respectively used to receive the target refresh signal flash and the signal for the chip to be enabled.

[0267] It can be understood that in the case where the chip exits the light load mode, the signal burst for the chip to exit the light load mode is at a low level. After being operated by the logical NOT operator INV1, the signal burst for the chip to exit the light load mode is at a high level. When the target refresh signal flash, the signal for the chip to be enabled, and the signal burst for the chip to exit the light load mode output by the logical NOT operator INV1 are all at a high level, the reset signals (Reset) of D flip-flop 1 (the third flip-flop) and D flip-flop 2 (the fourth flip-flop) are at a high level, and D flip-flop 1 and D flip-flop 2 start to work.

[0268] During the actual execution process, when D flip-flop 1 and D flip-flop 2 detect the rising edge of the first square wave signal vd_ring, the output Q3 of D flip-flop 1 is at a high level. When detecting the falling edge of the first square wave signal vd_ring, the output Q4 of D flip-flop 2 is at a high level. After Q3 and Q4 are operated by the logical AND operator AND2, the first pulse signal vd_sel is obtained, that is, the first pulse signal vd_sel is the first pulse signal when the reset (Reset) terminal of the first square wave signal vd_ring changes from a low level to a high level, and can be used to select the corresponding reset signal and sampling signal of the peak voltage sampling and holding circuit based on the second state or the first state of the flyback switching power supply in the future.

[0269] As Figure 6 shown, in some embodiments, the first pulse signal vd_sel may obtain the first reset signal vd_rst through the first ost circuit, and its pulse width is td1; the first pulse signal vd_sel obtains the first sampling signal vd_sam through the first rising edge delay circuit, and its delay time is td2. Among them, in order to avoid simultaneous reset and sampling, which may cause a large current inside the chip, and to ensure the real-time performance of reset first and then sampling, during the actual execution process, td2 > td1 is set.

[0270] According to the control system provided by the embodiments of the present application, based on a refresh control circuit including an anomaly judgment module, a third trigger, a fourth trigger, a logical AND operator, a first ost circuit, and a first rising-edge delay circuit, it is possible to effectively judge whether the flyback switching power supply is in the first state based on the anomaly judgment module, and based on the judgment result, generate a first pulse signal for selecting a reset signal and a sampling signal of the peak voltage sampling and holding circuit corresponding to the flyback switching power supply being in the second state or the first state, and based on the first pulse signal, obtain the first reset signal and the first sampling signal when the flyback switching power supply is in the first state, so that other circuit structures in the control system can perform subsequent processing based on the first pulse signal, the first reset signal, and the first sampling signal, improving the control logic and reliability of the control system.

[0271] In some embodiments, the reset and sampling control circuit may include:

[0272] A second comparator, the fortieth input terminal of the second comparator is used to receive the drain voltage, the forty-first input terminal is used to receive the attenuated voltage of the platform voltage, and the eighteenth output terminal of the second comparator is used to output a second square wave signal; the rising edge moment of the second square wave signal is used to represent the moment when the drain voltage is greater than the attenuated voltage each time when the working state in the counting period is the second state;

[0273] A second ost circuit, the forty-second input terminal of the second ost circuit is connected to the eighteenth output terminal, and the nineteenth output terminal of the second ost circuit is used to output a second reset signal;

[0274] A third ost circuit, the forty-third input terminal of the third ost circuit is used to receive the gate drive voltage, and the twentieth output terminal of the third ost circuit is used to output a third reset signal;

[0275] A second rising-edge delay circuit, the forty-fourth input terminal of the second rising-edge delay circuit is used to receive the gate drive voltage;

[0276] A fourth ost circuit, the forty-fifth input terminal of the fourth ost circuit is connected to the twenty-first output terminal of the second rising-edge delay circuit, and the twenty-second output terminal of the fourth ost circuit is used to output a second sampling signal;

[0277] A first 2-to-1 data selector, the forty-sixth input terminal of the first 2-to-1 data selector is used to receive the first reset signal, the forty-seventh input terminal is connected to the nineteenth output terminal, the forty-eighth input terminal is used to receive the first pulse signal, and the twenty-third output terminal of the first 2-to-1 data selector is used to output a first target reset signal; the first target reset signal includes the first reset signal or the second reset signal;

[0278] The second two-way data selector, the forty-ninth input terminal of the second two-way data selector is used to receive the first reset signal, the fiftieth input terminal is connected to the twentieth output terminal, the fifty-first input terminal is used to receive the first pulse signal, and the twenty-fourth output terminal of the second two-way data selector is used to output the second target reset signal; the second target reset signal includes the first reset signal or the third reset signal;

[0279] The third two-way data selector, the fifty-second input terminal of the third two-way data selector is used to receive the first reset signal, the fifty-third input terminal is connected to the twenty-second output terminal, the fifty-fourth input terminal is used to receive the first pulse signal, and the twenty-fifth output terminal of the third two-way data selector is used to output the target sampling signal; the target sampling signal includes the first sampling signal or the second sampling signal.

[0280] In this embodiment, during the actual execution process, the drain voltage vd_sen is connected to the positive input terminal of the second comparator comp2, the attenuation voltage K*vdpk (0.5 < K < 1) of the platform voltage is connected to the negative input terminal of the second comparator comp2, and the second comparator comp2 is used to detect the platform voltage of vd_sen. In order to avoid sampling the ringing peak as much as possible, usually 2*Vo (the highest ringing voltage) < K*vdpk < vdpk (the platform voltage).

[0281] Among them, when vd_sen > K*vdpk, the second square wave signal vd_det output by the second comparator comp2 is at a high level, and when vd_sen < K*vdpk, the second square wave signal vd_det output by the second comparator comp2 is at a low level.

[0282] As Figure 8 shown, the second square wave signal vd_det passes through the second ost circuit to generate the second reset signal vd_rst1, and its pulse width is td3; the gate drive voltage DRV passes through the third ost circuit to generate the third reset signal DRV_rst, and its pulse width is td4; the gate drive voltage DRV passes through the second rising edge delay circuit and the fourth ost circuit to generate the second sampling signal DRV_sam. Among them, the rising edge delay time of the second sampling signal DRV_sam is td5, and the pulse width is td6. In order to avoid simultaneous reset and sampling, which may cause a large current inside the chip, and to ensure the real-time performance of reset first and then sampling, during the actual execution process, td5 > td4 is set.

[0283] As Figure 8 shown, mux1, 2, and 3 are the first two-way data selector, the second two-way data selector, and the third two-way data selector respectively. Among them, ctr is the selection signal. When ctr is at a high level, the output signal selects signal a, otherwise it selects b.

[0284] It can be understood that the first pulse signal vd_sel output by the refresh control circuit can be used as the ctr signal to select the reset and sampling signals of the peak voltage sampling and holding circuit: 1) When the first pulse signal vd_sel is at a high level, that is, during the chip startup phase, when exiting the light load mode and the gate drive voltage does not oscillate, the output terminals rst1 of mux1 (the first multiplexer) and rst2 of mux2 (the second multiplexer) both select the first reset signal vd_rst as the reset signals for the sampling capacitor C1 and the holding capacitor C2 in the peak sampling and holding circuit (the first target reset signal corresponding to C1 and the second target reset signal corresponding to C2); the output terminal sam of mux3 (the third multiplexer) selects the first sampling signal vd_sam as the sampling signal in the peak sampling and holding circuit (the target sampling signal); 2) When the first pulse signal vd_sel is at a low level, that is, when the chip is operating normally (the flyback switch power supply is in the second state), the output terminal rst1 of mux1 selects the second reset signal vd_rst1 as the reset signal for the sampling capacitor C1 in the peak sampling and holding circuit (the first target reset signal); the output terminal rst2 of mux2 selects the third reset signal DRV_rst as the reset signal for the holding capacitor C2 in the peak sampling and holding circuit (the second target reset signal); the output terminal sam of mux3 selects the second sampling signal DRV_sam as the sampling signal in the peak sampling and holding circuit (the target sampling signal).

[0285] According to the control system provided by the embodiments of the present application, based on the reset and sampling control circuit including a second comparator, a second ost circuit, a third ost circuit, a second rising edge delay circuit, a fourth ost circuit, a first multiplexer, a second multiplexer, and a third multiplexer, it is possible to obtain the reset signal and the sampling signal when the flyback switch power supply is in the second state, and to select the reset signal and the sampling signal corresponding to the second state or the first state of the flyback switch power supply based on the first pulse signal, so as to facilitate subsequent selection of effective reset signals and sampling signals based on the working state of the flyback switch power supply to implement sampling and holding of the platform voltage based on the peak voltage sampling and holding circuit.

[0286] As Figure 12 shown, in some embodiments, the reset and sampling control circuit may not include a second comparator, and the forty-second input terminal of the second ost circuit may directly receive the first square wave signal, and the nineteenth output terminal of the second ost circuit is used to output the second reset signal, and the rest of the circuit parts remain unchanged.

[0287] In this embodiment, the difference from the above embodiment is that the voltage Vc1 of the sampling capacitor C1 has multiple reset states within one sampling period, as Figure 13 shown, the first target reset signal rst1 and the voltage Vc1 of the sampling capacitor C1 have multiple reset states within one sampling period.

[0288] According to the control system provided by the embodiments of the present application, in the reset and sampling control circuit, the second comparator may not be included, and the forty-second input terminal of the second ost circuit may directly receive the first square wave signal. The nineteenth output terminal of the second ost circuit is used to output the second reset signal. When the rest of the circuit part remains unchanged, the same technical effect as the above reset and sampling control circuit including the second comparator, the second ost circuit, the third ost circuit, the second rising edge delay circuit, the fourth ost circuit, the first two-way data selector, the second two-way data selector, and the third two-way data selector can be achieved, that is, multiple acquisition methods of the second reset signal can be provided based on the reset and sampling control circuit when the flyback switching power supply is in the second state, improving the flexibility and adaptability of the control system.

[0289] In some embodiments, the peak voltage sampling and holding circuit may include:

[0290] An operational amplifier, the thirty-ninth input terminal of the operational amplifier is used to receive the drain voltage;

[0291] A triode, the base of the triode is connected to the seventeenth output terminal of the operational amplifier, and the collector of the triode is connected to the low-voltage power supply of the chip of the flyback switching power supply;

[0292] A sampling capacitor, the sampling capacitor is connected to the seventeenth output terminal of the operational amplifier and the emitter of the triode;

[0293] A first reset switch, the first reset switch is in parallel with the sampling capacitor, and the first end of the first reset switch is connected to the grounded side of the sampling capacitor, and the second end is connected to the non-grounded side of the sampling capacitor; the opening and closing state of the first reset switch is controlled based on the first target reset signal;

[0294] A sampling switch, the first end of the sampling switch is connected to the second end of the first reset switch;

[0295] A holding capacitor, the non-grounded side of the holding capacitor is connected to the second end of the sampling switch;

[0296] A current-limiting resistor;

[0297] A first current-limiting switch;

[0298] A second reset switch, the current-limiting resistor is in series with the second reset switch and in parallel with the holding capacitor, and the first current-limiting switch is in parallel with the current-limiting resistor;

[0299] The on / off state of the second reset switch is controlled based on a second target reset signal, and the on / off state of the first current-limiting switch is controlled based on a first reset signal.

[0300] In this embodiment, the on / off state of the first reset switch is controlled based on a first target reset signal.

[0301] The on / off state of the sampling switch is controlled based on a target sampling signal.

[0302] Among them, each switch is closed when the corresponding control signal is at a high level and opened when at a low level.

[0303] In some embodiments, the triode can also be replaced by a MOS transistor or a diode; each switch can be a single MOS transistor switch or a transmission gate switch.

[0304] Such as Figure 9 As shown, during the actual execution process, the peak voltage sampling and holding circuit is controlled by the first target reset signal rst1, the second target reset signal rst2, and the target sampling signal sam output from the reset and sampling control circuit. The first target reset signal rst1 controls the switch s1 (the first reset switch) to reset the voltage Vc1 of the sampling capacitor C1, and the second target reset signal rst2 controls the switch s3 (the second reset switch) to reset the voltage vdpk of the holding capacitor C2. The target sampling signal sam controls the switch s2 (the sampling switch) to sample the platform voltage of the drain terminal voltage vd_sen, that is, to make the voltage value vdpk on the holding capacitor C2 equal to the platform voltage value of the drain terminal voltage vd_sen. Among them, when the flyback switch power supply is in the first state, that is, during the chip startup phase, when exiting the light load mode and the gate drive voltage does not oscillate, the first reset signal vd_rst controls the first current-limiting switch to close, short-circuiting the current-limiting resistor R1, so as to control the reset voltage value of the holding capacitor C2 to be 0; when the flyback switch power supply is in the second state, the first reset signal vd_rst controls the first current-limiting switch to open, connecting the current-limiting resistor in series with the second reset switch, and controlling the reset voltage value of the holding capacitor C2 to be the second voltage.

[0305] Next, taking one sampling period as an example, how to reset, sample, and hold the peak voltage (platform voltage) vdpk of the drain terminal voltage vd_sen will be specifically introduced:

[0306] (1) At the beginning of each sampling period, the first target reset signal rst1 is at a high level to control the first reset switch s1 corresponding to the sampling capacitor C1 to close, and the other switches to open, clearing the voltage Vc1 of the sampling capacitor C1 to 0;

[0307] (2) When the drain terminal voltage vd_sen increases, all switches are turned off. When vd_sen > Vc1 + VBE (VBE is the turn-on voltage of the triode Q1), Q1 turns on, and the sampling capacitor C1 starts to charge. At this time, Vc1 = vd_sen;

[0308] (3) When the voltage of the sampling capacitor C1 charges to the peak voltage of the drain terminal voltage vd_sen, the triode Q1 turns off, and the sampling voltage Vc1 remains unchanged at the peak voltage of vd_sen;

[0309] (4) To ensure the real-time sampling of the platform voltage, it is necessary to reset the voltage vdpk of the hold capacitor C2; where the first reset switch s1 and the sampling switch s2 are turned off, the second target reset signal rst2 controls the second reset switch s3 corresponding to the hold capacitor C2 to close, and the first reset signal vd_rst controls the first current-limiting switch s4 to control the reset voltage of the hold capacitor C2; when the first reset signal vd_rst is at a high level, the current-limiting resistor R1 is short-circuited, and the voltage vdpk of the hold capacitor C2 is reset to 0 potential; when the first reset signal vd_rst is at a low level, the current-limiting resistor R1 is connected to the circuit, and the voltage vdpk of the hold capacitor C2 is reset to the second voltage vdpk_rst by limiting the reset current. The second voltage is related to the switching period and the change rate of the platform voltage;

[0310] (5) The second target reset signal rst2 at a high level controls the sampling switch s2 to close, and the rest of the switches are turned off. The sampling capacitor C1 charges the hold capacitor C2 until vdpk = Vc1 = the platform voltage of vd_sen;

[0311] (6) The sampling switch s2 is turned off, and the voltage vdpk of the hold capacitor C2 maintains the current voltage value.

[0312] Thus, one-time platform voltage sampling and holding of the drain terminal voltage vd_sen are completed.

[0313] Taking the application scenario of the secondary-side control chip as an example (the application scenario of this application is not limited to this application scenario), the important waveforms of sampling and holding the VD platform voltage of the SR tube proposed in this application are as Figure 10 shown. Among them, the dotted box represents the peak sampling and holding waveform when the flyback switch power supply is in the first state; the subsequent waveform is the peak sampling and holding waveform when the flyback switch power supply is in the second state. The difference between the two lies in the different reset and sampling signals selected.

[0314] According to the control system provided by the embodiments of the present application, based on a peak voltage sampling and holding circuit including an operational amplifier, a triode, a sampling capacitor, a first reset switch, a sampling switch, a holding capacitor, a current limiting resistor, a first current limiting switch, and a second reset switch, it is possible to control the switches corresponding to each control signal based on the high and low levels of the first target reset signal, the second target reset signal, the target sampling signal, and the first reset signal, and after resetting the sampling capacitor and before charging the holding capacitor based on the sampling capacitor, control the reset of the holding capacitor and the reset voltage value based on the second target reset signal and the first reset signal, so that regardless of whether the platform voltage in each sampling period rises or falls compared to the platform voltage in the previous sampling period, the platform voltage can be sampled, improving the real-time performance and accuracy of obtaining the platform voltage.

[0315] In some embodiments, the peak voltage sampling and holding circuit may include:

[0316] A third reset switch and a current mirror circuit. The current mirror circuit includes a second current limiting switch and a third current limiting switch. The second current limiting switch is in series with the third reset switch, and the third current limiting switch is in parallel with the second current limiting switch; the opening and closing state of the third reset switch is controlled based on the second target reset signal, the opening and closing state of the second current limiting switch is controlled based on the first reset signal, and the opening and closing state of the third current limiting switch is controlled based on the inverted signal of the first reset signal;

[0317] In this embodiment, the opening and closing states of each switch are configured to be closed when the control signal corresponding to each switch is at a high level and opened when it is at a low level.

[0318] It can be understood that the current limiting resistor and the first current limiting switch in the above embodiment can be replaced by a current mirror circuit.

[0319] As Figure 14 shown, during the actual execution process, the second current limiting switch S4 and the third current limiting switch S5 are controlled by the first reset signal VD_RST, and VD_RSTB is the inverted signal of the first reset signal VD_RST. That is, when the first reset signal VD_RST is at a high level, the second current limiting switch S4 is closed and the third current limiting switch S5 is opened, and the voltage VDPK of the holding capacitor is reset to 0 through the first reset current I1; when the first reset signal VD_RST is at a low level, the third current limiting switch S5 is closed and the second current limiting switch S4 is opened, and the voltage VDPK of the holding capacitor is reset to the second target set voltage VDPK_RST2 through the second reset current I2, where I1 > I2.

[0320] In some embodiments, the second target set voltage can be obtained based on the following formula:

[0321] VDPK_RST2 = VDPK - ΔV2

[0322] Wherein, vdpk_rst2 is the second target set voltage, vdpk is the voltage of the holding capacitor, and ΔV2 is the voltage change amount; wherein, the voltage change amount ΔV2 can be obtained based on the following formula:

[0323] ΔV2 = I2 * td4 / C2

[0324] Wherein, I2 is the second reset current, td4 is the pulse width of the reset signal corresponding to the holding capacitor, and C2 is the holding capacitor.

[0325] According to the control system provided by the embodiments of the present application, based on the peak voltage sampling and holding circuit including the third reset switch and the current mirror circuit, the same effect as that achieved by the combined action of the current limiting resistor, the first current limiting switch, and the second reset switch can be realized, that is, multiple ways to control the reset voltage of the holding capacitor are provided, improving the control flexibility and adaptability of the control system.

[0326] For the flyback switching power supply control method provided by the embodiments of the present application, the execution subject may be the control device of the flyback switching power supply. In the embodiments of the present application, taking the control device of the flyback switching power supply executing the flyback switching power supply control method as an example, the control device of the flyback switching power supply provided by the embodiments of the present application is described.

[0327] The embodiments of the present application also provide a control device for a flyback switching power supply.

[0328] As Figure 15 shown, the control device of the flyback switching power supply includes: a first processing module 1510, a second processing module 1520, and a third processing module 1530.

[0329] The first processing module 1510 is configured to count the number of times that the drain voltage of the switching transistor in the primary control module or the secondary control module is greater than the target voltage, and based on the waveform of the gate drive voltage of the switching transistor, determine the working state of the flyback switching power supply at the current moment; the working state includes a first state and a second state; the target voltage includes the output sampling voltage or the fixed voltage of the output capacitor in the secondary control module;

[0330] The second processing module 1520 is configured to determine the target reset signal and the target sampling signal based on the working state;

[0331] The third processing module 1530 is configured to reset the first capacitor and the second capacitor in the peak sampling and holding circuit based on the target reset signal, and sample the platform voltage of the drain voltage based on the target sampling signal.

[0332] According to the control device of the flyback switching power supply provided by the embodiments of the present application, when the counting period is reached, based on the waveform of the gate drive voltage of the switching tube, and when the gate drive voltage does not generate a waveform, based on the startup situation of the switching power supply chip and whether the light load mode is exited, it is determined whether the flyback switching power supply is in a normal state or in a working state where the chip is started, the light load mode is exited, and the gate drive voltage does not generate a waveform at the current moment. To reset the first capacitor and the second capacitor in the peak sampling and holding circuit based on the target reset signal corresponding to the working state, and after the first capacitor is recharged to a new peak voltage and the second capacitor is charged until the voltage of the second capacitor reaches the peak voltage, then sample the plateau voltage based on the target sampling signal corresponding to the working state. It can be realized that regardless of whether the peak voltage rises or falls and whether the gate drive voltage in the flyback switching power supply generates a waveform, the sampling of the plateau voltage can be completed, improving the real-time performance, recoverability, and accuracy of the plateau voltage sampling, and further enhancing the stability and reliability of the switching power supply.

[0333] In some embodiments, the first processing module 1510 may further be configured to:

[0334] When the waveform of the gate drive voltage is not detected and the chip of the flyback switching power supply is started and exits the light load mode, determine that the working state of the flyback switching power supply is the first state;

[0335] When the waveform of the gate drive voltage is detected, determine that the working state of the flyback switching power supply is the second state.

[0336] In some embodiments, the second processing module 1520 may further be configured to:

[0337] When the working state is the first state, determine the target reset signal as the first reset signal and the target sampling signal as the first sampling signal; the first reset signal and the first sampling signal are generated based on the drain voltage and the target voltage;

[0338] When the working state is the second state, determine the target reset signal as the second reset signal and the third reset signal, and determine the target sampling signal as the second sampling signal; the second reset signal is generated based on the drain voltage and the decay voltage of the plateau voltage, or based on the drain voltage and the target voltage, the third reset signal and the second sampling signal are generated based on the gate drive voltage; the decay voltage is less than the plateau voltage, and the target voltage is less than the decay voltage.

[0339] In some embodiments, the second processing module 1520 may further be configured to:

[0340] When the detected drain voltage is greater than the target voltage, the high and low levels of the first reset signal are replaced for the first time, and after the first duration, the high and low levels of the first reset signal are replaced for the second time; wherein, the moment of replacing the high and low levels of the first reset signal for the first time is the moment of resetting the first capacitor and the second capacitor;

[0341] After the second duration after the high and low levels of the first reset signal are replaced for the second time, the high and low levels of the first sampling signal are replaced, and after the third duration, the high and low levels of the first sampling signal are replaced for the second time; wherein, the moment of replacing the high and low levels of the first sampling signal for the first time is the moment of sampling the plateau voltage of the drain voltage.

[0342] In some embodiments, the second processing module 1520 may further be configured to:

[0343] When the detected drain voltage is greater than the attenuation voltage, the high and low levels of the second reset signal are replaced for the first time, and after the fourth duration, the high and low levels of the second reset signal are replaced for the second time; wherein, the moment of replacing the high and low levels of the second reset signal for the first time is the moment of resetting the first capacitor;

[0344] At the rising edge moment of the gate drive voltage, the high and low levels of the third reset signal are replaced for the first time, and after the fifth duration, the high and low levels of the third reset signal are replaced for the second time; wherein, the moment of replacing the high and low levels of the third reset signal for the first time is the moment of resetting the second capacitor;

[0345] After the sixth duration after the high and low levels of the third reset signal are replaced for the second time, the high and low levels of the second sampling signal are replaced for the first time, and after the seventh duration, the high and low levels of the second sampling signal are replaced for the second time; wherein, the moment of replacing the high and low levels of the second sampling signal for the first time is the moment of sampling the plateau voltage of the drain voltage.

[0346] In some embodiments, the third processing module 1530 may further be configured to:

[0347] Based on the target reset signal, reset the first capacitor and the second capacitor in the peak sampling and holding circuit, and sample the plateau voltage of the drain voltage based on the target sampling signal, including:

[0348] When the target reset signal is the first reset signal and the target sampling signal is the first sampling signal, at the rising edge moment of the first reset signal, reset the first capacitor and the second capacitor in the peak sampling and holding circuit, and at the rising edge moment of the first sampling signal, sample the plateau voltage of the drain voltage;

[0349] When the target reset signal is the second reset signal and the third reset signal, and the target sampling signal is the second sampling signal, at the rising edge moments of the second reset signal and the third reset signal, the first capacitor and the second capacitor are respectively reset, and at the rising edge moment of the second sampling signal, the platform voltage is sampled.

[0350] Among them, resetting the first capacitor is used to reset the voltage of the first capacitor to zero voltage, so that after the reset of the first capacitor ends, the first capacitor starts to charge from zero voltage to the peak voltage of the drain voltage; resetting the second capacitor is used to reset the voltage of the second capacitor to the first voltage, so that at the rising edge moment of the second sampling signal, the second capacitor is charged based on the voltage of the first capacitor, and the voltage of the second capacitor starts to charge from the first voltage to the platform voltage; the first voltage includes zero voltage or the second voltage; the second voltage is determined based on the switching period of the flyback switching power supply and the change rate of the platform voltage.

[0351] The control device of the flyback switching power supply in the embodiments of the present application can be a device with an operating system. The operating system can be the Android operating system, can be the IOS operating system, or can be other possible operating systems, which are not specifically limited in the embodiments of the present application.

[0352] The control device of the flyback switching power supply provided by the embodiments of the present application can implement Figure 1 each process implemented by the method embodiments. To avoid repetition, it will not be elaborated here.

[0353] In some embodiments, as Figure 16 shown, the embodiments of the present application further provide an electronic device 1600, including a processor 1601, a memory 1602, and a computer program stored on the memory 1602 and executable on the processor 1601. When the program is executed by the processor 1601, it implements each process of the above-mentioned method embodiments of the control of the flyback switching power supply, and can achieve the same technical effects. To avoid repetition, it will not be elaborated here.

[0354] It should be noted that the electronic devices in the embodiments of the present application include the above-mentioned mobile electronic devices and non-mobile electronic devices.

[0355] The embodiments of the present application further provide a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements each process of the above-mentioned method embodiments of the control of the flyback switching power supply, and can achieve the same technical effects. To avoid repetition, it will not be elaborated here.

[0356] Among them, the processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes computer-readable storage media such as computer read-only memory ROM, random access memory RAM, magnetic disk or optical disc, etc.

[0357] The embodiment of the present application further provides a computer program product, including a computer program, which when executed by a processor implements the control method of the flyback switching power supply described above.

[0358] Among them, the processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes computer-readable storage media such as computer read-only memory ROM, random access memory RAM, magnetic disk or optical disc, etc.

[0359] The embodiment of the present application further provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement each process of the embodiment of the control method of the flyback switching power supply described above, and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0360] It should be understood that the chip mentioned in the embodiment of the present application can also be referred to as a system-on-chip, system chip, chip system or system-on-chip, etc.

[0361] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including a..." does not exclude the existence of another identical element in the process, method, article or device including that element. In addition, it should be pointed out that the methods and devices in the embodiments of the present application are not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in a reverse order according to the functions involved. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0362] Through the description of the above embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases, the former is a better implementation method. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the related technology, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to enable a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of the present application.

[0363] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific implementation manners. The above specific implementation manners are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them belong to the protection scope of the present application.

[0364] In the description of this specification, the descriptions referring to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0365] Although the embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and purposes of the present application. The scope of the present application is defined by the claims and their equivalents.

Claims

1. A control method for a flyback switching power supply, characterized in that, Including: Counting the number of times that the drain voltage of the switching transistor in the primary side control module or the secondary side control module is greater than the target voltage. When the number reaches the target threshold, determining the operating state of the flyback switching power supply at the current moment based on the waveform of the gate drive voltage of the switching transistor; the operating state includes a first state and a second state; the target voltage includes the output sampling voltage of the output capacitor in the secondary side control module or a fixed voltage; Determining a target reset signal and a target sampling signal based on the operating state; Resetting the first capacitor and the second capacitor in the peak sampling and holding circuit based on the target reset signal, and sampling the platform voltage of the drain voltage based on the target sampling signal.

2. The control method of the flyback switching power supply according to claim 1, wherein Determining the operating state of the flyback switching power supply at the current moment based on the waveform of the gate drive voltage of the switching transistor; Determining a target reset signal and a target sampling signal based on the operating state, including: When the waveform of the gate drive voltage is not detected and the chip of the flyback switching power supply is turned on and exits the light load mode, determining that the operating state of the flyback switching power supply is the first state. When the operating state is the first state, determining the target reset signal as the first reset signal and the target sampling signal as the first sampling signal; the first reset signal and the first sampling signal are generated based on the drain voltage and the target voltage; When the waveform of the gate drive voltage is detected, determining that the operating state of the flyback switching power supply is the second state. When the operating state is the second state, determining the target reset signal as the second reset signal and the third reset signal, and determining the target sampling signal as the second sampling signal; the second reset signal is generated based on the drain voltage and the decay voltage of the platform voltage, or based on the drain voltage and the target voltage, and the third reset signal and the second sampling signal are generated based on the gate drive voltage; the decay voltage is less than the platform voltage, and the target voltage is less than the decay voltage.

3. The control method of the flyback switching power supply according to claim 2, wherein, The first reset signal and the first sampling signal are generated based on the drain voltage and the target voltage, including: When the moment when the drain voltage is detected to be greater than the target voltage is reached, performing a first replacement on the high and low levels of the first reset signal. After a first duration, performing a second replacement on the high and low levels of the first reset signal; wherein, the moment of the first replacement of the high and low levels of the first reset signal is the moment of resetting the first capacitor and the second capacitor; After a second duration after the second replacement of the high and low levels of the first reset signal, performing a replacement on the high and low levels of the first sampling signal. After a third duration, performing a second replacement on the high and low levels of the first sampling signal; wherein, the moment of the first replacement of the high and low levels of the first sampling signal is the moment of sampling the platform voltage of the drain voltage.

4. The control method of the flyback switching power supply according to claim 2, wherein The second reset signal is generated based on the decay voltage of the drain voltage and the platform voltage, and the third reset signal and the second sampling signal are generated based on the gate drive voltage, including: At the moment when it is detected that the drain voltage is greater than the decay voltage, the high and low levels of the second reset signal are replaced for the first time, and after a fourth time period, the high and low levels of the second reset signal are replaced for the second time; wherein, the moment of replacing the high and low levels of the second reset signal for the first time is the moment of resetting the first capacitor; At the rising edge moment of the gate drive voltage, the high and low levels of the third reset signal are replaced for the first time, and after a fifth time period, the high and low levels of the third reset signal are replaced for the second time; wherein, the moment of replacing the high and low levels of the third reset signal for the first time is the moment of resetting the second capacitor; After a sixth time period after the high and low levels of the third reset signal are replaced for the second time, the high and low levels of the second sampling signal are replaced for the first time, and after a seventh time period, the high and low levels of the second sampling signal are replaced for the second time; wherein, the moment of replacing the high and low levels of the second sampling signal for the first time is the moment of sampling the platform voltage of the drain voltage.

5. The control method of the flyback switching power supply according to any one of claims 1-4, characterized in that, Resetting the first capacitor and the second capacitor in the peak sampling and holding circuit based on the target reset signal, and sampling the platform voltage of the drain voltage based on the target sampling signal, including: When the target reset signal is the first reset signal and the target sampling signal is the first sampling signal, at the rising edge moment of the first reset signal, reset the first capacitor and the second capacitor in the peak sampling and holding circuit, and at the rising edge moment of the first sampling signal, sample the platform voltage of the drain voltage; When the target reset signal is the second reset signal and the third reset signal, and the target sampling signal is the second sampling signal, at the rising edge moments of the second reset signal and the third reset signal, reset the first capacitor and the second capacitor respectively, and at the rising edge moment of the second sampling signal, sample the platform voltage; Wherein, resetting the first capacitor is used to reset the voltage of the first capacitor to zero voltage, so that after the reset of the first capacitor ends, the first capacitor starts to charge from zero voltage to the peak voltage of the drain voltage; resetting the second capacitor is used to reset the voltage of the second capacitor to the first voltage, so that at the rising edge moment of the second sampling signal, charge the second capacitor based on the voltage of the first capacitor, so that the voltage of the second capacitor starts to charge from the first voltage to the platform voltage; the first voltage includes zero voltage or a second voltage; the second voltage is determined based on the switching period of the flyback switching power supply and the change rate of the platform voltage.

6. A control system based on the control method of the flyback switching power supply according to any one of claims 1-5, characterized in that, Including: A first comparator; A forced refresh circuit, the input end of the forced refresh circuit is connected to the output end of the first comparator; A refresh control circuit, the input end of the refresh control circuit is connected to the output end of the first comparator; A reset and sampling control circuit, the input end of the reset and sampling control circuit is connected to the output end of the refresh control circuit; A peak voltage sampling and holding circuit, the input end of the peak voltage sampling and holding circuit is respectively connected to the output end of the reset and sampling holding circuit and the output end of the peak voltage sampling and holding circuit, and the peak voltage sampling and holding circuit is used to sample the plateau voltage of the drain voltage.

7. The control system according to claim 6, wherein The forced refresh circuit includes: A counting circuit, the seventh input end of the counting circuit is connected to the output end of the first comparator, and the third output end of the counting circuit is used to output a first narrow pulse signal; the short-time high-level signal of the first narrow pulse signal is used to represent entering a new counting cycle; A first flip-flop; the eighth input end of the first flip-flop is connected to the third output end, the ninth input end is used to receive the gate drive voltage, and the fourth output end of the first flip-flop is used to output a first control signal; within each of the counting cycles, the rising edge moment of the first control signal is consistent with the first rising edge moment of the gate drive voltage, and the falling edge moment of the first control signal is consistent with the rising edge moment of the first narrow pulse signal; A falling edge delay circuit, the tenth input end of the falling edge delay circuit is connected to the fourth output end of the first flip-flop; A second flip-flop, the eleventh input end of the second flip-flop is connected to the fifth output end of the falling edge delay circuit, the twelfth input end is connected to the third output end, the thirteenth input end is used to receive an enable signal, and the sixth output end of the second flip-flop is used to output a second control signal; the enable signal is used to represent whether the control chip of the flyback switch power supply is enabled; the second control signal is used to represent whether the gate drive voltage generates a waveform within the current counting cycle; A logical NOR operator, the fourteenth input end of the logical NOR operator is connected to the sixth output end, the fifteenth input end is connected to the third output end, and the seventh output end of the logical NOR operator is used to output a target refresh signal; the high and low levels of the target refresh signal are used to participate in representing the working state.

8. The control system according to claim 6, characterized in that, The refresh control circuit includes: An abnormality judgment module, the three input ends of the abnormality judgment module are respectively used to receive an enable signal, a signal for exiting the light load mode, and a target refresh signal, and the eighth output end of the abnormality judgment module is used to output a fourth reset signal; the fourth reset signal is used to determine the target reset signal and the target sampling signal based on the working state; the signal for exiting the light load mode is used to represent whether the chip of the flyback switch power supply exits the light load mode; A third flip-flop, the sixteenth input end of the third flip-flop is connected to the output end of the first comparator, and the seventeenth input end is connected to the eighth output end; A fourth flip-flop, the eighteenth input end of the fourth flip-flop is connected to the output end of the first comparator, and the nineteenth input end is connected to the eighth output end; Logical AND operator; the twentieth input terminal and the twenty-first input terminal of the logical AND operator are respectively connected to the ninth output terminal of the third flip-flop and the tenth output terminal of the fourth flip-flop, and the eleventh output terminal of the logical AND operator is used to output a first pulse signal; the rising edge moment of the first pulse signal is used to represent the moment when the drain voltage is first detected to be greater than the target voltage when the working state in the counting period is the first state; First ost circuit; the twenty-second input terminal of the first ost circuit is connected to the eleventh output terminal, and the twelfth output terminal of the first ost circuit is used to output a first reset signal; First rising edge delay circuit; the twenty-third input terminal of the first rising edge delay circuit is connected to the eleventh output terminal, and the thirteenth output terminal of the first rising edge delay circuit is used to output a first sampling signal.

9. The control system according to any one of claims 6-8, characterized in that, The reset and sampling control circuit includes: Second comparator, the fortieth input terminal of the second comparator is used to receive the drain voltage, the forty-first input terminal is used to receive the attenuated voltage of the platform voltage, and the eighteenth output terminal of the second comparator is used to output a second square wave signal; the rising edge moment of the second square wave signal is used to represent the moment when the drain voltage is detected to be greater than the attenuated voltage each time when the working state in the counting period is the second state; Second ost circuit, the forty-second input terminal of the second ost circuit is connected to the eighteenth output terminal, and the nineteenth output terminal of the second ost circuit is used to output a second reset signal; Third ost circuit, the forty-third input terminal of the third ost circuit is used to receive the gate drive voltage, and the twentieth output terminal of the third ost circuit is used to output a third reset signal; Second rising edge delay circuit, the forty-fourth input terminal of the second rising edge delay circuit is used to receive the gate drive voltage; Fourth ost circuit, the forty-fifth input terminal of the fourth ost circuit is connected to the twenty-first output terminal of the second rising edge delay circuit, and the twenty-second output terminal of the fourth ost circuit is used to output a second sampling signal; First two-way one-select data selector, the forty-sixth input terminal of the first two-way one-select data selector is used to receive the first reset signal, the forty-seventh input terminal is connected to the nineteenth output terminal, the forty-eighth input terminal is used to receive the first pulse signal, and the twenty-third output terminal of the first two-way one-select data selector is used to output a first target reset signal; the first target reset signal includes the first reset signal or the second reset signal; Second two-way one-select data selector, the forty-ninth input terminal of the second two-way one-select data selector is used to receive the first reset signal, the fiftieth input terminal is connected to the twentieth output terminal, the fifty-first input terminal is used to receive the first pulse signal, and the twenty-fourth output terminal of the second two-way one-select data selector is used to output a second target reset signal; the second target reset signal includes the first reset signal or the third reset signal; The third multiplexer, the fifty-second input terminal of the third multiplexer is used to receive the first reset signal, the fifty-third input terminal is connected to the twenty-second output terminal, the fifty-fourth input terminal is used to receive the first pulse signal, and the twenty-fifth output terminal of the third multiplexer is used to output the target sampling signal; the target sampling signal includes the first sampling signal or the second sampling signal.

10. The control system according to any one of claims 6-8, characterized in that, The peak voltage sample and hold circuit includes: An operational amplifier, the thirty-ninth input terminal of the operational amplifier is used to receive the drain voltage; A triode, the base of the triode is connected to the seventeenth output terminal of the operational amplifier, and the collector of the triode is connected to the low-voltage power supply of the chip of the flyback switch power supply; A sampling capacitor, the sampling capacitor is connected to the seventeenth output terminal of the operational amplifier and the emitter of the triode; A first reset switch, the first reset switch is connected in parallel with the sampling capacitor, and the first end of the first reset switch is connected to the grounded side of the sampling capacitor, and the second end is connected to the non-grounded side of the sampling capacitor; the opening and closing state of the first reset switch is controlled based on the first target reset signal; A sampling switch, the first end of the sampling switch is connected to the second end of the first reset switch; the opening and closing state of the sampling switch is controlled based on the target sampling signal; A hold capacitor, the non-grounded side of the hold capacitor is connected to the second end of the sampling switch; A current-limiting resistor; A first current-limiting switch; A second reset switch, the current-limiting resistor is connected in series with the second reset switch and is connected in parallel with the hold capacitor, and the first current-limiting switch is connected in parallel with the current-limiting resistor; The opening and closing state of the second reset switch is controlled based on the second target reset signal, and the opening and closing state of the first current-limiting switch is controlled based on the first reset signal.

11. The control system according to any one of claims 6-8, characterized in that, The peak voltage sample and hold circuit includes: A third reset switch; A current mirror circuit, the current mirror circuit includes a second current-limiting switch and a third current-limiting switch, the second current-limiting switch is connected in series with the third reset switch, and the third current-limiting switch is connected in parallel with the second current-limiting switch; the opening and closing state of the third reset switch is controlled based on the second target reset signal, the opening and closing state of the second current-limiting switch is controlled based on the first reset signal, and the opening and closing state of the third current-limiting switch is controlled based on the inverted signal of the first reset signal.

12. A control device for a flyback switching power supply, characterized in that, Includes: A first processing module, configured to count the number of times that the drain voltage of the switching tube in the primary control module or the secondary control module is greater than the target voltage, and based on the waveform of the gate drive voltage of the switching tube when the number reaches the target threshold, determine the working state of the flyback switch power supply at the current moment; the working state includes a first state and a second state; the target voltage includes the output sampling voltage or the fixed voltage of the output capacitor in the secondary control module; A second processing module, configured to determine the target reset signal and the target sampling signal based on the working state; A third processing module, configured to reset a first capacitor and a second capacitor in a peak sampling and holding circuit based on the target reset signal, and sample a plateau voltage of the drain voltage based on the target sampling signal.

13. A chip, characterized in that, The chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run programs or instructions to implement the control method of the flyback switching power supply according to any one of claims 1-5.

Images