Method for realizing switching loss optimization through DPWM and VSV based on load condition

Abstract

The invention discloses a method for realizing switching loss optimization based on DPWM and VSV under a load condition, and the method comprises the steps: converting a T-type three-level inverter space vector diagram under an a-b-c coordinate system into an alpha-beta coordinate system, and obtaining the closest three vectors of a synthetic reference voltage vector Vref and the acting time of the closest three vectors; therefore, a foundation is laid for calculating the neutral-point charge Q1 with the clamping position being positive level and the neutral-point charge Q2 with the clamping position being negative level in the current switching period; then, according to a circuit topology structure of the T-type three-level inverter, obtaining a midpoint current corresponding to each vector in the positive and negative small vector switch sequences of each small sector; and finally, judging whether the reference voltage vector Vref is in a controllable region of DPWM neutral-point potential balance or not according to a sign of a product of a neutral-point charge Q1 clamped at a positive level and a neutral-point charge Q2 clamped at a negative level in a switching period when the reference voltage vector Vref is located in the small sector. And if yes, determining the capacitor voltage Udc1 of the upper bus and the capacitor voltage Udc1 of the lower bus at the direct current side of the T-type three-level inverter.

Description

Technical Field

[0001] The present invention belongs to the technical field of neutral point potential balance and switching loss optimization of T-type three-level inverters, and more specifically, relates to a method for optimizing switching losses by implementing DPWM and VSV based on load conditions. Background Art

[0002] In the field of medium-voltage high-power applications, T-type three-level inverters have been widely used due to their outstanding advantages such as low output voltage harmonics and small switching stress. However, with the increase in the number of power tubes, the complexity of its control algorithm has increased significantly, and a series of problems have inevitably arisen. Among them, the problems of neutral point potential offset and switching losses are particularly prominent. For a T-type three-level inverter, ensuring the neutral point potential balance is the key prerequisite for ensuring the safe and reliable operation of the converter. In a T-type three-level inverter, due to the charging and discharging processes of the positive and negative bus capacitors on the DC side, the offset of the neutral point potential will be caused. This offset will not only cause distortion of the output voltage and reduce the power quality, but also increase the voltage stress borne by the devices, thereby shortening the service life of the capacitors and seriously affecting the performance of the inverter. Currently, traditional independent virtual space vector modulation or discontinuous pulse width modulation methods have limitations and are difficult to achieve both the balance control of the neutral point potential and the comprehensive optimization of switching losses under all operating conditions. Therefore, how to control the neutral point potential fluctuation within the minimum range and minimize the switching losses under various operating conditions of the full modulation degree and the full load power factor angle has become an important criterion for measuring whether a T-type three-level inverter can operate efficiently.

[0003] Currently, there are two discontinuous pulse width modulation methods for realizing the neutral point potential balance and switching loss optimization of T-type three-level inverters. The first is a hybrid modulation method based on DPWM1 and DPWM3. This method uses two modulation algorithms, DPWM1 and DPWM3, which have opposite effects on the neutral point potential offset, and controls the neutral point potential offset within an acceptable range by means of hysteresis switching. The second is a switching loss optimization method based on the hybrid modulation of discontinuous pulse width modulation (abbreviated as DPWM) and virtual space vector pulse width modulation (abbreviated as VSVPWM). Both DPWM and VSVPWM modulation methods first need to obtain the action time of the nearest three vectors through coordinate transformation and trigonometric function operations, and then allocate the time of the nearest three vectors to obtain the modulation waves of 6 power switches. Finally, the modulation waves of 6 power switches are compared with the carrier wave to obtain the drive signal levels of 12 power switches of the T-type three-level inverter. ref The action time of the nearest three vectors, and then allocate the time of the nearest three vectors to obtain the modulation waves of 6 power switches, and finally compare the modulation waves of 6 power switches with the carrier wave to obtain the drive signal levels of 12 power switches of the T-type three-level inverter.

[0004] However, the above two modulation methods for achieving neutral point potential balance and switching loss optimization of the T-type three-level inverter have some non-negligible defects:

[0005] First, in the existing hybrid modulation method based on DPWM1 and DPWM3, since the switching sequences under different DPWM modes are not optimized, additional switching actions will occur during switching.

[0006] Second, the existing hybrid modulation method based on DPWM1 and DPWM3 cannot take into account neutral point balance under full modulation depth and full power factor conditions, which will increase the operation risk of the device under high-complexity conditions;

[0007] Third, the calculation process of obtaining the modulation waves of 6 power switching tubes in the existing switching loss optimization method based on the hybrid modulation of DPWM and VSVPWM is very complex, resulting in a high complexity of this implementation method, which is not conducive to real-time control and efficient implementation. Summary of the Invention

[0008] In view of the above defects or improvement requirements of the existing technology, the present invention provides a method for optimizing switching losses based on load conditions using DPWM and VSV. The purpose is to solve the technical problems that the existing hybrid modulation method based on DPWM1 and DPWM3 cannot take into account neutral point balance under full modulation depth and full power factor conditions, which will increase the operation risk of the device under high-complexity conditions, and the technical problem that additional switching actions will occur during switching due to the lack of optimization of the switching sequences under different DPWM modes; and the technical problem that the process of obtaining the modulation waves of 6 power switching tubes in the existing switching loss optimization method based on the hybrid modulation of DPWM and VSVPWM is very complex, resulting in a high complexity of this method and being not conducive to real-time control and efficient implementation.

[0009] To achieve the above object, according to one aspect of the present invention, a method for optimizing switching losses based on load conditions using DPWM and VSV is provided, including the following steps:

[0010] (1) Obtain the reference voltage vector V of the T-type three-level inverter ref and its large sector in the space vector diagram of the T-type three-level inverter, perform partitioning processing on this large sector to obtain multiple small sectors, and obtain the nearest three vectors NTV of the synthesized reference voltage vector V ref in each small sector.

[0011] (2) Perform volt-second balance calculation processing on the nearest three vectors of the synthesized reference voltage vector V ref obtained in step (1) in each small sector to obtain the action time of the nearest three vectors in this small sector.

[0012] (3) Synthesize the reference voltage vector V in each small sector obtained in step (1). ref Based on the three nearest vectors of V and the phase clamping state of this small sector, obtain the positive and negative small vector switching sequences corresponding to this small sector.

[0013] (4) According to the circuit topology of the T-type three-level inverter, obtain the midpoint currents i o1 , i o2 , i o3 corresponding to each vector in the positive and negative small vector switching sequences of each small sector obtained in step (3).

[0014] (5) According to the positive and negative small vector switching sequences corresponding to each small sector obtained in step (3), obtain their corresponding switching sequence diagrams, and according to these switching sequence diagrams, obtain the number of switching actions when each positive small vector switching sequence in this small sector switches to the negative small vector switching sequence, which is equal to the number of switching actions when each negative small vector switching sequence in this small sector switches to the positive small vector switching sequence;

[0015] (6) Select the positive and negative small vector switching sequences corresponding to the minimum number of switching actions from all the numbers of switching actions when all positive small vector switching sequences in each small sector obtained in step (5) switch to negative small vector switching sequences, as the optimal positive small vector switching sequence and the optimal negative small vector switching sequence respectively.

[0016] (7) According to the action times of the three nearest vectors of the synthesized reference voltage vector V in each small sector obtained in step (2), and the midpoint currents i ref corresponding to each vector in each positive and negative small vector switching sequence in this small sector obtained in step (4), i o1 , i o2 , i o3 , obtain the midpoint charge Q1 clamped at the positive level and the midpoint charge Q2 clamped at the negative level within one switching period when the reference voltage vector is located in this small sector.

[0017] (8) According to the midpoint charge Q1 clamped at the positive level and the midpoint charge Q2 clamped at the negative level within one switching period when the reference voltage vector V ref is located in this small sector obtained in step (7), judge whether the reference voltage vector V ref is located in the controllable region or the uncontrollable region of the midpoint potential balance of discontinuous pulse width modulation DPWM. If the reference voltage vector V ref is located in the controllable region, go to step (9); if it is located in the uncontrollable region, go to step (15).

[0018] (9) For the three-phase input voltages u a , u b, u c Sort them to obtain the phase u with the maximum voltage rmax , the phase u with the intermediate voltage rmid , and the phase u with the minimum voltage rmin ;

[0019] (10) Obtain the upper bus capacitor voltage U dc1 and the lower bus capacitor voltage U dc2 of the DC side of the T-type three-level inverter, and determine whether U dc1 > U dc2 holds. If so, obtain the zero-sequence component u zvs1 corresponding to the optimal positive small vector switching sequence in step (6) according to the phase with the maximum voltage obtained in step (9), and then transfer to step (11). Otherwise, obtain the zero-sequence component u zvs2 corresponding to the optimal negative small vector switching sequence obtained in step (6) according to the phase with the minimum voltage obtained in step (9), and then transfer to step (12).

[0020] (11) Superimpose the zero-sequence component corresponding to the optimal positive small vector switching sequence obtained in step (10) onto the three-phase input voltage of the T-type three-level inverter to obtain the first three-phase modulation wave u refx1 (which includes the first a-phase modulation wave u refa1 , the first b-phase modulation wave u refb1 , and the first c-phase modulation wave u refc1 ), and then transfer to step (13).

[0021] (12) Superimpose the zero-sequence component corresponding to the optimal negative small vector switching sequence obtained in step (10) onto the three-phase input voltage of the T-type three-level inverter to obtain the second three-phase modulation wave u refx2 (which includes the second a-phase modulation wave u refa2 , the second b-phase modulation wave u refb2 , and the second c-phase modulation wave u refc2 ), and then transfer to step (14).

[0022] (13) According to the first three-phase modulation wave u refx1 obtained in step (11), and the upper carrier wave v c1 and the lower carrier wave v c2 of the T-type three-level inverter, obtain the levels of the drive signals of the 12 power switches in the T-type three-level inverter, and then the process ends.

[0023] (14) According to the second three-phase modulation wave u refx2 obtained in step (12), and the upper carrier wave v c1 and the lower carrier wave v c2, the levels of the driving signals of the 12 power switch tubes in the T-type three-level inverter are obtained, and then the process ends.

[0024] (15) Obtain the three-phase load current i of the T-type three-level inverter a 、i b 、i c , for the three-phase load current i a 、i b 、i c Sort by phase to get the phase with the largest current rmax , current intermediate phase i rmid , the minimum current phase i rmin , then go to step (16);

[0025] (16) Obtain the upper bus capacitor voltage U on the DC side of the T-type three-level inverter dc1 and the lower bus capacitor voltage U dc2 , and determine whether there is U dc1 >U dc2 If yes, then the current intermediate phase i of the T-type three-level inverter obtained in step (15) is rmid With the minimum current i rmin Perform product processing, if i rmid with i rmin If the product of is less than 0, then go to step (17), otherwise the maximum current phase i of the T-type three-level inverter obtained in step (15) is rmax With the current intermediate phase i rmid Perform product processing, if i rmax with i rmid If it is less than 0, then go to step (18).

[0026] (17) According to step (16), i rmid with i rmin The product of is less than 0 to obtain the maximum voltage phase obtained in step (9) is clamped to a positive level (that is, the maximum voltage phase is in the P state, not in the O state and the N state, that is, d maxp =1,d maxo =d maxn =0) when the maximum voltage is u rmax The duty cycle corresponding to the P state, O state and N state, the voltage intermediate phase u rmid The duty cycle corresponding to the P state, O state and N state, and the minimum voltage phase u rmin The duty cycle corresponding to the P state, O state and N state, and then proceed to step (19).

[0027] (18) According to step (16), i rmax with i rmidThe product is less than 0. Obtain the minimum voltage obtained in step (9) and clamp it to a negative level (that is, the phase with the minimum voltage is in the N state, not in the P state and the O state, that is, d minn = 1, d minp = d mino = 0), and obtain the duty ratios corresponding to the P state, O state, and N state of the phase u rmax with the maximum voltage, the duty ratios corresponding to the P state, O state, and N state of the intermediate-phase voltage u rmid , and the duty ratios corresponding to the P state, O state, and N state of the phase u rmin with the minimum voltage, and then transfer to step (20).

[0028] (19) Calculate and process the duty ratios corresponding to the P state, O state, and N state of the phase u rmax with the maximum voltage when the phase with the maximum voltage obtained in step (17) is clamped to a positive level, the duty ratios corresponding to the P state, O state, and N state of the intermediate-phase voltage u rmid , and the duty ratios corresponding to the P state, O state, and N state of the phase u rmin with the minimum voltage, so as to obtain the third three-phase modulation wave u refx3 of VSVPWM (which includes the third a-phase modulation wave u refa3 , the third b-phase modulation wave u refb3 , and the third c-phase modulation wave u refc3 ), and then enter step (21).

[0029] (20) Calculate and process the duty ratios corresponding to the P state, O state, and N state of the phase u rmax with the maximum voltage when the phase with the minimum voltage obtained in step (18) is clamped to a negative level, the duty ratios corresponding to the P state, O state, and N state of the intermediate-phase voltage u rmid , and the duty ratios corresponding to the P state, O state, and N state of the phase u rmin with the minimum voltage, so as to obtain the fourth three-phase modulation wave u refx4 of VSVPWM (which includes the fourth a-phase modulation wave u refa4 , the fourth b-phase modulation wave u refb4 , and the fourth c-phase modulation wave u refc4 ), and then enter step (22).

[0030] (21) According to the third three-phase modulation wave u refx3 of VSVPWM obtained in step (19), and the upper carrier wave v c1 and the lower carrier wave v c2 of the T-type three-level inverter, obtain the levels of the drive signals of the 12 power switches in the T-type three-level inverter, and then the process ends.

[0031] (22) Obtain the fourth three-phase modulation wave u of VSVPWM according to step (20) refx4 and the upper carrier wave v of the T-type three-level inverter c1 and the lower carrier wave v c2 , and obtain the levels of the drive signals of the 12 power switches in the T-type three-level inverter, then the process ends.

[0032] Preferably, step (1) includes the following sub-steps:

[0033] (1-1) Obtain the three-phase input voltages u a , u b , u c of the T-type three-level inverter, and perform Clark transformation on the three-phase input voltages to obtain the α-axis component V ref of the reference voltage vector V in the α-β coordinate system α and the β-axis component V β ;

[0034] Specifically, this step uses the following formula:

[0035]

[0036]

[0037] where is the modulation degree, U dc is the DC bus voltage of the T-type three-level inverter, ω is the angular velocity of the three-phase input voltage, and t is the time.

[0038] (1-2) Process the α-axis component V ref and the β-axis component V α of the reference voltage vector V obtained in step (1-1) in the α-β coordinate system to obtain the amplitude |V β | and the phase angle θ of the reference voltage vector V ref ; ref Specifically, this step uses the following formula:

[0039]

[0040]

[0041]

[0042] (1-3) Obtain the large sector of the reference voltage vector V ref in the three-level space vector diagram according to the phase angle of the reference voltage vector V ref obtained in step (1-2);

[0042] (1-4) Obtain the synthetic reference voltage vector V refThe three nearest vectors. Specifically, in this step: First, obtain each basic voltage vector V corresponding to each small sector from the space vector diagram of the T-type three-level inverter refi , where i ∈ [1, the total number of basic voltage vectors corresponding to this small sector];

[0043] Then, calculate the distance d between the reference voltage vector V ref and each basic voltage vector V refi according to the Euclidean formula; i ;

[0044] Specifically, this step adopts the following formula:

[0045]

[0046] where V αi , V βi are respectively the α-axis component and the β-axis component of the basic voltage vector V refi in the α-β coordinate system.

[0047] Finally, select the three basic voltage vectors corresponding to the three smallest distances from all the obtained distances as the three nearest vectors for synthesizing the reference voltage vector V ref in this small sector.

[0048] Preferably, step (2) adopts the following formula:

[0049]

[0050] where T s represents the switching period of the T-type three-level inverter, V ref0 , V ref1 , V ref2 represent the three nearest vectors for synthesizing the reference voltage vector V ref in this small sector, and T1, T2, and T3 are respectively the action times of the three nearest vectors V ref0 , V ref1 , V ref2 .

[0051] The process of obtaining the positive small vector switching sequence in step (3) is specifically as follows: According to the three nearest vectors of the synthesized reference voltage vector in each small sector obtained in step (1) and the phase clamping state of this small sector, obtain three vectors containing this phase clamping state from the three nearest vectors of the synthesized reference voltage vector in this small sector, and sort the amplitudes of the three vectors containing this phase clamping state in this small sector in ascending order to obtain the sorted positive small vector switching sequence corresponding to this small sector;

[0052] The process of obtaining the negative small vector switching sequence in step (3) is specifically as follows: According to the three nearest vectors for synthesizing the reference voltage vector in each small sector obtained in step (1) and the phase clamping state of the small sector, three vectors containing the phase clamping state are obtained from the three nearest vectors for synthesizing the reference voltage vector in the small sector, and the amplitudes of the three vectors containing the phase clamping state in the small sector are sorted in ascending order to obtain the sorted negative small vector switching sequence corresponding to the small sector;

[0053] The T-type three-level inverter outputs three voltage states P, O, and N, where P represents the voltage state output by the a-phase, b-phase, or c-phase bridge arm in the three-phase bridge arm of the T-type three-level inverter, O represents the voltage state output by the a-phase, b-phase, or c-phase bridge arm in the three-phase bridge arm of the T-type three-level inverter, and N represents the voltage state output by the a-phase, b-phase, or c-phase bridge arm in the three-phase bridge arm of the T-type three-level inverter.

[0054] Preferably, step (4) adopts the following formula:

[0055] i ox =(1 - |S a |)i a +(1 - |S b |)i b +(1 - |S c |)i c (x = 1, 2, 3)

[0056] When the first element of a certain vector in the positive and negative small vector switching sequences is P, S a = 1,

[0057] When the second element of a certain vector in the positive and negative small vector switching sequences is O, S b = 0,

[0058] When the third element of a certain vector in the positive and negative small vector switching sequences is N, S c = -1,

[0059] i a represents the load current of the a-phase bridge arm of the T-type three-level inverter,

[0060] i b represents the load current of the b-phase bridge arm of the T-type three-level inverter,

[0061] i c represents the load current of the c-phase bridge arm of the T-type three-level inverter,

[0062] Step (7) specifically adopts the following calculation formula:

[0063]

[0064] Preferably, in step (8), if the reference voltage vector V obtained in step (7) ref is located in this small sector and the midpoint charge Q1 clamped to the positive level and the midpoint charge Q2 clamped to the negative level within one switching period have different signs (i.e., one is positive and the other is negative), it indicates that the reference voltage vector V ref is located in the controllable region of the midpoint potential balance of DPWM. Otherwise, it indicates that the reference voltage vector V ref is located in the uncontrollable region of the midpoint potential balance of DPWM.

[0065] Step (9) adopts the following formula:

[0066]

[0067] Step (10) adopts the following formula:

[0068]

[0069] Preferably, step (11) adopts the following formula:

[0070] u refx1 = u x + u zvs1 x = a, b, c

[0071] Step (12) adopts the following formula:

[0072] u refx2 = u x + u zvs2 x = a, b, c.

[0074] Preferably, in step (13), comparing the first a-phase modulation wave u refx1 in the first three-phase modulation wave u refa1 of DPWM with the upper carrier wave v c1 can obtain the driving signal of the power switch tube S a1 included in the a-phase bridge arm of the T-type three-level inverter. Comparing the first a-phase modulation wave u refx1 in the first three-phase modulation wave u refa1 of DPWM with the download wave v c2 can obtain the driving signal of the power switch tube S a2 included in the a-phase bridge arm of the T-type three-level inverter.

[0075] Comparing the first b-phase modulation wave u refx1 in the first three-phase modulation wave u refb1 of DPWM with the upper carrier wave v c1 can obtain the driving signal of the power switch tube S included in the b-phase bridge arm of the T-type three-level inverterb1 The driving signal is used to compare the first b-phase modulation wave u in the DPWM first three-phase modulation wave u refx1 with the download wave v refb1 to obtain the driving signal of the power switch tube S included in the b-phase bridge arm of the T-type three-level inverter c2 . b2

[0076] The first c-phase modulation wave u in the DPWM first three-phase modulation wave u refx1 is compared with the upper carrier wave v refc1 to obtain the driving signal of the power switch tube S included in the c-phase bridge arm of the T-type three-level inverter c1 . The driving signal of the power switch tube S included in the c-phase bridge arm of the T-type three-level inverter can be obtained by comparing the first c-phase modulation wave u in the DPWM first three-phase modulation wave u c1 with the download wave v refx1 . refc1 c2 to obtain the driving signal of the power switch tube S included in the c-phase bridge arm of the T-type three-level inverter c2 .

[0077] Preferably, when u refa1 > v c1 , the driving signal of the power switch tube S a1 is high level, otherwise the driving signal of the power switch tube S a1 is low level. When u refa1 > v c2 , the driving signal of the power switch tube S a2 is high level, otherwise the driving signal of the power switch tube S a2 is low level.

[0078] When u refb1 > v c1 , the driving signal of the power switch tube S b1 is high level, otherwise the driving signal of the power switch tube S b1 is low level. When u refb1 > v c2 , the driving signal of the power switch tube S b2 is high level, otherwise the driving signal of the power switch tube S b2 is low level.

[0079] When u refc1 > v c1 , the driving signal of the power switch tube S c1 is high level, otherwise the driving signal of the power switch tube S c1 is low level. When u refc1 > v c2 , the driving signal of the power switch tube S c2 ​​The drive signal is at a high level; otherwise, the power switch S c2 The drive signal is at a low level.

[0080] Preferably, step (15) uses the following formula:

[0081]

[0082] where I m is the peak value of the three-phase load current of the T-type three-level inverter, is the power factor angle of the three-phase load current.

[0083] Step (17) is calculated using the following formula:

[0084]

[0085] where d maxp , d maxo , d maxp respectively represent the duty cycles when the phase with the maximum voltage is in the P state, O state, and N state, d midp , d mido , d midn respectively represent the duty cycles when the phase with the intermediate voltage is in the P state, O state, and N state, d minp , d mino , d midp respectively represent the duty cycles when the phase with the minimum voltage is in the P state, O state, and N state.

[0086] Step (18) is calculated using the following formula:

[0087]

[0088] Preferably, step (19) uses the following formula:

[0089]

[0090] Step (20) uses the following formula:

[0091]

[0092] Generally speaking, compared with the prior art through the above technical solutions conceived by the present invention, the following beneficial effects can be achieved:

[0093] (1) Since the present invention adopts steps (1) to (6) to optimize the switching sequences under different DPWM modes, it can reduce the switching losses, significantly improve the overall performance and operating efficiency of the system, and solve the technical problem that the existing hybrid modulation method based on DPWM1 and DPWM3 causes additional switching actions during switching;

[0094] (2) Since the present invention adopts steps (7) to (14), in which the reference voltage vector V ref judges whether the reference voltage vector V is within the controllable region of DPWM midpoint potential balance by determining whether the midpoint charge Q1 clamped to the positive level and the midpoint charge Q2 clamped to the negative level have different signs within one switching period when it is located in this small sector ref Therefore, it can solve the technical problem that the existing hybrid modulation method based on DPWM1 and DPWM3 cannot take into account the midpoint balance under full modulation and full power factor conditions, resulting in an increased operation risk of the equipment under high-complexity conditions;

[0095] (3) Since the present invention adopts steps (15) to (18), clamping u rmax to the positive level or clamping u rmin to the negative level, and obtaining the duty ratios of each phase of the three-level under different clamping modes. Therefore, it can solve the problems of large computational amount and high complexity existing in the existing midpoint potential control method based on the hybrid modulation of DPWM and VSVPWM;

[0096] (4) Since the present invention adopts steps (19) to (20), calculating the duty ratios of each phase of the three-level to obtain three-phase modulation waves, and comparing the three-phase modulation waves with a carrier to generate a PWM switching sequence to realize the control of the T-type three-level inverter. Therefore, it can solve the technical problem that the midpoint potential control method based on the hybrid modulation of DPWM and VSVPWM is not conducive to real-time control and efficient implementation;

[0097] (5) The present invention breaks through the limitations of traditional methods and can comprehensively optimize key performance indicators such as midpoint potential fluctuation and switching loss under complex conditions of full modulation and full load power factor angle;

[0098] (6) The present invention effectively guarantees the balance of the midpoint voltage by precisely controlling the switching of the switching sequence, avoids the influence of large fluctuations in the midpoint potential on the performance and stability of the inverter, and at the same time minimizes the switching loss and significantly improves the energy conversion efficiency of the inverter. Brief Description of the Drawings

[0099] Figure 1 is the topology diagram of the T-type three-level inverter of the present invention;

[0100] Figure 2 is the space vector diagram of the T-type three-level inverter of the present invention;

[0101] Figure 3 is the three-level clamping diagram of the present invention; where Figure 3 (a) and Figure 3(b) are the clamping diagrams of three-level DPWM1 and DPWM3 respectively;

[0102] Figure 4 is the flowchart of the method for optimizing switching losses by DPWM and VSV based on load conditions in the present invention;

[0103] Figure 5 is the boundary diagram of the controllable and uncontrollable regions for DPWM midpoint balance in the present invention;

[0104] Figure 6 is the switching sequence diagram corresponding to some positive and negative small vector switching sequences; where Figure 6 (a) Switching sequence 1 and switching sequence 2 are the switching sequence diagrams corresponding to the positive small vector switching sequence when the reference voltage vector Vref of the present invention is in the Ι-1 small sector; Figure 6 (a) Switching sequence 3 and switching sequence 4 are the corresponding switching sequence diagrams of the negative small vector switching sequence when the reference voltage vector Vref of the present invention is in the Ι-1 small sector; Figure 6 (b) Switching sequence 1 and switching sequence 2 are the switching sequence diagrams corresponding to the positive small vector switching sequence when the reference voltage vector Vref of the present invention is in the Ι-2 small sector; Figure 6 (b) Switching sequence 3 and switching sequence 4 are the corresponding switching sequence diagrams of the negative small vector switching sequence when the reference voltage vector Vref of the present invention is in the Ι-2 small sector. Detailed implementation manners

[0105] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0106] The basic idea of the present invention is that, first, the space vector diagram of the T-type three-level inverter in the a-b-c coordinate system is transformed into the α-β coordinate system to obtain the nearest three vectors of the synthesized reference voltage vector V ref and the time of their action, thus laying a foundation for calculating the midpoint charge Q1 clamped at the positive level and the midpoint charge Q2 clamped at the negative level within the current switching period; then, according to the circuit topology of the T-type three-level inverter, the midpoint current corresponding to each vector in the positive and negative small vector switching sequences of each small sector is obtained; finally, by judging the sign of the product of the midpoint charge Q1 clamped at the positive level and the midpoint charge Q2 clamped at the negative level within one switching period when the reference voltage vector V ref is in this small sector, the reference voltage vector V refWhether it is in the controllable region of the DPWM midpoint potential balance. If the reference voltage vector V ref is in the DPWM midpoint potential controllable region, according to the upper bus capacitor voltage U of the DC side of the T-type three-level inverter dc1 and the lower bus capacitor voltage U dc2 , select the first three-phase modulation wave u of DPWM refx1 or the second three-phase modulation wave u of DPWM refx2 . Compare the obtained first three-phase modulation wave u of DPWM refx1 or the second three-phase modulation wave u refx2 with the upper carrier wave v c1 and the lower carrier wave v c2 to generate the levels of the drive signals of the 12 power switches in the T-type three-level inverter. Otherwise, according to the upper bus capacitor voltage U of the DC side of the T-type three-level inverter dc1 and the lower bus capacitor voltage U dc2 , select the third three-phase modulation wave u of VSVPWM refx3 or the fourth three-phase modulation wave u of VSVPWM refx4 . Compare the obtained third three-phase modulation wave u of VSVPWM refx3 or the fourth three-phase modulation wave u refx4 with the upper carrier wave v c1 and the lower carrier wave v c2 to generate the levels of the drive signals of the 12 power switches in the T-type three-level inverter. The balance of the upper bus capacitor and the lower bus capacitor voltages on the DC side of the T-type three-level inverter and the reduction of the losses of the T-type three-level inverter are achieved through the hybrid of the two modulation methods of DPWM and VSVPWM.

[0107] As Figure 4 shown, the present invention discloses a method for optimizing switching losses based on load conditions by DPWM and VSV, including the following steps:

[0108] (1) Obtain the reference voltage vector V of the T-type three-level inverter ref and its large sector in the space vector diagram of the T-type three-level inverter (as Figure 2 shown). Divide this large sector to obtain multiple small sectors, and obtain the nearest three vectors (Nearest Three Vectors, abbreviated as NTV) of the synthetic reference voltage vector V ref in each small sector.

[0109] The topological structure of the T-type three-level inverter is as Figure 1 shown, where each phase (i.e., phase a, phase b, and phase c) bridge arm includes 4 power switches S x1 ~S x4 , where x is equal to a, b, or c, and the power switch S x1and S x3 The drive signals of are complementary. The power switch tube S x2 and S x4 The drive signals of are complementary. The DC-side capacitor divides the DC bus voltage U of the T-type three-level inverter dc into three voltages (U dc / 2,, 0 - U dc / 2).

[0110] Taking the a-phase bridge arm as an example, when S a1 and S a2 are turned on, the output voltage is U dc / 2. When S a2 and S a3 are turned on, the output voltage is 0. When S a3 and S a4 are turned on, the output voltage is -U dc / 2. Each phase bridge arm outputs three voltages.

[0111] Specifically, this step includes the following sub-steps:

[0112] (1-1) Obtain the three-phase input voltages u a , u b , u c of the T-type three-level inverter, and perform a Clark transformation on the three-phase input voltages to obtain the α-axis component V ref and β-axis component V α of the reference voltage vector V β in the α-β coordinate system;

[0113] Specifically, this step uses the following formula:

[0114]

[0115]

[0116] where is the modulation index, U dc is the DC bus voltage of the T-type three-level inverter, ω is the angular velocity of the three-phase input voltage, and t is time.

[0117] (1-2) Process the α-axis component V ref and β-axis component V α of the reference voltage vector V β obtained in step (1-1) in the α-β coordinate system to obtain the amplitude |V ref | and phase angle θ of the reference voltage vector V ref ;

[0118] Specifically, this step uses the following formula:

[0119]

[0120] (1 - 3) Obtain the reference voltage vector V according to the reference voltage vector V obtained in step (1 - 2) ref and the phase angle of the reference voltage vector V ref in the large sector of the three - level space vector diagram;

[0121] Specifically, this step is to obtain the reference voltage vector V in the pre - established relationship list of large sector N and phase angle (as shown in Table 1 below) ref in the large sector of the three - level space vector diagram;

[0122] Table 1 Relationship list of large sector N and phase angle θ

[0123] θ 0°-60° 60°-120° 120°-180° 180°-240° 240°-300° 300°-360° N I II III IV V VI

[0124] (1 - 4) Obtain the three nearest vectors of the synthesized reference voltage vector V in each small sector of the T - type three - level inverter space vector diagram ref to the synthesized reference voltage vector V.

[0125] Specifically, this step is as follows: First, obtain each basic voltage vector V corresponding to each small sector from the space vector diagram of the T - type three - level inverter refi , where i ∈ [1, the total number of basic voltage vectors corresponding to this small sector];

[0126] Then, calculate the distance d between the reference voltage vector V ref and each basic voltage vector V refi according to the Euclidean formula i ;

[0127] Specifically, this step uses the following formula:

[0128]

[0129] where V αi and V βi are the α - axis component and β - axis component of the basic voltage vector V refi in the α - β coordinate system respectively.

[0130] Finally, select the three basic voltage vectors corresponding to the three smallest distances from all the obtained distances as the three nearest vectors of the synthesized reference voltage vector V ref in this small sector.

[0131] (2) Perform volt - second balance calculation on the three nearest vectors of the synthesized reference voltage vector V obtained in step (1) in each small sector to obtain the action time of the three nearest vectors in this small sector. ref to the synthesized reference voltage vector V.

[0132] Specifically, this step adopts the following formula:

[0133]

[0134] where T s represents the switching period of the T-type three-level inverter, and V ref0 , V ref1 , V ref2 represent the nearest three vectors of the synthesized reference voltage vector V ref in this small sector, and T1, T2, and T3 are the action times of the nearest three vectors V ref0 , V ref1 , V ref2 respectively.

[0135] For example, after the calculation of this step (2), the action times of the nearest three vectors of the synthesized reference voltage vector V ref in each small sector of the first large sector are shown in Table 2;

[0136] Table 2 Action times of the nearest three vectors in each small sector of the first large sector

[0137]

[0138] (3) According to the nearest three vectors of the synthesized reference voltage vector V ref in each small sector obtained in step (1) and the phase clamping state of this small sector, the positive and negative small vector switching sequences corresponding to this small sector are obtained, as shown in Table 3 below (it should be noted that only half of the switching sequences are given in Table 3 below, and the other half can be obtained by symmetry).

[0139] Specifically, P, O, and N are used to represent three voltage states output by the T-type three-level inverter. Among them, P represents the voltage state output by the a-phase, b-phase, or c-phase bridge arm in the three-phase bridge arm of the T-type three-level inverter (i.e., when S x1 , S x2 are turned on), O represents the voltage state output by the a-phase, b-phase, or c-phase bridge arm in the three-phase bridge arm of the T-type three-level inverter (i.e., when S x2 , S x3 are turned on), and N represents the voltage state output by the a-phase, b-phase, or c-phase bridge arm in the three-phase bridge arm of the T-type three-level inverter (i.e., when S x3 , S x4 are turned on).

[0140] In this step, the process of obtaining the positive small vector switching sequence is specifically as follows. According to the nearest three vectors of the synthesized reference voltage vector in each small sector obtained in step (1) and the phase clamping state of this small sector (such as Figure 3(as shown in (a)), obtain three vectors containing the phase clamping state from the three nearest vectors for synthesizing the reference voltage vector in this small sector (for example, if c = 0, indicating that phase c is clamped at the 0 state, then three vectors with phase c clamped at the 0 state need to be selected from the three nearest vectors for synthesizing the reference voltage vector in this small sector), sort the magnitudes of the three vectors containing the phase clamping state in this small sector in ascending order to obtain the sorted positive small vector switching sequence corresponding to this small sector (for example, for the small sector 1 in Figure 2 ), the sorted positive small vector switching sequence after sorting the magnitudes of the three obtained vectors is OOO - POO - PPO);

[0141] In this step, the process of obtaining the negative small vector switching sequence is specifically as follows. According to the three nearest vectors for synthesizing the reference voltage vector in each small sector obtained in step (1) and the phase clamping state of this small sector (as Figure 3 (shown in (b)), obtain three vectors containing the phase clamping state from the three nearest vectors for synthesizing the reference voltage vector in this small sector (for example, if a = 0, indicating that phase a is clamped at the 0 state, then three vectors with phase a clamped at the 0 state need to be selected from the three nearest vectors for synthesizing the reference voltage vector in this small sector), sort the magnitudes of the three vectors containing the phase clamping state in this small sector in ascending order to obtain the sorted negative small vector switching sequence corresponding to this small sector (for example, for the small sector 1 in Figure 2 ), the sorted negative small vector switching sequence after sorting the magnitudes of the three obtained vectors is OOO - OON - ONN);

[0142] Table 3 Positive and negative small vector switching sequences of each small sector in the first large sector

[0143]

[0144] (4) According to the circuit topology of the T-type three-level inverter, obtain the midpoint currents corresponding to each vector in the positive and negative small vector switching sequences of each small sector obtained in step (3) as i o1 , i o2 , i o3 .

[0145] Specifically, this step uses the following formula:

[0146] i ox = (1 - |S a |)i a + (1 - |S b |)i b + (1 - |S c |)i c (x = 1, 2, 3)

[0147] When the first element of a vector in the positive and negative small vector switching sequences is P, S a = 1,

[0148] When the second element of a vector in the positive and negative small vector switching sequences is O, S b = 0,

[0149] When the third element of a vector in the positive and negative small vector switching sequences is N, S c = -1,

[0150] i a represents the load current of the a-phase bridge arm of the T-type three-level inverter,

[0151] i b represents the load current of the b-phase bridge arm of the T-type three-level inverter,

[0152] i c represents the load current of the c-phase bridge arm of the T-type three-level inverter,

[0153] For example, in the positive small vector switching sequence (POO - PPO - PON), the first element of the first vector POO is P, Sa = 1; the second element is O, Sb = 0; the third element is O, Sc = 0. According to the above formula, the midpoint current i o1 for POO is i b + i c . For the second vector PPO, the first element is P, Sa = 1; the second element is P, Sb = 1; the third element is O, Sc = 0. According to the above formula, the midpoint current i o2 for PPO is i c ; for the third vector PON, the first element is P, Sa = 1; the second element is O, Sb = 0; the third element is N, Sc = -1. According to the above formula, the midpoint current i o3 for PON is i a .

[0154] After calculating according to the above formula, the relationship between the midpoint current i o1 、i o2 、i o3 corresponding to each vector in the positive and negative small vector switching sequences in each small sector of the space vector diagram of the T-type three-level inverter and the phase clamping states of different small sectors is shown in Table 4 below:

[0155] Table 4 Phase clamping states of different small sectors and midpoint currents corresponding to each vector in the positive and negative small vector switching sequences

[0156]

[0157]

[0158] (5) Obtain the corresponding switching sequence diagrams according to the positive and negative small vector switching sequences corresponding to each small sector obtained in step (3) (the switching sequence diagrams of the positive small vector switching sequences are as shown by switching sequence 1 and switching sequence 2 in Figure 6 (a), and the switching sequence diagrams of the negative small vector switching sequences are as shown by switching sequence 3 and switching sequence 4 in Figure 6 (a)), and obtain the number of switching actions when each positive small vector switching sequence in this small sector switches to a negative small vector switching sequence according to this switching sequence diagram, which is equal to the number of switching actions when each negative small vector switching sequence in this small sector switches to a positive small vector switching sequence, as shown in Table 5 below;

[0159] For example, when switching from switching sequence 1 to switching sequence 3 (OOO switches to OOO), no switching actions are generated. When switching from switching sequence 3 to switching sequence 1 (OOO switches to OOO), no switching actions are generated. When switching from switching sequence 2 to switching sequence 4 (PPO switches to OOO), 2 switching actions are generated. When switching from switching sequence 4 to switching sequence 2 (OOO switches to PPO), 2 switching actions are generated.

[0160] It should be noted that Figure 6 the switching sequence diagrams corresponding to switching sequence 1 and switching sequence 2 in Figure 6 (a) for the positive small vector switching sequences, and the switching sequence diagrams corresponding to switching sequence 3 and switching sequence 4 in

[0161] (b) for the negative small vector switching sequences. Since the switching sequences are symmetric, only the first basic vector of the positive small vector switching sequence before switching and the first basic vector of the negative small vector after switching need to be considered for the number of actions generated by the switching sequence switching. Whether it is the positive small vector switching sequence switching to the negative small vector or the negative small vector switching to the positive small vector, the number of actions generated is the same.

[0162]

[0163] (6) Select the positive small vector switching sequence and the negative small vector switching sequence corresponding to the minimum number of switching actions from all the numbers of switching actions when all positive small vector switching sequences in each small sector obtained in step (5) switch to negative small vector switching sequences, as the optimal positive small vector switching sequence and the optimal negative small vector switching sequence respectively.

[0164] The advantage of this step (6) is that by selecting the positive and negative small vector switching sequences corresponding to the minimum number of switching actions from all the switching actions when all the positive small vector switching sequences in each small sector are switched to the negative small vector switching sequences, the switching losses of the T-type three-level inverter can be reduced.

[0165] (7) According to the action times of the three nearest vectors of the synthesized reference voltage vector V in each small sector obtained in step (2), and the midpoint currents i, i, i corresponding to each vector in each positive and negative small vector switching sequence in this small sector obtained in step (4), obtain the midpoint charge Q1 clamped at the positive level and the midpoint charge Q2 clamped at the negative level within one switching period when the reference voltage vector is located in this small sector. ref The specific calculation formula adopted in this step is as follows: o1 i o2 i o3 For example, when the reference voltage vector V is located in the 2nd small sector of the I-th large sector, the expression of the midpoint charge Q1 clamped at the positive level within one switching period of the reference voltage vector V is the sum of the products of the midpoint currents (i, i, i) corresponding to the three vectors of the positive small vector switching sequence (POO - PPO - PON) in this small sector and the action times (T1, T2, T3) of the three nearest vectors in this small sector. The expression of the midpoint charge Q2 clamped at the negative level within one switching period of the reference voltage vector V is the sum of the products of the midpoint currents (i, i, i) corresponding to the three vectors of the negative small vector switching sequence (OON - ONN - PON) in this small sector and the action times (T1, T2, T3) of the three nearest vectors in this small sector.

[0166] This step specifically uses the following calculation formula:

[0167]

[0168] For example, when the reference voltage vector V ref is located in the 2nd small sector of the I-th large sector, the expression of the midpoint charge Q1 clamped at the positive level within one switching period of the reference voltage vector V ref is the sum of the products of the midpoint currents (i 01 , i 02 , i 03 ) corresponding to the three vectors of the positive small vector switching sequence (POO - PPO - PON) in this small sector and the action times (T1, T2, T3) of the three nearest vectors in this small sector. The expression of the midpoint charge Q2 clamped at the negative level within one switching period of the reference voltage vector V ref is the sum of the products of the midpoint currents (i o1 , i o2 , i o3 ) corresponding to the three vectors of the negative small vector switching sequence (OON - ONN - PON) in this small sector and the action times (T1, T2, T3) of the three nearest vectors in this small sector.

[0169] (8) According to the midpoint charge Q1 clamped at the positive level and the midpoint charge Q2 clamped at the negative level within one switching period when the reference voltage vector V is located in this small sector obtained in step (7), determine whether the reference voltage vector V is located in the controllable region or the uncontrollable region of the midpoint potential balance of Discontinuous Pulse Width Modulation (DPWM) (the controllable region of the midpoint potential balance of DPWM is as ref when the reference voltage vector V ref is located in this small sector, obtain the midpoint charge Q1 clamped at the positive level and the midpoint charge Q2 clamped at the negative level within one switching period, and judge whether the reference voltage vector V is located in the controllable region or the uncontrollable region of the midpoint potential balance of Discontinuous Pulse Width Modulation (DPWM) (the controllable region of the midpoint potential balance of DPWM is asFigure 5 As shown by the shaded part in Figure 5 the blank area in ref If the reference voltage vector V is located in the controllable region, go to step (9); if it is located in the uncontrollable region, go to step (15).

[0170] Specifically, if the reference voltage vector V obtained in step (7) ref when located in this small sector, the midpoint charge Q1 clamped to the positive level and the midpoint charge Q2 clamped to the negative level within one switching period have different signs (i.e., one is positive and the other is negative), it indicates that the reference voltage vector V ref is located in the controllable region of the midpoint potential balance of DPWM; otherwise, it indicates that the reference voltage vector V ref is located in the uncontrollable region of the midpoint potential balance of DPWM.

[0171] (9) Sort the three-phase input voltages u a 、u b 、u c of the T-type three-level inverter to obtain the phase with the maximum voltage u rmax 、the phase with the intermediate voltage u rmid 、the phase with the minimum voltage u rmin ;

[0172] Specifically, this step uses the following formula:

[0173]

[0174] (10) Obtain the upper bus capacitor voltage U dc1 and the lower bus capacitor voltage U dc2 of the DC side of the T-type three-level inverter, and judge whether U dc1 > U dc2 holds. If so, obtain the zero-sequence component u zvs1 corresponding to the optimal positive small vector switching sequence in step (6) according to the phase with the maximum voltage obtained in step (9), and then go to step (11); otherwise, obtain the zero-sequence component u zvs2 corresponding to the optimal negative small vector switching sequence obtained in step (6) according to the phase with the minimum voltage obtained in step (9), and then go to step (12).

[0175] Specifically, this step uses the following formula:

[0176]

[0177] (11) Superimpose the zero-sequence component corresponding to the optimal positive small vector switching sequence obtained in step (10) onto the three-phase input voltages of the T-type three-level inverter to obtain the first three-phase modulation wave u of DPWMrefx1 (It includes the first a-phase modulation wave u refa1 , the first b-phase modulation wave u refb1 , and the first c-phase modulation wave u refc1 ), and then proceed to step (13).

[0178] Specifically, this step uses the following formula:

[0179] u refx1 = u x + u zvs1 x = a, b, c

[0180] (12) Superimpose the zero-sequence component corresponding to the optimal negative small vector switching sequence obtained in step (10) onto the three-phase input voltages of the T-type three-level inverter to obtain the DPWM second three-phase modulation wave u refx2 (It includes the second a-phase modulation wave u refa2 , the second b-phase modulation wave u refb2 , and the second c-phase modulation wave u refc2 ), and then proceed to step (14).

[0181] Specifically, this step uses the following formula:

[0182] u refx2 = u x + u zvs2 x = a, b, c

[0183] (13) According to the DPWM first three-phase modulation wave u refx1 obtained in step (11), and the upper carrier v c1 and the lower carrier v c2 of the T-type three-level inverter, obtain the levels of the drive signals for the 12 power switching tubes in the T-type three-level inverter, and then the process ends.

[0184] Specifically, the T-type three-level inverter has a total of 12 power switching tubes, so 12 drive signals are required to control these power switching tubes.

[0185] Compare the first a-phase modulation wave u refx1 in the DPWM first three-phase modulation wave u refa1 with the upper carrier v c1 to obtain the drive signal for the power switching tube S a1 included in the a-phase bridge arm of the T-type three-level inverter. Compare the first a-phase modulation wave u refx1 in the DPWM first three-phase modulation wave u refa1 with the lower carrier v c2 to obtain the drive signal for the power switching tube S a2The drive signal.

[0186] Specifically, when u refa1 > v c1 the drive signal of the power switch tube S a1 is at a high level, otherwise the drive signal of the power switch tube S a1 is at a low level. When u refa1 > v c2 the drive signal of the power switch tube S a2 is at a high level, otherwise the drive signal of the power switch tube S a2 is at a low level.

[0187] By comparing the first b-phase modulation wave u refx1 in the DPWM first three-phase modulation wave u refb1 with the upper carrier wave v c1 the drive signal of the power switch tube S b1 included in the b-phase bridge arm of the T-type three-level inverter can be obtained. By comparing the first b-phase modulation wave u refx1 in the DPWM first three-phase modulation wave u refb1 with the downloaded wave v c2 the drive signal of the power switch tube S b2 included in the b-phase bridge arm of the T-type three-level inverter can be obtained.

[0188] Specifically, when u refb1 > v c1 the drive signal of the power switch tube S b1 is at a high level, otherwise the drive signal of the power switch tube S b1 is at a low level. When u refb1 > v c2 the drive signal of the power switch tube S b2 is at a high level, otherwise the drive signal of the power switch tube S b2 is at a low level.

[0189] By comparing the first c-phase modulation wave u refx1 in the DPWM first three-phase modulation wave u refc1 with the upper carrier wave v c1 the drive signal of the power switch tube S c1 included in the c-phase bridge arm of the T-type three-level inverter can be obtained. By comparing the first c-phase modulation wave u refx1 in the DPWM first three-phase modulation wave u refc1 with the downloaded wave v c2 the drive signal of the power switch tube S c2 included in the c-phase bridge arm of the T-type three-level inverter can be obtained.

[0190] Specifically, when u refc1>v c1 When u c1 >v, the driving signal of the power switch tube S c1 is at a high level; otherwise, the driving signal of the power switch tube S refc1 is at a low level. When u c2 >v, the driving signal of the power switch tube S c2 is at a high level; otherwise, the driving signal of the power switch tube S c2 is at a low level.

[0191] It should be noted that the driving signals of S x1 and S x3 , S x2 and S x4 are complementary. The driving signals of any two tubes in each phase leg can be obtained by logically inverting the driving signals of the other two tubes.

[0192] After comparing the first three-phase modulation wave u refx1 of DPWM with the carrier wave v c1 and the sub-carrier wave v c2 , the levels of the driving signals of the 12 power switch tubes of the T-type three-level inverter can be obtained to control the conduction and cutoff of each power switch tube in the T-type three-level inverter, thereby controlling the normal operation of the T-type three-level inverter.

[0193] (14) According to the second three-phase modulation wave u refx2 of DPWM obtained in step (12), as well as the carrier wave v c1 and the sub-carrier wave v c2 of the T-type three-level inverter, obtain the levels of the driving signals of the 12 power switch tubes in the T-type three-level inverter, and then the process ends.

[0194] The principle of obtaining the driving signals of the 12 power switch tubes of the T-type three-level inverter by comparing the second three-phase modulation wave u refx2 of DPWM with the carrier wave v c1 and the sub-carrier wave v c2 is the same as that in step (13).

[0195] (15) Obtain the three-phase load currents i a , i b , i c of the T-type three-level inverter, sort the three-phase load currents i a , i b , i c to obtain the phase with the largest current i rmax , the phase with the intermediate current i rmid , and the phase with the smallest current i rmin , and then transfer to step (16);

[0196] Specifically, this step uses the following formula:

[0197]

[0198] where I m is the peak value of the three-phase load current of the T-type three-level inverter, and

[0199] (16) Obtain the upper bus capacitor voltage U dc1 and the lower bus capacitor voltage U dc2 of the DC side of the T-type three-level inverter, and determine whether U dc1 > U dc2 holds. If so, perform a product operation on the current intermediate phase i rmid and the current minimum phase i rmin of the T-type three-level inverter obtained in step (15). If the product of i rmid and i rmin is less than 0, then enter step (17). Otherwise, perform a product operation on the current maximum phase i rmax and the current intermediate phase i rmid of the T-type three-level inverter obtained in step (15). If the product of i rmax and i rmid is less than 0, then enter step (18).

[0200] (17) Obtain the duty ratios corresponding to the P state, O state, and N state of the maximum voltage phase u rmid and i rmin when the maximum voltage phase obtained in step (9) is clamped to the positive level (i.e., the voltage maximum phase is in the P state, not in the O state and N state, i.e., d maxp = 1, d maxo = d maxn = 0), the duty ratios corresponding to the P state, O state, and N state of the intermediate voltage phase u rmax , and the duty ratios corresponding to the P state, O state, and N state of the minimum voltage phase u rmid , and then transfer to step (19). rmin Specifically, this step is calculated using the following formula:

[0201] where d

[0202]

[0203] where d maxp , d maxo , d maxp respectively represent the duty ratios of the maximum voltage phase in the P state, O state, and N state, d midp, d mido , d midn respectively represent the duty cycles when the intermediate voltage phase is in the P state, O state, and N state, d minp , d mino , d midp respectively represent the duty cycles when the minimum voltage phase is in the P state, O state, and N state.

[0204] For example, after the calculation of this step (17), when the maximum voltage phase u rmax is clamped to a positive level, the duty cycles of each phase of the three-level are shown in Table 6.

[0205] Table 6 Duty Cycles of Each Phase When Clamped to a Positive Level

[0206]

[0207] (18) Obtain the product of i rmax and i rmid less than 0, and obtain the duty cycles corresponding to the maximum voltage phase u minn when the minimum voltage phase obtained in step (9) is clamped to a negative level (that is, the minimum voltage phase is in the N state, not in the P state and O state, that is, d minp = 1, d mino = d rmax = 0) in the P state, O state, and N state, the duty cycles corresponding to the intermediate voltage phase u rmid in the P state, O state, and N state, and the duty cycles corresponding to the minimum voltage phase u rmin in the P state, O state, and N state, and then transfer to step (20).

[0208] Specifically, this step is calculated using the following formula:

[0209]

[0210] where d maxp , d maxo , d maxp respectively represent the duty cycles when the maximum voltage phase is in the P state, O state, and N state, d midp , d mido , d midn respectively represent the duty cycles when the intermediate voltage phase is in the P state, O state, and N state, d minp , d mino , d midp respectively represent the duty cycles when the minimum voltage phase is in the P state, O state, and N state.

[0211] For example, after the calculation of this step (18), the minimum voltage phase u rminWhen the clamping is at a negative level, the duty ratios of each phase of the three-level are shown in Table 7;

[0212] Table 7 Duty ratios of each phase when clamped to a negative level

[0213]

[0214] (19) For the phase with the maximum voltage obtained in step (17), when the clamping is at a positive level, the phase with the maximum voltage u rmax The duty ratios corresponding to the P state, O state, and N state, the phase with the intermediate voltage u rmid The duty ratios corresponding to the P state, O state, and N state, and the phase with the minimum voltage u rmin The duty ratios corresponding to the P state, O state, and N state are calculated and processed to obtain the third three-phase modulation wave u of VSVPWM refx3 (which includes the third a-phase modulation wave u refa3 , the third b-phase modulation wave u refb3 , and the third c-phase modulation wave u refc3 ), and then enter step (21).

[0215] Specifically, this step uses the following formula:

[0216]

[0217] (20) For the phase with the maximum voltage obtained in step (18), when the clamping is at a negative level, the phase with the maximum voltage u rmax The duty ratios corresponding to the P state, O state, and N state, the phase with the intermediate voltage u rmid The duty ratios corresponding to the P state, O state, and N state, and the phase with the minimum voltage u rmin The duty ratios corresponding to the P state, O state, and N state are calculated and processed to obtain the fourth three-phase modulation wave u of VSVPWM refx4 (which includes the fourth a-phase modulation wave u refa4 , the fourth b-phase modulation wave u refb4 , and the fourth c-phase modulation wave u refc4 ), and then enter step (22).

[0218] Specifically, this step uses the following formula:

[0219]

[0220] (21) According to the third three-phase modulation wave u of VSVPWM obtained in step (19) refx3 , and the upper carrier v of the T-type three-level inverter c1 and the lower carrier v c2 , obtain the levels of the drive signals of the 12 power switches in the T-type three-level inverter, and then the process ends.

[0221] The third three-phase modulation wave u of VSVPWM refx3 and the upper carrier wave v c1 and the lower carrier wave v c2 After comparison, the principle and steps (13) for obtaining the drive signals of the 12 power switches of the T-type three-level inverter are the same.

[0222] (22) According to the fourth three-phase modulation wave u of VSVPWM obtained in step (20) refx4 , and the upper carrier wave v of the T-type three-level inverter c1 and the lower carrier wave v c2 , obtain the levels of the drive signals of the 12 power switches in the T-type three-level inverter, and then the process ends.

[0223] The fourth three-phase modulation wave u of VSVPWM refx4 and the upper carrier wave v c1 and the lower carrier wave v c1 After comparison, the principle and steps (13) for obtaining the drive signals of the 12 power switches of the T-type three-level inverter are the same.

[0224] Those skilled in the art can easily understand that the above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for optimizing switching losses by implementing DPWM and VSV based on load conditions, characterized in that, It includes the following steps: (1) Obtaining the reference voltage vector V of the T-type three-level inverter ref and a large sector in the space vector diagram of the T-type three-level inverter, the large sector is divided to obtain multiple small sectors, and the synthetic reference voltage vector V in each small sector is obtained ref The nearest three vector NTV. (2) Perform the volt-second balance calculation process on the three nearest vectors of the synthesized reference voltage vector V in each small sector obtained in step (1) to obtain the action time of the three nearest vectors in this small sector. ref ​ (3) Synthesize the reference voltage vector V in each small sector obtained in step (1). ref Obtain the positive and negative small vector switching sequences corresponding to the small sector according to the three nearest vectors of V and the phase clamping state of the small sector. (4) Obtain the midpoint currents corresponding to each vector in the positive and negative small vector switch sequences of each small sector obtained in step (3) according to the circuit topology of the T-type three-level inverter, which are \(i\) o1 、 \(i\) o2 、 \(i\) o3 respectively. (5) Obtain the corresponding switching sequence diagram according to the positive and negative small vector switching sequences corresponding to each small sector obtained in step (3), and obtain the number of switching actions when each positive small vector switching sequence in this small sector switches to the negative small vector switching sequence according to this switching sequence diagram, which is equal to the number of switching actions when each negative small vector switching sequence in this small sector switches to the positive small vector switching sequence; (6) Select the positive small vector switching sequence and the negative small vector switching sequence corresponding to the minimum number of switching actions from all the number of switching actions when all positive small vector switching sequences in each small sector obtained in step (5) switch to negative small vector switching sequences, and use them as the optimal positive small vector switching sequence and the optimal negative small vector switching sequence respectively. (7) Synthesize the reference voltage vector V in each small sector obtained according to step (2). ref The action time of the three nearest vectors of, and the midpoint current i corresponding to each vector in each positive and negative small vector switching sequence in this small sector obtained in step (4). o1 , i o2 , i o3 , obtain the midpoint charge Q1 clamped to the positive level and the midpoint charge Q2 clamped to the negative level within one switching period when the reference voltage vector is located in this small sector. (8) The reference voltage vector V obtained according to step (7) ref When it is located in this small sector, the midpoint charge Q1 clamped to the positive level and the midpoint charge Q2 clamped to the negative level within one switching period are used to determine the reference voltage vector V ref Is it located in the controllable region or the uncontrollable region of the midpoint potential balance of the discontinuous pulse width modulation DPWM? If the reference voltage vector V ref Is located in the controllable region, go to step (9); if it is located in the uncontrollable region, go to step (15). (9) Sort the three-phase input voltages u a 、u b 、u c of the T-type three-level inverter to obtain the phase with the maximum voltage u rmax 、the phase with the intermediate voltage u rmid 、and the phase with the minimum voltage u rmin ; (10) Obtain the upper bus capacitor voltage U of the DC side of the T-type three-level inverter dc1 and the lower bus capacitor voltage U dc2 , and determine whether U dc1 > U dc2 holds. If so, obtain the zero-sequence component u of the optimal positive small-vector switching sequence in step (6) according to the phase with the maximum voltage obtained in step (9) zvs1 , and then transfer to step (11). Otherwise, obtain the zero-sequence component u of the optimal negative small-vector switching sequence obtained in step (6) according to the phase with the minimum voltage obtained in step (9) zvs2 , and then transfer to step (12). (11) Superimpose the zero-sequence component corresponding to the optimal positive small vector switching sequence obtained in step (10) onto the three-phase input voltages of the T-type three-level inverter to obtain the first three-phase modulation wave u of DPWM refx1 (which includes the first modulation wave u of phase a refa1 , the first modulation wave u of phase b refb1 , and the first modulation wave u of phase c refc1 ), and then proceed to step (13). (12) Superimpose the zero-sequence component corresponding to the optimal negative small vector switching sequence obtained in step (10) onto the three-phase input voltages of the T-type three-level inverter to obtain the second three-phase modulation wave u of DPWM refx2 (which includes the second a-phase modulation wave u refa2 , the second b-phase modulation wave u refb2 , and the second c-phase modulation wave u refc2 ), and then proceed to step (14). (13) Obtain the first three-phase modulation wave u of DPWM according to step (11) refx1 , and the upper carrier v c1 and the lower carrier v c2 of the T-type three-level inverter, obtain the levels of the drive signals of the 12 power switches in the T-type three-level inverter, and then the process ends. (14) Obtain the second three-phase modulation wave u of DPWM according to step (12) refx2 , and the upper carrier wave v of the T-type three-level inverter c1 and the lower carrier wave v c2 , obtain the levels of the drive signals of the 12 power switches in the T-type three-level inverter, and then the process ends. (15) Obtain the three-phase load currents \(i_{a}\), \(i_{b}\), \(i_{c}\) of the T-type three-level inverter, sort the three-phase load currents \(i_{a}\), \(i_{b}\), \(i_{c}\) to obtain the phase with the largest current \(i_{max}\), the phase with the intermediate current \(i_{mid}\), and the phase with the smallest current \(i_{min}\), and then transfer to step (16); a , \(i\) b , \(i\) c , for the three-phase load currents \(i\) a , \(i\) b , \(i\) c perform sorting to obtain the phase with the largest current \(i\) rmax , the phase with the intermediate current \(i\) rmid , the phase with the smallest current \(i\) rmin , and then transfer to step (16); (16) Obtain the upper bus capacitor voltage U of the DC side of the T-type three-level inverter dc1 and the lower bus capacitor voltage U dc2 , and determine whether U dc1 > U dc2 holds. If so, perform a product operation on the current intermediate phase i rmid of the T-type three-level inverter obtained in step (15) and the current minimum phase i rmin . If the product of i rmid and i rmin is less than 0, then enter step (17). Otherwise, perform a product operation on the current maximum phase i rmax of the T-type three-level inverter obtained in step (15) and the current intermediate phase i rmid . If the product of i rmax and i rmid is less than 0, then enter step (18). (17) The i obtained according to step (16) rmid and i rmin The product of is less than 0. Obtain the maximum voltage obtained in step (9) and clamp it to a positive level (that is, the phase with the maximum voltage is in the P state, not in the O state and the N state, that is, d maxp = 1, d maxo = d maxn = 0) When the phase u with the maximum voltage rmax The duty ratios corresponding to the P state, the O state, and the N state, the intermediate voltage phase u rmid The duty ratios corresponding to the P state, the O state, and the N state, and the minimum voltage phase u rmin The duty ratios corresponding to the P state, the O state, and the N state, and then transfer to step (19). (18) The i obtained according to step (16) rmax and i rmid The product of is less than 0. Obtain the minimum voltage obtained in step (9) and clamp it to a negative level (that is, the phase with the minimum voltage is in the N state, not in the P state and the O state, that is, d minn = 1, d minp = d mino = 0), the duty ratios corresponding to the phase with the maximum voltage u rmax being in the P state, the O state and the N state, the duty ratios corresponding to the phase with the intermediate voltage u rmid being in the P state, the O state and the N state, and the duty ratios corresponding to the phase with the minimum voltage u rmin being in the P state, the O state and the N state, and then go to step (20). (19) Clamp the phase with the maximum voltage obtained in step (17) to the positive level as phase u with the maximum voltage rmax The duty ratios corresponding to the P state, O state, and N state, and phase u with the intermediate voltage rmid The duty ratios corresponding to the P state, O state, and N state, and phase u with the minimum voltage rmin Perform calculation processing on the duty ratios corresponding to the P state, O state, and N state to obtain the third three-phase modulation wave u of VSVPWM refx3 (which includes the third a-phase modulation wave u refa3 , the third b-phase modulation wave u refb3 , and the third c-phase modulation wave u refc3 ), and then enter step (21). (20) Clamp the phase with the minimum voltage obtained in step (18) to the maximum phase u when the voltage of the negative level rmax The duty ratios corresponding to the P state, O state, and N state, and the intermediate voltage phase u rmid The duty ratios corresponding to the P state, O state, and N state, and the minimum voltage phase u rmin Calculate and process the duty ratios corresponding to the P state, O state, and N state to obtain the fourth three-phase modulation wave u of VSVPWM refx4 (which includes the fourth a-phase modulation wave u refa4 , the fourth b-phase modulation wave u refb4 , and the fourth c-phase modulation wave u refc4 ), and then enter step (22). (21) Obtain the third three-phase modulation wave u of VSVPWM according to step (19) refx3 , as well as the upper carrier v of the T-type three-level inverter c1 and the lower carrier v c2 , obtain the levels of the drive signals of the 12 power switches in the T-type three-level inverter, and then the process ends. (22) The fourth three-phase modulation wave u of VSVPWM obtained according to step (20) refx4 , and the upper carrier v c1 and the lower carrier v c2 of the T-type three-level inverter are used to obtain the levels of the drive signals of the 12 power switches in the T-type three-level inverter, and then the process ends.

2. The method for optimizing switching losses by implementing DPWM and VSV based on load conditions according to claim 1, wherein Step (1) includes the following sub-steps: (1-1) Obtain the three-phase input voltages u a , u b , u c of the T-type three-level inverter, and perform Clark transformation on the three-phase input voltages to obtain the α-axis component V ref of the reference voltage vector V in the α-β coordinate system and the β-axis component V α ; β ; Specifically, this step uses the following formula: where is the modulation index, U dc is the DC bus voltage of the T-type three-level inverter, ω is the angular velocity of the three-phase input voltage, and t is time. (1-2) Process the α-axis component V ref and the β-axis component V α of the reference voltage vector V β obtained in step (1-1) in the α-β coordinate system to obtain the amplitude |V ref | and phase angle θ of the reference voltage vector V ref ; Specifically, this step uses the following formula: (1-3) Obtain the reference voltage vector V according to the reference voltage vector V obtained in step (1-2). ref Obtain the large sector of the reference voltage vector V in the three-level space vector diagram according to the phase angle of ref the reference voltage vector V; (1-4) Obtain the three nearest vectors of the synthesized reference voltage vector V in each small sector of the space vector diagram of the T-type three-level inverter. This step is specifically as follows: First, obtain each basic voltage vector V corresponding to each small sector from the space vector diagram of the T-type three-level inverter ref , where i ∈ [1, the total number of basic voltage vectors corresponding to this small sector]; refi ​ Then, calculate the reference voltage vector V according to Euclidean formula ref and the distance d refi from each basic voltage vector V i ; Specifically, this step uses the following formula: where V αi and V βi are the α-axis component and β-axis component of the basic voltage vector V refi in the α-β coordinate system, respectively. Finally, from all the obtained distances, select the three basic voltage vectors corresponding to the smallest three distances as the nearest three vectors of the synthesized reference voltage vector V ref in this small sector.

3. The method for optimizing switching losses by implementing DPWM and VSV based on load conditions according to claim 1 or 2, characterized in that Step (2) uses the following formula: Among which T s represents the switching period of the T-type three-level inverter, and V ref0 , V ref1 , V ref2 represent the three nearest vectors of the synthesized reference voltage vector V ref in this small sector. T1, T2, and T3 are the action times of the three nearest vectors V ref0 , V ref1 , V ref2 respectively. The process of obtaining the positive small vector switching sequence in step (3) is specifically as follows: According to the nearest three vectors of the synthesized reference voltage vector in each small sector obtained in step (1) and the phase clamping state of this small sector, obtain three vectors containing this phase clamping state from the nearest three vectors of the synthesized reference voltage vector in this small sector, and sort the amplitudes of the three vectors containing this phase clamping state in this small sector in ascending order to obtain the sorted positive small vector switching sequence corresponding to this small sector; The process of obtaining the negative small vector switching sequence in step (3) is specifically as follows: According to the nearest three vectors of the synthesized reference voltage vector in each small sector obtained in step (1) and the phase clamping state of this small sector, obtain three vectors containing this phase clamping state from the nearest three vectors of the synthesized reference voltage vector in this small sector, and sort the amplitudes of the three vectors containing this phase clamping state in this small sector in ascending order to obtain the sorted negative small vector switching sequence corresponding to this small sector; The T-type three-level inverter outputs three voltage states P, O, and N, where P represents the voltage state output by the a-phase, b-phase, or c-phase bridge arm in the three-phase bridge arm of the T-type three-level inverter, O represents the voltage state output by the a-phase, b-phase, or c-phase bridge arm in the three-phase bridge arm of the T-type three-level inverter, and N represents the voltage state output by the a-phase, b-phase, or c-phase bridge arm in the three-phase bridge arm of the T-type three-level inverter.

4. The method for optimizing switching losses by implementing DPWM and VSV based on load conditions according to any one of claims 1 to 3, characterized in that Step (4) uses the following formula: i ox = (1 - |S a |)i a + (1 - |S b |)i b + (1 - |S c |)i c (x = 1, 2, 3) When the first element of a vector in the positive and negative small vector switch sequences is P, S a = 1, When the second element of a certain vector in the positive and negative small vector switch sequences is 0, S b = 0, When the third element of a certain vector in the positive and negative small vector switch sequences is N, S c = -1, i a represents the load current of the a-phase bridge arm of the T-type three-level inverter i b represents the load current of the b-phase bridge arm of the T-type three-level inverter i c represents the load current of the C-phase bridge arm of the T-type three-level inverter Step (7) specifically uses the following calculation formula:

5. The method for optimizing switching losses by implementing DPWM and VSV based on load conditions according to claim 4, characterized in that In step (8), if the reference voltage vector V obtained in step (7) ref is located in this small sector and the midpoint charge Q1 clamped to the positive level and the midpoint charge Q2 clamped to the negative level are of different signs within one switching period (i.e., one is positive and the other is negative), it indicates that the reference voltage vector V ref is located in the controllable region of the midpoint potential balance of DPWM. Otherwise, it indicates that the reference voltage vector V ref is located in the uncontrollable region of the midpoint potential balance of DPWM. Step (9) uses the following formula: Step (10) uses the following formula:

6. The method for optimizing switching losses by implementing DPWM and VSV based on load conditions according to claim 5, wherein: Step (11) uses the following formula: u refx1 = u x + u zvs1 x = a, b, c Step (12) uses the following formula: u refx2 = u x + u zvs2 where x = a, b, c.

7. The method for optimizing switching losses by implementing DPWM and VSV based on load conditions according to claim 6, wherein: In step (13), compare the first a-phase modulation wave u refx1 in the DPWM first three-phase modulation wave u refa1 with the upper carrier wave v c1 to obtain the drive signal of the power switch tube S a1 included in the a-phase bridge arm of the T-type three-level inverter. Compare the first a-phase modulation wave u refx1 in the DPWM first three-phase modulation wave u refa1 with the download wave v c2 to obtain the drive signal of the power switch tube S a2 included in the a-phase bridge arm of the T-type three-level inverter. Compare the first b-phase modulation wave u refx1 in the DPWM first three-phase modulation wave u refb1 with the upper carrier wave v c1 to obtain the drive signal of the power switch tube S b1 included in the b-phase bridge arm of the T-type three-level inverter. Compare the first b-phase modulation wave u refx1 in the DPWM first three-phase modulation wave u refb1 with the download wave v c2 to obtain the drive signal of the power switch tube S b2 included in the b-phase bridge arm of the T-type three-level inverter. Compare the first c-phase modulation wave u refx1 in the DPWM first three-phase modulation wave u refc1 with the upper carrier wave v c1 to obtain the drive signal of the power switch tube S c1 included in the c-phase bridge arm of the T-type three-level inverter. Compare the first c-phase modulation wave u refx1 in the DPWM first three-phase modulation wave u refc1 with the downloaded wave v c2 to obtain the drive signal of the power switch tube S c2 included in the c-phase bridge arm of the T-type three-level inverter.

8. The method for optimizing switching losses by implementing DPWM and VSV based on load conditions according to claim 7, wherein: When u refa1 > v c1 , the drive signal of the power switch tube S a1 is high level, otherwise the drive signal of the power switch tube S a1 is low level. When u refa1 > v c2 , the drive signal of the power switch tube S a2 is high level, otherwise the drive signal of the power switch tube S a2 is low level. When u refb1 > v c1 the drive signal of the power switch tube S b1 is high level, otherwise the drive signal of the power switch tube S b1 is low level. When u refb1 > v c2 the drive signal of the power switch tube S b2 is high level, otherwise the drive signal of the power switch tube S b2 is low level. When u refc1 > v c1 the drive signal of the power switch tube S c1 is at a high level, otherwise the drive signal of the power switch tube S c1 is at a low level. When u refc1 > v c2 the drive signal of the power switch tube S c2 is at a high level, otherwise the drive signal of the power switch tube S c2 is at a low level.

9. The method for optimizing switching losses by implementing DPWM and VSV based on load conditions according to claim 8, wherein: Step (15) uses the following formula: Where I m is the peak value of the three-phase load current of the T-type three-level inverter, is the power factor angle of the three-phase load current. Step (17) is calculated using the following formula: where d maxp , d maxo , d maxp respectively represent the duty cycles when the phase with the maximum voltage is in the P state, O state, and N state, d midp , d mido , d midn respectively represent the duty cycles when the phase with the intermediate voltage is in the P state, O state, and N state, d minp , d mino , d midp respectively represent the duty cycles when the phase with the minimum voltage is in the P state, O state, and N state. Step (18) is calculated using the following formula:

10. The method for optimizing switching losses by implementing DPWM and VSV based on load conditions according to claim 9, wherein: Step (19) uses the following formula: Step (20) uses the following formula:

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