Ringing suppression circuit, buck-boost converter, chip, and electronic device

Abstract

The invention provides a ringing suppression circuit, a buck-boost converter, a chip and electronic equipment. The ringing suppression circuit comprises a detection circuit and a power tube. After enabling, the detection circuit can obtain a first signal used for controlling the power tube to be turned on or turned off according to the voltage and zero voltage of the switch node, and transmits the first signal to the power tube, so that the power tube can obtain the first signal. Therefore, when the voltage of the switch node is increased to zero voltage from the output voltage of the buck-boost converter, the power tube can be turned on according to the first signal, so that the power tube can control the switch node to be connected with the ground potential, and the ringing phenomenon of the switch node is eliminated. When the power tube is turned on, the voltage of the switch node is zero voltage, so that the voltage at the two ends of the power tube is very small. Therefore, the power consumption of the power tube can be reduced, the power consumption of the ringing suppression circuit is reduced, and the influence on the efficiency of the buck-boost converter is avoided.

Description

Technical Field

[0001] This application relates to the technical field of power management chips, and particularly to a ringing suppression circuit, a buck-boost converter, a chip, and an electronic device. Background Art

[0002] A buck-boost converter (Buck-Boost) generally includes: an inductor, a high-side power transistor, and a low-side power transistor. When the Buck-Boost operates at a small load, after detecting that the current of the inductor is 0, a zero-crossing signal is triggered to control the simultaneous turn-off of the high-side power transistor and the low-side power transistor, so as to avoid the current of the inductor from continuing to flow as a negative current. In this way, it is possible to avoid the current of the inductor from being a negative current for a period of time, so that the inductor does not draw charge from the load capacitor of the Buck-Boost during this period. Furthermore, it is possible to avoid the waste of this part of the charge. Thus, power consumption can be saved and efficiency can be improved.

[0003] However, when the low-side power transistor is turned off, since the current of the inductor cannot change suddenly, the current of the inductor resonates with the parasitic capacitance of the switching node. As a result, a ringing phenomenon appears at the switching node, causing energy loss of the Buck-Boost. Therefore, in the related art, a ringing elimination circuit is used to eliminate the resonance. Among them, the switching node is arranged between the high-side power transistor and the low-side power transistor.

[0004] In the related art, when the current of the inductor is lower than 0 and the low-side power transistor is turned off, since the current of the inductor will charge up the voltage of the switching node. Therefore, when the voltage of the switching node rises, the ringing elimination circuit will be turned on, so that the potential of the switching node is directly connected to the ground potential. Thus, the ringing elimination circuit can eliminate the ringing phenomenon and reduce power consumption. However, the ringing elimination circuit in the related art has the problem of large power consumption, which affects the efficiency of the Buck-Boost. Summary of the Invention

[0005] This application provides a ringing suppression circuit, a buck-boost converter, a chip, and an electronic device, which can reduce the power consumption of the ringing suppression circuit and avoid affecting the efficiency of the Buck-Boost.

[0006] In a first aspect, this application provides a ringing suppression circuit, which is applied to a buck-boost converter. The buck-boost converter includes: a switching node; the ringing suppression circuit includes: a detection circuit and a power transistor;

[0007] The enable terminal of the detection circuit is used to access a zero-crossing detection signal, and the zero-crossing detection signal is used to enable the detection circuit. The first input terminal of the detection circuit and the first terminal of the power transistor are both electrically connected to the switching node. The second input terminal of the detection circuit and the second terminal of the power transistor are both electrically connected to the ground potential. The first output terminal of the detection circuit is electrically connected to the control terminal of the power transistor;

[0008] The detection circuit is configured to obtain a first signal based on the voltage of the switching node and the zero voltage after being enabled, and transmit the first signal to the power transistor. The first signal is used to control the power transistor to turn on or off. The zero voltage is the voltage of the ground potential;

[0009] The power transistor is configured to control the connection between the switching node and the ground potential according to the first signal when the voltage of the switching node rises from the output voltage of the buck-boost converter to the zero voltage, so as to eliminate the ringing phenomenon of the switching node.

[0010] Through the ringing suppression circuit provided by the first aspect, after being enabled, the detection circuit can obtain a first signal for controlling the power transistor to turn on or off based on the voltage of the switching node and the zero voltage, and transmit the first signal to the power transistor, so that the power transistor can obtain the first signal, where the zero voltage is the voltage of the ground potential. In this way, when the voltage of the switching node rises from the output voltage of the buck-boost converter to the zero voltage, the power transistor can be turned on according to the first signal, so that the power transistor can control the connection between the switching node and the ground potential to eliminate the ringing phenomenon of the switching node. Since the voltage of the switching node is the zero voltage when the power transistor is turned on, the voltage across the power transistor is very small. Therefore, the power consumption of the power transistor can be reduced, the power consumption of the ringing suppression circuit can be reduced, and the influence on the efficiency of the buck-boost converter can be avoided.

[0011] In a possible design, the ringing suppression circuit further includes: an adaptive zero-crossing detection circuit;

[0012] The first input terminal of the adaptive zero-crossing detection circuit is used to obtain a pulse signal. The pulse width of the pulse signal is used to represent the time required for the inductor current in the buck-boost converter to start decreasing from zero and the voltage of the switching node to rise from the output voltage to the zero voltage. The second input terminal of the adaptive zero-crossing detection circuit is electrically connected to the second output terminal of the detection circuit. The output terminal of the adaptive zero-crossing detection circuit is electrically connected to the enable terminal of the detection circuit;

[0013] The adaptive zero-crossing detection circuit is configured to obtain a second signal from the detection circuit, and adaptively adjust the trigger point of the zero-crossing detection signal according to the level inversion of the second signal within or after the pulse width of the pulse signal, so as to obtain an adjusted zero-crossing detection signal until the trigger point of the adjusted zero-crossing detection signal is at the falling edge of the pulse signal. The second signal is used to indicate whether the voltage of the switching node reaches the zero voltage. The trigger point refers to the moment when the zero-crossing detection signal or the adjusted zero-crossing detection signal flips from a first level to a second level. At the rising edge of the pulse signal, the low-side power transistor in the buck-boost converter is turned off.

[0014] Based on this, the adaptive zero-crossing detection circuit can obtain a second signal from the detection circuit, which is used to indicate whether the voltage of the switching node reaches the zero voltage, and adaptively adjust the trigger point of the zero-crossing detection signal according to the level inversion of the second signal within or after the pulse width of the pulse signal, so as to obtain an adjusted zero-crossing detection signal until the trigger point of the adjusted zero-crossing detection signal is at the falling edge of the pulse signal. Since the trigger point is at the falling edge of the pulse signal, and the pulse width of the pulse signal is used to indicate the time required for the inductor current in the buck-boost converter to decrease from zero and the voltage of the switching node to rise from the output voltage to the zero voltage. At the same time, at the rising edge of the pulse signal, the low-side power transistor in the buck-boost converter is turned off. Therefore, it can be ensured that the inductor current is exactly 0 when the low-side power transistor is turned off, and the voltage of the switching node is exactly the zero voltage when the power transistor is turned on. Thus, the comparison delay and the drive delay can be compensated. Wherein, the trigger point refers to the moment when the zero-crossing detection signal or the adjusted zero-crossing detection signal flips from a first level to a second level.

[0015] In a possible design, the adaptive zero-crossing detection circuit includes: a logic circuit, a counter, a voltage output circuit, and a zero-crossing comparator;

[0016] The first input terminal of the logic circuit is used to receive the pulse signal. The second input terminal of the logic circuit is electrically connected to the second output terminal of the detection circuit. The third input terminal of the logic circuit is used to receive a third signal, and the third signal is used to raise the potential of the counting input terminal of the counter. The output terminal of the logic circuit is electrically connected to the counting input terminal of the counter. The clock input terminal of the counter is used to receive a fourth signal, and the fourth signal is used to drive the high-side power transistor in the buck-boost converter to turn on or off. The output terminal of the counter is electrically connected to the first input terminal of the voltage output circuit. The second input terminal of the voltage output circuit is used to receive a first voltage, and the first voltage is used to represent the magnitude of the inductor current. The output terminal of the voltage output circuit is electrically connected to the positive-phase input terminal of the zero-crossing comparator. The negative-phase input terminal of the zero-crossing comparator is electrically connected to the ground potential. The output terminal of the zero-crossing comparator is electrically connected to the enable terminal of the detection circuit;

[0017] The logic circuit is configured to generate a first counting signal when the level of the second signal flips within the pulse width, and transmit the first counting signal to the counter;

[0018] The counter is configured to, at the rising edge of the fourth signal, perform a down-counting on the first value of the counter according to the first counting signal to obtain a first adjustment signal, and transmit the first adjustment signal to the voltage output circuit;

[0019] The voltage output circuit is configured to generate a first offset voltage corresponding to the first adjustment signal, and obtain a second voltage according to the first offset voltage and the first voltage, and transmit the second voltage to the zero-crossing comparator;

[0020] The zero-crossing comparator is configured to compare the magnitude relationship between the second voltage and the zero voltage to obtain the adjusted zero-crossing detection signal, and the trigger point of the adjusted zero-crossing detection signal is earlier than the trigger point of the zero-crossing detection signal;

[0021] Or,

[0022] The logic circuit is configured to generate a second counting signal when the level of the second signal flips after the pulse width, and transmit the second counting signal to the counter;

[0023] The counter is configured to, at the rising edge of the fourth signal, perform an up-counting on the first value of the counter according to the second counting signal to obtain a second adjustment signal, and transmit the second adjustment signal to the voltage output circuit;

[0024] The voltage output circuit is used to generate a second offset voltage corresponding to the second adjustment signal, obtain the third voltage based on the second offset voltage and the first voltage, and transmit the third voltage to the zero-crossing comparator;

[0025] The zero-crossing comparator is used to compare the magnitude relationship between the third voltage and the zero voltage to obtain the adjusted zero-crossing detection signal, and the trigger point of the adjusted zero-crossing detection signal is later than the trigger point of the zero-crossing detection signal.

[0026] Based on this, when the level of the second signal flips within the pulse width, the logic circuit can generate a first count signal and transmit the first count signal to the counter, enabling the counter to obtain the first count signal. In this way, at the rising edge of the fourth signal, the counter can perform a down-count on the first value of the counter according to the first count signal to obtain a first adjustment signal, and transmit the first adjustment signal to the voltage output circuit, enabling the voltage output circuit to obtain the first adjustment signal. Thus, the voltage output circuit can generate a first offset voltage corresponding to the first adjustment signal, obtain a second voltage based on the first offset voltage and the first voltage, and transmit the second voltage to the zero-crossing comparator, enabling the zero-crossing comparator to obtain the second voltage. Furthermore, the zero-crossing comparator can compare the magnitude relationship between the second voltage and the zero voltage to obtain an adjusted zero-crossing detection signal whose trigger point is earlier than the trigger point of the zero-crossing detection signal. Or, when the level of the second signal flips after the pulse width, the logic circuit can generate a second count signal and transmit the second count signal to the counter, enabling the counter to obtain the second count signal. In this way, at the rising edge of the fourth signal, the counter can perform an up-count on the first value of the counter according to the second count signal to obtain a second adjustment signal, and transmit the second adjustment signal to the voltage output circuit, enabling the voltage output circuit to obtain the second adjustment signal. Thus, the voltage output circuit can generate a second offset voltage corresponding to the second adjustment signal, obtain a third voltage based on the second offset voltage and the first voltage, and transmit the third voltage to the zero-crossing comparator, enabling the zero-crossing comparator to obtain the third voltage. Furthermore, the zero-crossing comparator can compare the magnitude relationship between the third voltage and the zero voltage to obtain an adjusted zero-crossing detection signal whose trigger point is later than the trigger point of the zero-crossing detection signal. Therefore, the adaptive zero-crossing detection circuit can adaptively adjust the trigger point of the zero-crossing detection signal according to whether the level of the second signal flips within or after the pulse width of the pulse signal to obtain the adjusted zero-crossing detection signal until the trigger point of the adjusted zero-crossing detection signal is at the falling edge of the pulse signal.

[0027] In a possible design, the voltage output circuit includes: an offset voltage output circuit and an adder;

[0028] The input end of the offset voltage output circuit is electrically connected to the output end of the counter, the output end of the offset voltage output circuit is electrically connected to the first input end of the adder, the second input end of the adder is used for accessing the first voltage, and the output end of the adder is electrically connected to the positive-phase input end of the zero-crossing comparator;

[0029] The offset voltage output circuit is used to generate the first offset voltage corresponding to the first adjustment signal and transmit the first offset voltage to the adder;

[0030] The adder is used to perform an addition operation on the first offset voltage and the first voltage to obtain the second voltage;

[0031] Or,

[0032] The offset voltage output circuit is used to generate the second offset voltage corresponding to the second adjustment signal and transmit the second offset voltage to the adder;

[0033] The adder is used to perform an addition operation on the second offset voltage and the first voltage to obtain the third voltage.

[0034] Based on this, the offset voltage output circuit can generate the first offset voltage corresponding to the first adjustment signal and transmit the first offset voltage to the adder, so that the adder can obtain the first offset voltage. In this way, the adder can perform an addition operation on the first offset voltage and the first voltage to obtain the second voltage. Or, the offset voltage output circuit can generate the second offset voltage corresponding to the second adjustment signal and transmit the second offset voltage to the adder, so that the adder can obtain the second offset voltage. In this way, the adder can perform an addition operation on the second offset voltage and the first voltage to obtain the third voltage. Thus, the voltage output circuit can obtain the second voltage and the third voltage.

[0035] In a possible design, the ringing suppression circuit further includes: a pulse signal generation circuit;

[0036] The first input end of the pulse signal generation circuit is used for accessing a fifth signal, the fifth signal is used to drive the low-side power transistor in the buck-boost converter to turn on or off, the second input end of the pulse signal generation circuit is electrically connected to the output end of the adaptive zero-crossing detection circuit, and the output end of the pulse signal generation circuit is electrically connected to the first input end of the adaptive zero-crossing detection circuit;

[0037] The pulse signal generation circuit is used to generate the pulse signal according to the fifth signal and the zero-crossing detection signal, and the rising edge of the pulse signal is the same as the rising edge of the fifth signal.

[0038] Based on this, the pulse signal generation circuit can generate a pulse signal with a rising edge identical to that of the fifth signal according to the fifth signal and the zero-crossing detection signal. Thus, the adaptive zero-crossing detection circuit can be connected to the pulse signal.

[0039] In a possible design, the pulse signal generation circuit includes: a delay element, a first inverter, a first NOR gate device, and a first AND gate device;

[0040] The input terminal of the delay element and the input terminal of the first inverter are both used to connect to the fifth signal. The output terminal of the delay element is electrically connected to the first input terminal of the first NOR gate device. The output terminal of the first inverter is electrically connected to the second input terminal of the first NOR gate device. The output terminal of the first NOR gate device is electrically connected to the first input terminal of the first AND gate device. The second input terminal of the first AND gate device is electrically connected to the output terminal of the adaptive zero-crossing detection circuit. The output terminal of the first AND gate device is electrically connected to the first input terminal of the adaptive zero-crossing detection circuit.

[0041] In a possible design, the detection circuit includes: a detection comparator and a first latch;

[0042] The enable terminal of the detection comparator is used to connect to the zero-crossing detection signal. The positive input terminal of the detection comparator is connected to the switch node. The negative input terminal of the detection comparator is connected to the ground potential. The output terminal of the detection comparator is respectively connected to the data input terminal of the first latch and the second input terminal of the adaptive zero-crossing detection circuit. The enable terminal of the first latch is used to connect to the fourth signal. The output terminal of the first latch is connected to the control terminal of the power transistor;

[0043] The detection comparator is configured to, after being enabled, compare the voltage of the switch node with the zero voltage to obtain a second signal, and transmit the second signal to the first latch;

[0044] The first latch is configured to generate the first signal according to the second signal and the fourth signal.

[0045] Based on this, the detection comparator can compare the voltage of the switch node with the zero voltage to obtain a second signal, and transmit the second signal to the first latch, enabling the first latch to acquire the second signal. In this way, the first latch can generate the first signal according to the second signal and the fourth signal. Thus, after being enabled, the detection circuit can obtain the first signal according to the voltage of the switch node and the zero voltage.

[0046] In a possible design, the detection comparator includes: a detection signal output circuit, a bias circuit, a comparison circuit, and a shaping circuit;

[0047] The first input terminal of the detection signal output circuit is used to access the zero-crossing detection signal, the second input terminal of the detection signal output circuit is used to access the fifth signal, the third input terminal of the detection signal output circuit is electrically connected to the data input terminal of the first latch and the output terminal of the shaping circuit, the output terminal of the detection signal output circuit is electrically connected to the first terminal of the comparison circuit, the second terminal of the comparison circuit is used to access the sixth signal, the sixth signal is used to enable the comparison circuit, the third terminal of the comparison circuit is electrically connected to the output terminal of the bias circuit, the fourth terminal of the comparison circuit is electrically connected to the switch node, the input terminal of the bias circuit is used to access the output voltage of the buck-boost converter, the ground terminal of the bias circuit is electrically connected to the ground potential, and the fifth terminal of the comparison circuit is electrically connected to the input terminal of the shaping circuit;

[0048] The detection signal output circuit is configured to generate a detection signal according to the zero-crossing detection signal, the second signal and the fifth signal, and transmit the detection signal to the comparison circuit, and the detection signal is used to indicate whether the zero-crossing detection signal enables the detection circuit;

[0049] The bias circuit is configured to generate a bias voltage according to the zero voltage and the output voltage of the buck-boost converter, and transmit the bias voltage to the comparison circuit;

[0050] After being enabled, the comparison circuit is configured to control the pull-down current of the first P-type transistor in the comparison circuit according to the bias voltage and the voltage of the switch node, and provide a first pull-up current to the first P-type transistor after the detection signal indicates that the zero-crossing detection signal enables the detection circuit, and compare the magnitude relationship between the pull-down current and the first pull-up current to obtain a seventh signal; wherein, the width-to-length ratio of the first P-type transistor is greater than a preset width-to-length ratio;

[0051] The shaping circuit is configured to obtain the seventh signal from the comparison circuit and shape the seventh signal to obtain the second signal.

[0052] In a possible design, the detection comparator further includes: a sixth signal output circuit;

[0053] The first input terminal of the sixth signal output circuit is used to access an eighth signal, the level of the eighth signal is opposite to the level of the fifth signal, the second input terminal of the sixth signal output circuit is used to access the fourth signal, the third input terminal of the sixth signal output circuit is used to access the zero-crossing detection signal, the fourth input terminal of the sixth signal output circuit is electrically connected to the output terminal of the shaping circuit, and the output terminal of the sixth signal output circuit is electrically connected to the second terminal of the comparison circuit;

[0054] The sixth signal output circuit is configured to generate the sixth signal according to the eighth signal, the fourth signal, the zero-crossing detection signal, and the second signal.

[0055] In a possible design, the sixth signal output circuit includes: a second inverter, a first NAND gate device, a second NAND gate device, and a second latch;

[0056] The first input terminal of the first NAND gate device is configured to receive the zero-crossing detection signal, the second input terminal of the first NAND gate device is electrically connected to the output terminal of the shaping circuit, the output terminal of the first NAND gate device is electrically connected to the first input terminal of the second NAND gate device, the input terminal of the second inverter is configured to receive the fourth signal, the output terminal of the second inverter is electrically connected to the second input terminal of the second NAND gate device, the output terminal of the second NAND gate device is electrically connected to the enable terminal of the second latch, the data input terminal of the second latch is configured to receive the eighth signal, and the output terminal of the second latch is electrically connected to the second terminal of the comparison circuit.

[0057] In a possible design, the comparison circuit includes: a first resistor, a second resistor, a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor; wherein, the resistance value of the first resistor is less than a first preset resistance value, the resistance value of the second resistor is greater than a second preset resistance value, and the difference between the second preset resistance value and the first preset resistance value is greater than a third preset resistance value;

[0058] The first terminal of the first resistor and the second terminal of the second resistor are both configured to receive a power supply voltage. The second terminal of the first resistor is electrically connected to the source electrode of the second P-type transistor. The gate electrode of the second P-type transistor is electrically connected to the output terminal of the detection signal output circuit. The drain electrode of the second P-type transistor, the second terminal of the second resistor, and the input terminal of the shaping circuit are all electrically connected to the drain electrode of the first N-type transistor. The gate electrode of the first N-type transistor is configured to receive the sixth signal. The source electrode of the first N-type transistor is electrically connected to the source electrode of the first P-type transistor. The gate electrode of the first P-type transistor is electrically connected to the output terminal of the bias circuit. The drain electrode of the first P-type transistor is electrically connected to the drain electrode and the gate electrode of the second N-type transistor respectively. The source electrode of the second N-type transistor is electrically connected to the switch node.

[0059] In a possible design, the detection signal output circuit includes: a third inverter and an OR gate device;

[0060] The input terminal of the third inverter is used to receive the zero-crossing detection signal. The output terminal of the third inverter is electrically connected to the first input terminal of the OR gate device. The second input terminal of the OR gate device is electrically connected to the output terminal of the shaping circuit. The third input terminal of the OR gate device is used to receive the fifth signal. The output terminal of the OR gate device is electrically connected to the first terminal of the comparison circuit.

[0061] In a possible design, the bias circuit includes: a third P-type transistor and a third resistor;

[0062] The source electrode of the third P-type transistor is electrically connected to the ground potential. The gate electrode of the third P-type transistor, the drain electrode of the third P-type transistor, and the first terminal of the third resistor are all electrically connected to the third terminal of the comparison circuit. The second terminal of the third resistor is used to receive the output voltage of the buck-boost converter.

[0063] In a possible design, the shaping circuit includes: a fourth P-type transistor, a third N-type transistor, and a fourth inverter; wherein, the threshold voltage of the third N-type transistor is equal to the gate-source voltage of the second N-type transistor;

[0064] The source electrode of the fourth P-type transistor is used to receive the power supply voltage. The gate electrode of the fourth P-type transistor and the gate electrode of the third N-type transistor are both electrically connected to the drain electrode of the first N-type transistor. The drain electrode of the fourth P-type transistor is electrically connected to the drain electrode of the third N-type transistor. The source electrode of the third N-type transistor is electrically connected to the ground potential. The input terminal of the fourth inverter is electrically connected between the drain electrode of the fourth P-type transistor and the drain electrode of the third N-type transistor. The output terminal of the fourth inverter is electrically connected to the third input terminal of the detection signal output circuit.

[0065] In a second aspect, the present application provides a buck-boost converter, which includes: a high-side power transistor, a low-side power transistor, a freewheeling inductor, a load capacitor, and a ringing suppression circuit in the first aspect and each possible design of the first aspect above;

[0066] The drain of the high-side power transistor is used to connect to the input voltage of the buck-boost converter. The source of the high-side power transistor is electrically connected to the drain of the low-side power transistor. The gate of the high-side power transistor is used to connect to a fourth signal, and the gate of the low-side power transistor is used to connect to a fifth signal. A switching node is located between the source of the low-side power transistor and the drain of the high-side power transistor. The first end of the flyback inductor and the first end of the ringing suppression circuit are both electrically connected to the switching node. The second end of the flyback inductor, the second end of the ringing suppression circuit, and the upper plate of the load capacitor are all electrically connected to the ground potential. The source of the low-side power transistor is electrically connected to the lower plate of the load capacitor, and the source of the low-side power transistor is also used to output the output voltage of the buck-boost converter;

[0067] The ringing suppression circuit is configured to control the connection between the switching node and the ground potential when the voltage of the switching node rises from the output voltage to the zero voltage, so as to prevent the switching node from ringing.

[0068] For the buck-boost converter provided in the second aspect and each possible design of the second aspect, the beneficial effects can be referred to the beneficial effects brought by the first aspect and each possible implementation manner of the first aspect, which will not be elaborated here.

[0069] In a third aspect, the present application provides a chip, which includes: the ringing suppression circuit in the first aspect and each possible design of the first aspect, and / or, the buck-boost converter in the second aspect and each possible design of the second aspect.

[0070] In a fourth aspect, the present application provides an electronic device, which includes the chip in the third aspect.

[0071] The above description is only an overview of the technical solutions of the embodiments of the present application. In order to understand the technical means of the embodiments of the present application more clearly, it can be implemented according to the content of the description. And in order to make the above and other purposes, features, and advantages of the embodiments of the present application more obvious and understandable, the following specifically describes the embodiments of the present application. Description of the Drawings

[0072] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0073] Figure 1Schematic diagram of a ringing suppression circuit provided by an embodiment of the present application;

[0074] Figure 2 Schematic diagram of a working waveform of a ringing suppression circuit provided by an embodiment of the present application;

[0075] Figure 3 Schematic diagram of another working waveform of a ringing suppression circuit provided by an embodiment of the present application;

[0076] Figure 4 Schematic diagram of yet another working waveform of a ringing suppression circuit provided by an embodiment of the present application;

[0077] Figure 5 Schematic diagram of the detection comparator in a ringing suppression circuit provided by an embodiment of the present application;

[0078] Figure 6 Schematic diagram of a buck-boost converter provided by an embodiment of the present application. Detailed implementation manners

[0079] In the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a alone, b alone, or c alone can represent: a alone, b alone, c alone, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0080] The orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "upper", "lower", "left", "right", "front", "rear", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0081] The terms "connected" and "coupled" should be understood in a broad sense. For example, the "connection" or "coupling" of a circuit structure can refer not only to a physical connection but also to an electrical connection or a signal connection. For instance, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is electrically connected. It can also be the internal connection of two components. A signal connection can be made not only through a circuit but also through a media medium, such as radio waves. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0082] In the related art, typically when it is detected that the voltage of the switching node starts to rise from zero voltage, the ringing cancellation circuit is turned on to pull down the potential of the switching node to the ground potential. However, since the output voltage of the Buck - Boost is a negative voltage, and at the moment when the zero - crossing signal is just triggered, the voltage of the switching node is approximately equal to the output voltage. Therefore, when the voltage of the switching node is approximately equal to the output voltage and the ringing cancellation circuit is turned on, it will cause a relatively large voltage across the metal - oxide - semiconductor field - effect transistor (MOSFET) used to connect the switching node and the ground potential in the ringing cancellation circuit.

[0083] At the same time, due to the relatively large parasitic capacitance of the switching node and in order to quickly pull down the potential of the switching node to the ground potential, generally, the size of the metal - oxide - semiconductor field - effect transistor (MOSFET) is relatively large.

[0084] Since the voltage across the metal - oxide - semiconductor field - effect transistor (MOSFET) is relatively large and the size of the metal - oxide - semiconductor field - effect transistor (MOSFET) is relatively large, a relatively large power consumption will be generated on the metal - oxide - semiconductor field - effect transistor (MOSFET), which affects the efficiency of the Buck - Boost.

[0085] In addition, when detecting whether the inductor current drops to 0, since there is a comparison delay in the process of comparing the inductor current and there is also a drive delay from the triggering of the zero - crossing signal to the turn - off of the low - side power transistor. As a result, when the low - side power transistor is turned off, the inductor current has already dropped below 0. At the same time, it is very difficult to compensate for the comparison delay and the drive delay through a fixed delay in different application scenarios, process corners, and different temperatures.

[0086] In addition, the potential of the switching node and the ground potential are usually compared by a comparator to detect whether the voltage of the switching node starts to rise from zero voltage. The conventional comparator is a positive voltage domain comparator, which can only compare negative voltages with relatively low absolute values. For a Buck-Boost with a negative output voltage, after the low-side power transistor is turned off, the potential of the switching node gradually rises from the output voltage to a positive voltage. Since the absolute value of the output voltage is relatively high, a conventional positive voltage domain comparator cannot be used. At the same time, in the related art, a capacitor is used to lift the negative voltage to the positive voltage domain for comparison. However, during the comparison, the voltage of the switching node will rise from a negative voltage to a positive voltage. If the method of lifting the voltage by the capacitor in the related art is still used, the voltage of the switching node will rise to a positive voltage and then be lifted by the capacitor, resulting in exceeding the withstand voltage range of the internal devices of the positive voltage domain comparator. Therefore, a logical error will occur in the detection of the zero-crossing signal.

[0087] To solve the above problems, the present application provides a ringing suppression circuit, a buck-boost converter, a chip, and an electronic device.

[0088] Referring to Figure 1 , Figure 1 is a schematic structural diagram of a ringing suppression circuit provided by an embodiment of the present application. As Figure 1 shown, the ringing suppression circuit 100 may include: a detection circuit 110 and a power transistor 120.

[0089] The enable terminal of the detection circuit 110 is used to access a zero-crossing detection signal ZCD, and the zero-crossing detection signal ZCD is used to enable the detection circuit 110. The first input terminal of the detection circuit 110 and the first terminal of the power transistor 120 are both electrically connected to the switching node SW. The second input terminal of the detection circuit 110 and the second terminal of the power transistor 120 are both electrically connected to the ground potential. The first output terminal of the detection circuit 110 is electrically connected to the control terminal of the power transistor 120.

[0090] Among them, the detection circuit 110 and the power transistor 120 may be separately provided or integrally provided. The embodiments of the present application do not make specific limitations on this.

[0091] In some examples, the power transistor 120 is a metal-oxide-semiconductor field-effect transistor NMOSFET. The first terminal of the power transistor 120 is the drain of the metal-oxide-semiconductor field-effect transistor NMOSFET, the second terminal of the power transistor 120 is the source of the metal-oxide-semiconductor field-effect transistor NMOSFET, and the control terminal of the power transistor 120 is the gate of the metal-oxide-semiconductor field-effect transistor NMOSFET.

[0092] Among them, the zero-crossing detection signal ZCD is also used to control the turn-off of the low-side power transistor LS in the buck-boost converter 1000. After the buck-boost converter 1000 receives the zero-crossing detection signal ZCD, the buck-boost converter 1000 controls the low-side power transistor LS to turn off.

[0093] Among them, the voltage of the switch node SW can characterize the state of the inductor current IL.

[0094] After being enabled, the detection circuit 110 can obtain the first signal EN_RK according to the voltage of the switch node SW and the zero voltage. And the detection circuit 110 can transmit the first signal EN_RK to the power transistor 120, so that the power transistor 120 can obtain the first signal EN_RK.

[0095] Among them, the first signal EN_RK is used to control the turn-on or turn-off of the power transistor 120, and the zero voltage is the voltage of the ground potential. Exemplarily, when the first signal EN_RK is at a high level, the power transistor 120 turns on. When the first signal EN_RK is at a low level, the power transistor 120 turns off.

[0096] In this way, when the voltage of the switch node SW rises from the output voltage VOUT of the buck-boost converter 1000 to the zero voltage, the power transistor 120 can turn on according to the first signal EN_RK, so that the power transistor 120 can control the connection between the switch node SW and the ground potential to eliminate the ringing phenomenon of the switch node SW. Since when the power transistor 120 turns on, the voltage of the switch node SW is the zero voltage, the voltage across the power transistor 120 is very small. Thus, the power consumption of the power transistor 120 can be reduced, the power consumption of the ringing suppression circuit 100 can be reduced, and the influence on the efficiency of the buck-boost converter 1000 can be avoided.

[0097] The ringing suppression circuit, buck-boost converter, chip and electronic device provided by the embodiments of the present application, after being enabled, the detection circuit can obtain the first signal for controlling the turn-on or turn-off of the power transistor according to the voltage of the switch node and the zero voltage, and transmit the first signal to the power transistor, so that the power transistor can obtain the first signal, where the zero voltage is the voltage of the ground potential. In this way, when the voltage of the switch node rises from the output voltage of the buck-boost converter to the zero voltage, the power transistor can turn on according to the first signal, so that the power transistor can control the connection between the switch node and the ground potential to eliminate the ringing phenomenon of the switch node. Since when the power transistor turns on, the voltage of the switch node is the zero voltage, the voltage across the power transistor is very small. Thus, the power consumption of the power transistor can be reduced, the power consumption of the ringing suppression circuit can be reduced, and the influence on the efficiency of the buck-boost converter can be avoided.

[0098] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the ringing suppression circuit 100. As Figure 1As shown, the ringing suppression circuit 100 may further include: an adaptive zero-crossing detection circuit 130.

[0099] The first input terminal of the adaptive zero-crossing detection circuit 130 is used to obtain a pulse signal EN_CAL. The pulse width dly of the pulse signal EN_CAL is used to represent the time required for the inductor current IL in the buck-boost converter 1000 to decrease from zero and the voltage of the switch node SW to increase from the output voltage VOUT to zero voltage. The second input terminal of the adaptive zero-crossing detection circuit 130 is electrically connected to the second output terminal of the detection circuit 110, and the output terminal of the adaptive zero-crossing detection circuit 130 is electrically connected to the enable terminal of the detection circuit 110.

[0100] Wherein, the third input terminal of the adaptive zero-crossing detection circuit 130 is used to connect to a third signal HSON_dly. After the adaptive zero-crossing detection circuit 130 receives the third signal HSON_dly, the adaptive zero-crossing detection circuit 130 resets to adjust the trigger point of the zero-crossing detection signal ZCD again.

[0101] The adaptive zero-crossing detection circuit 130 can obtain a second signal ZMP from the detection circuit 110. And the adaptive zero-crossing detection circuit 130 can adaptively adjust the trigger point of the zero-crossing detection signal ZCD according to the level of the second signal ZMP flipping within or after the pulse width dly of the pulse signal EN_CAL to obtain an adjusted zero-crossing detection signal ZCD until the trigger point of the adjusted zero-crossing detection signal ZCD is at the falling edge of the pulse signal EN_CAL.

[0102] Wherein, the zero-crossing detection signal ZCD is within the current cycle. The adjusted zero-crossing detection signal ZCD is within the next cycle.

[0103] Exemplarily, the level of the second signal ZMP flipping means that the second signal ZMP flips from a low level to a high level.

[0104] Wherein, when the level of the second signal ZMP flips within the pulse width of the pulse signal EN_CAL, it means that the zero-crossing detection signal ZCD flips too late. When the level of the second signal ZMP flips after the pulse width, it means that the zero-crossing detection signal ZCD flips too early.

[0105] Wherein, the second signal ZMP is used to represent whether the voltage of the switch node SW reaches zero voltage. Exemplarily, when the second signal ZMP is at a high level, the voltage of the switch node SW reaches zero voltage. When the second signal ZMP is at a low level, the voltage of the switch node SW does not reach zero voltage.

[0106] Among them, the trigger point refers to the moment when the zero-crossing detection signal ZCD flips from the first level to the second level. Alternatively, the trigger point refers to the moment when the adjusted zero-crossing detection signal ZCD flips from the first level to the second level. At the rising edge of the pulse signal EN_CAL, the low-side power transistor LS in the buck-boost converter 1000 is turned off. Exemplarily, when the first level is high, the second level is low. When the first level is low, the second level is high. In the embodiments of the present application, the case where the first level is low and the second level is high is taken as an example for illustration.

[0107] Since the trigger point is at the falling edge of the pulse signal EN_CAL, and the pulse width of the pulse signal EN_CAL is used to characterize the time required for the inductor current IL in the buck-boost converter 1000 to start decreasing from zero and the voltage of the switching node SW to rise from the output voltage VOUT to zero voltage. At the same time, at the rising edge of the pulse signal EN_CAL, the low-side power transistor LS is turned off. Therefore, it can be ensured that the inductor current IL is exactly 0 when the low-side power transistor LS is turned off, and when the power transistor 120 is turned on, the voltage of the switching node SW is exactly zero voltage. Thus, the comparison delay and drive delay can be compensated.

[0108] In summary, the adaptive zero-crossing detection circuit can obtain a second signal from the detection circuit for characterizing whether the voltage of the switching node reaches zero voltage, and adaptively adjust the trigger point of the zero-crossing detection signal according to the level flip of the second signal within or after the pulse width of the pulse signal, so as to obtain an adjusted zero-crossing detection signal until the trigger point of the adjusted zero-crossing detection signal is at the falling edge of the pulse signal. Since the trigger point is at the falling edge of the pulse signal, and the pulse width of the pulse signal is used to characterize the time required for the inductor current in the buck-boost converter to start decreasing from zero and the voltage of the switching node to rise from the output voltage to zero voltage. At the same time, at the rising edge of the pulse signal, the low-side power transistor in the buck-boost converter is turned off. Therefore, it can be ensured that the inductor current is exactly 0 when the low-side power transistor is turned off, and when the power transistor is turned on, the voltage of the switching node is exactly zero voltage. Thus, the comparison delay and drive delay can be compensated. Among them, the trigger point refers to the moment when the zero-crossing detection signal or the adjusted zero-crossing detection signal flips from the first level to the second level.

[0109] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the adaptive zero-crossing detection circuit 130. As Figure 1 shown, the adaptive zero-crossing detection circuit 130 may include: a logic circuit 131, a counter 132, a voltage output circuit 133, and a zero-crossing comparator CMP2.

[0110] The first input terminal of the logic circuit 131 is used to receive the pulse signal EN_CAL. The second input terminal of the logic circuit 131 is electrically connected to the second output terminal of the detection circuit 110. The third input terminal of the logic circuit 131 is used to receive the third signal HSON_dly, and the third signal HSON_dly is used to raise the potential of the counting input terminal of the counter 132. The output terminal of the logic circuit 131 is electrically connected to the counting input terminal of the counter 132. The clock input terminal of the counter 132 is used to receive the fourth signal HSON, and the fourth signal HSON is used to drive the high-side power transistor HS in the buck-boost converter 1000 to turn on or off. The output terminal of the counter 132 is electrically connected to the first input terminal of the voltage output circuit 133. The second input terminal of the voltage output circuit 133 is used to receive the first voltage VL, and the first voltage VL is used to represent the magnitude of the inductor current IL. The output terminal of the voltage output circuit 133 is electrically connected to the positive-phase input terminal of the zero-crossing comparator CMP2. The negative-phase input terminal of the zero-crossing comparator CMP2 is electrically connected to the ground potential. The output terminal of the zero-crossing comparator CMP2 is electrically connected to the enable terminal of the detection circuit 110.

[0111] Among them, the first input terminal of the logic circuit 131 is the first input terminal of the adaptive zero-crossing detection circuit 130, the second input terminal of the logic circuit 131 is the second input terminal of the adaptive zero-crossing detection circuit 130, the third input terminal of the logic circuit 131 is the third input terminal of the adaptive zero-crossing detection circuit 130, and the output terminal of the zero-crossing comparator CMP2 is the output terminal of the adaptive zero-crossing detection circuit 130.

[0112] Among them, the first voltage VL is proportional to the inductor current IL.

[0113] Exemplarily, when the fourth signal HSON is at a high level, the high-side power transistor HS turns on. When the fourth signal HSON is at a low level, the high-side power transistor HS turns off.

[0114] Among them, the third signal HSON_dly is obtained by delaying the fourth signal HSON. After the logic circuit 131 receives the third signal HSON_dly, the logic circuit 131 transmits a set signal to the counter 132 to reset the potential of the counting input terminal of the counter 132 to a high level, so that the adaptive zero-crossing detection circuit 130 can adjust the trigger point of the zero-crossing detection signal ZCD again.

[0115] Among them, for example, if the counter 132 is a four - digit counter, then both the first adjustment signal and the second adjustment signal are adjustment signals Q<4:0>. Exemplarily, in the second period, the first value is the value output by the counter 132 in the first period, that is to say, the first value is the value corresponding to the adjustment signal Q<4:0> in the first period. For example, in the fourth period, the first value is the value output by the counter 132 in the third period, that is to say, the first value is the value corresponding to the adjustment signal Q<4:0> in the third period.

[0116] Among them, both the first offset voltage and the second offset voltage are offset voltage Vos. The step size of each bit of the adjustment signal corresponding to the offset voltage Vos is negatively correlated with the adjustment accuracy of the adaptive zero - crossing detection circuit 130. If the step size of each bit of the adjustment signal is larger, the adjustment accuracy of the adaptive zero - crossing detection circuit 130 is lower. If the step size of each bit of the adjustment signal is smaller, the adjustment accuracy of the adaptive zero - crossing detection circuit 130 is higher.

[0117] The following combines Figures 2 - 4 , and details the working principle of the adaptive zero - crossing detection circuit 130 as follows:

[0118] Referring to Figure 2 , Figure 2 is a schematic diagram of a working waveform of a ringing suppression circuit provided by an embodiment of the present application. As Figure 2 shown, since in the stage where the inductor current IL is a negative current, the low - side power transistor LS is turned off, making the inductor current IL unable to continue flowing and can only charge the parasitic capacitance of the switching node SW. Therefore, the voltage of the switching node SW will immediately start to rise from zero voltage when the low - side power transistor LS is turned off, that is, at time T1.

[0119] In addition, in the stage where the inductor current IL is from 0A to the low - side power transistor LS is turned off, that is, in the time period T0 - T1, the inductor current IL will increase in the reverse direction, making the inductor current IL charging the parasitic capacitance of the switching node SW larger. Thus, the voltage of the switching node SW rises to zero voltage 0V faster, and the time for the voltage of the switching node SW to rise to zero voltage 0V is shorter. Thus, the level of the second signal ZMP flips within the pulse width dly of the pulse signal EN_CAL, that is, it flips within the pulse width dly of the pulse signal EN_CAL.

[0120] Based on this, the level of the second signal ZMP flips within the pulse width dly of the pulse signal EN_CAL, which means that the zero-crossing detection signal ZCD flips too late. Thus, when the level of the second signal ZMP flips within the pulse width dly, the logic circuit 131 can generate a first count signal. And the logic circuit 131 can transmit the first count signal to the counter 132, enabling the counter 132 to obtain the first count signal.

[0121] In this way, at the rising edge of the fourth signal HSON, the counter 132 can count down the first value of the counter 132 according to the first count signal to obtain a first adjustment signal. And the counter 132 can transmit the first adjustment signal to the voltage output circuit 133, enabling the voltage output circuit 133 to obtain the first adjustment signal.

[0122] Furthermore, the voltage output circuit 133 can generate a first offset voltage corresponding to the first adjustment signal to reduce the first offset voltage. And the voltage output circuit 133 can obtain a second voltage based on the first offset voltage and the first voltage VL, and transmit the second voltage to the zero-crossing comparator CMP2, enabling the zero-crossing comparator CMP2 to obtain the second voltage.

[0123] Accordingly, the zero-crossing comparator CMP2 can compare the magnitude relationship between the second voltage and the zero voltage to obtain an adjusted zero-crossing detection signal ZCD. Since the first offset voltage decreases, when the output voltage of the zero-crossing comparator CMP2 flips, the first voltage VL increases compared to the first offset voltage before the decrease. Therefore, the adjusted zero-crossing detection signal ZCD will flip at a larger inductor current IL, that is to say, the trigger point of the adjusted zero-crossing detection signal ZCD is earlier than the trigger point of the zero-crossing detection signal ZCD.

[0124] Among them, when the second voltage is greater than the zero voltage, the adjusted zero-crossing detection signal ZCD is at a high level. When the second voltage is less than the zero voltage, the adjusted zero-crossing detection signal ZCD is at a low level.

[0125] Refer to Figure 3 , Figure 3 which is a schematic diagram of another working waveform of a ringing suppression circuit provided by an embodiment of the present application. As Figure 3As shown, during the stage when the inductor current IL is still a positive current, that is, in the time period from T0 to T1, even if the low-side power transistor LS is turned off, the inductor current IL can still continue to flow through the parasitic body diode of the low-side power transistor LS. During this stage, the voltage of the switching node SW is the output voltage VOUT minus the turn-on voltage of the parasitic body diode of the low-side power transistor LS. Therefore, after the inductor current IL becomes a negative current, that is, after the moment T1, the voltage of the switching node SW begins to rise, causing the level of the second signal ZMP to flip after the pulse width dly, that is to say, the voltage of the switching node SW reaches zero voltage only after the pulse width dly of the pulse signal EN_CAL.

[0126] Based on this, the level of the second signal ZMP flips after the pulse width dly, which means that the zero-crossing detection signal ZCD flips too early. In this way, when the level of the second signal ZMP flips after the pulse width dly, the logic circuit 131 can generate a second count signal. And the logic circuit 131 can transmit the second count signal to the counter 132, so that the counter 132 can obtain the second count signal.

[0127] In this way, at the rising edge of the fourth signal HSON, the counter 132 can increment the first value of the counter 132 upward according to the second count signal to obtain a second adjustment signal. And the counter 132 can transmit the second adjustment signal to the voltage output circuit 133, so that the voltage output circuit 133 can obtain the second adjustment signal.

[0128] Furthermore, the voltage output circuit 133 can generate a second offset voltage corresponding to the second adjustment signal, increasing the second offset voltage. And the voltage output circuit 133 can obtain a third voltage according to the second offset voltage and the first voltage VL, and transmit the third voltage to the zero-crossing comparator CMP2, so that the zero-crossing comparator CMP2 can obtain the third voltage.

[0129] Thus, the zero-crossing comparator CMP2 can compare the magnitudes of the third voltage and the zero voltage to obtain an adjusted zero-crossing detection signal ZCD. Since the second offset voltage increases, when the output voltage of the zero-crossing comparator CMP2 flips, the first voltage VL decreases compared to the first offset voltage before the increase. Therefore, the adjusted zero-crossing detection signal ZCD will flip at a smaller inductor current IL, that is to say, the trigger point of the adjusted zero-crossing detection signal ZCD is later than the trigger point of the zero-crossing detection signal ZCD.

[0130] Among them, when the third voltage is greater than the zero voltage, the adjusted zero-crossing detection signal ZCD is at a high level. When the third voltage is less than the zero voltage, the adjusted zero-crossing detection signal ZCD is at a low level.

[0131] Based on the above description, after several cycles, the adjustment signal Q<4:0> will switch between two adjacent values on a per-cycle basis. Refer to Figure 4 , Figure 4 which is a schematic diagram of yet another working waveform of a ringing suppression circuit provided in an embodiment of the present application. As Figure 4 shown, at time T0, the moment when the level of the second signal ZMP flips happens exactly at the falling edge of the pulse signal EN_CAL. Thus, it can be ensured that the inductor current IL is exactly 0 when the low-side power transistor LS turns off, and at the moment when the power transistor 120 turns on, i.e., at time T1, the voltage of the switching node SW is exactly the zero voltage 0V.

[0132] In summary, when the level of the second signal flips within the pulse width, the logic circuit can generate a first count signal and transmit the first count signal to the counter, enabling the counter to obtain the first count signal. In this way, at the rising edge of the fourth signal, the counter can perform a down-count on the first value of the counter according to the first count signal to obtain a first adjustment signal, and transmit the first adjustment signal to the voltage output circuit, enabling the voltage output circuit to obtain the first adjustment signal. Thus, the voltage output circuit can generate a first offset voltage corresponding to the first adjustment signal, and based on the first offset voltage and the first voltage, obtain a second voltage, and transmit the second voltage to the zero-crossing comparator, enabling the zero-crossing comparator to obtain the second voltage. Furthermore, the zero-crossing comparator can compare the magnitude relationship between the second voltage and the zero voltage to obtain an adjusted zero-crossing detection signal whose trigger point is earlier than that of the zero-crossing detection signal. Or, when the level of the second signal flips after the pulse width, the logic circuit can generate a second count signal and transmit the second count signal to the counter, enabling the counter to obtain the second count signal. In this way, at the rising edge of the fourth signal, the counter can perform an up-count on the first value of the counter according to the second count signal to obtain a second adjustment signal, and transmit the second adjustment signal to the voltage output circuit, enabling the voltage output circuit to obtain the second adjustment signal. Thus, the voltage output circuit can generate a second offset voltage corresponding to the second adjustment signal, and based on the second offset voltage and the first voltage, obtain a third voltage, and transmit the third voltage to the zero-crossing comparator, enabling the zero-crossing comparator to obtain the third voltage. Furthermore, the zero-crossing comparator can compare the magnitude relationship between the third voltage and the zero voltage to obtain an adjusted zero-crossing detection signal whose trigger point is later than that of the zero-crossing detection signal. Thus, the adaptive zero-crossing detection circuit can adaptively adjust the trigger point of the zero-crossing detection signal according to whether the level of the second signal flips within or after the pulse width of the pulse signal to obtain an adjusted zero-crossing detection signal until the trigger point of the adjusted zero-crossing detection signal is at the falling edge of the pulse signal.

[0133] Based on the description of the above embodiment, exemplarily, a possible implementation manner of the voltage output circuit 133. AsFigure 1 As shown, the voltage output circuit 133 may include: an offset voltage output circuit TRIM_VOS and an adder.

[0134] The input terminal of the offset voltage output circuit TRIM_VOS is electrically connected to the output terminal of the counter 132. The output terminal of the offset voltage output circuit TRIM_VOS is electrically connected to the first input terminal of the adder. The second input terminal of the adder is used to connect to the first voltage VL. The output terminal of the adder is electrically connected to the positive input terminal of the zero-crossing comparator CMP2.

[0135] Among them, the input terminal of the offset voltage output circuit TRIM_VOS is the first input terminal of the voltage output circuit 133, and the second input terminal of the adder is the second input terminal of the voltage output circuit 133.

[0136] The offset voltage output circuit TRIM_VOS can generate a first offset voltage corresponding to the first adjustment signal. And the offset voltage output circuit TRIM_VOS can transmit the first offset voltage to the adder, so that the adder can obtain the first offset voltage.

[0137] In this way, the adder can perform an addition operation on the first offset voltage and the first voltage VL to obtain a second voltage. Thus, the voltage output circuit 133 can obtain the second voltage according to the first offset voltage and the first voltage VL.

[0138] Or,

[0139] The offset voltage output circuit TRIM_VOS can generate a second offset voltage corresponding to the second adjustment signal. And the offset voltage output circuit TRIM_VOS can transmit the second offset voltage to the adder, so that the adder can obtain the second offset voltage.

[0140] In this way, the adder can perform an addition operation on the second offset voltage and the first voltage VL to obtain a third voltage. Thus, the voltage output circuit 133 can obtain the third voltage according to the second offset voltage and the first voltage VL.

[0141] In summary, the offset voltage output circuit can generate a first offset voltage corresponding to the first adjustment signal and transmit the first offset voltage to the adder, so that the adder can obtain the first offset voltage. In this way, the adder can perform an addition operation on the first offset voltage and the first voltage to obtain a second voltage. Or, the offset voltage output circuit can generate a second offset voltage corresponding to the second adjustment signal and transmit the second offset voltage to the adder, so that the adder can obtain the second offset voltage. In this way, the adder can perform an addition operation on the second offset voltage and the first voltage to obtain a third voltage. Thus, the voltage output circuit can obtain the second voltage and the third voltage.

[0142] Based on the description of the above embodiments, exemplarily, another possible implementation of the ringing suppression circuit 100. As Figure 1 shown, the ringing suppression circuit 100 may further include: a pulse signal generation circuit 140.

[0143] The first input terminal of the pulse signal generation circuit 140 is used to access the fifth signal LSOFF, and the fifth signal LSOFF is used to drive the low-side power transistor LS in the buck-boost converter 1000 to turn on or off. The second input terminal of the pulse signal generation circuit 140 is electrically connected to the output terminal of the adaptive zero-crossing detection circuit 130, and the output terminal of the pulse signal generation circuit 140 is electrically connected to the first input terminal of the adaptive zero-crossing detection circuit 130.

[0144] Exemplarily, when the fifth signal LSOFF is at a high level, the low-side power transistor LS is turned off. When the fifth signal LSOFF is at a low level, the low-side power transistor LS is turned on.

[0145] The pulse signal generation circuit 140 may generate a pulse signal EN_CAL according to the fifth signal LSOFF and the zero-crossing detection signal ZCD.

[0146] Among them, the rising edge of the pulse signal EN_CAL is the same as the rising edge of the fifth signal LSOFF.

[0147] Among them, when the rising edge of the fifth signal LSOFF arrives and the zero-crossing detection signal ZCD is also at a high level, the pulse signal generation circuit 140 may generate a pulse signal EN_CAL with a pulse width of dly.

[0148] Among them, due to the transmission delay in the buck-boost converter 1000. Therefore, the rising edge of the fifth signal LSOFF is later than the rising edge of the zero-crossing detection signal ZCD.

[0149] In summary, the pulse signal generation circuit may generate a pulse signal whose rising edge is the same as the rising edge of the fifth signal according to the fifth signal and the zero-crossing detection signal. Thus, the adaptive zero-crossing detection circuit may access the pulse signal.

[0150] Based on the description of the above embodiments, exemplarily, a possible implementation of the pulse signal generation circuit 140. As Figure 1 shown, the pulse signal generation circuit 140 may include: a delay element 143, a first inverter 141, a first nor gate device 144, and a first and gate device 142.

[0151] The input ends of the delay device 143 and the first inverter 141 are both used to connect to the fifth signal LSOFF. The output end of the delay device 143 is electrically connected to the first input end of the first NOR gate device 144. The output end of the first inverter 141 is electrically connected to the second input end of the first NOR gate device 144. The output end of the first NOR gate device 144 is electrically connected to the first input end of the first AND gate device 142. The second input end of the first AND gate device 142 is electrically connected to the output end of the adaptive zero-crossing detection circuit 130. The output end of the first AND gate device 142 is electrically connected to the first input end of the adaptive zero-crossing detection circuit 130.

[0152] Among them, the input ends of the delay device 143 and the first inverter 141 are both the first input end of the pulse signal generation circuit 140. The second input end of the first AND gate device 142 is the second input end of the pulse signal generation circuit 140. The output end of the first AND gate device 142 is the output end of the pulse signal generation circuit 140.

[0153] Among them, the first NOR gate device 144 performs a NOR operation. The first AND gate device 142 performs an AND operation.

[0154] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the detection circuit 110. As Figure 2 shown, the detection circuit 110 may include: a detection comparator CMP1 and a first latch 111.

[0155] The enable end of the detection comparator CMP1 is used to connect to the zero-crossing detection signal ZCD. The positive input end of the detection comparator CMP1 is electrically connected to the switch node SW. The negative input end of the detection comparator CMP1 is electrically connected to the ground potential. The output end of the detection comparator CMP1 is respectively electrically connected to the data input end of the first latch 111 and the second input end of the adaptive zero-crossing detection circuit 130. The enable end of the first latch 111 is used to connect to the fourth signal HSON. The output end of the first latch 111 is electrically connected to the control end of the power transistor 120.

[0156] Among them, the enable end of the detection comparator CMP1 is the enable end of the detection circuit 110. The positive input end of the detection comparator CMP1 is the first input end of the detection circuit 110. The negative input end of the detection comparator CMP1 is the second input end of the detection circuit 110. The output end of the first latch 111 is the first output end of the detection circuit 110. The output end of the detection comparator CMP1 is the second output end of the detection circuit 110.

[0157] After being enabled, the detection comparator CMP1 can compare the voltage of the switching node SW with the zero voltage to obtain a second signal ZMP. Moreover, the detection comparator CMP1 can transmit the second signal ZMP to the first latch 111, enabling the first latch 111 to obtain the second signal ZMP.

[0158] Among them, when the voltage of the switching node SW is greater than the zero voltage, the second signal ZMP is at a high level. When the voltage of the switching node SW is less than the zero voltage, the second signal ZMP is at a low level.

[0159] In this way, the first latch 111 can generate a first signal EN_RK according to the second signal ZMP and the fourth signal HSON. Thus, the detection circuit 110 can obtain the first signal EN_RK based on the voltage of the switching node SW and the zero voltage.

[0160] In some examples, the first latch 111 may include: a NOR gate NOR1 and a NOR gate NOR2.

[0161] The first input terminal of the NOR gate NOR1 is electrically connected to the output terminal of the detection comparator CMP1. The second input terminal of the NOR gate NOR1 is electrically connected to the output terminal of the NOR gate NOR2. The output terminal of the NOR gate NOR1 is electrically connected to the first input terminal of the NOR gate NOR2. The second input terminal of the NOR gate NOR2 is used to receive the fourth signal HSON. The output terminal of the NOR gate NOR2 is also electrically connected to the control terminal of the power transistor 120.

[0162] Among them, the first input terminal of the NOR gate NOR1 is the data input terminal of the first latch 111. The second input terminal of the NOR gate NOR2 is the enable terminal of the first latch 111. The output terminal of the NOR gate NOR2 is the output terminal of the first latch 111.

[0163] In summary, after being enabled, the detection comparator can compare the voltage of the switching node with the zero voltage to obtain a second signal and transmit the second signal to the first latch, enabling the first latch to obtain the second signal. In this way, the first latch can generate a first signal according to the second signal and the fourth signal. Thus, after being enabled, the detection circuit can obtain the first signal based on the voltage of the switching node and the zero voltage.

[0164] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the detection comparator CMP1. Refer to Figure 5 , Figure 5 This is a schematic structural diagram of the detection comparator in a ringing suppression circuit provided by an embodiment of the present application. As Figure 5 shown, the detection comparator CMP1 may include: a detection signal output circuit 112, a bias circuit 115, a comparison circuit 113, and a shaping circuit 114.

[0165] The first input terminal of the detection signal output circuit 112 is used to connect to the zero-crossing detection signal ZCD. The second input terminal of the detection signal output circuit 112 is used to connect to the fifth signal LSOFF. The third input terminal of the detection signal output circuit 112 is electrically connected to the data input terminal of the first latch 111 and the output terminal of the shaping circuit 114. The output terminal of the detection signal output circuit 112 is electrically connected to the first terminal of the comparison circuit 113. The second terminal of the comparison circuit 113 is used to connect to the sixth signal EN_TEST. The sixth signal EN_TEST is used to enable the comparison circuit 113. The third terminal of the comparison circuit 113 is electrically connected to the output terminal of the bias circuit 115. The fourth terminal of the comparison circuit 113 is electrically connected to the switch node SW. The input terminal of the bias circuit 115 is used to connect to the output voltage VOUT of the buck-boost converter 1000. The ground terminal of the bias circuit 115 is electrically connected to the ground potential. The fifth terminal of the comparison circuit 113 is electrically connected to the input terminal of the shaping circuit 114.

[0166] Among them, the ground terminal of the bias circuit 115 is the negative-phase input terminal of the detection comparator CMP1. The fourth terminal of the comparison circuit 113 is the positive-phase input terminal of the detection comparator CMP1. The first input terminal of the detection signal output circuit 112 is the enable terminal of the detection comparator CMP1.

[0167] Exemplarily, when the sixth signal EN_TEST is at a high level, the sixth signal EN_TEST enables the comparison circuit 113. When the sixth signal EN_TEST is at a low level, the sixth signal EN_TEST does not enable the comparison circuit 113.

[0168] The detection signal output circuit 112 can generate a detection signal PULL according to the zero-crossing detection signal ZCD, the second signal ZMP, and the fifth signal LSOFF. And the detection signal output circuit 112 can transmit the detection signal PULL to the comparison circuit 113 so that the comparison circuit 113 can obtain the detection signal PULL.

[0169] Among them, the detection signal PULL is used to represent whether the zero-crossing detection signal ZCD enables the detection circuit 110. Exemplarily, when the detection signal PULL is at a low level, the detection signal PULL represents that the zero detection signal ZCD enables the detection circuit 110. When the detection signal PULL is at a high level, the detection signal PULL represents that the zero detection signal ZCD does not enable the detection circuit 110.

[0170] The bias circuit 115 can generate a bias voltage VB according to the zero voltage and the output voltage VOUT of the buck-boost converter 1000. And the bias circuit 115 can transmit the bias voltage VB to the comparison circuit 113 so that the comparison circuit 113 can obtain the bias voltage VB.

[0171] Based on this, after enabling, the comparison circuit 113 can control the pull-down current of the first P-type transistor P1 in the comparison circuit 113 according to the bias voltage VB and the voltage of the switch node SW. And, after the detection signal PULL enables the detection circuit 110 by detecting the zero-crossing detection signal ZCD, the comparison circuit 113 can provide a first pull-up current to the first P-type transistor P1, and compare the magnitudes of the pull-down current and the first pull-up current to obtain a seventh signal.

[0172] Wherein, the width-to-length ratio of the first P-type transistor P1 is greater than a preset width-to-length ratio.

[0173] Exemplarily, when the first pull-up current is greater than the pull-down current, the seventh signal is at a high level. When the first pull-up current is less than the pull-down current, the seventh signal is at a low level.

[0174] Furthermore, the shaping circuit 114 can obtain the seventh signal from the comparison circuit 113. And, the shaping circuit 114 can shape the seventh signal to obtain a second signal ZMP, so that the detection comparator CMP1 can obtain the second signal ZMP.

[0175] In summary, the detection signal output circuit can generate a detection signal according to the zero-crossing detection signal, the second signal, and the fifth signal, and transmit a detection signal for characterizing whether the zero-crossing detection signal enables the detection circuit to the comparison circuit, so that the comparison circuit can obtain the detection signal. The bias circuit can generate a bias voltage according to the zero voltage and the output voltage of the buck-boost converter, and transmit the bias voltage to the comparison circuit, so that the comparison circuit can obtain the bias voltage. Based on this, after enabling, the comparison circuit can control the pull-down current of the first P-type transistor in the comparison circuit according to the bias voltage and the voltage of the switch node, and provide a first pull-up current to the first P-type transistor after the detection signal characterizes that the zero-crossing detection signal enables the detection circuit, and compare the magnitudes of the pull-down current and the first pull-up current to obtain a seventh signal; wherein, the width-to-length ratio of the first P-type transistor is greater than a preset width-to-length ratio. Furthermore, the shaping circuit can obtain the seventh signal from the comparison circuit and shape the seventh signal to obtain a second signal. Thus, the detection comparator can obtain the second signal.

[0176] Based on the description of the above embodiments, exemplarily, another possible implementation manner of the detection comparator CMP1. As Figure 5 shown, the detection comparator CMP1 may further include: a sixth signal output circuit 116.

[0177] The first input terminal of the sixth signal output circuit 116 is used to receive the eighth signal LSON, the level of the eighth signal LSON is opposite to that of the fifth signal LSOFF, the second input terminal of the sixth signal output circuit 116 is used to receive the fourth signal HSON, the third input terminal of the sixth signal output circuit 116 is used to receive the zero-crossing detection signal ZCD, the fourth input terminal of the sixth signal output circuit 116 is electrically connected to the output terminal of the shaping circuit 114, and the output terminal of the sixth signal output circuit 116 is electrically connected to the second terminal of the comparison circuit 113.

[0178] Exemplarily, when the low-side power transistor LS is turned off, the fifth signal LSOFF is at a high level and the eighth signal LSON is at a low level. When the low-side power transistor LS is turned on, the fifth signal LSOFF is at a low level and the eighth signal LSON is at a high level.

[0179] The sixth signal output circuit 116 can generate a sixth signal EN_TEST according to the eighth signal LSON, the fourth signal HSON, the zero-crossing detection signal ZCD, and the second signal ZMP.

[0180] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the sixth signal output circuit 116. As Figure 5 shown, the sixth signal output circuit 116 may include: a second inverter 116-1, a first NAND gate device 116-2, a second NAND gate device 116-3, and a second latch 116-4.

[0181] The first input terminal of the first NAND gate device 116-2 is used to receive the zero-crossing detection signal ZCD, the second input terminal of the first NAND gate device 116-2 is electrically connected to the output terminal of the shaping circuit 114, the output terminal of the first NAND gate device 116-2 is electrically connected to the first input terminal of the second NAND gate device 116-3, the input terminal of the second inverter 116-1 is used to receive the fourth signal HSON, the output terminal of the second inverter 116-1 is electrically connected to the second input terminal of the second NAND gate device 116-3, the output terminal of the second NAND gate device 116-3 is electrically connected to the enable terminal of the second latch 116-4, the data input terminal of the second latch 116-4 is used to receive the eighth signal LSON, and the output terminal of the second latch 116-4 is electrically connected to the second terminal of the comparison circuit 113.

[0182] Among them, the first input terminal of the first NAND gate device 116-2 is the third input terminal of the sixth signal output circuit 116, the second input terminal of the first NAND gate device 116-2 is the fourth input terminal of the sixth signal output circuit 116, the input terminal of the second inverter 116-1 is the second input terminal of the sixth signal output circuit 116, the data input terminal of the second latch 116-4 is the first input terminal of the sixth signal output circuit 116, and the output terminal of the second latch 116-4 is the output terminal of the sixth signal output circuit 116.

[0183] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the comparison circuit 113. As Figure 5 shown, the comparison circuit 113 may include: a first resistor R0, a second resistor R1, a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor M1, and a second N-type transistor M2.

[0184] Among them, the resistance value of the first resistor R0 is less than a first preset resistance value, the resistance value of the second resistor R1 is greater than a second preset resistance value, and the difference between the second preset resistance value and the first preset resistance value is greater than a third preset resistance value.

[0185] Among them, the current-carrying capacity of the first resistor R0 is less than the current-carrying capacity of the first P-type transistor P1 in the saturation region.

[0186] Among them, since the resistance value of the first resistor R0 is less than the first preset resistance value, the resistance value of the first resistor R0 is very small. Since the resistance value of the second resistor R1 is greater than the second preset resistance value, the resistance value of the second resistor R1 is very large. Since the difference between the second preset resistance value and the first preset resistance value is greater than the third preset resistance value, the resistance value of the first resistor R0 is much smaller than the resistance value of the second resistor R1.

[0187] The first end of the first resistor R0 and the second end of the second resistor R1 are both used to connect to the power supply voltage VDD. The second end of the first resistor R0 is electrically connected to the source of the second P-type transistor P2. The gate of the second P-type transistor P2 is electrically connected to the output terminal of the detection signal output circuit 112. The drain of the second P-type transistor P2, the second end of the second resistor R1, and the input terminal of the shaping circuit 114 are all electrically connected to the drain of the first N-type transistor M1. The gate of the first N-type transistor M1 is used to connect to the sixth signal EN_TEST. The source of the first N-type transistor M1 is electrically connected to the source of the first P-type transistor P1. The gate of the first P-type transistor P1 is electrically connected to the output terminal of the bias circuit 115. The drain of the first P-type transistor P1 is electrically connected to the drain and the gate of the second N-type transistor M2 respectively. The source of the second N-type transistor M2 is electrically connected to the switch node SW.

[0188] Among them, the gate of the second P-type transistor P2 is the first end of the comparison circuit 113, the gate of the first N-type transistor M1 is the second end of the comparison circuit 113, the gate of the first P-type transistor P1 is the third end of the comparison circuit 113, the source of the second N-type transistor M2 is the fourth end of the comparison circuit 113, and the drain of the first N-type transistor M1 is the fifth end of the comparison circuit 113.

[0189] In some examples, the on-resistance of the first N-type transistor M1 is approximately 0. That is to say, after the first N-type transistor M1 is turned on, the drain voltage of the first N-type transistor is approximately equal to the source voltage of the first N-type transistor.

[0190] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the detection signal output circuit 112. As Figure 5 shown, the detection signal output circuit 112 may include: a third inverter 112-1 and an OR gate device 112-2.

[0191] The input end of the third inverter 112-1 is used to access the zero-crossing detection signal ZCD. The output end of the third inverter 112-1 is electrically connected to the first input end of the OR gate device 112-2. The second input end of the OR gate device 112-2 is electrically connected to the output end of the shaping circuit 114. The third input end of the OR gate device 112-2 is used to access the fifth signal LSOFF. The output end of the OR gate device 112-2 is electrically connected to the first end of the comparison circuit 113.

[0192] Among them, the input end of the third inverter 112-1 is the first input end of the detection signal output circuit 112, the second input end of the OR gate device 112-2 is the third input end of the detection signal output circuit 112, and the third input end of the OR gate device 112-2 is the second input end of the detection signal output circuit 112.

[0193] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the bias circuit 115. As Figure 5 shown, the bias circuit 115 may include: a third P-type transistor P3 and a third resistor R2.

[0194] The source of the third P-type transistor P3 is electrically connected to the ground potential. The gate, the drain of the third P-type transistor P3 and the first end of the third resistor R2 are all electrically connected to the third end of the comparison circuit 113. The second end of the third resistor R2 is used to access the output voltage VOUT of the buck-boost converter 1000.

[0195] Among them, the source of the third P-type transistor P3 is the grounding end of the bias circuit 115, the gate of the third P-type transistor P3 is the output end of the bias circuit 115, and the second end of the third resistor R2 is the input end of the bias circuit 115.

[0196] Based on the description of the above embodiments, exemplarily, a possible implementation of the shaping circuit 114. As Figure 5 shown, the shaping circuit 114 may include: a fourth P-type transistor P4, a third N-type transistor M3, and a fourth inverter 114-1.

[0197] Among them, the threshold voltage VTH of the third N-type transistor M3 is equal to the gate-source voltage VGSM2 of the second N-type transistor M2.

[0198] The source of the fourth P-type transistor P4 is used to access the power supply voltage VDD. The gates of the fourth P-type transistor P4 and the third N-type transistor M3 are both electrically connected to the drain of the first N-type transistor M1. The drain of the fourth P-type transistor P4 is electrically connected to the drain of the third N-type transistor M3. The source of the third N-type transistor M3 is electrically connected to the ground potential. The input terminal of the fourth inverter 114-1 is electrically connected between the drain of the fourth P-type transistor P4 and the drain of the third N-type transistor M3. The output terminal of the fourth inverter 114-1 is electrically connected to the third input terminal of the detection signal output circuit 112.

[0199] Among them, the gates of the fourth P-type transistor P4 and the third N-type transistor M3 are both the input terminals of the shaping circuit 114, and the output terminal of the fourth inverter 114-1 is the output terminal of the shaping circuit 114.

[0200] Next, the working principle of the detection comparator CMP1 will be described in detail.

[0201] When the high-side power transistor HS is turned off and the low-side power transistor LS is turned on, that is, when the fourth signal HSON is at a low level, the eighth signal LSON is at a high level, and the zero-crossing detection signal ZCD is at a low level, the sixth signal EN_TEST is at a high level, turning on the first N-type transistor M1, enabling the comparison circuit 113, and the detection signal PULL is at a high level, turning off the second P-type transistor P2. At this time, since the voltage of the switch node SW is close to the output voltage VOUT of the buck-boost converter 1000, the first P-type transistor P1 is in the saturation region. In this way, the current-carrying capacity of the first P-type transistor P1 is greater than that of the second resistor R1, that is, the pull-down current of the first P-type transistor P1 is greater than the second pull-up current provided by the second resistor R1.

[0202] Among them, the gate voltage of the first P-type transistor P1 is determined by the bias voltage VB provided by the bias circuit 115. That is to say, the gate voltage of the first P-type transistor P1 is determined by the third P-type transistor P3 with its gate and drain short-circuited. The bias voltage VB is 0 - VSGP3, where VSGP3 is the gate-source voltage of the third P-type transistor P3. In this way, the source voltage VSP1 of the first P-type transistor P1 is VB + VSGP1, where VSGP1 is the gate-source voltage of the first P-type transistor P1. Based on this, since the sizes of the third P-type transistor P3 and the first P-type transistor P1 are close, the source voltage VSP1 of the first P-type transistor P1 is approximately 0 at the lowest, making the potential of the fifth terminal of the comparison circuit 113 at a low level, so that the seventh signal is at a low level. Thus, the second signal ZMP is at a low level.

[0203] When the inductor current IL is 0, that is to say, when the fourth signal HSON is at a low level, the eighth signal LSON is at a low level, and the zero-crossing detection signal ZCD is at a high level, the sixth signal EN_TEST is at a high level, turning on the first N-type transistor M1, enabling the comparison circuit 113, and the detection signal PULL is at a low level, turning on the second P-type transistor P2, so that the first pull-up current provided by the first resistor R0 and the second resistor R1 to the first P-type transistor P1. At this time, since the voltage of the switch node SW is still a negative voltage when the zero-crossing detection signal ZCD turns off the low-side power transistor LS, the current-carrying capacity of the first P-type transistor P1 is still greater than that of the first resistor R0 and the second resistor R1. That is to say, the pull-down current of the first P-type transistor P1 is still greater than the first pull-up current provided by the first resistor R0 and the second resistor R1. In this way, the source voltage VSP1 of the first P-type transistor P1 is still close to 0, making the potential of the fifth terminal of the comparison circuit 113 at a low level, so that the seventh signal is at a low level. Thus, the second signal ZMP is at a low level.

[0204] As the voltage of the switch node SW rises, the drain voltage of the first P-type transistor P1 also rises, making the first P-type transistor P1 in the linear region, so that the pull-down current of the first P-type transistor P1 begins to decrease. That is to say, the pull-down ability of the first P-type transistor P1 begins to decrease. Furthermore, the source voltage VSP1 of the first P-type transistor P1 will be pulled up by the first pull-up current provided by the first resistor R0 and the second resistor R1, making the potential of the fifth terminal of the comparison circuit 113 at a high level. When the source voltage VSP1 of the first P-type transistor P1 rises to the threshold voltage VTH of the third N-type transistor M3, the inverter composed of the fourth P-type transistor P4 and the third N-type transistor M3 flips, making the second signal ZMP at a high level. At this time, the voltage of the switch node SW can be expressed by formula (1):

[0205] VSW = VTH - VSDP1 - VGSM2 = 0 (1)

[0206] Wherein, VSW is the voltage of the switching node SW, VTH is the threshold voltage of the third N-type transistor M3, VGSM2 is the gate-source voltage of the second N-type transistor M2, and VSDP1 is the gate-source voltage of the first P-type transistor P1.

[0207] Since the first P-type transistor P1 is in the linear region, the gate-source voltage of the first P-type transistor P1 is relatively small. At the same time, the threshold voltage VTH of the third N-type transistor M3 is equal to the gate-source voltage VGSM2 of the second N-type transistor M2. Thus, it can be ensured that when the voltage of the switching node SW rises to zero voltage, the second signal ZMP is at a high level.

[0208] When the high-side power transistor HS is turned on, the fourth signal HSON is at a high level, causing the sixth signal EN_TEST to be reset to a low level by the second latch 116-4, turning off the first N-type transistor M1, and disabling the comparison circuit 113. At this time, since the high-side power transistor HS is turned on, the low-side power transistor LS must be turned off. In this way, the fifth signal LSOFF is at a low level, making the detection signal PULL at a high level. Furthermore, the drain voltage of the second P-type transistor P2 is pulled up to the power supply voltage VDD by the second resistor R1, that is, the source voltage VSP1 of the first P-type transistor P1 is the power supply voltage VDD, making the potential of the fifth terminal of the comparison circuit 113 at a high level, and making the seventh signal at a high level. Thus, the second signal ZMP is at a high level.

[0209] The embodiment of the present application also provides a buck-boost converter. Refer to Figure 6 , Figure 6 which is a schematic structural diagram of a buck-boost converter provided by an embodiment of the present application. As Figure 6 shown, the buck-boost converter 1000 may include: a high-side power transistor HS, a low-side power transistor LS, a flyback inductor L, a load capacitor C, and a ringing suppression circuit 100.

[0210] The drain of the high-side power transistor HS is used to access the input voltage VIN of the buck-boost converter 1000. The source of the high-side power transistor HS is electrically connected to the drain of the low-side power transistor LS. The gate of the high-side power transistor HS is used to access the fourth signal HSON, and the gate of the low-side power transistor LS is used to access the fifth signal LSOFF. The switching node SW is located between the source of the low-side power transistor LS and the drain of the high-side power transistor HS. The first end of the flyback inductor L and the first end of the ringing suppression circuit 100 are both electrically connected to the switching node SW. The second end of the flyback inductor L, the second end of the ringing suppression circuit 100, and the upper plate of the load capacitor C are all electrically connected to the ground potential. The source of the low-side power transistor LS is electrically connected to the lower plate of the load capacitor C, and the source of the low-side power transistor LS is also used to output the output voltage VOUT of the buck-boost converter 1000.

[0211] When the voltage of the switching node SW rises from the output voltage VOUT to zero voltage, the ringing suppression circuit 100 can control the connection between the switching node SW and the ground potential, so that no ringing phenomenon occurs at the switching node SW. Since the ringing suppression circuit 100 is only turned on when the voltage of the switching node SW rises from the output voltage VOUT to zero voltage, the voltage across the ringing suppression circuit 100 is small, reducing the power consumption of the ringing suppression circuit 100 and avoiding affecting the efficiency of the buck-boost converter 1000.

[0212] Among them, when the fourth signal HSON is at a high level, the high-side power transistor HS is turned on. When the fourth signal HSON is at a low level, the high-side power transistor HS is turned off.

[0213] Among them, the high-side power transistor HS usually refers to the upper transistor, and the low-side power transistor LS usually refers to the lower transistor.

[0214] The buck-boost converter provided by the embodiment of the present application has the same beneficial effects as the ringing suppression circuit provided by the embodiment of the present application, which will not be elaborated here.

[0215] The embodiment of the present application also provides a chip, including: a ringing suppression circuit, and / or, a buck-boost converter.

[0216] Among them, the ringing suppression circuit and the buck-boost converter can be a chip or a circuit module.

[0217] Among them, the ringing suppression circuit and the buck-boost converter can be integrated in the same chip or in different chips. The embodiment of the present application does not make specific limitations on this.

[0218] The chip provided by the embodiment of the present application has the same beneficial effects as the ringing suppression circuit provided by the embodiment of the present application, which will not be elaborated here.

[0219] An embodiment of the present application further provides an electronic device, including: a chip.

[0220] In the present application, the electronic device may include, but is not limited to: a tablet computer, a notebook computer, a navigation system, a wearable device, and a smart home device.

[0221] The electronic device provided by the embodiment of the present application has the same beneficial effects as the chip provided by the embodiment of the present application, which will not be elaborated here.

[0222] Finally, it should be noted that: the above embodiments are only specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A ringing suppression circuit, characterized in that, The ringing suppression circuit is applied to a buck-boost converter, and the buck-boost converter includes: a switching node; the ringing suppression circuit includes: a detection circuit and a power transistor; The enable terminal of the detection circuit is used to access a zero-crossing detection signal, the zero-crossing detection signal is used to enable the detection circuit, the first input terminal of the detection circuit and the first terminal of the power transistor are both electrically connected to the switching node, the second input terminal of the detection circuit and the second terminal of the power transistor are both electrically connected to the ground potential, and the first output terminal of the detection circuit is electrically connected to the control terminal of the power transistor; The detection circuit is used to obtain a first signal according to the voltage of the switching node and the zero voltage after being enabled, and transmit the first signal to the power transistor. The first signal is used to control the power transistor to turn on or off, and the zero voltage is the voltage of the ground potential; The power transistor is used to control the connection between the switching node and the ground potential according to the first signal when the voltage of the switching node rises from the output voltage of the buck-boost converter to the zero voltage, so as to eliminate the ringing phenomenon of the switching node.

2. The ringing suppression circuit according to claim 1, wherein The ringing suppression circuit further includes: an adaptive zero-crossing detection circuit; The first input terminal of the adaptive zero-crossing detection circuit is used to obtain a pulse signal. The pulse width of the pulse signal is used to represent the time required for the inductor current in the buck-boost converter to start decreasing from zero and the voltage of the switching node to rise from the output voltage to the zero voltage. The second input terminal of the adaptive zero-crossing detection circuit is electrically connected to the second output terminal of the detection circuit, and the output terminal of the adaptive zero-crossing detection circuit is electrically connected to the enable terminal of the detection circuit; The adaptive zero-crossing detection circuit is used to obtain a second signal from the detection circuit, and adaptively adjust the trigger point of the zero-crossing detection signal according to the inversion of the level of the second signal within the pulse width of the pulse signal or after the pulse width, so as to obtain an adjusted zero-crossing detection signal until the trigger point of the adjusted zero-crossing detection signal is at the falling edge of the pulse signal. The second signal is used to represent whether the voltage of the switching node reaches the zero voltage. The trigger point refers to the moment when the zero-crossing detection signal or the adjusted zero-crossing detection signal flips from the first level to the second level. At the rising edge of the pulse signal, the low-side power transistor in the buck-boost converter turns off.

3. The ringing suppression circuit according to claim 2, wherein The adaptive zero-crossing detection circuit includes: a logic circuit, a counter, a voltage output circuit and a zero-crossing comparator; The first input terminal of the logic circuit is used to receive the pulse signal. The second input terminal of the logic circuit is electrically connected to the second output terminal of the detection circuit. The third input terminal of the logic circuit is used to receive a third signal, and the third signal is used to raise the potential of the counting input terminal of the counter. The output terminal of the logic circuit is electrically connected to the counting input terminal of the counter. The clock input terminal of the counter is used to receive a fourth signal, and the fourth signal is used to drive the on or off of the high-side power transistor in the buck-boost converter. The output terminal of the counter is electrically connected to the first input terminal of the voltage output circuit. The second input terminal of the voltage output circuit is used to receive a first voltage, and the first voltage is used to represent the magnitude of the inductor current. The output terminal of the voltage output circuit is electrically connected to the positive-phase input terminal of the zero-crossing comparator. The negative-phase input terminal of the zero-crossing comparator is electrically connected to the ground potential. The output terminal of the zero-crossing comparator is electrically connected to the enable terminal of the detection circuit; The logic circuit is configured to generate a first counting signal when the level of the second signal flips within the pulse width, and transmit the first counting signal to the counter; The counter is configured to, at the rising edge of the fourth signal, perform a down-count on the first value of the counter according to the first counting signal to obtain a first adjustment signal, and transmit the first adjustment signal to the voltage output circuit; The voltage output circuit is configured to generate a first offset voltage corresponding to the first adjustment signal, and obtain a second voltage according to the first offset voltage and the first voltage, and transmit the second voltage to the zero-crossing comparator; The zero-crossing comparator is configured to compare the magnitude relationship between the second voltage and the zero voltage to obtain the adjusted zero-crossing detection signal, and the trigger point of the adjusted zero-crossing detection signal is earlier than the trigger point of the zero-crossing detection signal; Or, The logic circuit is configured to generate a second counting signal when the level of the second signal flips after the pulse width, and transmit the second counting signal to the counter; The counter is configured to, at the rising edge of the fourth signal, perform an up-count on the first value of the counter according to the second counting signal to obtain a second adjustment signal, and transmit the second adjustment signal to the voltage output circuit; The voltage output circuit is configured to generate a second offset voltage corresponding to the second adjustment signal, and obtain the third voltage according to the second offset voltage and the first voltage, and transmit the third voltage to the zero-crossing comparator; The zero-crossing comparator is configured to compare the magnitude relationship between the third voltage and the zero voltage to obtain the adjusted zero-crossing detection signal, and the trigger point of the adjusted zero-crossing detection signal is later than the trigger point of the zero-crossing detection signal.

4. The ringing suppression circuit according to claim 3, wherein The voltage output circuit includes: an offset voltage output circuit and an adder; The input end of the offset voltage output circuit is electrically connected to the output end of the counter, the output end of the offset voltage output circuit is electrically connected to the first input end of the adder, the second input end of the adder is used for accessing the first voltage, and the output end of the adder is electrically connected to the positive-phase input end of the zero-crossing comparator; The offset voltage output circuit is used for generating the first offset voltage corresponding to the first adjustment signal and transmitting the first offset voltage to the adder; The adder is used for performing an addition operation on the first offset voltage and the first voltage to obtain the second voltage; Or, The offset voltage output circuit is used for generating the second offset voltage corresponding to the second adjustment signal and transmitting the second offset voltage to the adder; The adder is used for performing an addition operation on the second offset voltage and the first voltage to obtain the third voltage.

5. The ringing suppression circuit according to claim 2, characterized in that, The ringing suppression circuit further includes: a pulse signal generation circuit; The first input end of the pulse signal generation circuit is used for accessing a fifth signal, the fifth signal is used for driving the low-side power transistor in the buck-boost converter to turn on or off, the second input end of the pulse signal generation circuit is electrically connected to the output end of the adaptive zero-crossing detection circuit, and the output end of the pulse signal generation circuit is electrically connected to the first input end of the adaptive zero-crossing detection circuit; The pulse signal generation circuit is used for generating the pulse signal according to the fifth signal and the zero-crossing detection signal, and the rising edge of the pulse signal is the same as the rising edge of the fifth signal.

6. The ringing suppression circuit according to claim 5, characterized in that, The pulse signal generation circuit includes: a delay element, a first inverter, a first NOR gate device, and a first AND gate device; The input end of the delay element and the input end of the first inverter are both used for accessing the fifth signal, the output end of the delay element is electrically connected to the first input end of the first NOR gate device, the output end of the first inverter is electrically connected to the second input end of the first NOR gate device, the output end of the first NOR gate device is electrically connected to the first input end of the first AND gate device, the second input end of the first AND gate device is electrically connected to the output end of the adaptive zero-crossing detection circuit, and the output end of the first AND gate device is electrically connected to the first input end of the adaptive zero-crossing detection circuit.

7. The ringing suppression circuit according to any one of claims 1-6, characterized in that, The detection circuit includes: a detection comparator and a first latch; The enable end of the detection comparator is used for accessing the zero-crossing detection signal, the positive-phase input end of the detection comparator is electrically connected to the switch node, the negative-phase input end of the detection comparator is electrically connected to the ground potential, the output end of the detection comparator is respectively electrically connected to the data input end of the first latch and the second input end of the adaptive zero-crossing detection circuit, the enable end of the first latch is used for accessing a fourth signal, and the output end of the first latch is electrically connected to the control end of the power transistor; The detection comparator is used for comparing the magnitude relationship between the voltage of the switch node and the zero voltage after being enabled to obtain a second signal and transmitting the second signal to the first latch; The first latch is configured to generate the first signal according to the second signal and the fourth signal.

8. The ringing suppression circuit according to claim 7, wherein The detection comparator includes: a detection signal output circuit, a bias circuit, a comparison circuit, and a shaping circuit; A first input terminal of the detection signal output circuit is configured to receive the zero-crossing detection signal, a second input terminal of the detection signal output circuit is configured to receive a fifth signal, a third input terminal of the detection signal output circuit is electrically connected to a data input terminal of the first latch and an output terminal of the shaping circuit, an output terminal of the detection signal output circuit is electrically connected to a first terminal of the comparison circuit, a second terminal of the comparison circuit is configured to receive a sixth signal, the sixth signal is used to enable the comparison circuit, a third terminal of the comparison circuit is electrically connected to an output terminal of the bias circuit, a fourth terminal of the comparison circuit is electrically connected to the switching node, an input terminal of the bias circuit is configured to receive an output voltage of the buck-boost converter, a ground terminal of the bias circuit is electrically connected to the ground potential, and a fifth terminal of the comparison circuit is electrically connected to an input terminal of the shaping circuit; The detection signal output circuit is configured to generate a detection signal according to the zero-crossing detection signal, the second signal, and the fifth signal, and transmit the detection signal to the comparison circuit, where the detection signal is used to indicate whether the zero-crossing detection signal enables the detection circuit; The bias circuit is configured to generate a bias voltage according to the zero voltage and the output voltage of the buck-boost converter, and transmit the bias voltage to the comparison circuit; The comparison circuit is configured to, after being enabled, control a pull-down current of a first P-type transistor in the comparison circuit according to the bias voltage and the voltage of the switching node, and provide a first pull-up current to the first P-type transistor after the detection signal indicates that the zero-crossing detection signal enables the detection circuit, and compare a magnitude relationship between the pull-down current and the first pull-up current to obtain a seventh signal; wherein, a width-to-length ratio of the first P-type transistor is greater than a preset width-to-length ratio; The shaping circuit is configured to obtain the seventh signal from the comparison circuit and shape the seventh signal to obtain the second signal.

9. The ringing suppression circuit according to claim 8, wherein The detection comparator further includes: a sixth signal output circuit; A first input terminal of the sixth signal output circuit is configured to receive an eighth signal, a level of the eighth signal is opposite to a level of the fifth signal, a second input terminal of the sixth signal output circuit is configured to receive the fourth signal, a third input terminal of the sixth signal output circuit is configured to receive the zero-crossing detection signal, a fourth input terminal of the sixth signal output circuit is electrically connected to an output terminal of the shaping circuit, and an output terminal of the sixth signal output circuit is electrically connected to a second terminal of the comparison circuit; The sixth signal output circuit is configured to generate the sixth signal according to the eighth signal, the fourth signal, the zero-crossing detection signal, and the second signal.

10. The ringing suppression circuit according to claim 9, characterized in that, The sixth signal output circuit includes: a second inverter, a first NAND gate device, a second NAND gate device, and a second latch; The first input terminal of the first NAND gate device is used to receive the zero-crossing detection signal. The second input terminal of the first NAND gate device is electrically connected to the output terminal of the shaping circuit. The output terminal of the first NAND gate device is electrically connected to the first input terminal of the second NAND gate device. The input terminal of the second inverter is used to receive the fourth signal. The output terminal of the second inverter is electrically connected to the second input terminal of the second NAND gate device. The output terminal of the second NAND gate device is electrically connected to the enable terminal of the second latch. The data input terminal of the second latch is used to receive the eighth signal. The output terminal of the second latch is electrically connected to the second terminal of the comparison circuit.

11. The ringing suppression circuit according to claim 8, wherein The comparison circuit includes: a first resistor, a second resistor, a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor; wherein, the resistance value of the first resistor is less than a first preset resistance value, the resistance value of the second resistor is greater than a second preset resistance value, and the difference between the second preset resistance value and the first preset resistance value is greater than a third preset resistance value; The first terminal of the first resistor and the second terminal of the second resistor are both used to receive the power supply voltage. The second terminal of the first resistor is electrically connected to the source electrode of the second P-type transistor. The gate electrode of the second P-type transistor is electrically connected to the output terminal of the detection signal output circuit. The drain electrode of the second P-type transistor, the second terminal of the second resistor, and the input terminal of the shaping circuit are all electrically connected to the drain electrode of the first N-type transistor. The gate electrode of the first N-type transistor is used to receive the sixth signal. The source electrode of the first N-type transistor is electrically connected to the source electrode of the first P-type transistor. The gate electrode of the first P-type transistor is electrically connected to the output terminal of the bias circuit. The drain electrode of the first P-type transistor is electrically connected to the drain electrode of the second N-type transistor and the gate electrode of the second N-type transistor respectively. The source electrode of the second N-type transistor is electrically connected to the switch node.

12. The ringing suppression circuit according to claim 8, wherein, The detection signal output circuit includes: a third inverter and an OR gate device; The input terminal of the third inverter is used to receive the zero-crossing detection signal. The output terminal of the third inverter is electrically connected to the first input terminal of the OR gate device. The second input terminal of the OR gate device is electrically connected to the output terminal of the shaping circuit. The third input terminal of the OR gate device is used to receive the fifth signal. The output terminal of the OR gate device is electrically connected to the first terminal of the comparison circuit.

13. The ringing suppression circuit according to claim 8, characterized in that, The bias circuit includes: a third P-type transistor and a third resistor; The source electrode of the third P-type transistor is electrically connected to the ground potential. The gate electrode of the third P-type transistor, the drain electrode of the third P-type transistor, and the first terminal of the third resistor are all electrically connected to the third terminal of the comparison circuit. The second terminal of the third resistor is used to receive the output voltage of the buck-boost converter.

14. The ringing suppression circuit according to claim 11, wherein The shaping circuit includes: a fourth P-type transistor, a third N-type transistor, and a fourth inverter; wherein, the threshold voltage of the third N-type transistor is equal to the gate-source voltage of the second N-type transistor; The source of the fourth P-type transistor is used to connect to the power supply voltage. The gates of the fourth P-type transistor and the third N-type transistor are both electrically connected to the drain of the first N-type transistor. The drain of the fourth P-type transistor is electrically connected to the drain of the third N-type transistor. The source of the third N-type transistor is electrically connected to the ground potential. The input terminal of the fourth inverter is electrically connected between the drain of the fourth P-type transistor and the drain of the third N-type transistor. The output terminal of the fourth inverter is electrically connected to the third input terminal of the detection signal output circuit.

15. A buck-boost converter, characterized in that, Comprising: a high-side power transistor, a low-side power transistor, a freewheeling inductor, a load capacitor, and a ringing suppression circuit according to any one of claims 1-14; The drain of the high-side power transistor is used to connect to the input voltage of the buck-boost converter. The source of the high-side power transistor is electrically connected to the drain of the low-side power transistor. The gate of the high-side power transistor is used to connect to a fourth signal. The gate of the low-side power transistor is used to connect to a fifth signal. A switching node is located between the source of the low-side power transistor and the drain of the high-side power transistor. The first end of the freewheeling inductor and the first end of the ringing suppression circuit are both electrically connected to the switching node. The second end of the freewheeling inductor, the second end of the ringing suppression circuit, and the upper plate of the load capacitor are all electrically connected to the ground potential. The source of the low-side power transistor is electrically connected to the lower plate of the load capacitor. The source of the low-side power transistor is further used to output the output voltage of the buck-boost converter; The ringing suppression circuit is configured to control the connection between the switching node and the ground potential when the voltage of the switching node rises from the output voltage to zero voltage, so that no ringing phenomenon occurs at the switching node.

16. A chip, characterized in that, Comprising: a ringing suppression circuit according to any one of claims 1-14; and / or, a buck-boost converter according to claim 15.

17. An electronic device, characterized in that, Comprising: a chip according to claim 16.

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