Power supply circuit, power taking method thereof and power supply chip

Abstract

The invention discloses a power supply circuit, a power taking method thereof and a power supply chip, and belongs to the technical field of power supply chips, the power supply circuit comprises a logic sub-circuit, a driving sub-circuit and a driving energy storage capacitor, and the driving sub-circuit is used for supplying power to the driving energy storage capacitor and the logic sub-circuit; the first voltage end and the second voltage end of the driving sub-circuit are connected to the two ends of the driving energy storage capacitor respectively, and the driving sub-circuit is configured to detect the voltage difference between the two ends of the driving energy storage capacitor and control the charging state of the driving energy storage capacitor; the current input end of the logic sub-circuit is connected with the third voltage end so that the logic sub-circuit and the driving sub-circuit can be connected in series, and the output control end of the logic sub-circuit is connected with the control end of the logic sub-circuit and used for establishing voltage for driving the two ends of the energy storage capacitor. The driving sub-circuit supplies power to the logic sub-circuit and charges the driving energy storage capacitor of the driving sub-circuit at the same time, the two circuits use the same path of current, and the power consumption of the chip is saved.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply chips, and particularly to a power supply circuit, a power supply taking method thereof, and a power supply chip. Background Art

[0002] Switching power supply chips are mainly used for power conversion, such as boosting, bucking, or buck-boosting. The power transistors inside generally use power triodes or power MOS transistors. For buck-type switching power supplies, the MOS transistors integrated inside the chip are divided into two types of power transistors, PMOS and NMOS, corresponding to two different drive circuits; there are various technical solutions to improve the conversion efficiency of power supply chips, and reducing the power consumption of the chips themselves is the current mainstream technical solution.

[0003] Among them, the inherent power consumption inside the power supply chip is mainly generated by the internal logic circuit and the power transistor drive circuit of the chip (here, the switching loss and conduction loss of the power transistor are not considered because these two losses can be solved by increasing the switching speed of the MOS transistor inside the chip and reducing the on-resistance of the MOS transistor). Since the internal logic circuit of the chip draws power from the power supply, and at the same time the drive circuit draws power from the power supply separately, the power supply circuits of the two modules are independent and do not affect each other. However, the problem is that the power consumption of the chip is relatively large. When the chip is working, the internal logic and drive circuits are both in the working state, so the generated loss is basically fixed, and the inherent power consumption of the chip is large.

[0004] It should be noted that the information disclosed in the background art part of this invention is only intended to deepen the understanding of the general background art of this invention, and should not be regarded as an admission or any form of suggestion that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide a power supply circuit, a power supply taking method thereof, and a power supply chip to solve the problem of relatively large inherent power consumption of the power supply chip.

[0006] To solve the above technical problem, the present invention provides a power supply circuit, including a logic sub-circuit, a drive sub-circuit, and a drive energy storage capacitor. The drive sub-circuit is used to supply power to the drive energy storage capacitor and the logic sub-circuit. The drive sub-circuit has an output control end, a first voltage end, a second voltage end, and a third voltage end. The first voltage end and the second voltage end are respectively connected to both ends of the drive energy storage capacitor. The drive sub-circuit is configured to detect the voltage difference across the drive energy storage capacitor and control the charging state of the drive energy storage capacitor. The current input end of the logic sub-circuit is connected to the third voltage end, so that the logic sub-circuit and the drive sub-circuit are in series. The output control end is connected to the control end of the logic sub-circuit for establishing the voltage across the drive energy storage capacitor.

[0007] Preferably, when the power transistor operates normally, the driving sub - circuit supplies the required current to the logic sub - circuit.

[0008] Preferably, the driving sub - circuit includes a clamping module. The output control terminal, the first voltage terminal, the second voltage terminal, and the third voltage terminal all belong to the clamping module. The clamping module includes a voltage detection component and a current control component. The output terminal of the voltage detection component and the input terminal of the current control component are commonly connected and taken out as the output control terminal. The voltage detection component is used to detect the voltage difference across the driving energy - storage capacitor and output a corresponding level signal. The current control component is used to supply corresponding currents to the driving energy - storage capacitor and the logic sub - circuit respectively according to the output of the voltage detection component. When the power transistor operates normally, the driving sub - circuit supplies the required current to the logic sub - circuit.

[0009] Preferably, the voltage detection component includes a second comparator, a third switching element, a third constant - current source, a fourth constant - current source, and a first resistor. The first input terminal of the second comparator is connected to both ends of the driving energy - storage capacitor through two resistors respectively. The second input terminal of the second comparator, the second end of the first resistor, the input terminal of the third constant - current source, and the input terminal of the fourth constant - current source are connected. The first end of the first resistor is connected to the first end of the driving energy - storage capacitor. The output terminal of the fourth constant - current source is connected to the input terminal of the third switching element. The control terminal of the third switching element is connected to the output terminal of the second comparator. The output terminals of the third switching element and the third constant - current source are both grounded. When the voltage difference across the driving energy - storage capacitor reaches a second preset value, the second comparator causes the output control terminal to output a second level signal to the logic sub - circuit, the power transistor operates normally, the power supply circuit operates normally, and the charging current of the driving sub - circuit to the driving energy - storage capacitor is also reduced to lower the voltage difference across the driving energy - storage capacitor to a first preset value.

[0010] Preferably, the current control component includes a first current output unit and a second current output unit. The output terminals of the first current output unit and the second current output unit are commonly connected as the third voltage terminal to be connected to the current input terminal of the logic sub - circuit. The first current output unit is used to provide a compensation current to the logic sub - circuit when the power transistor is in the frequency - down state. The second current output unit is used to provide a charging current to the logic sub - circuit when the power transistor operates normally.

[0011] Preferably, when the power transistor is operating normally, the second current output unit is further configured to stop or reduce the output of the first current output unit; when the power transistor is in a frequency-down state, the first current output unit is further configured to stop or reduce the output of the second current output unit.

[0012] Preferably, the logic sub-circuit includes an instantaneous latching unit and a first comparator. The input end of the instantaneous latching unit is connected to the output control end, and the output end is connected to the second input end of the first comparator, and is configured to receive the control signal provided by the output control end, and control the power transistor through the first comparator.

[0013] Preferably, the instantaneous latching unit adopts the structure of an RS latch and a timer, and is configured to pull down the level signal of the second input end for a preset duration to turn off the power transistor, so that the drive sub-circuit charges the drive energy storage capacitor.

[0014] A power supply method for a power supply circuit, including the power supply circuit as described above, and the following method is used to obtain power: The drive sub-circuit provides the required current to the logic sub-circuit; The drive sub-circuit is used to detect the voltage difference across the drive energy storage capacitor. When the voltage difference across the drive energy storage capacitor reaches a second preset value: The drive sub-circuit outputs a second level signal to the logic sub-circuit, the power transistor operates normally, so that the power supply circuit operates normally, reduces the charging current of the drive energy storage capacitor, and reduces the voltage difference across the drive energy storage capacitor, so that the voltage difference across the drive energy storage capacitor drops to a first preset value.

[0015] A power supply chip includes the power supply circuit as described above.

[0016] In the power supply circuit provided by the present invention, by adopting a series power supply mode for the logic sub-circuit and the drive sub-circuit, that is, while supplying power to the logic sub-circuit, charging the drive energy storage capacitor of the drive sub-circuit, the two circuits use the same current path, and the drive sub-circuit also switches the current according to the voltage of the drive energy storage capacitor, saving the self-power consumption of the chip.

[0017] In the power supply taking method of the power supply circuit provided by the present invention, by using the driving sub-circuit to supply power to the driving energy storage capacitor and the logic sub-circuit synchronously, the inherent power consumption of the chip is reduced, and the voltage across the driving energy storage capacitor is monitored, and based on this, a corresponding current is set to charge the driving energy storage capacitor. The driving sub-circuit provides the required current according to the working state of the power supply circuit, further reducing the power consumption. A set of dynamic power supply control and output optimization system is constructed, realizing the reduction of the chip power consumption, and ensuring that the chip can stably control the switching of the internal power supply circuit and the normal logic operation in any state, ensuring the normal function and long-term reliability of the chip. The power supply taking method of the power supply circuit provided by the present invention and the power supply circuit provided by the present invention belong to the same inventive concept. Therefore, the power supply taking method of the power supply circuit provided by the present invention has at least all the advantages of the power supply circuit provided by the present invention, which will not be elaborated here.

[0018] The power supply chip provided by the present invention and the power supply circuit provided by the present invention belong to the same inventive concept. Therefore, the power supply chip provided by the present invention has at least all the advantages of the power supply circuit provided by the present invention, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them: Figure 1 is a schematic diagram of the internal structure of an existing power supply chip; Figure 2 is a schematic diagram of the internal structure of the power supply chip according to an embodiment of the present invention; Figure 3 is a schematic diagram of the current control component in the clamping module according to an embodiment of the present invention; Figure 4 is a schematic diagram of the voltage detection component in the clamping module according to an embodiment of the present invention; Figure 5 is a schematic diagram of the instantaneous latching unit according to an embodiment of the present invention. DRAWINGS

[0020] 100. Existing power supply chip; 200. Power supply chip.

[0021] Existing logic sub-circuit; 2. Existing driving sub-circuit; 3. Existing power transistor; 4. Logic sub-circuit; 5. Driving sub-circuit; 6. Power transistor.

[0022] 101. Existing startup and voltage regulation module; 102. Existing logic function module; 1021. Existing error amplifier; 1022. Existing compensation unit; 1023. Existing comparator; 1024. Existing oscillator; 1025. Existing overcurrent protection unit; 1026. Existing latch; 1027. Existing overtemperature protection unit; 103. Existing clamping module; 104. Existing drive module.

[0023] 201. Startup and voltage regulation module; 202. Logic function module; 2021. Error amplifier; 2022. Compensation unit; 2023. First comparator; 2024. Oscillator; 2025. Overcurrent protection unit; 2026. Latch; 2027. Overtemperature protection unit; 2028. Instantaneous latch unit; 203. Clamping module; 2031. First voltage terminal; 2032. Second voltage terminal; 2033. First current output unit; 2034. Second current output unit; 2035. Second comparator; 2036. Third voltage terminal; 204. Drive module; 2041. First drive terminal; 2042. Second drive terminal; 2043. Third drive terminal; 2044. Fourth drive terminal. Detailed implementation manners

[0024] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in very simplified forms and are not drawn to scale, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different focuses and sometimes different scales are adopted.

[0025] As used in the present invention, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" is usually the end close to the operator, the term "distal end" is usually the end close to the patient, "one end" and "the other end" as well as "proximal end" and "distal end" usually refer to two corresponding parts, which include not only the endpoints. The terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements. In addition, as used in the present invention, an element is disposed on another element, which usually only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, and should not be construed as indicating or implying the spatial position relationship between the two elements, that is, an element may be inside, outside, above, below or on one side of another element, etc. in any orientation, unless otherwise explicitly specified in the context. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] The core idea of the present invention is to provide a power supply circuit, a power supply taking method thereof and a power supply chip. By adopting a series power supply mode for the logic sub-circuit and the drive sub-circuit, that is, while supplying power to the logic sub-circuit, charging the drive energy storage capacitor of the drive sub-circuit. The two circuits use the same current path, and the drive sub-circuit will also switch the current according to the voltage of the drive energy storage capacitor, saving the self-power consumption of the chip.

[0027] The following is a description with reference to the accompanying drawings.

[0028] Research findings show that the breakdown voltage between the drain and source of a MOS transistor is relatively high, but the breakdown voltage between the gate and source is generally within 20V. For high-voltage power supply chips, a dedicated MOS transistor drive circuit is required to quickly turn on or off the power transistor inside the chip. The CISS capacitance (the input capacitance of the MOS transistor, referring to the parasitic capacitance) or COSS capacitance (the output capacitance of the MOS transistor, referring to the parasitic capacitance) of the power MOS is relatively large. If the power MOS needs to be quickly turned on or off, it is necessary to charge the gate-source of the MOS (charge the parasitic capacitance) at the moment of turning on, and the peak current is in the order of hundreds of milliamperes (mA). After the power transistor is turned on, only a tiny current is required to maintain the device in the on state. When turning off the power transistor, it is necessary to short-circuit the gate-source of the MOS, so that the charge of the gate-source parasitic capacitance can be discharged instantly, quickly turning off the power transistor.

[0029] In the existing technical solutions, the internal logic sub-circuit of the chip draws power from the power supply, and at the same time, the drive module draws power separately from the power supply. The power supply circuits of the two modules are independent of each other and do not affect each other. However, the problem is that the power consumption of the chip is relatively large, especially when the input voltage increases. Due to the relatively large inherent power consumption, when the input voltage is high, the chip temperature rises significantly, and it is unable to stably output high power.

[0030] For example Figure 1 As shown in the existing power supply chip 100, the existing internal logic sub-circuit 1 and the existing drive sub-circuit 2 are respectively powered, which can be called parallel power supply. The existing internal logic sub-circuit 1 includes an existing startup and voltage stabilization module 101 and an existing logic function module 102. The existing logic function module 102 contains an existing error amplifier 1021, an existing compensation unit 1022, an existing comparator 1023, an existing oscillator 1024, an existing overcurrent protection unit 1025, an existing latch 1026, an existing overtemperature protection unit 1027, etc. The specific functions of the above units and modules can be understood according to their names.

[0031] The existing power supply chip 100 also includes an existing power transistor 3, a VIN port, a VC port, a SW port, a GND port, and an FB port. Among them, the VC port and the VIN port are used to connect the drive energy storage capacitor CC, the SW port is used to output voltage, the FB port is used to obtain the feedback voltage, and the GND port is used for grounding. The VIN port is also used to obtain the input power supply. It can be seen from the block diagram that the two modules are independently powered, and the total current consumed by the chip during operation is IQ1 + IQ2. The consumed current is relatively large. For a high-voltage power management chip, the power consumption generated by this current is too large, and the heat generation is serious, so the chip cannot output high power.

[0032] Further research found that to solve the above problem of large current consumption, a series power supply mode can be adopted, that is, while supplying power to the logic circuit, the energy storage capacitor of the drive module is charged, and the two modules use the same current to save the power consumption of the chip itself. However, due to the significant difference between the power supply mode and the conventional circuit, the original circuit design architecture cannot ensure the stable and reliable operation of the chip, and an additional auxiliary judgment module needs to be added to improve the reliability of the chip.

[0033] Based on this, the present invention judges the voltage difference across the drive energy storage capacitor CC, and controls the power supply of the third voltage terminal (i.e., the C node) to the internal logic sub-circuit of the chip and the charging of the drive energy storage capacitor CC through the output control terminal (i.e., VON) signal, so as to make the series power supply mode more precisely controllable. This avoids large changes in the voltage of the clamping module driving the energy storage capacitor during the operation of the chip due to changes in the working state.

[0034] Specifically, please refer to Figures 2 - 5 , which is a schematic diagram of an embodiment of the present invention. As Figure 2 shown, a power supply circuit includes a logic sub-circuit 4, a drive sub-circuit 5, and a drive energy storage capacitor CC. The drive sub-circuit 5 is used to supply power to the drive energy storage capacitor CC and the logic sub-circuit 4. The drive sub-circuit 5 has an output control terminal VON, a first voltage terminal 2031, a second voltage terminal 2032, and a third voltage terminal 2036. The first voltage terminal 2031 and the second voltage terminal 2032 are respectively connected to both ends of the drive energy storage capacitor CC. The drive sub-circuit 5 is configured to detect the voltage difference across the drive energy storage capacitor CC and control the charging state of the drive energy storage capacitor CC. The current input terminal of the logic sub-circuit 4 is connected to the third voltage terminal 2036, so that the logic sub-circuit 4 and the drive sub-circuit 5 are in series. The output control terminal VON is connected to the control terminal of the logic sub-circuit 4 to establish the voltage across the drive energy storage capacitor CC.

[0035] As Figure 2As shown, power is supplied through the series-connected logic sub-circuit 4 and drive sub-circuit 5. It can be understood that the series power supply mode is quite different from the conventional circuit. The original circuit design architecture cannot ensure that the chip can work stably and reliably, and an additional auxiliary judgment module needs to be added to improve the reliability of the chip. For example, at the moment when the chip is powered on, the voltage of the internal logic sub-circuit 4 is established relatively quickly. However, the drive energy storage capacitor CC of the drive sub-circuit 5 needs to store a certain amount of energy first to ensure the subsequent fast and normal opening or closing of the power transistor 6. If the energy stored in the drive energy storage capacitor CC is abnormal (too high or too low), the power transistor 6 cannot be normally opened or closed. If it starts to work at this time, it may cause the chip to fail. Therefore, to improve the reliability of the series power supply circuit, while the drive sub-circuit 5 supplies power to the logic sub-circuit 4, it also monitors the voltage difference across the drive energy storage capacitor CC. For example Figure 2 and Figure 3 , since the VIN voltage remains basically unchanged after power-on, the VON signal is output by judging the voltage condition at the VC point to control the power supply state of the third voltage terminal 2036 to the internal logic sub-circuit 4 of the chip, and the charging state of the VIN terminal of the drive energy storage capacitor CC by the drive sub-circuit 5 according to the VON signal, so as to establish the voltage across the drive energy storage capacitor CC at the initial stage of power-on and make the series power supply mode more precisely controllable. To avoid large changes in the voltage of the drive energy storage capacitor CC of the VC clamping circuit due to changes in the working state during chip operation (the drive energy storage capacitor CC of the VC clamping circuit supplies power to the drive module 204, which is convenient for the drive module 204 to provide a transient large current to the MOS transistor gate-source to quickly turn on the power transistor 6), and the normal opening and closing of the power transistor 6 cannot be controlled.

[0036] Such as Figure 2 , the control terminal and input terminal of the power transistor 6 are both connected to the output terminal of the drive sub-circuit 5. Specifically, the control terminal and input terminal of the power transistor 6 are connected to the drive module 204 to be connected to the output terminal of the logic sub-circuit 4 through the drive module 204. The first voltage terminal 2031 and the second voltage terminal 2032 correspond to VIN and VC respectively, the third voltage terminal 2036 corresponds to the C node, and the output control terminal corresponds to VON. The two expressions have the same meaning.

[0037] In one embodiment, when the power transistor 6 is operating normally, the driving sub-circuit 5 supplies the required current to the logic sub-circuit 4. The switching frequency of the switching power supply is several hundred kHz. To reduce the switching loss of the power transistor, the turn-on time of the power transistor inside the chip is at the nanosecond level. Since the power transistor has parasitic capacitance, a dedicated MOS transistor driving circuit is required to control the power transistor 6 inside the chip. A current of hundreds of milliamperes needs to be provided to the gate-source of the power transistor instantaneously to quickly turn on the MOS transistor. As the MOS transistor is a voltage-controlled device, once the power transistor 6 is turned on, the subsequent continuous turn-on duration of several microseconds basically no longer consumes driving current. Among them, the energy consumed each time the MOS transistor is turned on can be considered fixed. The more times it is turned on per unit time, the more energy is consumed. When operating normally, the switching frequency of the chip is the highest, that is, the most energy is consumed. In light load, short circuit and other states, the chip will reduce the operating frequency, that is, the chip operates in a frequency-down state. When the power transistor 6 is operating normally, that is, when the power supply chip is operating normally, there is no need to continue using the instantaneous current of hundreds of milliamperes, and only a tiny current can maintain the device in the on state. When the power supply chip is operating in the frequency-down state, to prevent the voltage of the driving energy storage capacitor CC from being too high due to continuous charging, damaging the power transistor, reducing the charging current of the driving energy storage capacitor CC, and reducing the voltage difference across the driving energy storage capacitor CC, the driving sub-circuit 5 can supply current according to the current operating state of the current power transistor 6, that is, supply current according to the voltage difference across the driving energy storage capacitor CC, reducing the inherent power consumption of the entire power supply circuit.

[0038] Specifically, the driving sub-circuit 5 includes a clamping module 203. The output control terminal VON, the first voltage terminal 2031, the second voltage terminal 2032, and the third voltage terminal 2036 all belong to the clamping module 203. The clamping module 203 includes a voltage detection component and a current control component. The output terminal of the voltage detection component and the input terminal of the current control component are commonly connected and led out as the output control terminal. The voltage detection component is used to detect the voltage difference across the driving energy storage capacitor CC and output a corresponding level signal. The current control component is used to supply corresponding currents to the driving energy storage capacitor CC and the logic sub-circuit 4 respectively according to the output of the voltage detection component. When the power transistor is operating normally, the driving sub-circuit 5 supplies the required current to the logic sub-circuit 4.

[0039] It can be understood that the logic sub-circuit 4 and the drive sub-circuit 5 are connected in series through the clamping module 203. The voltage detection component in the clamping module 203 detects the voltage across the drive energy storage capacitor CC, and outputs a corresponding level signal to the output control terminal VON and the current control component according to the voltage magnitude of the drive energy storage capacitor CC. The current control component can control the constant current source for internal power supply to charge the drive energy storage capacitor CC according to this level signal. The output control terminal VON is also externally connected to the logic sub-circuit 4, which is used to delay the startup of the power transistor 6 in the initial stage of power-on, charge the drive energy storage capacitor CC, establish the voltage across the drive energy storage capacitor CC, and enable the drive energy storage capacitor CC to store a certain amount of energy, so as to achieve the purpose of quickly turning on and off the power transistor 6.

[0040] Among them, the drive sub-circuit 5 also includes a drive module 204. The first drive terminal 2041 of the drive module 204 is connected to the output terminal of the latch 2026 in the logic sub-circuit 4, the second drive terminal 2042 is connected to the second voltage terminal 2032, that is, VC, and the third drive terminal 2043 and the fourth drive terminal 2044 are respectively connected to the source and gate of the power transistor 6. The source is also connected to VIN. Therefore, by accessing the logic sub-circuit 4 through the output control terminal VON, the power transistor 6 can be delayed to turn on in the initial stage of power-on, and the drive energy storage capacitor CC can be charged through the drive module 204 to establish the voltage across the drive energy storage capacitor CC.

[0041] As Figure 4 shown, the voltage detection component includes a second comparator 2035, a third switching element Q3, a third constant current source IS3, a fourth constant current source IS4, and a first resistor R1. The first input terminal of the second comparator 2035 is connected to both ends of the drive energy storage capacitor CC through two resistors respectively. The second input terminal of the second comparator 2035 is connected to the second end of the first resistor R1, the input terminal of the third constant current source IS3, and the input terminal of the fourth constant current source IS4. The first end of the first resistor R1 is connected to the first end of the drive energy storage capacitor CC. The output terminal of the fourth constant current source IS4 is connected to the input terminal of the third switching element Q3. The control terminal of the third switching element Q3 is connected to the output terminal of the second comparator 2035. The output terminals of the third switching element Q3 and the third constant current source IS3 are both grounded.

[0042] The second comparator 2035 is configured to output a second-level signal from the output control terminal VON to the logic sub-circuit 4 when the voltage difference across the driving energy storage capacitor CC reaches a second preset value. The power transistor 6 operates normally, enabling the power supply circuit to operate normally. Additionally, the charging current to the driving energy storage capacitor CC is reduced to lower the voltage difference across the driving energy storage capacitor CC to a first preset value. Otherwise, a first-level signal is output to continue charging the driving energy storage capacitor CC and increase the voltage difference across the driving energy storage capacitor CC. Exemplarily, since the voltage at the VIN terminal of the driving energy storage capacitor CC remains basically unchanged, the purpose of changing the voltage difference across the driving capacitor CC can be achieved by charging the VC terminal.

[0043] It should be noted that after the voltage difference across the driving energy storage capacitor CC reaches the second preset value, when the voltage difference across the driving energy storage capacitor CC is reduced to the first preset value by charging, the output control terminal VON correspondingly switches to output the first-level signal, the power transistor 6 switches normally, and the entire chip operates normally. The non-inverting input terminal of the second comparator 2035 is connected to the A node. The A node is respectively connected to the second resistor R2 and the third resistor R3. The other ends of the second resistor R2 and the third resistor R3 are respectively connected to both ends of the driving energy storage capacitor CC, that is, VIN and VC of the driving energy storage capacitor CC. The inverting input terminal of the second comparator 2035 is used to provide a reference value for comparison with the non-inverting input terminal, which is provided by the third constant current source IS3, the fourth constant current source IS4, the first resistor R1, and the third switching element Q3. The first resistor R1 is connected to the third constant current source IS3. The B node is also connected to the fourth constant current source IS4. The other end of the fourth constant current source IS4 is also connected to the input terminal of the third switching element Q3. The control terminal of the third switching element Q3 is connected to the output control terminal VON. The third switching element Q3 and the third constant current source IS3 are added to change the voltage value of the B node. When the output control terminal VON is high, the third switching element Q3 conducts to lower the voltage value of the B node, achieving an increased hysteresis window and avoiding the occurrence of VON oscillation. The output terminal of the second comparator 2035 is the output control terminal VON.

[0044] In one embodiment, the third switching element Q3 is an NPN transistor. The first-level signal and the second-level signal are relative high-level and low-level signals. After VON is triggered low, regardless of the signal state of the output control terminal VON, the logic sub-circuit 4 no longer controls the output, and the power transistor 6 and the entire chip operate normally.

[0045] Specifically, the current control component includes a first current output unit 2033 and a second current output unit 2034. The output ends of the first current output unit 2033 and the second current output unit 2034 are commonly connected as the third voltage terminal 2036 and are connected to the current input end of the logic sub-circuit 4. The first current output unit 2033 is configured to provide a compensation current for the logic sub-circuit 4 when the power transistor 6 is in a frequency-down state, and the second current output unit 2034 is configured to provide a charging current for the logic sub-circuit 4 when the power transistor 6 is operating normally.

[0046] It can be understood that the second current output unit 2034 is further configured to stop or reduce the output of the first current output unit 2033 when the power transistor 6 is operating normally; the first current output unit 2033 is further configured to stop or reduce the output of the second current output unit 2034 when the power transistor 6 is in a frequency-down state.

[0047] The compensation current I1 output by the first current output unit 2033 and the charging Electricity current I2 output by the second current output unit 2034 are used to supply power jointly or separately under the control of a signal provided by the output control terminal VON.

[0048] Based on the current I1 output by the first current output unit 2033, the current I2 output by the second current output unit 2034, and the output control terminal VON signal provided by the voltage detection component, there are the following situations for the change of the circuit working state: First, when the chip is working with a load normally, the switching frequency is fixed. At this time, the amount of charge generated by the current I2 that powers the logic sub-circuit 4 per unit time is the same as the amount of charge generated by the current I3 that discharges the MOS transistor to turn on the driving module 204. Since the amount of charge for charging and discharging is basically the same, the voltage VC will not change, and the current I1 can be turned off, leaving only I2. Second, when the chip starts with a load or enters the discontinuous mode, no-load, or short-circuit working conditions, the chip is working in a frequency-down state, and the frequency is 1 / 4 - 1 / 5 of the normal working frequency. After the frequency decreases, the amount of charge generated by the discharge current I3 is less than the amount of charge generated by the charging current I2. When the charging charge is greater than the discharge charge, the voltage across the driving energy storage capacitor CC will continue to increase. To prevent the voltage from being too high and damaging the power transistor 6 (the voltage difference between the gate and source of the power transistor is generally controlled within 20V), when the voltage reaches the second preset value, it is necessary to reduce the current I2 or even turn off I2, that is, the VON outputs a low level at this time, and I1 starts to power the logic sub-circuit 4. In this way, the charging of the driving energy storage capacitor CC starts to decrease, and the voltage difference across the capacitor will gradually decrease and be maintained within the normal range. Third, when the chip is working in the light-load mode, the switching frequency will be even lower. After I2 works for a period of time, the capacitor voltage will reach the first preset value. At this time, the control logic of the chip can refer to the second situation to ensure that the entire chip works in a normal state.

[0049] Such as Figure 3As shown, the first current output unit 2033 includes a first switching element Q1, a first constant current source IS1, a first voltage stabilizing diode DZ1, and a first diode D1. The input end of the first switching element Q1 is connected to the input end of the first constant current source IS1, the control end is connected to the output end of the first constant current source IS1, the output end is connected to the first diode D1, the input end of the first voltage stabilizing diode DZ1 is connected to the output end of the first constant current source IS1, and the output end is grounded; the second current output unit 2034 includes a second switching element Q2, a second constant current source IS2, a second voltage stabilizing diode DZ2, and a second diode D2. The input end of the second constant current source IS2 is commonly connected to the input end of the first constant current source IS1 and serves as the first voltage terminal 2031, i.e., VIN, which is connected to one end of the driving energy storage capacitor CC. The output end of the second constant current source IS2 is connected to the control end of the second switching element Q2 and the input end of the second voltage stabilizing diode DZ2. The input end of the second switching element Q2 serves as the second voltage terminal 2032, i.e., VC, which is connected to the other end of the driving energy storage capacitor CC. The output end of the second voltage stabilizing diode DZ2 is grounded, the output end of the second switching element Q2 is connected to the input end of the second diode D2, and the output terminals of the first diode D1 and the second diode D2 are connected to the C node, i.e., the third voltage terminal 2036, and are connected to the start-up and voltage stabilizing module 201 of the logic sub-circuit 4 through the C node.

[0050] The current control component further includes a switching element Q0, a first capacitor C1, and a fourth switching element Q4. The input end of the switching element Q0 is connected to the control end of the first current output unit 2033 to control the first current output unit 2033. More preferably, the input end of the switching element Q0 is connected to the control end of the first switching element Q1. The control end of the switching element Q0 is commonly connected to the second comparator 2035 of the voltage detection component as the output control terminal VON. The output end of the switching element Q0 is grounded. The first end of the first capacitor C1, the input end of the fourth switching element Q4, and the third voltage terminal 2036, i.e., the C node, are connected. The control end of the fourth switching element Q4 is connected to the first voltage terminal 2031, i.e., VIN, and the output end of the fourth switching element Q4 and the second end of the first capacitor C1 are both grounded to prevent the third voltage terminal 2036 from oscillating. The second driving end 2042 and the third driving end 2043 of the driving module 204 are respectively connected to both ends of the driving energy storage capacitor CC, and the third driving end 2043 is further connected to the source electrode of the power transistor 6, and the fourth driving end 2044 is connected to the gate electrode of the power transistor 6.

[0051] Among them, the switching element Q0, the first switching element Q1, and the second switching element Q2 are all NPN triodes, and the fourth switching element Q4 is a PNP triode.

[0052] As described above, at the initial stage of power-on, in order to ensure that the driving energy storage capacitor CC of the VC clamping module 203 can be charged, I1 needs to be turned off and only I2 works. Since the logic sub-circuit 4 can work as long as there is current, and it takes a certain amount of time for the driving energy storage capacitor CC to charge the voltage. If the voltage of the VC capacitor is not established and the voltage value is too small, when the power transistor 6 is turned on at this time, the gate-source voltage of the power transistor 6 will be too small, and the power transistor 6 cannot be fully turned on, resulting in large MOS transistor losses. In severe cases, the power transistor 6 will be thermally broken down. To solve such problems, the output control terminal VON of the clamping module 203 can be used to output a corresponding level signal to control the logic sub-circuit 4, so as to turn off the power transistor 6 for a certain period of time at the initial stage of power-on.

[0053] At the initial stage of power-on, the working state of the power transistor 6 is controlled to turn off the power transistor 6. The output control terminal VON outputs a first level signal, that is, a high level. When I2 charges the driving energy storage capacitor CC to a second preset value, since it is the first power-on and only I2 charges the driving energy storage capacitor CC and the power transistor 6 does not work, so I3 is 0. When the voltage of the driving energy storage capacitor CC is charged to the second preset value, a second level signal, that is, a low level, will be output to make the chip start to work normally, that is, the power transistor 6 turns on the normal switch. Since this second preset value is a bit large, I1 will be turned on to supply power to the logic sub-circuit 4 synchronously. When the VC voltage returns to the first preset value, the power supply by I2 alone is restored and I1 is turned off. In the whole working logic, I1 participates in the power supply briefly and is basically powered by I2, so the power consumption can be reduced. At this time, the signal of the module output control terminal VON is switched to the second level signal, and the control of the power transistor 6 is also released.

[0054] To solve the problem that the power transistor 6 may be thermally broken down at the initial stage of power-on, the present invention introduces an instantaneous latching unit 2028, as Figure 2 shown, the logic sub-circuit 4 includes an instantaneous latching unit 2028 and a first comparator 2023. The input terminal of the instantaneous latching unit 2028 is connected to the output control terminal VON, and the output terminal is connected to the second input terminal of the first comparator 2023, which is used to receive the control signal provided by the output control terminal VON, and control the power transistor 6 through the first comparator 2023. At the initial stage of power-on, the power transistor 6 is turned off to charge the driving energy storage capacitor CC to ensure the energy stored at both ends. The second input terminal is the inverting input terminal of the first comparator 2023, that is, the VE node. The instantaneous latching unit 2028 can pull down VE for a period of time according to the level signal of the output control terminal VON, thereby turning off the power transistor 6 to charge both ends of the driving energy storage capacitor CC.

[0055] At the initial stage of power-on, the VE is pulled low in advance by the instantaneous latching unit 2028 (the VE signal is used to control the working state of the power transistor. When the VE signal is pulled low, the power transistor 6 inside the chip will not turn on and is in the off state) and locked for a preset time (this time is relatively short). When I2 charges the driving energy storage capacitor CC to the second preset value, (since it is the first power-on, only I2 charges the driving energy storage capacitor CC and the power transistor 6 does not work, so I3 is 0) when the voltage is charged to the second preset value, a signal will be output to make the chip start to work normally, that is, the power transistor 6 turns on and switches normally. Since the second preset value is a bit too large, I1 will be turned on and I1 is used to supply power to the logic sub-circuit 4 synchronously. When the VC voltage returns to the first preset value, the power supply by I2 alone is restored and I1 is turned off. In the whole working logic, I1 participates in the power supply briefly and is basically powered by I2, so the power consumption can be reduced. At this time, the VON signal output by the module is a low-level signal.

[0056] More preferably, as Figure 5 shown, the instantaneous latching unit 2028 adopts the structure of an RS latch and a timer, and is used to pull down the level signal of the second input terminal VE for a preset duration to turn off the power transistor 6, so that the driving sub-circuit 5 charges the driving energy storage capacitor CC.

[0057] Therefore, after the instantaneous latching unit 2028 detects that the VON signal is low, a high-level signal is output at the Q point and no longer controls the VE signal, and the chip resumes normal operation. When this module uses an RS latch, as long as it is triggered when VON is low, regardless of the state of the VON signal (since the S terminal is only briefly at a high level and is at a low-level signal at other times, the high-level state of the Q point can be maintained continuously), the Q point always outputs a high-level signal.

[0058] Specifically, the logic sub-circuit 4 further includes a start-up and voltage regulation module 201. The start-up and voltage regulation module 201 receives current from the second voltage terminal 2032, that is, VC, and supplies current to the logic function module 202. The logic function module 202 includes an error amplifier 2021, a compensation unit 2022, an oscillator 2024, an over-current protection unit 2025, a latch 2026, and an over-temperature protection unit 2027. The above modules and devices have the same connection control method as the existing scheme, and will not be elaborated here.

[0059] As Figure 5As shown, the instantaneous latching unit 2028 includes a fifth switching element Q5 to an eighteenth switching element Q18, a fifth constant current source IS5, a fourth resistor R4 to a sixth resistor R6, and a capacitor C0. The fifth switching element Q5 to the eleventh switching element Q11 are PNP transistors, and the rest are NPN transistors. The tenth switching element Q10 and the capacitor C0 form a timer. The input terminals of the fifth switching element Q5, the seventh switching element Q7, the eighth switching element Q8, the ninth switching element Q9, the tenth switching element Q10, and the eleventh switching element Q11 are all connected to VDD, and the control terminals are commonly connected. The input terminal of the sixth switching element Q6 is connected to the control terminal of the fifth switching element Q5. The control terminal of the sixth switching element Q6 is connected to the input terminal of the fifth constant current source IS5 and the output terminal of the fifth switching element Q5. The output terminal of the sixth switching element Q6 is grounded. The output terminal of the fifth constant current source IS5 is grounded. The input terminal of the twelfth switching element Q12 is connected to the output terminal of the seventh switching element Q7. The control terminal of the twelfth switching element Q12 is connected to one end of the fourth resistor R4. The other end of the fourth resistor R4 is connected to VON. The input terminal of the twelfth switching element Q12 is also connected to the control terminal of the thirteenth switching element Q13. The input terminal of the thirteenth switching element Q13, the input terminal of the fourteenth switching element Q14, and the control terminal of the fifteenth switching element Q15 are commonly connected to the output terminal of the eighth switching element Q8. The control terminal of the fourteenth switching element Q14 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5, one end of the sixth resistor R6, the input terminal of the fifteenth switching element Q15, and the input terminal of the sixteenth switching element Q16 are commonly connected to the output terminal of the ninth switching element Q9. One end of the capacitor C0 is connected to the output terminal of the tenth switching element Q10, and the flowing current is IC5. The other end of the capacitor C0 is connected to the control terminal of the sixteenth switching element Q16. The control terminal of the seventeenth switching element Q17 is connected to the other end of the sixth resistor R6. The input terminal of the seventeenth switching element Q17 is connected to the output terminal of the eleventh switching element Q11 and the control terminal of the eighteenth switching element Q18. The input terminal of the eighteenth switching element Q18 is VE. The output terminals of the twelfth switching element Q12 to the eighteenth switching element Q18 are all grounded.

[0060] As Figure 5As shown, the specific circuit mainly consists of an RS latch and a timer. When the chip starts up, VC has not been successfully established yet. VON is high, the R terminal is low, and the S terminal uses the charging effect of capacitor C0 at this time, so the S terminal is high, and the RS output Q is low. Therefore, VE is low, thus achieving the purpose of pulling down VE. When the capacitor is fully charged, the S terminal becomes low. When waiting for VC to be fully charged and VON becomes low, the R terminal is high, the Q signal is high, and the pull-down of the VE signal is released. Since S is low, R will not change its level state afterwards, and Q is in a high-level state, both of which will not affect the VE voltage. Thus, the delay function is completed, achieving soft start and avoiding the abnormal operation of power transistor 6. This delay function mainly relies on the charge and discharge characteristics of the capacitor. At the beginning, the voltage across capacitor C0 is zero. When charging capacitor C0, the S terminal is high, and the sixteenth switching element Q16 is conducting. When capacitor C0 is fully charged, the sixteenth switching element Q16 is cut off, and the delay time is t1. The delay time is related to the capacitance value, and the charging current is equal to IC5; the delay time t1 = C0 * V0 / IC5. Where C0 is the capacitance, and V0 is 0.7V in the present invention.

[0061] Through the coordinated design of the clamping module 203 and the instantaneous latching unit 2028, a set of dynamic power supply control and output optimization system is constructed, realizing the reduction of chip power consumption, and ensuring that the chip can stably control the switching of the internal power supply circuit and the normal operation of the logic in any state, ensuring the normal function and long-term reliability of the chip.

[0062] Based on the same technical concept, the present invention also provides a power taking method for a power supply circuit, including the power supply circuit as described above, and taking power by the following method: The driving sub-circuit 5 supplies the required current to the logic sub-circuit 4; The driving sub-circuit 5 is used to detect the voltage difference across the driving energy storage capacitor CC. When the voltage difference across the driving energy storage capacitor CC reaches the second preset value: The driving sub-circuit 5 outputs a second level signal to the logic sub-circuit 4, and the power transistor 6 operates normally, enabling the power supply circuit to operate normally, reducing the charging current of the driving energy storage capacitor CC, and reducing the voltage difference across the driving energy storage capacitor CC, so that the voltage difference across the driving energy storage capacitor CC drops to the first preset value.

[0063] Among them, when the voltage difference across the driving energy storage capacitor CC does not reach the second preset value, the driving sub-circuit 5 outputs a first level signal to the logic sub-circuit 4, the power transistor 6 is turned off, and the driving sub-circuit 5 continues to charge both ends of the driving energy storage capacitor CC to establish the voltage across the driving energy storage capacitor CC; and during the process of the voltage difference across the driving energy storage capacitor CC dropping to the first preset value, after being triggered by the second level signal, regardless of the state of the output control terminal VON signal, the power transistor 6 and the power supply circuit both operate normally.

[0064] By connecting the logic sub-circuit 4 and the drive sub-circuit 5 in series, the drive sub-circuit 5 is used to synchronously supply power to the drive energy storage capacitor CC and the logic sub-circuit 4, reducing the inherent power consumption of the chip. The voltage across the drive energy storage capacitor CC is monitored, and based on this, a corresponding current is set to charge the drive energy storage capacitor CC. The current provided inside the drive sub-circuit 5 is variable, and the required current IQ3 is provided according to the working state of the power supply circuit, further reducing the power consumption. For example, when the power supply circuit is working normally, the required current is less than the turn-on current. That is, when powering on, the turn-on current is used to turn on the power transistor 6, the voltage of the drive energy storage capacitor CC changes, and the drive sub-circuit 5 can correspondingly change the current based on the change in the voltage of the drive energy storage capacitor CC, providing a smaller current.

[0065] Regarding the internal structure of the clamping module 203 described above, the compensation current I1 output by the first current output unit 2033 in the current control component and the charging current I2 output by the second current output unit 2034 are used to supply power jointly or separately under the control of the signal provided at the output control terminal VON. When the chip is working normally, I2 is provided, and in other cases, such as when powering on and starting up, I1 can also be introduced.

[0066] Figure 3 and Figure 4 For the circuit structure of the clamping module 203, due to the working characteristics of the DCDC circuit, the MOS transistor is in a periodic switching state during normal operation. Therefore, the charge on the drive energy storage capacitor CC is also periodically discharged. I2 is the charging current of the drive energy storage capacitor CC (this current is a continuous current), and I3 is the discharge current of the drive energy storage capacitor CC (this current is a switching current). I3 charges the CISS of the power transistor PMOS in parallel, enabling the PMOS power transistor 6 to conduct quickly (the amount of charge consumed each time the power transistor 6 is turned on can be considered fixed. The more times it is turned on per unit time, the greater the total amount of charge consumed). The charging charge and discharge charge of I3 and I2 per unit time are the same, which can achieve continuous power supply of I2 and continuous shutdown of I1. As described above, the I2 current is not completely constant. When the chip operates in the discontinuous mode, no-load, or short-circuit, the chip will reduce its frequency, and the switching loss current of its PMOS power transistor 6 becomes smaller, that is, the amount of charge discharged by I3 becomes smaller. At this time, after the voltage difference VC reaches the second preset value, VON outputs a low level, and I1 also supplies power to the logic sub-circuit 4 at the same time. By adjusting the parameters, it can be achieved that when I2 and I1 supply power simultaneously, the current required by the logic sub-circuit 4 is mainly provided by I1, then the I2 current can become very small. By reducing the value of the I2 current that charges the drive energy storage capacitor CC, it is ensured that the voltage of the drive energy storage capacitor CC will not continue to increase (if the power transistor 6 is turned on after the CC voltage exceeds 20V, it will cause damage to the power transistor 6).

[0067] As Figure 4The voltage detection component, to achieve accurate detection of the VC voltage status, uses a high-sensitivity comparator COMP, a preset constant current source, and a resistor to set the reference voltage of the second comparator 2035, and compares the VC voltage with the set reference voltage. When it is detected that the voltage of the lower plate of the driving energy storage capacitor CC is lower than the set internal reference value, it indicates that the driving energy storage capacitor CC has been charged with sufficient charge at this time. VON outputs a low level, and I1 starts to supply power to the logic sub-circuit 4. By reasonably setting, I2 is made close to zero to avoid further increase in the voltage difference of the driving energy storage capacitor CC. During normal operation, through reasonable setting, the charging charge of I2 and the discharging charge of I3 are made equal per unit time. In this way, the main power consumption of the power supply chip is still I2. After the chip works normally, I1 is turned off. Only during low-frequency operations such as startup, short-circuit protection, and light load, the state of the power supply terminal of I1 will be switched. On this basis, a fourth switching element Q4 and a first capacitor C1 are added to stably supply power to the startup and voltage regulation module 201, and ensure that the charge on the first capacitor C1 is discharged when the chip is shut down, ensuring that the startup and voltage regulation module 201 shuts down quickly. A first diode D1 and a second diode D2 are added to clamp the voltage at point C to ensure the stability of point C. A third switching element Q3 and a third constant current source IS3 are added to change the voltage value at point B. When VON is high, the third switching element Q3 conducts to change the reference at point B, realizing an increased hysteresis window to avoid the occurrence of VON oscillation.

[0068] Based on the same technical concept, the present invention also provides a power supply chip, including the power supply circuit as described above.

[0069] In the existing power supply chip, the logic power supply circuit and the power transistor driving circuit are separately powered, resulting in relatively large power consumption of the chip itself and affecting the output power under high-voltage conditions. To reduce power consumption, the present invention uses a series power supply mode to reuse a current path and does not require separate power supply for the logic sub-circuit. Due to the change in the power supply state, multiple detection modes and power supply modes are provided to solve the possible abnormalities of the chip under different working modes.

[0070] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the technical field of the present invention based on the above disclosure fall within the protection scope of the technical solution of the present invention.

Claims

1. A power supply circuit, characterized in that, It includes a logic sub-circuit, a drive sub-circuit, and a drive energy storage capacitor. The drive sub-circuit is used to supply power to the drive energy storage capacitor and the logic sub-circuit; The drive sub-circuit has an output control terminal, a first voltage terminal, a second voltage terminal, and a third voltage terminal. The first voltage terminal and the second voltage terminal are respectively connected to both ends of the drive energy storage capacitor. The drive sub-circuit is configured to detect the voltage difference across the drive energy storage capacitor and control the charging state of the drive energy storage capacitor; The current input terminal of the logic sub-circuit is connected to the third voltage terminal, so that the logic sub-circuit and the drive sub-circuit are in series. The output control terminal is connected to the control terminal of the logic sub-circuit and is used to establish the voltage across the drive energy storage capacitor.

2. The power supply circuit according to claim 1, wherein When the power transistor operates normally, the drive sub-circuit provides the required current to the logic sub-circuit.

3. The power supply circuit according to claim 2, characterized in that, The drive sub-circuit includes a clamping module. The output control terminal, the first voltage terminal, the second voltage terminal, and the third voltage terminal all belong to the clamping module. The clamping module includes a voltage detection component and a current control component. The output terminal of the voltage detection component and the input terminal of the current control component are commonly connected and are taken out as the output control terminal; The voltage detection component is used to detect the voltage difference across the drive energy storage capacitor and output a corresponding level signal; The current control component is used to provide corresponding currents to the drive energy storage capacitor and the logic sub-circuit respectively according to the output of the voltage detection component. When the power transistor operates normally, the drive sub-circuit provides the required current to the logic sub-circuit.

4. The power supply circuit according to claim 3, wherein The voltage detection component includes a second comparator, a third switching element, a third constant current source, a fourth constant current source, and a first resistor. The first input terminal of the second comparator is connected to both ends of the drive energy storage capacitor through two resistors respectively. The second input terminal of the second comparator is connected to the second end of the first resistor, the input terminal of the third constant current source, and the input terminal of the fourth constant current source. The first end of the first resistor is connected to the first end of the drive energy storage capacitor. The output terminal of the fourth constant current source is connected to the input terminal of the third switching element. The control terminal of the third switching element is connected to the output terminal of the second comparator. The output terminals of the third switching element and the third constant current source are both grounded; When the voltage difference across the drive energy storage capacitor reaches a second preset value, the second comparator causes the output control terminal to output a second level signal to the logic sub-circuit, and when the power transistor operates normally, the power supply circuit operates normally, reducing the charging current of the drive energy storage capacitor to reduce the voltage difference across the drive energy storage capacitor to a first preset value.

5. The power supply circuit according to claim 3, wherein The current control component includes a first current output unit and a second current output unit. The output ends of the first current output unit and the second current output unit are commonly connected as the third voltage end and are connected to the current input end of the logic sub-circuit. The first current output unit is configured to provide a compensation current for the logic sub-circuit when the power tube is in a frequency-down state, and the second current output unit is configured to provide a charging current for the logic sub-circuit when the power tube is operating normally.

6. The power supply circuit according to claim 5, wherein The second current output unit is further configured to stop or reduce the output of the first current output unit when the power tube is operating normally; the first current output unit is further configured to stop or reduce the output of the second current output unit when the power tube is in a frequency-down state.

7. The power supply circuit according to claim 1, characterized in that The logic sub-circuit includes an instantaneous latch unit and a first comparator. The input end of the instantaneous latch unit is connected to the output control end, and the output end is connected to the second input end of the first comparator. It is configured to receive the control signal provided by the output control end and control the power tube through the first comparator.

8. The power supply circuit according to claim 7, characterized in that, The instantaneous latch unit adopts the structure of an RS latch and a timer, and is configured to pull down the level signal of the second input end for a preset duration to turn off the power tube, so that the drive sub-circuit charges the drive energy storage capacitor.

9. A power taking method for a power supply circuit, characterized in that, It includes the power supply circuit according to any one of claims 1-8, and the power is taken in by the following method: The required current is provided to the logic sub-circuit through the drive sub-circuit; The drive sub-circuit is used to detect the voltage difference across the drive energy storage capacitor. When the voltage difference across the drive energy storage capacitor reaches the second preset value: The drive sub-circuit outputs a second level signal to the logic sub-circuit, the power tube operates normally, the power supply circuit operates normally, the charging current for the drive energy storage capacitor is reduced, and the voltage difference across the drive energy storage capacitor is reduced so that the voltage difference across the drive energy storage capacitor drops to the first preset value.

10. A power chip, characterized in that, It includes the power supply circuit according to any one of claims 1-8.

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