Balanced power amplifier synthesis circuit and radio frequency power supply

Abstract

The invention provides a balanced power amplifier synthesis circuit and a radio frequency power supply. The balanced power amplifier synthesis circuit comprises a power divider, N power amplification channels and a synthesizer. The power divider is used for dividing an input signal into N first sub-signals and outputting the N first sub-signals to the corresponding power amplification channels. Each power amplification channel comprises a first phase shifter, a power amplifier and a second phase shifter which are connected in sequence, the first phase shifter is used for applying a first phase shift amount associated with the channel sequence number to the received first sub-signal, and the second phase shifter is used for applying a first compensation phase shift amount to the signal. The synthesizer is used for synthesizing each received signal into a first synthesized signal and outputting the first synthesized signal. According to the invention, due to the fact that the 180 / N phase shift difference exists between the second phase shifters of any two adjacent channels, reflected signals at the output end can be offset through the synthesizer after being subjected to phase shifting through the second phase shifters, the reflected signals are prevented from entering the output end, interference of the reflected signals to the interior of the system is reduced, and the overall stability of the system is enhanced.

Description

Technical Field

[0001] This application relates to the field of electronic power technology, and mainly relates to a balanced power amplifier synthesis circuit and a radio frequency power supply. Background Art

[0002] With the continuous progress and development of science and technology, radio frequency power supplies are increasingly widely used in various fields such as semiconductor production. The future development trend of radio frequency power supplies is to improve their output efficiency and stability. The topological circuit design of a balanced power amplifier (BPA) is crucial for achieving high-efficiency and high-stability power synthesis in radio frequency power supplies. Balanced power amplifier synthesis is a commonly used technology in radio frequency and microwave systems. It combines the output powers of two or more amplifiers into a single output to increase the output power and efficiency of the entire system.

[0003] The inventors of this application found in the process of research and practice that in the prior art, balanced power amplifier synthesis is achieved through a coupler or a cable. However, using a coupler to achieve balanced power amplifier synthesis can only perform two-way synthesis, with a narrow bandwidth and poor applicability. When using a cable to achieve balanced power amplifier synthesis, phase shift in the same direction is usually achieved through cables of different lengths. The cables occupy a large amount of space, and when the load impedance at the output end is mismatched, a reflected signal is generated. If the reflected signal enters the output end after being reflected by the amplifier, it will interfere with and damage the system performance. Summary of the Invention

[0004] This application provides a balanced power amplifier synthesis circuit and a radio frequency power supply, which can achieve multi-channel signal and wide-bandwidth signal power synthesis, can cancel the reflected signal at the output end, reduce the interference of the reflected signal to the inside of the system, and enhance the overall stability of the system.

[0005] In a first aspect, the present application provides a balanced power amplifier combining circuit, which includes a power divider, N power amplification channels, and a combiner. The power divider includes a first input terminal and N first output terminals. The N first output terminals correspond to the N power amplification channels one by one. The power divider is configured to divide an input signal received at the first input terminal into N first sub-signals with equal amplitude and in-phase, and output them to the corresponding power amplification channels through each of the first output terminals. Each of the N power amplification channels includes a first phase shifter, a power amplifier, and a second phase shifter connected in sequence. The first phase shifter is configured to apply a first phase shift amount associated with the channel number to the received first sub-signal. The second phase shifter is configured to apply a first compensation phase shift amount to the signal amplified by the power amplifier, so that the combined phase difference between the signals output to the combiner through each of the power amplification channels is 0. The combiner includes N second input terminals and a second output terminal. The combiner is configured to combine the phase-modulated signals received at each of the second input terminals into a first combined signal, and output the first combined signal through the second output terminal; wherein, the first phase shift amount in the i-th power amplification channel among the N power amplification channels satisfies:

[0006]

[0007] wherein, is the first phase shift amount, N is an integer greater than or equal to 3; i is an integer, and i = 1, 2, 3....N, is a first preset phase difference. In the present application, through multiple power amplification channels composed of two phase shifters and a power amplifier, in cooperation with a power divider and a combiner, power amplification and combination of signals can be achieved. The power divider can provide sub-signals with equal amplitude and in-phase as inputs for each power amplification channel. In each power amplification channel, the first phase shift amount and the first compensation phase shift amount can be calculated based on the channel number, and then the first phase shifter and the second phase shifter can be designed. Based on the first phase shift amount and the first compensation phase shift amount with the same magnitude and opposite phases, it is possible to cancel out the positive and negative phase shifts of the signals within each power amplification channel, so that there is no phase difference between the phase-modulated signals input to the combiner. At the same time, since there is a phase shift amount difference of 180 / N between the second phase shifters of any two adjacent channels, the reflected signals can be shifted by the second phase shifter and then cancel each other out at the combiner, preventing the reflected signals from entering the output terminal, reducing the interference of the reflected signals to the inside of the system, and enhancing the overall stability of the system.

[0008] In a possible implementation of the first aspect, the above-mentioned first phase shift amount is a negative phase, the above-mentioned first phase shifter is one of a low-pass filter, a cable, and a PCB trace, the above-mentioned first compensation phase shift amount is a positive phase, and the above-mentioned second phase shifter is a high-pass filter. In the present application, the first phase shifter can be selected from a low-pass filter, a cable, and a PCB trace to apply a first phase shift amount with a negative phase to the input signal. Correspondingly, the second phase shifter on the other side in the same power amplification channel can be selected as a high-pass positive-phase filter to apply a first phase shift amount with a positive phase to the input signal. In the power amplification channel, the introduction of the high-pass positive-phase filter can make the phase-frequency responses of the phase shifters between channels closer, that is, the slopes or gradients of the phases generated by the phase shifters with respect to frequency are close, so that in a wider frequency range, the combined phase difference of the output signals of each channel is close to 0, and the balanced power amplifier synthesis circuit can have a wider operating bandwidth.

[0009] In a possible implementation of the first aspect, the above-mentioned first phase shift amount is a positive phase, the above-mentioned first phase shifter is a high-pass filter, the above-mentioned first compensation phase shift amount is a negative phase, and the above-mentioned second phase shifter is one of a low-pass filter, a cable, and a PCB trace. In the present application, the first phase shifter can be selected as a high-pass positive-phase filter to apply a first phase shift amount with a positive phase to the input signal. Correspondingly, the second phase shifter on the other side in the same power amplification channel can be selected from a low-pass filter, a cable, and a PCB trace to apply a first compensation phase shift amount with a negative phase to the amplified signal, which can realize the design of two phase shifters with the same magnitude and opposite phases inside the power amplification channel, improve the flexibility of device selection, enrich the optional schemes of circuit design, and can improve the flexibility of circuit design. At the same time, the introduction of the high-pass positive filter can make the balanced power amplifier synthesis circuit have a wider operating bandwidth.

[0010] In a possible implementation of the first aspect, both the above-mentioned first phase shift amount and the above-mentioned first compensation phase shift amount are zero, and at least one of the above-mentioned first phase shifter and the above-mentioned second phase shifter is a band-pass filter. In the present application, both the first phase shift amount and the first compensation phase shift amount can be zero, which can reduce phase distortion and optimize the frequency response of the circuit. In each power amplification channel, at least one of the first phase shifter and the second phase shifter can be selected as a band-pass zero-phase filter. By using the band-pass zero-phase filter, the phase-frequency responses of the phase shifters between channels can be made closer, that is, the slopes or gradients of the phases generated by the phase shifters with respect to frequency are close, so that in a wider frequency range, the combined phase difference of the output signals of each channel is close to zero, and the balanced power amplifier synthesis circuit has a wider operating bandwidth.

[0011] In a possible implementation of the first aspect, the first phase shifter is configured to transform the output impedance of the power divider to a target input impedance, and the target input impedance is conjugate-matched with the input impedance of the power amplifier; the second phase shifter is configured to transform the output impedance of the power amplifier to a target output impedance, and the target output impedance is conjugate-matched with the input impedance of the synthesizer. In the present application, the first phase shifter and the second phase shifter can participate in impedance adjustment, and can appropriately match the impedance between the output impedance of the power divider and the input impedance of the power amplifier, and between the output impedance of the power amplifier and the input impedance of the synthesizer, thereby improving the circuit's ability to resist load mismatch, obtaining maximum power transmission, and reducing the impact of signal reflection, with strong applicability.

[0012] In a possible implementation of the first aspect, the power divider includes a first power divider and at least two second power dividers. The input end of the first power divider serves as the first input end of the power divider. The first power divider includes at least two output ends. One output end of the first power divider is connected to the input end of one of the second power dividers. At least four output ends of the at least two second power dividers all serve as the first output end of the power divider; the first power divider is configured to divide the input signal received at the input end of the first power divider into at least two second sub-signals with equal amplitude and in-phase, and output them to the corresponding second power dividers through the output ends of the first power divider respectively; the second power divider is configured to divide the second sub-signal received at the input end of the second power divider into at least two first sub-signals, and output them to the corresponding power amplification channels through the output ends of each second power divider respectively. In the present application, the signal splitting function of the power divider can be realized by cascading power dividers, improving the flexibility of device selection, with a simple circuit structure and enabling circuit miniaturization.

[0013] In a possible implementation of the first aspect, the synthesizer includes a first synthesizer and at least two second synthesizers. The output end of the first synthesizer serves as the second output end of the synthesizer. The first synthesizer includes at least two input ends. One input end of the first synthesizer is connected to the output end of one of the second synthesizers. The second synthesizer includes at least two input ends, and one input end is connected to one of the power amplification channels. At least four input ends of the at least two second synthesizers serve as the second input ends of the synthesizer. The second synthesizer is configured to synthesize the phase-modulated signals received at the respective input ends of the second synthesizer into a second synthesized signal, and output the second synthesized signal from the output end of the second synthesizer. The first synthesizer is configured to synthesize the second synthesized signals received at the respective input ends of the first synthesizer into the first synthesized signal, and output the first synthesized signal from the output end of the first synthesizer. In this application, the cascaded circuit has a better output port reflection coefficient. The reflected power caused by non-ideal factors in the first-stage synthesis can be dissipated on the isolation resistor of the next-stage synthesizer, thereby increasing the output power.

[0014] In a possible implementation of the first aspect, the above-mentioned N power amplification channels include at least two groups of power amplification channels; the above-mentioned first phase shifter is used to apply a first phase shift amount associated with the channel serial number in each group to the received above-mentioned first sub-signal; the power splitter includes a first power splitter and at least two second power splitters. The input end of the first power splitter serves as the first input end of the power splitter. The first power splitter includes at least two output ends, and one output end is connected to the input end of one of the above-mentioned second power splitters through a third phase shifter. The at least two output ends of the at least two second power splitters serve as the first output end of the power splitter and are connected to the above-mentioned at least two groups of power amplification channels. The input ends of at least two of the above-mentioned power amplification channels in the same group are connected to the same above-mentioned second power splitter; the first power splitter is used to divide the input signal received at the input end of the first power splitter into at least two second sub-signals with equal amplitude and in-phase, and output them to the corresponding above-mentioned second power splitters through the output ends of the first power splitter respectively; the second power splitter is used to divide the above-mentioned second sub-signal received at the input end of the second power splitter into at least two of the above-mentioned first sub-signals, and output them to the corresponding above-mentioned power amplification channels through the output ends of each of the above-mentioned second power splitters respectively; the synthesizer includes a first synthesizer and at least two second synthesizers. The output end of the first synthesizer serves as the second output end of the synthesizer. The first synthesizer includes at least two input ends, and one input end is connected to the output end of one of the above-mentioned second synthesizers through a fourth phase shifter. At least two input ends of one of the above-mentioned second synthesizers are connected to at least two of the above-mentioned power amplification channels. The output ends of at least two of the above-mentioned power amplification channels in the same group are connected to the same above-mentioned second synthesizer; the second synthesizer is used to synthesize the above-mentioned phase-modulated signals received at each input end of the second synthesizer into a second synthesized signal, and output the second synthesized signal from the output end of the second synthesizer; the first synthesizer is used to synthesize the above-mentioned second synthesized signals received at each input end of the first synthesizer into the above-mentioned first synthesized signal, and output the first synthesized signal from the output end of the first synthesizer; the third phase shifter is used to apply a second phase shift amount associated with the channel group serial number connected to the received above-mentioned second sub-signal; the fourth phase shifter is used to apply a second compensation phase shift amount to the above-mentioned second synthesized signal synthesized by the above-mentioned second synthesizer, so that the synthesized phase difference between the signals output to the first synthesizer through each of the above-mentioned fourth phase shifters is 0. In the present application, the cascaded power splitter and the cascaded synthesizer can improve the flexibility of device selection, enrich the optional schemes of circuit design, and improve the flexibility of circuit design.By connecting a third phase shifter between two-level power dividers and a fourth phase shifter between two-level combiners, the fourth phase shifter is used to compensate for the phase shift provided by the third phase shifter, which can make the combined phase difference between the signals output to the first combiner be 0, so as to obtain the signal synthesis output with the maximum power. At the same time, the cascaded circuit has a better reflection coefficient of the output port. The reflected power caused by non-ideal factors in the first-level synthesis can be dissipated on the isolation resistor of the next-level combiner, thereby reducing the reflection phenomenon of signals in the circuit and improving the stability of the circuit.

[0015] In a possible implementation manner of the first aspect, the above at least two groups of power amplification channels are K groups of power amplification channels; wherein, the second phase shift amount applied to the third phase shifter connected to the t-th group of the above K groups of power amplification channels satisfies:

[0016]

[0017] Wherein, is the second phase shift amount, K is an integer greater than or equal to 2; t is an integer, and t = 1, 2, 3....K, Δμ is the second preset phase difference. In the present application, the second phase shift amount applied to the corresponding third phase shifter can be calculated based on the group serial number of the power amplification channel connected to the third phase shifter through the above formula, and then the second compensation phase shift amount used to compensate for the second phase shift amount applied by the fourth phase shifter can be obtained, realizing positive and negative phase shift cancellation, which can make the combined phase difference between the signals input to the first combiner be 0, and then realizing the signal synthesis with the maximum power. At the same time, by calculating the second phase shift amount and the second compensation phase shift amount, the device parameters and circuit composition of the third phase shifter and the fourth phase shifter can be determined, and the circuit design is simple and has strong applicability.

[0018] In the second aspect, the present application provides a radio frequency power supply, and the above radio frequency circuit includes a signal generation unit and the balanced power amplifier synthesis circuit provided in the first aspect. In the present application, based on the collaborative work of the signal generation and amplification unit and the balanced power amplifier synthesis circuit, the synthesis efficiency of the signal power can be improved, the output signal quality of the radio frequency power supply can be improved, at the same time, the total output power of the radio frequency power supply can be significantly improved, the energy loss can be reduced, the system structure is simple, and the applicability is strong. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic structural diagram of the balanced power amplifier synthesis circuit provided by the present application;

[0020] Figure 2 is another schematic structural diagram of the balanced power amplifier synthesis circuit provided by the present application;

[0021] Figure 3AIt is another structural schematic diagram of the balanced power amplifier synthesis circuit provided by this application;

[0022] Figure 3B It is a phasor schematic diagram of the three-way reflected signals provided by this application;

[0023] Figure 4A It is a structural schematic diagram of the phase shifter in the balanced power amplifier synthesis provided by this application;

[0024] Figure 4B It is another structural schematic diagram of the phase shifter in the balanced power amplifier synthesis provided by this application;

[0025] Figure 5 It is another structural schematic diagram of the phase shifter in the balanced power amplifier synthesis provided by this application;

[0026] Figure 6 It is another structural schematic diagram of the balanced power amplifier synthesis circuit provided by this application;

[0027] Figure 7 It is another structural schematic diagram of the balanced power amplifier synthesis circuit provided by this application;

[0028] Figure 8 It is another structural schematic diagram of the balanced power amplifier synthesis circuit provided by this application;

[0029] Figure 9 It is another structural schematic diagram of the balanced power amplifier synthesis circuit provided by this application;

[0030] Figure 10 It is a structural schematic diagram of the RF power supply provided by this application;

[0031] Figure 11 It is a structural schematic diagram of the electronic device provided by this application. Detailed implementation manners

[0032] As one of the indispensable topological circuits in the field of power electronics technology, the balanced power amplifier synthesis circuit is widely used in power systems such as radio frequency power supplies, industrial control, energy storage systems, and wireless communication base stations. Balanced power amplifier synthesis is a technology that combines the outputs of multiple power amplifiers through a specific network to increase the output power. In common balanced power amplifier synthesis topological circuits, couplers or cables are usually used to achieve balanced power amplifier synthesis. However, when using a coupler to achieve balanced power amplifier synthesis, the traditional coupler can essentially only combine two signals into one and maintain a certain isolation degree and phase difference, with problems such as narrow bandwidth, inability to perform arbitrary path synthesis, and poor applicability. When using cables to achieve balanced power amplifier synthesis, phase shift in the same direction is usually achieved through cables of different lengths, and positive and negative phase shifts cannot be achieved. Moreover, when using cables for phase adjustment, it is usually only applicable to narrowband applications. In broadband applications, the dispersion effect caused by different phase delays of each frequency component of the signal during transmission is more obvious, resulting in poor synthesis effects. At the same time, the cables occupy a large space and cannot achieve circuit miniaturization. The balanced power amplifier synthesis circuit provided in this application can achieve signal power synthesis of arbitrary paths and broadband widths, and at the same time can achieve circuit miniaturization, with a simple circuit structure and strong applicability. Here, the above-mentioned balanced power amplifier synthesis circuit can be used in fields involving signal power amplification and synthesis, including but not limited to radio frequency power supplies, wireless communication, and industrial control, and can be specifically determined according to the actual application scenario, without limitation here.

[0033] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of the balanced power amplifier synthesis circuit provided in this application. As Figure 1As shown in the figure, the balanced power amplifier synthesis circuit provided by the present application may include a power divider, N power amplification channels, and a synthesizer. The above-mentioned power divider may include a first input end and N first output ends. The above-mentioned N first output ends correspond to the above-mentioned N power amplification channels one by one. The power divider can be used to divide the input signal received at the first input end into N first sub-signals with equal amplitude and the same phase, and output them to the corresponding power amplification channels through each of the above-mentioned first output ends. Each of the above-mentioned N power amplification channels may include a first phase shifter, a power amplifier, and a second phase shifter connected in sequence. The first phase shifter can be used to apply a first phase shift amount associated with the channel number to the received first sub-signal. The second phase shifter can be used to apply a first compensation phase shift amount to the signal amplified by the power amplifier, so that the combined phase difference between the signals output from each of the above-mentioned power amplification channels to the synthesizer is 0. The synthesizer may include N second input ends and a second output end. The synthesizer can be used to combine the phase-modulated signals received at each of the above-mentioned second input ends into a first combined signal, and output the first combined signal from the second output end; where, the first phase shift amount in the i-th power amplification channel among the above-mentioned N power amplification channels may satisfy:

[0034]

[0035] Wherein, is the above-mentioned first phase shift amount, N is an integer greater than or equal to 3; i is an integer, and i = 1, 2, 3....N, is the first preset phase difference. Here, the above-mentioned power divider can be a microstrip power divider, a resistive power divider, a waveguide power divider, etc. The above-mentioned synthesizer can be a co-frequency combiner, a microwave hybrid bridge synthesizer, a microstrip balun synthesizer, a symmetric balun synthesizer, etc. The specific implementation forms of the power divider and the splitter can be determined according to the actual application scenario and are not limited here. The input of the above-mentioned power divider, that is, the input of the balanced power amplifier synthesis circuit, can be various signal sources such as electrical signals and radio frequency signals, which can be specifically determined according to the actual application scenario and are not limited here. It can be understood that the power divider may cause phase delay to the signal. However, the phase delays between the divided signals are the same. Therefore, there is no phase difference between the multiple first sub-signals output by the power divider, that is, the multiple first sub-signals output by the power divider have equal amplitude and the same phase. Here, there is no phase difference between the first sub-signals output from the power divider to any two adjacent above-mentioned power amplification channels, and there is also no phase difference between the signals output from any two adjacent above-mentioned power amplification channels to the synthesizer. For example, if Figure 1As shown in the figure, the balanced power amplifier combining circuit includes a power divider, a combiner, and N power amplification channels (N is an integer greater than or equal to 3), including but not limited to power amplification channel 1, power amplification channel 2,..., power amplification channel N, etc. Correspondingly, the power divider is a 1-to-N power divider, and the combiner is an N-to-1 combiner. The power divider has N output terminals corresponding to connect N power amplification channels, and the combiner has N input terminals corresponding to connect N power amplification channels. In Figure 1 In the balanced power amplifier combining circuit shown, the input terminal of the 1-to-N power divider can be used as the input terminal of the balanced power amplifier combining circuit. Suppose a test signal is input into the balanced power amplifier combining circuit from the input terminal of the power divider. The 1-to-N power divider divides the above test signal into N branch signals and inputs them into N power amplification channels. At this time, the signals input into each power amplification channel have no phase difference with each other, and the N branch signals output to the N-to-1 combiner through each power amplification channel also have no phase difference, that is, there is no combined phase difference among the N signals input into the input terminal of the N-to-1 combiner. Please refer to Figure 2 , Figure 2 which is another structural schematic diagram of the balanced power amplifier combining circuit provided by this application. As Figure 2As shown, any one of the above power amplification channels includes a first phase shifter, a power amplifier (PA), and a second phase shifter connected in sequence. The first phase shifter can be used to apply a first phase shift amount associated with the channel number to the received first sub-signal, and the second phase shifter can be used to apply a first compensation phase shift amount to the signal amplified by the power amplifier, so that the combined phase difference between the signals output from each of the above power amplification channels to the above combiner is 0. It can be understood that the first phase shift amount and the first compensation phase shift amount can be a set of phase shift amounts with the same magnitude and opposite phases, or the first phase shift amount and the first compensation phase shift amount can both be 0. Therefore, the phase shift amounts applied by the first phase shifter and the second phase shifter can cancel each other out. So when the first sub-signals input to each power amplification channel are in the same phase (i.e., there is no phase difference), the signals output from each power amplification channel also remain in the same phase, that is, the combined phase difference between the signals output from each of the above power amplification channels to the above combiner is 0. It can be understood that the power amplifier may cause a phase impact on the signal during the signal amplification process. Since the same power amplifier can be selected for each power amplification channel, the phase changes generated by the power amplifier during operation are the same for the signals. Therefore, this phase change can be ignored, that is, it does not affect that the signals output after inputting signals with the same phase are still in the same phase. Here, the above power amplifier can be a class A amplifier, a class B amplifier, a class AB amplifier, etc. The above power amplifier includes but is not limited to topological structures such as power tubes, input / output matching networks, bias networks, and control circuits, which can be specifically determined according to the actual application scenario and are not limited here. It can be understood that the values of the above first phase shift amount and the first compensation phase shift amount are related to the channel number. That is to say, the above multiple power amplification channels can be sorted, and the phase shift amount of each first phase shifter is associated with the channel number of the power amplification channel where it is located. For example, in the balanced power amplifier synthesis circuit as shown in Figure 2 includes N power amplification channels (N is an integer greater than or equal to 3), including but not limited to power amplification channel 1, power amplification channel 2,..., power amplification channel i,..., power amplification channel N, etc. The first power amplification channel can be called power amplification channel 1, and the second power amplification channel can be called power amplification channel 2, which will not be elaborated here. It can be understood that i can be any integer from 1 to N, and power amplification channel i is the i-th power amplification channel. The above first phase shift amount in the i-th of the above N power amplification channels can satisfy:

[0036]

[0037] where, is the above first phase shift amount, N is an integer greater than or equal to 3; i is an integer, and i = 1, 2, 3....N, is the first preset phase difference. Here, the first preset phase difference can be used as a preset value or a redundant value and added to the first phase shift amount. As a result, the phase range that the phase shifter can cover can be enriched, and it can be applied to more application scenarios. It can be a positive number or a negative number. The specific value can be determined according to the actual application scenario and is not limited here. It can be understood that the above formula is applicable to the case where N is an integer greater than or equal to 3, and i takes any integer from 1 to N. The value of i can be determined according to the channel number of the power amplification channel, and the value of N can be determined according to the actual application scenario and is not limited here. Please refer to Figure 2 again. In Figure 2 the balanced power amplifier synthesis circuit shown in i includes a power splitter, a synthesizer, and N power amplification channels. Among them, the input end of the power splitter can be used as the input end of the balanced power amplifier synthesis circuit, and the output end of the synthesizer can be used as the output end of the balanced power amplifier synthesis circuit. For the convenience of description, the above N power amplification channels can be exemplified by power amplification channel 1 to power amplification channel N. The value of i can be any integer from 1 to N. Any one of the above power amplification channels can be composed of a first phase shifter, a power amplifier PA, and a second phase shifter connected in series in sequence. Taking the i-th power amplification channel as an example, the first phase shifter i, the power amplifier PA i and the second phase shifter i are connected in series in sequence to form the power amplification channel i. Among them, the first phase shift amount applied by the first phase shifter i to the signal input to the first phase shifter i satisfies:

[0038]

[0039] Correspondingly, the first compensation phase shift amount applied by the second phase shifter i to the signal input to the second phase shifter i can be calculated. The first compensation phase shift amount in a power amplification channel can satisfy being the same in magnitude but opposite in phase to the first phase shift amount, or both being 0. It can be understood that the signals input to the first phase shifter and the second phase shifter can have the original phase. The phase of the signal output from the first phase shifter can be the superposition of the original phase of the signal and the first phase shift amount, and the phase of the signal output from the second phase shifter can be the superposition of the original phase of the signal and the first compensation phase shift amount. The corresponding relationship between the positive and negative of the phase shift amount and phase delay or advance is determined according to the actual application scenario and is not limited here. Since the first phase shift amount and the first compensation phase shift amount are the same in magnitude but opposite in phase, or both are 0, positive and negative phase shift cancellation can be achieved, that is, the second phase shifter can cancel the effect of the first phase shifter on the phase shift of the signal. For the convenience of description, in the following, the value will be described as 0.

[0040] Exemplarily, when N takes 3, please refer to Figure 3A again.Figure 3A is another structural schematic diagram of the balanced power amplifier combining circuit provided by the present application. In Figure 3A the shown balanced power amplifier combining circuit, it includes a one-to-three power divider, a three-in-one combiner, power amplification channel 1, power amplification channel 2, and power amplification channel 3. In power amplification channel 1, it includes a first phase shifter 1, a power amplifier PA1, and a second phase shifter 1. In power amplification channel 2, it includes a first phase shifter 2, a power amplifier PA2, and a second phase shifter 2. In power amplification channel 3, it includes a first phase shifter 3, a power amplifier PA3, and a second phase shifter 3. Among them, the input end of the one-to-three power divider can be used as the input end of the balanced power amplifier combining circuit, and the output end of the three-in-one combiner can be used as the output end of the balanced power amplifier combining circuit. Here, according to the above first phase shift amount calculation formula, the first phase shift amount in power amplification channel 1 can be calculated to be -60°, the first phase shift amount in power amplification channel 2 is 0°, and the first phase shift amount in power amplification channel 3 is +60°. Correspondingly, since the magnitudes of the first phase shift amount and the first compensation phase shift amount in the same channel are the same, the phases are opposite or both are 0, the first compensation phase shift amount in power amplification channel 1 is +60°, the first compensation phase shift amount in power amplification channel 2 is 0°, and the first compensation phase shift amount in power amplification channel 3 is -60°. It can be understood that the first phase shifter can be designed based on the calculated first phase shift amount, so that the first phase shifter can apply the first phase shift amount to the signal input to the first phase shifter. Similarly, the second phase shifter can be designed based on the first compensation phase shift amount, so that the second phase shifter can apply the first compensation phase shift amount to the signal input to the second phase shifter, such as Figure 3AAs shown in the figure, when the sub-signal is input to the power amplification channel 1, the phase of the sub-signal is first delayed by 60° by the first phase shifter 1 and then advanced by 60° by the second phase shifter 1; when the sub-signal is input to the power amplification channel 2, the phase of the sub-signal remains unchanged through the first phase shifter 2 and then remains unchanged through the second phase shifter 2; when the sub-signal is input to the power amplification channel 3, the phase of the sub-signal is first advanced by 60° by the first phase shifter 3 and then delayed by 60° by the second phase shifter 3. It can be understood that positive and negative phase shifts can be canceled out through the first and second phase shifters of each channel. Here, the phase difference between the sub-signals input to the power amplification channel 1, the power amplification channel 2, and the power amplification channel 3 by the one-to-three power divider is 0°. After passing through the first phase shifter 1, the first phase shifter 2, and the first phase shifter 3, the phase difference between the signals input to PA1, PA2, and PA3 is 60°. Since PA1, PA2, and PA3 can be the same power amplifier and the phase delays brought are the same, the phase difference between the signals output from PA1, PA2, and PA3 still remains 60°. Furthermore, after passing through the second phase shifter 1, the second phase shifter 2, and the second phase shifter 3, the phase difference between the signals output from the power amplification channel 1, the power amplification channel 2, and the power amplification channel 3 is 0°. Here, there may be a situation of impedance mismatch at the load at the output end of the balanced power amplifier synthesis circuit. For example, the load impedance does not match the characteristic impedance of the transmission line, etc., which can be determined according to the actual situation and is not limited here. The impedance mismatch at the output end load may cause the reflected signal to flow back into the amplifier. The reflected signal then flows into the synthesizer after being reflected by the amplifier and then into the output end of the balanced power amplifier synthesis circuit, which will interfere with and damage the system performance. Such as Figure 3AAs shown in the figure, it is assumed that the reflected signals formed after the signals output from the power amplifier 1, the power amplifier 2, and the power amplifier 3 to the synthesizer are reflected by the load at the output end of the synthesizer (not shown in the figure) are the reflected signal 1, the reflected signal 2, and the reflected signal 3 respectively. The reflection path of the reflected signal 1 is: load (not shown in the figure) -> three-in-one synthesizer -> 1 -> 2 -> PA1 -> 3 -> 4 -> three-in-one synthesizer. At this time, since the reflection path of the reflected signal 1 passes through the second phase shifter 1 twice, the second phase shifter 1 will apply the first compensation phase amount in the power amplification channel 1 (i.e., the aforementioned +60°) to the reflected signal 1 twice. It can be understood that the phase value of the reflected signal 1 finally reaching the three-in-one synthesizer after passing through the above reflection path should be +120°. The reflection path of the reflected signal 2 is: load (not shown in the figure) -> three-in-one synthesizer -> 5 -> 6 -> PA2 -> 7 -> 8 -> three-in-one synthesizer. At this time, since the reflection path of the reflected signal 2 passes through the second phase shifter 2 twice, the second phase shifter 2 will apply the first compensation phase amount in the power amplification channel 2 (i.e., the aforementioned 0°) to the reflected signal 2 twice. It can be understood that the phase value of the reflected signal 2 finally reaching the three-in-one synthesizer after passing through the above reflection path should be 0°. The reflection path of the reflected signal 3 is: load (not shown in the figure) -> three-in-one synthesizer -> 9 -> 10 -> PA3 -> 11 -> 12 -> three-in-one synthesizer. At this time, since the reflection path of the reflected signal 3 passes through the second phase shifter 3 twice, the second phase shifter 3 will apply the first compensation phase amount in the power amplification channel 3 (i.e., the aforementioned -60°) to the reflected signal 3 twice. It can be understood that the phase value of the reflected signal 3 finally reaching the three-in-one synthesizer after passing through the above reflection path should be -120°. Please refer to Figure 3B , Figure 3B which is a phasor schematic diagram of the three-way reflected signals provided by this application. As Figure 3B shown, when the amplitudes of the reflected signal 1, the reflected signal 2, and the reflected signal 3 are the same, since the phase of the reflected signal 1 is +120°, the phase of the reflected signal 2 is 0, and the phase of the reflected signal 3 is -120°, the three reflected signals are evenly distributed in phase and can form a closed vector loop, that is, the three reflected signals can be completely canceled when the amplitudes are the same. Please refer to Figure 3A again. As Figure 3A shown, the three-in-one synthesizer shown in the figure may include an isolation resistor (not shown in the figure) to cancel the above-mentioned reflected signal 1, reflected signal 2, and reflected signal 3. The connection method and component parameters of the isolation resistor in the three-in-one synthesizer can be determined according to the actual application scenario and are not limited here. It can be understood that the reflected signal 1, reflected signal 2, and reflected signal 3 can be mutually canceled by the isolation resistor on the three-in-one synthesizer, thereby eliminating the reflected signal, preventing the reflected signal from entering the output end, reducing the interference of the reflected signal to the system internal, and enhancing the overall stability of the system.

[0041] In the embodiments of the present application, through multiple power amplification channels each composed of two phase shifters and a power amplifier, and in cooperation with a power divider and a synthesizer, power amplification and synthesis of signals can be achieved. The power divider can provide sub-signals with equal amplitude and in-phase as inputs for each power amplification channel. In each power amplification channel, a first phase shift amount and a first compensation phase shift amount can be calculated based on the channel number, and then the first phase shifter and the second phase shifter can be designed. Based on the first phase shift amount and the first compensation phase shift amount that are the same in magnitude and opposite in phase, the positive and negative phases of the signals within each power amplification channel can be cancelled out, such that there is no phase difference between the modulated phase signals input to the synthesizer. At the same time, since there is a phase shift amount difference of 180 / N between the second phase shifters of any two adjacent channels, the reflected signals at the output end can be cancelled out with each other through the phase shift of the second phase shifter and then through the synthesizer, preventing the reflected signals from entering the output end, reducing the interference of the reflected signals on the internal part of the system, and enhancing the overall stability of the system.

[0042] In some feasible embodiments, the above-mentioned first phase shift amount is a negative phase, the above-mentioned first phase shifter is one of a low-pass filter, a cable, and a PCB trace, the above-mentioned first compensation phase shift amount is a positive phase, and the above-mentioned second phase shifter is a high-pass filter. Here, the low-pass filter and the high-pass filter can be composed of capacitors (C) and inductors (L) with different device parameters connected in series and parallel. It can be understood that since the high-pass positive-phase filter has relatively stable phase characteristics, by introducing the high-pass positive-phase filter, the slope difference of the phase with respect to frequency can be effectively reduced, and the phase-frequency responses of the phase shifters between channels can be made closer, reducing the slope or gradient difference of the phase with respect to frequency, such that in a wider frequency range, the combined phase difference of the output signals of each channel is close to 0, and the balanced power amplifier synthesis circuit can have a wider operating bandwidth.

[0043] Optionally, in some feasible embodiments, the above-mentioned first phase shifter and the above-mentioned second phase shifter are composed of capacitors and inductors connected in series and parallel, and the device parameters of the above-mentioned capacitors and the above-mentioned inductors are obtained from the above-mentioned first phase shift amount and the above-mentioned first compensation phase shift amount. Here, the selection of the capacitors includes but is not limited to ceramic capacitors, electrolytic capacitors, thin-film capacitors, tantalum capacitors, etc., and the selection of the inductors includes but is not limited to wound inductors, ceramic-core inductors, ferrite-core inductors, air-core inductors, planar inductors, etc., which can be specifically determined according to the actual application scenario and are not limited herein.

[0044] Exemplarily, please refer to Figure 4A and Figure 4B , Figure 4A which is a schematic structural diagram of a phase shifter in the balanced power amplifier synthesis provided by the present application, Figure 4B andFigure 4A The phase shifter shown may include an inductor L1, capacitors C1 and C2 connected in series and parallel. In Figure 4B the phase shifter shown may include an inductor L2, capacitors C3 and C4 connected in series and parallel. Here, the selection and values of the inductor L1, capacitor C1, capacitor C2, inductor L2, capacitor C3 and capacitor C4 can all be determined according to the actual application scenario and are not limited here. Assuming to achieve signal phase adjustment with a phase shift of -45°, in the phase shifter as Figure 4A shown, both ends of the inductor L1 are grounded via the capacitor C1 and the capacitor C2. The capacitor C1 is connected between the input side of the inductor L1 (i.e., the input end of the phase shifter) and the ground, and the inductor C2 is connected between the output side of the inductor L1 (i.e., the output end of the phase shifter) and the ground. Assuming the signal frequency of the test signal input to the phase shifter is 13.56 megahertz (MHz), at this time, the inductance value of the inductor L1 can be 413 nanohenries (nH), and the capacitance values of the capacitors C1 and C2 can be 98 picofarads (pF). When this phase shifter works, it can achieve a phase shift of -45° for the input signal, that is, a phase shift of -45° can be applied to the input signal; assuming to achieve signal phase adjustment with a phase shift of +45°, in the phase shifter as Figure 4B shown, the capacitors C3 and C4 are in series. One end of the inductor L2 is connected to the series connection point of the capacitors C3 and C4, and the other end is grounded. The inductance value of the inductor L2 can be 845 nH, and the capacitance values of the capacitors C3 and C4 can be 555 pF. When this phase shifter works, it can achieve a phase shift of 45° for the input signal, that is, a phase shift of +45° can be applied to the input signal. Therefore, with the above parameter settings of the capacitors and inductors, the two phase shifters as Figure 4A and Figure 4B shown can be used in the balanced power amplifier synthesis circuit as Figure 4A shown to achieve the balanced power amplifier synthesis of two signals.

[0045] It can be understood that the device parameters of the above capacitors and the above inductors are obtained from the above first phase shift. By changing the device parameters of the capacitors and inductors, different phase adjustment effects can be achieved. When the signal frequency of the test signal input to the phase shifter is 13.56 MHz, assuming to achieve signal phase adjustment with a phase shift of -60°, in the phase shifter as Figure 4A shown, the inductance value of the inductor L1 can be 510 nH, and the capacitance values of the capacitors C1 and C2 can be 140 pF. When this phase shifter works, it can achieve a phase shift of -60° for the input signal; assuming to achieve signal phase adjustment with a phase shift of +60°, in the phase shifter as Figure 4BIn the phase shifter shown, the inductance value of inductor L1 can be 845 nH, and the capacitance values of capacitors C1 and C2 can be 555 pF. When the phase shifter operates, it can shift the phase of the input signal by 60°. Assume that at this time, to implement a balanced power amplifier combining circuit as shown in Figure 3A , a phase shifter with a phase shift of 0° needs to be introduced. It can be understood that a phase shifter with a phase shift of 0° can be a zero-phase band-pass filter or a circuit path without any components connected. It can be determined specifically according to the actual application scenario and is not limited here. Exemplarily, taking a phase shifter with a phase shift of 0° composed of series and parallel capacitors and inductors as an example, please refer to Figure 5 . Figure 5 is another schematic diagram of the structure of the phase shifter in the balanced power amplifier combination provided by this application. In Figure 5 , the phase shifter shown may include inductors L3, L4, capacitors C5 and C6 connected in series and parallel. Capacitor C5 is in series with inductor L3, and inductors L4 and capacitor C6 are respectively connected in parallel between the output terminal and the ground. Assume that when the signal frequency of the test signal input to the phase shifter is 13.56 MHz, the inductance value of inductor L3 can be 280 nH, the inductance value of inductor L4 can be 840 nH, the capacitance value of capacitor C5 can be 500 pF, and the capacitance value of capacitor C6 can be 165 pF. When the phase shifter operates, it can shift the phase of the input signal by 0°. Therefore, with the above parameter settings of the capacitor and inductor, the two phase shifters shown in Figure 4A and Figure 4B and the phase shifter shown in Figure 5 can be used in the balanced power amplifier combination circuit shown in Figure 3A to achieve the balanced power amplifier combination of three signals. In the embodiments of this application, based on the phase shifter composed of series and parallel inductors and capacitors, by adjusting the device parameters of the inductors and capacitors, the phase of the signal input to the phase shifter can be adjusted, so that the positive and negative phase shifts of the signals at both ends of the power amplifier are cancelled out, and thus there is no phase difference between the signals input to the synthesizer, and further the balanced power amplifier combination with the maximum output power is achieved.

[0046] Optionally, in some feasible embodiments, the above first phase shift amount is a negative phase, the above first phase shifter can be one of a low-pass negative-phase filter, a cable, and a PCB trace, and the above second phase shifter can be a high-pass positive-phase filter. Here, the low-pass negative-phase filter and the high-pass positive-phase filter can be implemented by an LC circuit composed of capacitors and resistors. For specific device parameters, reference can be made to the foregoing embodiments and will not be elaborated here. The above cable can be a copper cable, an optical fiber cable, a coaxial cable, etc., and the above PCB trace can be a copper trace, a microstrip line, a stripline, a controlled-impedance trace, etc. By adjusting the physical length and material properties of the cable or adjusting the length and layout of the PCB trace, etc., the required phase shift can be achieved, which can be specifically determined according to the actual application scenario and is not limited here. Since one of the above low-pass filter, cable, or PCB trace can achieve negative-phase phase shift as a phase shifter, and using a high-pass filter as a phase shifter can achieve positive-phase phase shift, the two can be combined to achieve positive and negative phase shifts. For example, please refer to Figure 6 , Figure 6 is another structural schematic diagram of the balanced power amplifier synthesis circuit provided by the present application. In Figure 6The shown balanced power amplifier combining circuit includes a one-to-three power divider, a three-in-one combiner, power amplification channel 1, power amplification channel 2, and power amplification channel 3. Power amplification channel 1 includes a first phase shifter 1, a power amplifier PA1, and a second phase shifter 1. Power amplification channel 2 includes a first phase shifter 2, a power amplifier PA2, and a second phase shifter 2. Power amplification channel 3 includes a first phase shifter 3, a power amplifier PA3, and a second phase shifter 3. Here, according to the above first phase shift amount calculation formula, the first phase shift amount in power amplification channel 1 can be calculated to be -60°, and correspondingly, the first compensation phase shift amount in power amplification channel 1 is +60°. It can be understood that since the first phase shift amount in power amplification channel 1 is a negative phase (i.e., the above -60°), the first phase shifter 1 can be designed based on the calculated first phase shift amount. The first phase shifter 1 can be one of a low-pass negative phase filter, a cable, and a PCB trace, so that the first phase shifter 1 can apply a phase shift amount of -60° to the signal input to the first phase shifter 1. The second phase shifter 1 can be selected as a high-pass filter, which can achieve applying a phase shift amount of +60° to the signal input to the second phase shifter 1. The phase shift amounts of the first phase shifter 1 and the second phase shifter 1 in power amplification channel 1 can cancel each other out positively and negatively, meeting the design requirements of the power amplification channel. In the embodiment of the present application, when the first phase shift amount is a negative phase, the first phase shifter can be selected from one of a low-pass filter, a cable, and a PCB trace to apply a negative-phase first phase shift amount to the input signal. Correspondingly, the second phase shifter on the other side within the same power amplification channel can be selected as a high-pass positive-phase filter to apply a positive-phase first phase shift amount to the input signal. In the power amplification channel, the introduction of the high-pass positive-phase filter can make the phase frequency responses of the phase shifters between channels closer, that is, the slopes or gradients of the phases generated by the phase shifters with frequency changes are close, so that in a wider frequency range, the combined phase difference of the output signals of each channel is close to 0, and the balanced power amplifier combining circuit can have a wider operating bandwidth.

[0047] In some feasible embodiments, the above-mentioned first phase shift amount is a positive phase, the above-mentioned first phase shifter is a high-pass filter, the above-mentioned first compensation phase shift amount is a negative phase, and the above-mentioned second phase shifter is one of a low-pass filter, a cable, and a PCB trace. Here, the above-mentioned low-pass negative-phase filter and high-pass positive-phase filter can be implemented by an LC circuit composed of a capacitor and a resistor. The above-mentioned cable can be a copper cable, an optical fiber cable, a coaxial cable, etc. The above-mentioned PCB trace can be a copper trace, a microstrip line, a stripline, a controlled-impedance trace, etc. By adjusting the physical length and material properties of the cable or adjusting the length and layout of the PCB trace, etc., specific details can be referred to the foregoing embodiments and will not be elaborated here. It can be understood that since the high-pass positive-phase filter has relatively stable phase characteristics, introducing the high-pass positive-phase filter can effectively reduce the slope difference of the phase change with frequency, and can effectively make the phase-frequency responses of the phase shifters between channels closer, reduce the slope or gradient difference of the phase change with frequency, so that within a wider frequency range, the combined phase difference of the output signals of each channel is close to 0, and the balanced power amplifier synthesis circuit can have a wider operating bandwidth. For example, reference can be made to Figure 6 the power amplification channel 3 shown in Figure 6 . The power amplification channel 3 includes a first phase shifter 3, a power amplifier PA3, and a second phase shifter 3. Here, according to the above-mentioned first phase shift amount calculation formula, the first phase shift amount in the power amplification channel 3 can be calculated to be +60°, and correspondingly, the first compensation phase shift amount in the power amplification channel 3 is -60°. It can be understood that since the first phase shift amount in the power amplification channel 3 is a positive phase (i.e., the above-mentioned +60°), the first phase shifter 3 can be designed based on the calculated first phase shift amount. The first phase shifter 3 can be selected as a high-pass filter, so that the first phase shifter 3 can apply a phase shift amount of +60° to the signal input to the first phase shifter 3. The second phase shifter 3 can be one of a low-pass negative-phase filter, a cable, and a PCB trace, and can apply a phase shift amount of -60° to the signal input to the second phase shifter 3. The phase shift amounts of the first phase shifter 3 and the second phase shifter 3 in the power amplification channel 3 can cancel each other out positively and negatively, meeting the design requirements of the power amplification channel. For the specific selection and parameters of the phase shifter, reference can be made to the foregoing embodiments and will not be elaborated here. In the embodiments of the present application, the first phase shifter can be selected as a high-pass positive-phase filter to apply a positive-phase first phase shift amount to the input signal. Correspondingly, the second phase shifter on the other side within the same power amplification channel can be selected as one of a low-pass filter, a cable, and a PCB trace to apply a negative-phase first compensation phase shift amount to the amplified signal, which can realize the design of two phase shifters with positive and negative phase inversion inside the power amplification channel, improve the flexibility of device selection, enrich the optional schemes of circuit design, improve the flexibility of circuit design. At the same time, the introduction of the high-pass positive filter can enable the balanced power amplifier synthesis circuit to have a wider operating bandwidth.

[0048] In some feasible embodiments, both the above-mentioned first phase shift amount and the above-mentioned first compensation phase shift amount are zero, and at least one of the above-mentioned first phase shifter and the above-mentioned second phase shifter is a band-pass filter. It can be understood that a phase shifter with a phase shift of 0° can be a band-pass filter or a circuit path without any components connected. Since the band-pass zero-phase filter combines the frequency selectivity of the band-pass filter and the phase compensation ability of the zero-phase filter, it can select signals within a specific frequency range and also eliminate phase delay, making the phase-frequency responses of each channel closer, that is, the slope or gradient of the phase generated by the phase shifter with respect to frequency is more consistent, so that within a wider frequency range, the combined phase difference of the output signals of each channel is close to zero, and the balanced power amplifier combining circuit has a wider operating bandwidth. Therefore, when both the first phase shift amount and the first compensation phase shift amount are 0, at least one of the first phase shifter and the second phase shifter can be selected as a band-pass filter. That is to say, both the first phase shifter and the second phase shifter can be selected as band-pass filters, or one can be selected as a band-pass filter and the other can be a circuit path without any components connected, which can be specifically determined according to the actual application scenario and is not limited here. For example, reference can be made to Figure 6 the power amplification channel 2 shown in. The power amplification channel 2 includes a first phase shifter 2, a power amplifier PA2, and a second phase shifter 2. Here, according to the above-mentioned first phase shift amount calculation formula, it can be calculated that the first phase shift amount in the power amplification channel 2 is 0°, and correspondingly, the first compensation phase shift amount in the power amplification channel 2 is 0°. It can be understood that since both the first phase shift amount and the first compensation phase shift amount in the power amplification channel 2 are 0, both the first phase shifter 2 and the second phase shifter 2 can be selected as band-pass filters 1 to meet the design requirements of the power amplification channel. For the specific selection and parameters of the phase shifter, reference can be made to the foregoing embodiments and will not be elaborated here. In the embodiments of the present application, both the first phase shift amount and the first compensation phase shift amount can be zero, which can reduce phase distortion and optimize the frequency response of the circuit. In each power amplification channel, at least one of the first phase shifter and the second phase shifter can be selected as a band-pass zero-phase filter. By using the band-pass zero-phase filter, the phase-frequency responses of the phase shifters between channels can be made closer, that is, the slope or gradient of the phase generated by the phase shifter with respect to frequency is close, so that within a wider frequency range, the combined phase difference of the output signals of each channel is close to zero, and the balanced power amplifier combining circuit has a wider operating bandwidth.

[0049] In some feasible embodiments, the first phase shifter is used to transform the output impedance of the power divider to a target input impedance, and the target input impedance is conjugate-matched with the input impedance of the power amplifier; the second phase shifter is used to transform the output impedance of the power amplifier to a target output impedance, and the target output impedance is conjugate-matched with the input impedance of the synthesizer. Here, the first phase shifter and the second phase shifter can participate in impedance adjustment to ensure impedance matching between the input, transmission channels, and output, reduce the interference caused by the backflow of reflected signals when impedance mismatch occurs, reduce the interference of reflected signals to the inside of the system, and enhance the overall stability of the system. It can be understood that an inductor has inductive reactance, which impedes high-frequency signals, while a capacitor has capacitive reactance, which has a smaller impedance to high-frequency signals. The first phase shifter and the second phase shifter can participate in impedance matching by adjusting the internal inductor and capacitor connection methods and device parameters. In the embodiments of the present application, the first phase shifter and the second phase shifter can participate in impedance adjustment, appropriately match the impedance between the output impedance of the power divider and the input impedance of the power amplifier, and between the output impedance of the power amplifier and the input impedance of the synthesizer, thereby improving the circuit's ability to resist load mismatch, achieving maximum power transmission, reducing the interference of signal reflection to the inside of the system, and enhancing the overall stability of the system.

[0050] In some feasible embodiments, the power divider includes a first power divider and at least two second power dividers. The input end of the first power divider serves as the first input end of the power divider. The first power divider includes at least two output ends. One output end of the first power divider is connected to the input end of one of the second power dividers. At least four output ends of the at least two second power dividers all serve as the first output end of the power divider; the first power divider is used to divide the input signal received at the input end of the first power divider into at least two second sub-signals with equal amplitude and in-phase, and output them to the corresponding second power dividers through the output ends of the first power divider respectively; the second power divider is used to divide the second sub-signal received at the input end of the second power divider into at least two first sub-signals, and output them to the corresponding power amplification channels through the output ends of each second power divider respectively. For example, please refer to Figure 7 , Figure 7 is another structural schematic diagram of the balanced power amplifier synthesis circuit provided by the present application. In Figure 7The balanced power amplifier synthesis circuit shown includes a one-to-two power divider, two one-to-three power dividers, six power amplification channels, and a six-in-one synthesizer. The one-to-two power divider, as the first power divider, can output two signals to the two one-to-three power dividers. The two one-to-three power dividers, as the second power dividers, can output a total of six signals to the six power amplification channels, and then they are combined into one output signal by the six-in-one synthesizer. Here, the six power amplification channels include power amplification channel 1, power amplification channel 2,..., power amplification channel 6. At this time, the first phase shift amount and the first compensation phase shift amount in each power amplification channel can be calculated. Taking power amplification channel 1 as an example, the first phase shift amount in power amplification channel 1 is calculated to be -75°. Then, the first phase shifter 1 can apply a phase shift amount of -75° to the input signal, and correspondingly, the second phase shifter 1 can apply a compensation phase shift amount of +75° to the input signal. Here, the specific parameter design or component selection of the first phase shifter and the second phase shifter in each path can refer to the foregoing embodiments, which will not be elaborated here. There is no phase difference between the 6 signals output from power amplification channel 1 to power amplification channel 6, and they are output as a combined signal through the six-in-one synthesizer. In the embodiment of the present application, the signal splitting function of the power divider can be realized by cascading power dividers, which improves the flexibility of component selection, has a simple circuit structure, and can achieve circuit miniaturization.

[0051] In some feasible embodiments, the above-mentioned synthesizer includes a first synthesizer and at least two second synthesizers. The output end of the first synthesizer serves as the second output end of the synthesizer. The first synthesizer includes at least two input ends. One input end of the first synthesizer is connected to the output end of one of the second synthesizers. The second synthesizer includes at least two input ends, and one input end is connected to one of the power amplification channels. At least four input ends of the at least two second synthesizers serve as the second input ends of the synthesizer. The second synthesizer is used to combine the phase-modulated signals received by each input end of the second synthesizer into a second combined signal and output the second combined signal from the output end of the second synthesizer. The first synthesizer is used to combine the second combined signals received by each input end of the first synthesizer into the first combined signal and output the first combined signal from the output end of the first synthesizer. For example, please refer to Figure 8 , Figure 8 which is another schematic structural diagram of the balanced power amplifier synthesis circuit provided by the present application. In Figure 8The shown balanced power amplifier combining circuit includes a one-to-six-way power divider, two three-in-one combiners, six power amplification channels, and a two-in-one combiner. The one-to-six-way power divider can output six signals to the six power amplification channels. The two three-in-one combiners, as the second combiners, can output two signals to the two-in-one combiner, and then be combined into one output signal by the two-in-one combiner. Here, the six power amplification channels include power amplification channel 1, power amplification channel 2, …, power amplification channel 6. At this time, the first phase shift amount and the first compensation phase shift amount in each power amplification channel can be calculated. Taking power amplification channel 1 as an example, if the first phase shift amount in power amplification channel 1 is calculated to be -75°, then the first phase shifter 1 can apply a phase shift amount of -75° to the input signal, and correspondingly, the second phase shifter 1 can apply a compensation phase shift amount of +75° to the input signal. Here, the specific parameter design or component selection of the first phase shifter and the second phase shifter in each path can refer to the foregoing embodiments, which will not be elaborated here. There is no phase difference between the six signals output from power amplification channel 1 to power amplification channel 6. After passing through the three-in-one combiner, two signals are output. At this time, there is no phase difference between these two signals, and then a combined signal is output through the two-in-one combiner. In the embodiment of the present application, the cascaded circuit has a better output port reflection coefficient. In the first-stage combination, the reflected power caused by non-ideal factors can be dissipated on the isolation resistor of the next-stage combiner, reducing the interference of the reflected signal to the inside of the system and enhancing the overall stability of the system.

[0052] In some feasible embodiments, the above-mentioned N power amplification channels include at least two groups of power amplification channels; the above-mentioned first phase shifter is used to apply a first phase shift amount associated with the channel serial number in each group to the received above-mentioned first sub-signal; the above-mentioned power splitter includes a first power splitter and at least two second power splitters. The input end of the first power splitter serves as the above-mentioned first input end of the power splitter. The first power splitter includes at least two output ends, and one output end is connected to the input end of one of the above-mentioned second power splitters through a third phase shifter. At least two output ends of the at least two second power splitters serve as the above-mentioned first output end of the power splitter and are connected to the above-mentioned at least two groups of power amplification channels. The input ends of at least two of the above-mentioned power amplification channels in the same group are connected to the same above-mentioned second power splitter; the first power splitter is used to divide the above-mentioned input signal received at the input end of the first power splitter into at least two second sub-signals with equal amplitude and the same phase, and output them to the corresponding above-mentioned second power splitters through the output ends of the first power splitter respectively; the second power splitter is used to divide the above-mentioned second sub-signal received at the input end of the second power splitter into at least two of the above-mentioned first sub-signals, and output them to the corresponding above-mentioned power amplification channels through the output ends of each of the second power splitters respectively; the above-mentioned synthesizer includes a first synthesizer and at least two second synthesizers. The output end of the first synthesizer serves as the above-mentioned second output end of the synthesizer. The first synthesizer includes at least two input ends, and one input end is connected to the output end of one of the above-mentioned second synthesizers through a fourth phase shifter. At least two input ends of one of the above-mentioned second synthesizers are connected to at least two of the above-mentioned power amplification channels. The output ends of at least two of the above-mentioned power amplification channels in the same group are connected to the same above-mentioned second synthesizer; the second synthesizer is used to synthesize the above-mentioned phase-modulated signals received at each input end of the second synthesizer into a second synthesized signal, and output the second synthesized signal from the output end of the second synthesizer; the first synthesizer is used to synthesize the above-mentioned second synthesized signals received at each input end of the first synthesizer into the above-mentioned first synthesized signal, and output the first synthesized signal from the output end of the first synthesizer; the above-mentioned third phase shifter is used to apply a second phase shift amount associated with the channel group serial number connected to the received above-mentioned second sub-signal; the above-mentioned fourth phase shifter is used to apply a second compensation phase shift amount to the above-mentioned second synthesized signal synthesized by the above-mentioned second synthesizer, so that the synthesized phase difference between the signals output to the first synthesizer through each of the above-mentioned fourth phase shifters is 0. Here, the signals input to the third phase shifter and the fourth phase shifter can have the original phase. The phase of the signal output by the third phase shifter can be the superposition of the original phase of the signal and the second phase shift amount. The phase of the signal output by the fourth phase shifter can be the superposition of the original phase of the signal and the second compensation phase shift amount. The corresponding relationship between the positive and negative of the phase shift amount and the phase delay or advance is determined according to the actual application scenario and is not limited here.Since the magnitudes of the second phase shift amount and the second compensation phase shift amount are the same and the phases are opposite, or both are 0, positive and negative phase shifts can be cancelled out, that is, the fourth phase shifter can cancel out the effect of the third phase shifter on the signal phase shift. It can be understood that the second phase shift amount is calculated based on the channel group number to which the third phase shifter is connected. The third phase shifter can apply the calculated second phase shift amount to the signal input to the third phase shifter. The second compensation phase shift amount can be used to compensate for the second phase shift amount. That is to say, the second compensation phase shift amount has the same magnitude as the second phase shift amount and the opposite phase, or both the second phase shift amount and the second compensation phase shift amount are 0. The fourth phase shifter can apply the above-mentioned second supplementary phase shift amount to the signal input to the fourth phase shifter. Here, when designing the phases of the third phase shifter and the fourth phase shifter based on the second phase shift amount and the second compensation phase shift amount, the third phase shifter and the fourth phase shifter can be designed using, including but not limited to, filters, cables, PCB traces, etc. Specific device parameters, device selection, etc. can refer to the design of the aforementioned first phase shifter and second phase shifter, which will not be elaborated here. In the embodiments of the present application, cascaded power dividers and cascaded combiners can improve the flexibility of device selection, enrich the optional solutions for circuit design, and improve the flexibility of circuit design. By connecting the third phase shifter between two levels of power dividers and connecting the fourth phase shifter between two levels of combiners, and the fourth phase shifter is used to compensate for the phase shift amount provided by the third phase shifter, the combined phase difference between the signals output to the first combiner can be made 0 to obtain the signal synthesis output with the maximum power. At the same time, the cascaded circuit has a better output port reflection coefficient, and the reflected power caused by non-ideal factors in the first-level synthesis can be dissipated on the isolation resistor of the next-level combiner, thereby reducing the interference of the reflected signal to the inside of the system and enhancing the overall stability of the system.

[0053] In some feasible implementation manners, the above at least two groups of power amplification channels are K groups of power amplification channels; wherein, the second phase shift amount applied by the third phase shifter connected to the t-th group of the above K groups of power amplification channels satisfies:

[0054]

[0055] Wherein, For the above-mentioned second phase shift amount, K is an integer greater than or equal to 2; t is an integer, and t = 1, 2, 3....K, and Δμ is the second preset phase difference. Here, the second preset phase difference Δμ can be supplemented as a preset value or a redundant value to the second phase shift amount, thereby enriching the phase range that the phase shifter can adjust and cover, and can be applicable to more application scenarios. Δμ can be a positive number or a negative number, and the specific value of Δμ can be determined according to the actual application scenario and is not limited herein. For ease of understanding, the case where Δμ is 0 will be described hereinafter. It can be understood that the above formula is applicable to the case where K takes an integer greater than or equal to 2, and t takes any integer from 1 to K. The value of i can be determined according to the channel group number to which the third phase shifter is connected, and the value of K can be determined according to the actual application scenario and is not limited herein.

[0056] Exemplarily, for ease of description, a balanced power amplifier combining circuit including two groups of power amplification channels will be taken as an example for illustration. It is assumed that each group has three power amplification channels. Refer to Figure 9 , Figure 9 which is another structural schematic diagram of the balanced power amplifier combining circuit provided by the present application. In Figure 9 the shown balanced power amplifier combining circuit, it includes a one-to-two power divider, two one-to-three power dividers, six power amplification channels, a third phase shifter 1, a third phase shifter 2, a fourth phase shifter 1, a fourth phase shifter 2, two three-in-one combiners, and a two-in-one combiner. The one-to-two power divider can output two signals and input them to the two one-to-three power dividers through the third phase shifter 1 and the third phase shifter 2 respectively. Here, the six power amplification channels can be divided into two groups, that is to say, one group of power amplification channels includes three power amplification channels, and the power amplification channels in the same group are connected to a three-in-one combiner. The power amplification channels include a first phase shifter, a power amplifier, and a second phase shifter connected in sequence. Here, the first phase shift amount applied by the first phase shifter to the input signal is related to the channel number in each group. For ease of understanding, as shown in Figure 9 in which the six power amplification channels are divided into two groups, and each group of power amplification channels includes a power amplification channel 1, a power amplification channel 2, and a power amplification channel 3. The power amplification channels with the same channel number between different groups may have different structures, which can be specifically determined according to the actual application scenario and are not limited herein. The two three-in-one combiners, as the second combiners, can output two signals to the two-in-one combiner through the fourth phase shifter 1 and the fourth phase shifter 2 respectively, and then are combined into a combined signal and output after passing through the two-in-one combiner. It can be understood that in Figure 9The balanced power amplifier synthesis circuit shown adopts a three-way cascaded two-way structure, and realizes the amplification and synthesis of the circuit through a two-stage circuit structure. The first-stage circuit includes two groups of power amplification channels. Each group of power amplification channels divides the circuit into three paths through a one-to-three power divider. The first phase shift amounts in the three power amplification channels are -60°, 0°, and 60° respectively. Thus, the circuit structures of the first phase shifter and the second phase shifter in each power amplification channel can be designed. It can be understood that in the above power amplification channels, there is a 60° phase difference between the three signals output by the first phase shifter 1, the first phase shifter 2, and the first phase shifter 3, and there is also a 60° phase difference between the three signals output by the first phase shifter 4, the first phase shifter 5, and the first phase shifter 6. However, there is no phase difference between the three signals output by the second phase shifter 1, the second phase shifter 2, and the second phase shifter 3, and there is no phase difference between the three signals output by the second phase shifter 4, the second phase shifter 5, and the second phase shifter 6. In the second-stage circuit, one signal is divided into two signals, and the second phase shift amounts obtained by calculation are -45° and 45° respectively. Thus, the circuit structures of the third phase shifter 1, the third phase shifter 2, the fourth phase shifter 1, and the fourth phase shifter 2 can be designed. It can be understood that there is a 90° phase difference between the two signals output by the third phase shifter 1 and the third phase shifter 2, and there is no phase difference between the two signals output by the fourth phase shifter 1 and the fourth phase shifter 2.

[0057] In the embodiment of the present application, the second phase shift amount applied to the corresponding third phase shifter can be calculated through the above formula based on the group serial number of the power amplification channel connected to the third phase shifter, and then the second compensation phase shift amount used to compensate the second phase shift amount applied to the fourth phase shifter can be obtained, so as to realize the cancellation of positive and negative phase shifts, which can make the phase difference between the signals input to the first synthesizer be 0, and further realize the signal synthesis with the maximum power. At the same time, by calculating the second phase shift amount and the second compensation phase shift amount, the device parameters and circuit composition of the third phase shifter and the fourth phase shifter can be determined. The circuit design is simple and has strong applicability.

[0058] See Figure 10 , Figure 10 is a schematic structural diagram of the radio frequency power supply provided by the present application. The embodiment of the present application also provides a radio frequency power supply. The above radio frequency circuit includes a signal generation unit and the balanced power amplifier synthesis circuit provided in the above embodiment. As Figure 10As shown, the radio frequency circuit includes a signal generation unit and a balanced power amplifier synthesis circuit. The signal generation unit can serve as the signal input device for the balanced power amplifier synthesis circuit. The signals input into the balanced power amplifier synthesis circuit by the signal generation unit can be various signal sources such as electrical signals and radio frequency signals, which can be specifically determined according to the actual application scenario and are not limited here. Optionally, a power supply unit (not shown in the figure) can also be integrated in the above radio frequency circuit. The power supply unit can provide a stable power input for the power amplifier in the balanced power amplifier synthesis circuit to ensure the reliability of the circuit. Here, the power supply unit includes but is not limited to a battery pack, an uninterruptible power supply (UPS), a DC power module, etc., which are specifically determined according to the actual application scenario and are not limited here. The balanced power amplifier synthesis circuit can be Figures 1 to 9 any of the balanced power amplifier synthesis circuits shown. For the circuit structure and implementation method of the balanced power amplifier synthesis circuit, reference can be made to the above Figures 1 to 9 provided circuit structure and implementation method, which will not be elaborated here. As Figure 10 shown, the balanced power amplifier synthesis circuit can divide the signal output by the signal generation unit into multiple paths of signals, amplify them, and then synthesize them into one path of output signal to increase the output power. Here, a thermal management module (not shown in the figure) can also be integrated in the balanced power amplifier synthesis circuit to increase the heat loss of the circuit, so that a large amount of heat generated by devices such as power amplifiers during the operation of the circuit can be released, thereby maintaining the performance of the devices and the reliability of the circuit operation. The thermal management module can include but is not limited to heat sinks, fans, or liquid cooling systems, etc., which can be specifically determined according to the actual application scenario and are not limited here.

[0059] In the embodiments of the present application, based on the collaborative work of the signal generation and amplification unit and the balanced power amplifier synthesis circuit, the synthesis efficiency of the signal power can be improved, the output signal quality of the radio frequency power supply can be improved, the total output power of the radio frequency power supply can be significantly increased, the energy loss can be reduced, the system structure is simple, and the applicability is strong.

[0060] See Figure 11 , Figure 11 which is the structural schematic diagram of the electronic device provided by the present application. Embodiments of the present application also provide an electronic device. As Figure 11 shown, the electronic device 1000 can include a radio frequency power supply 1001, a processor 1002, a memory 1003, an input / output device 1004, a communication module 1005, and other necessary electronic components (not shown in the figure) and an interface 1006. In addition, at least one communication bus 1007 can also be included in the above electronic device 1000. The communication bus 1007 can be used to realize the connection and communication between these components. The radio frequency power supply 1001 described in this embodiment can be the above Figure 10The RF power supply provided in the illustrated embodiment. The input / output device 1004 may include a display, a keyboard, a touch screen, etc. The communication module 1005 may optionally include Wi-Fi, Bluetooth, NFC, etc. The interface 1006 may optionally include a standard wired interface, a wireless interface. The memory 1003 includes a random access memory (RAM) and a non-volatile memory (NVM), such as an erasable programmable read-only memory (EPROM). The memory 1003 may optionally also be at least one storage device located away from the aforementioned processor 1002. As Figure 11 shown, the memory 1003, as a computer-readable storage medium, may include an operating system, a network communication module, a user interface module, and a device control application program. In this embodiment, the memory 1003 is used to store program codes. As Figure 11 shown, the RF power supply 1001, as a core component, incorporates a signal generation unit (not shown in the figure) and a balanced power amplifier synthesis circuit (not shown in the figure) provided according to any one of the Figures 1 to 9 illustrated embodiments, which is responsible for generating RF signals and amplifying these signals efficiently and stably to ensure balanced output of the signals. When the electronic device 1000 is started, the processor 1002 loads necessary programs and configurations, and the RF power supply 1001 starts to work. The signal generation unit generates RF signals with specific frequencies and amplitudes under the control of the processor 1002, and after being amplified by the balanced power amplifier synthesis circuit, they are output to the output terminal. The electronic device may be one of a communication device (such as a smart phone, a tablet computer, a wireless router, etc.), a wireless broadcast and television device, a medical device (such as a radiofrequency ablation instrument, a nuclear magnetic resonance imaging device, etc.), and an industrial and scientific research device (such as in the fields of radio frequency identification, material heating, plasma generation, etc.).

[0061] In the embodiment of the present application, due to the phase shift amount difference of 180 / N between any two adjacent channels of the second phase shifters in the balanced power amplifier synthesis circuit, the reflected signals generated by the balanced power amplifier synthesis circuit are shifted in phase by the second phase shifters and cancel each other out at the synthesizer of the balanced power amplifier synthesis circuit, preventing the reflected signals from entering the output terminal of the balanced power amplifier synthesis circuit, reducing the interference caused by the reflected signals to the electronic device, and enhancing the overall stability of the electronic device.

Claims

1. A balanced power amplifier synthesis circuit, characterized in that Comprising: A power divider, N power amplification channels, and a synthesizer; The power divider includes a first input terminal and N first output terminals, and the N first output terminals correspond to the N power amplification channels one by one; the power divider is configured to divide an input signal received at the first input terminal into N first sub-signals with equal amplitude and in-phase, and output the first sub-signals to the corresponding power amplification channels through the respective first output terminals; Each of the N power amplification channels includes a first phase shifter, a power amplifier, and a second phase shifter connected in sequence. The first phase shifter is configured to apply a first phase shift amount associated with the channel number to the received first sub-signal; The second phase shifter is configured to apply a first compensation phase shift amount to the signal amplified by the power amplifier, so that the combined phase difference between the signals output from the respective power amplification channels to the synthesizer is 0; The synthesizer includes N second input terminals and a second output terminal. The synthesizer is configured to combine the phase-modulated signals received at the respective second input terminals into a first combined signal, and output the first combined signal from the second output terminal; Wherein, the first phase shift amount in the i-th power amplification channel among the N power amplification channels satisfies: Wherein, is the first phase shift amount; N is an integer greater than or equal to 3; i is an integer, and i = 1, 2, 3.... N; is the first preset phase difference.

2. The balanced power amplifier synthesis circuit according to claim 1, wherein The first phase shift amount is a negative phase, the first phase shifter is one of a low-pass filter, a cable, and a PCB trace, the first compensation phase shift amount is a positive phase, and the second phase shifter is a high-pass filter.

3. The balanced power amplifier combining circuit according to claim 1, wherein The first phase shift amount is a positive phase, the first phase shifter is a high-pass filter, the first compensation phase shift amount is a negative phase, and the second phase shifter is one of a low-pass filter, a cable, and a PCB trace.

4. The balanced power amplifier synthesis circuit according to claim 1, wherein Both the first phase shift amount and the first compensation phase shift amount are zero, and at least one of the first phase shifter and the second phase shifter is a band-pass filter.

5. The balanced power amplifier synthesis circuit according to any one of claims 1 to 4, characterized in that The first phase shifter is configured to transform the output impedance of the power divider to a target input impedance, and the target input impedance is conjugate-matched with the input impedance of the power amplifier; the second phase shifter is configured to transform the output impedance of the power amplifier to a target output impedance, and the target output impedance is conjugate-matched with the input impedance of the synthesizer.

6. The balanced power amplifier synthesis circuit according to any one of claims 1 to 5, characterized in that The power divider includes a first power divider and at least two second power dividers. The input terminal of the first power divider serves as the first input terminal of the power divider. The first power divider includes at least two output terminals. One output terminal of the first power divider is connected to the input terminal of one second power divider. At least four output terminals of the at least two second power dividers all serve as the first output terminals of the power divider; The first power divider is configured to divide the input signal received at the input terminal of the first power divider into at least two second sub-signals with equal amplitude and in-phase, and output the second sub-signals to the corresponding second power dividers through the output terminals of the first power divider; The second power divider is configured to divide the second sub-signal received at the input terminal of the second power divider into at least two first sub-signals, and output the first sub-signals to the corresponding power amplification channels through the respective output terminals of the second power dividers.

7. The balanced power amplifier synthesis circuit according to any one of claims 1 to 6, characterized in that, The synthesizer includes a first synthesizer and at least two second synthesizers. The output end of the first synthesizer serves as the second output end of the synthesizer. The first synthesizer includes at least two input ends, and one input end of the first synthesizer is connected to the output end of one of the second synthesizers. The second synthesizer includes at least two input ends, and one input end is connected to one of the power amplification channels. At least four input ends of the at least two second synthesizers serve as the second input end of the synthesizer; The second synthesizer is configured to synthesize the phase-modulated signals received at the respective input ends of the second synthesizer into a second synthesized signal, and output the second synthesized signal from the output end of the second synthesizer; The first synthesizer is configured to synthesize the second synthesized signals received at the respective input ends of the first synthesizer into the first synthesized signal, and output the first synthesized signal from the output end of the first synthesizer.

8. The balanced power amplifier synthesis circuit according to any one of claims 1 to 5, characterized in that The N power amplification channels include at least two groups of power amplification channels; the first phase shifter is configured to apply a first phase shift amount associated with the channel sequence number in each group to the received first sub-signal; The power splitter includes a first power splitter and at least two second power splitters. The input end of the first power splitter serves as the first input end of the power splitter. The first power splitter includes at least two output ends, and one output end is connected to the input end of one of the second power splitters through a third phase shifter. At least two output ends of the at least two second power splitters serve as the first output end of the power splitter and are connected to the at least two groups of power amplification channels. The input ends of at least two power amplification channels in the same group are connected to the same second power splitter; The first power splitter is configured to divide the input signal received at the input end of the first power splitter into at least two second sub-signals with equal amplitude and in-phase, and respectively output them to the corresponding second power splitters through the output ends of the first power splitter; The second power splitter is configured to divide the second sub-signal received at the input end of the second power splitter into at least two first sub-signals, and respectively output them to the corresponding power amplification channels through the output ends of the respective second power splitters; The synthesizer includes a first synthesizer and at least two second synthesizers. The output end of the first synthesizer serves as the second output end of the synthesizer. The first synthesizer includes at least two input ends, and one input end is connected to the output end of one of the second synthesizers through a fourth phase shifter. At least two input ends of one of the second synthesizers are connected to at least two power amplification channels. The output ends of at least two power amplification channels in the same group are connected to the same second synthesizer; The second synthesizer is configured to synthesize the phase-modulated signals received at each input terminal of the second synthesizer into a second synthesized signal, and output the second synthesized signal from the output terminal of the second synthesizer; the first synthesizer is configured to synthesize the second synthesized signals received at each input terminal of the first synthesizer into the first synthesized signal, and output the first synthesized signal from the output terminal of the first synthesizer; The third phase shifter is configured to apply a second phase shift amount associated with the channel group number to which it is connected to the received second sub-signal; The fourth phase shifter is configured to apply a second compensation phase shift amount to the second synthesized signal synthesized by the second synthesizer, so that the synthesized phase difference between the signals output to the first synthesizer through each of the fourth phase shifters is 0.

9. The balanced power amplifier synthesis circuit according to claim 8, wherein The at least two sets of power amplification channels are K sets of power amplification channels; wherein, the second phase shift amount applied by the third phase shifter to which the t-th set of the K sets of power amplification channels is connected satisfies: Wherein, is the second phase shift amount; K is an integer greater than or equal to 2; t is an integer, and t = 1, 2, 3....K; Δμ is the second preset phase difference.

10. A radio frequency power supply, characterized in that, The radio frequency power supply includes a signal generation unit and a balanced power amplifier synthesis circuit according to any one of claims 1 to 9.

11. An electronic device, characterized in that, Including the radio frequency power supply according to claim 10.

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