A multi-phase clock circuit and a multi-phase clock signal generating method

Abstract

The present disclosure provides a multi-phase clock circuit and a multi-phase clock signal generation method, which are applied to the field of integrated circuit technology. The multi-phase clock circuit includes a mode switching unit and a ring oscillator with m-phase injection and N-stage output. The mode switching unit is configured to control the ring oscillator to open or close the loop. The ring oscillator is configured to: when closed, adjust its self-oscillating frequency toward the clock frequency of the clock signal to be injected; when open, disconnect at m injection nodes to form m coupled delay chains; each coupled delay chain is used to generate N / m phase clock signals and output them at N / m output nodes, respectively. According to embodiments of the present disclosure, injection phase deviation can be reduced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a multi-phase clock circuit and a method for generating a multi-phase clock signal. Background Art

[0002] Multi-phase clocks can be implemented using a ring oscillator, typically using the injection locking principle to keep the ring oscillator operating at the desired frequency. However, the current and load differences between the ring oscillator's injection node and other clock nodes can be significant, resulting in significant phase deviations in the injected clock. Summary of the Invention

[0003] The present disclosure provides a multi-phase clock circuit and a multi-phase clock signal generating method.

[0004] In a first aspect, an embodiment of the present disclosure provides a multi-phase clock circuit, which includes a mode switching switch unit and a ring oscillator with m-phase injection and N-stage output; the mode switching switch unit is configured to control the ring oscillator to be open or closed; the ring oscillator is configured to: when closed, adjust the self-oscillation frequency to the clock frequency of the clock signal to be injected; when open, disconnect at m injection nodes to be divided into m coupled delay chains; each coupled delay chain is used to generate N / m phase clock signals and output them at N / m output nodes respectively.

[0005] In a possible implementation, the ring oscillator includes N main-ring inverters cascaded into a ring, each coupled delay chain includes N / m adjacent main-ring inverters, and an output end of each main-ring inverter is an output node;

[0006] Each of the injection nodes is located between two adjacent stages of the main-ring inverters.

[0007] In a possible implementation, the output node of each main-ring inverter is further connected to the output nodes of subsequent j-stage main-ring inverters through a coupling inverter.

[0008] In a possible implementation, the clock signal to be injected includes m phase clock signals to be injected corresponding one-to-one to the m injection nodes, and each phase clock signal to be injected is used to be injected into a corresponding injection node.

[0009] In a possible implementation, the phases of the m phase clock signals to be injected are differentially distributed.

[0010] In one possible implementation, the multi-phase clock circuit includes m mode switching switch units corresponding one-to-one to m injection nodes, each of the mode switching switch units includes an injection buffer, and each of the injection buffers is used to inject a phase clock signal to be injected into the corresponding injection node.

[0011] In a possible implementation, for any one of the mode switching switch units, the mode switching switch unit includes a first switch, a second switch, and a third switch, wherein:

[0012] The first end of the first switch is used to access the phase clock signal to be injected corresponding to the mode switching switch unit, and the second end is connected to the input end of the injection buffer in the mode switching switch unit;

[0013] A first end of the second switch is connected to the injection node corresponding to the mode switching switch unit, and a second end is connected to the output node of the main ring inverter before the injection node corresponding to the mode switching switch unit;

[0014] The first end of the third switch is connected to a main ring inverter input load and a coupling inverter input load, and the second end is connected to the output node of the previous stage main ring inverter of the injection node corresponding to the mode switching switch unit.

[0015] In a possible implementation, the first switch and the third switch are controlled by a first switch signal; and the second switch is controlled by a second switch signal.

[0016] In a possible implementation, the ring oscillator is configured as follows:

[0017] In a closed loop, the self-oscillation frequency is compared with the clock frequency of the clock signal to be injected, and the self-oscillation frequency is adjusted toward the clock frequency of the clock signal to be injected through negative feedback loop tuning.

[0018] In a second aspect, an embodiment of the present disclosure provides a method for generating a multi-phase clock signal, wherein the method is applied to the multi-phase clock circuit of the first aspect, and the method includes: controlling the ring oscillator to close the loop through the mode switching switch unit until the self-oscillation frequency of the ring oscillator matches the clock frequency of the clock signal to be injected; controlling the ring oscillator to break the loop through the mode switching switch unit to obtain m coupled delay chains, and using each coupled delay chain to generate N / m phase clock signals and output them at N / m output nodes respectively.

[0019] In the disclosed embodiment, a mode switching unit is added to an m-phase injection, N-stage output ring oscillator to control the ring oscillator's loop opening or closing. When closed, the ring oscillator is configured to adjust its self-oscillating frequency toward the clock frequency of the clock signal to be injected. When broken, the ring oscillator is disconnected at its m injection nodes, dividing into m coupled delay chains. Each coupled delay chain is used to generate N / m phase clock signals and output them at N / m output nodes. In this way, while ensuring that the clock frequency of the clock signal to be injected is injected into the ring oscillator, the ring oscillator is disconnected at the m injection nodes, isolating the injection nodes from the output nodes, thereby avoiding injection phase deviation introduced by the load and current of the injection nodes and reducing the injection phase deviation. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In the accompanying drawings of the embodiments of the present disclosure:

[0021] Figure 1 A schematic structural diagram of a multi-phase clock circuit provided by an embodiment of the present disclosure;

[0022] Figure 2 A schematic structural diagram of another multi-phase clock circuit provided by an embodiment of the present disclosure;

[0023] Figure 3 Schematic diagram of the state of the mode switching unit in the closed-loop ring oscillator;

[0024] Figure 4 Schematic diagram of the state of the mode switching unit when the ring oscillator is broken;

[0025] Figure 5 A schematic diagram of the connection relationship of the injection nodes in the related technology;

[0026] Figure 6 A schematic diagram of the connection relationship of the injection nodes in an embodiment of the present disclosure;

[0027] Figure 7 A waveform diagram of an output clock signal based on a small-size injection buffer in the related art;

[0028] Figure 8 Schematic diagram of the waveform of the output clock signal based on the small-size injection buffer in an embodiment of the present disclosure;

[0029] Figure 9 A waveform diagram of an output clock signal based on a large-size injection buffer in the related art;

[0030] Figure 10 Schematic diagram of the waveform of the output clock signal based on the large-size injection buffer in an embodiment of the present disclosure;

[0031] Figure 11 A flowchart of a method for generating a multi-phase clock signal provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0033] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, but the illustrated embodiments may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully understand the scope of the present disclosure to those skilled in the art.

[0034] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the detailed embodiments, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the accompanying drawings.

[0035] The present disclosure may be described with reference to plan views and / or cross-sectional views by way of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0036] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0037] The terms used in this disclosure are only used to describe specific embodiments and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more related enumerated items. As used in this disclosure, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. As used in this disclosure, the terms "comprising" and "made of" specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0038] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this disclosure.

[0039] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0040] High-speed multi-phase clock generators (MPCGs) are widely used in modern communication systems, such as high-speed multi-channel analog-to-digital converters. With the rapid development of high-speed connectivity, optical communications, and next-generation wireless communications, the continuous increase in sampling rates has made multi-channel time-domain interleaving a primary choice. This also places demands on multi-phase clocks for higher speeds and lower phase deviation.

[0041] Clock phase deviation has a significant impact on time-domain interleaved analog-to-digital converters, especially in high-speed and high-precision applications. When sampling high-speed signals, even a small deviation in the sampling moment can cause a large signal difference, resulting in a loss of output signal-to-noise ratio.

[0042] Some related technologies use a ring oscillator structure to implement multi-phase clocks, using the injection locking principle to keep the ring oscillator operating at the desired frequency. However, the injection-locked ring oscillator has significant current and load differences between the injection node and other clock nodes, resulting in significant phase deviation in the injected clock.

[0043] In the disclosed embodiment, a mode switching unit is added to an m-phase injection, N-stage output ring oscillator to control the ring oscillator's loop opening or closing. When closed, the ring oscillator is configured to adjust its self-oscillating frequency toward the clock frequency of the clock signal to be injected. When broken, the ring oscillator is disconnected at its m injection nodes, dividing into m coupled delay chains. Each coupled delay chain is used to generate N / m phase clock signals and output them at N / m output nodes. In this way, while ensuring that the clock frequency of the clock signal to be injected is injected into the ring oscillator, the ring oscillator is disconnected at m injection nodes, isolating the injection nodes from the output nodes, thereby avoiding phase deviation introduced by the load and current of the injection nodes and reducing the phase deviation of the injected clock.

[0044] In a first aspect, an embodiment of the present disclosure provides a multi-phase clock circuit.

[0045] Reference Figure 1The multi-phase clock circuit of the embodiment of the present disclosure includes: a mode switching switch unit and a ring oscillator with m-phase injection and N-stage output; the mode switching switch unit is configured to control the ring oscillator to open or close the loop; the ring oscillator is configured to: when the loop is closed, adjust the self-oscillation frequency to the clock frequency of the clock signal to be injected; when the loop is open, disconnect at m injection nodes to divide into m coupled delay chains; each coupled delay chain is used to generate N / m phase clock signals and output them at N / m output nodes respectively.

[0046] In the disclosed embodiments, an m-phase injection, N-stage output ring oscillator refers to a ring oscillator in which the injected clock signal has m phases and the output clock signal has N phases. m is a positive integer, such as 2, 4, and 8; N is a positive integer, such as 4, 16, and 32. In the disclosed embodiments, there is no restriction on the number of stages (i.e., the value of N) of the m-phase injection, N-stage output ring oscillator (referred to as the ring oscillator) or the number of injected phases (i.e., the value of m).

[0047] The clock signal to be injected may represent a clock signal to be injected into the ring oscillator. In the embodiment of the present disclosure, the clock signal to be injected includes clock signals of m phases. In one example, the clock signal to be injected includes a clock signal with a phase of 0° and a clock signal with a phase of 180°, and the value of m is 2. In another example, the clock signal to be injected includes a clock signal with a phase of 0°, a clock signal with a phase of 90°, a clock signal with a phase of 180°, and a clock signal with a phase of 270°, and the value of m is 4. It should be understood that the above is only an example of the value of m and is not intended to limit the value of m.

[0048] The output clock signal may represent a clock signal outputted by the ring oscillator at the output node. After the to-be-injected clock signal is injected into the ring oscillator, the output node of the ring oscillator may output clock signals of N phases, ie, the output clock signal.

[0049] In an embodiment of the present disclosure, the mode switch is configured to control the ring oscillator to be closed or open. In one example, the mode switch can control the ring oscillator to be closed before the clock signal to be injected is injected into the ring oscillator, and control the ring oscillator to be closed after the clock signal to be injected is injected into the ring oscillator.

[0050] It should be understood that a closed ring oscillator means that its main ring inverter forms a closed loop, while a broken ring oscillator means that its main ring inverter is broken into multiple parts and no longer forms a closed loop.

[0051] In an embodiment of the present disclosure, the ring oscillator is configured to adjust its self-oscillating frequency toward the clock frequency of the clock signal to be injected when the loop is closed. When the loop is closed, the ring oscillator is in a tuning mode, in which the clock is in a self-oscillating state. Therefore, when the loop is closed, the self-oscillating frequency of the ring oscillator can be adjusted. Considering that by comparing the self-oscillating frequency (fosc) of the ring oscillator with the clock frequency (finj) of the clock signal to be injected, it is possible to indirectly determine whether the transmission delay (td) of the coupled delay chain matches the unit delay (tui) of the ring oscillator. Therefore, negative feedback can be used to adjust the self-oscillating frequency of the ring oscillator toward the clock frequency of the clock signal to be injected until the self-oscillating frequency of the ring oscillator matches the clock frequency of the clock signal to be injected.

[0052] In one example, when the ring oscillator's self-oscillation frequency fosc is less than the clock frequency finj of the clock signal to be injected, the value of fosc is increased. When the ring oscillator's self-oscillation frequency fosc is greater than the clock frequency finj of the clock signal to be injected, the value of fosc is decreased until the ring oscillator's self-oscillation frequency matches the clock frequency of the clock signal to be injected. The adjustment step size (increase or decrease step size) of the ring oscillator's self-oscillation frequency fosc can be set as needed and is not limited in this embodiment of the present disclosure.

[0053] In one example, when the difference between the self-oscillation frequency fosc of the ring oscillator and the clock frequency finj of the clock signal to be injected is less than a first preset value, it can be confirmed that the self-oscillation frequency of the ring oscillator matches the clock frequency of the clock signal to be injected. The first preset value can be set as needed, and the embodiment of the present disclosure is not limited. In another example, when the difference between the self-oscillation frequency fosc of the ring oscillator and the clock frequency finj of the clock signal to be injected is less than a second preset value and the number of adjustments of the self-oscillation frequency fosc of the ring oscillator is greater than a third preset value, it can be confirmed that the self-oscillation frequency of the ring oscillator matches the clock frequency of the clock signal to be injected. The second preset value and the third preset value can be set as needed, and the embodiment of the present disclosure is not limited.

[0054] It should be noted that the above is merely an exemplary description of a method for adjusting the self-oscillation frequency fosc of the ring oscillator and a method for confirming that the self-oscillation frequency of the ring oscillator matches the clock frequency finj of the clock signal to be injected, and is not intended to limit the embodiments of the present disclosure. Other methods in the relevant technology may also be used to adjust the self-oscillation frequency fosc of the ring oscillator and confirm that the self-oscillation frequency fosc of the ring oscillator matches the clock frequency finj of the clock signal to be injected.

[0055] After the self-oscillation frequency of the ring oscillator is adjusted, the injection of the clock signal to be injected can be started. At this time, the mode switching switch controls the ring oscillator to disconnect the ring.

[0056] In the embodiment of the present disclosure, the ring oscillator is further configured to: when the ring is broken, it is disconnected at m injection nodes to be divided into m coupled delay chains; each coupled delay chain is used to generate N / m phase clock signals and output them at N / m output nodes respectively.

[0057] Because the clock signal to be injected into the ring oscillator includes clock signals of m phases, the ring oscillator has m injection nodes, each used to inject a clock signal of one phase. When the ring is broken, the ring oscillator is disconnected at the m injection nodes and divided into m coupled delay chains. It should be understood that the ring oscillator is an N-stage ring oscillator, and each coupled delay chain obtained after the ring is broken is an N / m-stage coupled delay chain. The ring oscillator can generate clock signals of N phases, and each coupled delay chain obtained after the ring is broken can generate clock signals of N / m phases, and output these clock signals at N / m output nodes respectively.

[0058] In the disclosed embodiment, a mode switching unit is added to an m-phase injection, N-stage output ring oscillator to control the ring oscillator's loop opening or closing. When closed, the ring oscillator is configured to adjust its self-oscillating frequency toward the clock frequency of the clock signal to be injected. When broken, the ring oscillator is disconnected at its m injection nodes, dividing into m coupled delay chains. Each coupled delay chain is used to generate N / m phase clock signals and output them at N / m output nodes. In this way, while ensuring that the clock frequency of the clock signal to be injected is injected into the ring oscillator, the ring oscillator is disconnected at the m injection nodes, isolating the injection nodes from the output nodes, thereby avoiding injection phase deviation introduced by the load and current of the injection nodes and reducing the injection phase deviation.

[0059] In some embodiments, the ring oscillator includes N main ring inverters cascaded into a ring, each coupled delay chain includes N / m adjacent main ring inverters, the output end of each main ring inverter is an output node; each injection node is located between two adjacent stages of the main ring inverters.

[0060] The main ring inverter can be an inverter provided on the main ring of the ring oscillator, which can be denoted as D. The output end of the main ring inverter in the ring oscillator can be used as the output node of the ring oscillator, for outputting the clock signal generated by the ring oscillator. The output node of the ring oscillator can be represented as , 0≤i≤N-1, i is an integer.

[0061] Reference Figure 2The multi-phase clock circuit of the present disclosure is described using a 2-phase injection 16-stage output (i.e., m is 2, N is 16) ring oscillator as an example. The ring oscillator includes 16 main ring inverters D cascaded into a ring. That is, the 16 main ring inverters D are connected end to end in sequence in a clockwise direction. The output end of each main ring inverter (i.e., the output node of the ring oscillator) is denoted as CKO. <0> , CKO <1> , CKO <2> ...CKO <14> and CKO <15> .

[0062] The ring oscillator can be divided into m coupled delay chains at m injection nodes. Each coupled delay chain can include N / m adjacent main ring inverters. The output end of the main ring inverter in the coupled delay chain can serve as the output node of the coupled delay chain, used to output the clock signal generated by the coupled delay chain. Figure 2 The ring oscillator is divided into two coupled delay chains at the two injection nodes. Each coupled delay chain includes eight adjacent main ring inverters. The output node of one coupled delay chain includes CKO <1> To CKO <8> , the output nodes of another coupled delay chain include CKO <9> To CKO <0> .

[0063] The ring oscillator has m injection nodes, each of which is located between two adjacent stages of the main ring inverters. Figure 2 , the ring oscillator has two injection nodes, one of which is located at CKO <0> The corresponding main ring inverter and CKO <1> Between the corresponding main loop inverters (i.e. CKO <0> The output of the corresponding main loop inverter is connected to CKO <1> The other injection node is located between the input terminals of the corresponding main loop inverters; <8> Corresponding main loop inverter CKO <9> Between the corresponding main loop inverters (i.e. CKO <8> The output of the corresponding main loop inverter is connected to CKO <9> between the input terminals of the corresponding main-loop inverters).

[0064] It should be noted that Figure 2 This is an exemplary description of the injection node and the coupled delay chain, and is not intended to limit the injection node and the coupled delay chain. In the embodiment of the present disclosure, after the injection node disconnects the ring oscillator, it can be divided into m coupled delay chains. For example, Figure 2 The ring oscillator is split into output nodes CKO <0> To CKO <7> The coupled delay chain and output node CKO <8> To CKO <15> The coupled delay chain (not shown). Figure 2 The ring oscillator is split into output nodes CKO <4> To CKO <11> The coupled delay chain and output node CKO <12> To CKO <3> coupled delay chains (not shown).

[0065] As one embodiment of the present disclosure, a ring oscillator is formed by cascading N main-ring inverters into a ring, and an injection node is set between two adjacent stages of the main-ring inverters, so that the ring oscillator can be disconnected from the ring to form multiple coupled delay chains. Furthermore, after the injection node is disconnected, the ring oscillator can still maintain the cascade of N / m adjacent main-ring inverters, thereby forming N / m stages of coupled delay chains. These coupled delay chains can generate N / m phase clock signals and output them at N / m output nodes.

[0066] In some embodiments, the output node of each main-ring inverter is further connected to the output nodes of subsequent j-stage main-ring inverters through a coupling inverter.

[0067] The coupling inverter may refer to an inverter for connecting non-adjacent main-ring inverters, and is denoted by F. The main-ring inverter D and the coupling inverter F may refer to inverters in related art, and the embodiments of the present disclosure do not limit them.

[0068] Among them, j is an integer and can be set as needed. For the output node , the output node can be connected by coupling inverter F That is to say, and The connection is made through a coupled inverter F. It should be noted that, in the case of i+j>N-1, and The connection is made through a coupled inverter F.

[0069] For example, let's take N as 16 and j as 6 as an example. Figure 2 , CKO <0> and CKO <6> Connected via coupled inverter F; CKO <1> and CKO <7> Connected via coupled inverter F; CKO <2> and CKO <8> Connected via coupled inverter F; CKO <8> and CKO <14> Connected via coupled inverter F; CKO <9> and CKO <15> Connected via coupled inverter F; CKO <10> and CKO <1> Connected via coupled inverter F; CKO <11> and CKO <2> Connected via coupled inverter F. Other The coupling connection is the same and will not be described here.

[0070] As one embodiment of the present disclosure, the output node of the main loop inverter is connected to the output node of the main loop inverter of the subsequent j stages through a coupling inverter, so that the coupled delay chains can be connected using coupling inverters, such as Figure 2CKO shown <4> and CKO <10> By connecting through the coupling inverter F, a connection is provided between the coupled delay chains when the loop is broken, thereby improving the accuracy of the phase relationship of the clock node (ie, the output node), which is conducive to reducing the phase deviation.

[0071] In some embodiments, the clock signal to be injected includes m phase clock signals to be injected corresponding to the m injection nodes one by one, and each phase clock signal to be injected is used to be injected into a corresponding injection node.

[0072] Wherein, "phase to be injected" represents the phase of the clock signal to be injected. For a ring oscillator with m-phase injection and N-stage output, it is necessary to inject clock signals of m phases. In other words, the clock signals to be injected include m clock signals of the phase to be injected. For example, the clock signals to be injected include two clock signals of the phase to be injected: a 0° clock signal and a 180° clock signal.

[0073] The m injection nodes correspond one-to-one to the m phase clock signals to be injected. That is, each injection node corresponds to a phase clock signal to be injected. Each phase clock signal to be injected can be injected into the corresponding injection node.

[0074] Reference Figure 2 The clock signal to be injected includes two phase clock signals to be injected, namely a positive clock signal (Clock Positive, CKP) and a reverse clock signal (Clock Negative, CKN), which correspond to the injection node IN1 and the injection node IN2 respectively.

[0075] As one method of an embodiment of the present disclosure, by setting a corresponding injection node for each phase clock signal to be injected, each phase clock signal to be injected can be injected into the ring oscillator at the correct position, thereby improving the accuracy of the phase relationship of the clock nodes and helping to reduce phase deviation.

[0076] In some embodiments, the phases of the m phase clock signals to be injected are differentially distributed.

[0077] The phase differential distribution of the m phase clock signals to be injected means that the m phase clock signals to be injected are one or more pairs of differential clock signals. In one example, the clock signals to be injected include two phase clock signals to be injected, namely a 0° clock signal and a 180° clock signal, both of which are differential clock signals. In another example, the clock signals to be injected include four phase clock signals to be injected, namely a 0° clock signal, a 90° clock signal, a 180° clock signal, and a 270° clock signal, wherein the 0° clock signal and the 180° clock signal have opposite phases and form a pair of differential clock signals, and the 90° clock signal and the 270° clock signal have opposite phases and form a pair of differential clock signals.

[0078] As one approach of an embodiment of the present disclosure, by adopting a differentially distributed phase clock signal to be injected, the anti-interference capability, signal integrity and data transmission rate of the clock signal to be injected are improved.

[0079] In some embodiments, the multi-phase clock circuit includes m mode switching switch units corresponding one-to-one to m injection nodes, each mode switching switch unit includes an injection buffer, and each injection buffer is used to inject a phase clock signal to be injected into the corresponding injection node.

[0080] The multi-phase clock circuit includes m mode switching units, each corresponding to an injection node and configured to control the ring oscillator to open or close at the corresponding injection node. Therefore, the m mode switching units are configured to jointly control the ring oscillator to open or close the loop.

[0081] Each mode switching switch unit may include an injection buffer. Since each mode switching switch corresponds to an injection node, each phase clock signal to be injected corresponds to an injection node. Therefore, each mode switching switch corresponds to a phase clock signal to be injected. The injection buffer included in each mode switching switch can be used to inject the phase clock signal to be injected corresponding to the mode switching switch into the ring oscillator. The input end of the injection buffer of each mode switching switch is used to connect its corresponding clock signal to be injected, and the output end of the injection buffer of each mode switching switch is used to connect its corresponding injection node. In this way, a phase clock signal to be injected can be injected into the corresponding injection node after being enhanced by the injection buffer of the corresponding mode switching switch.

[0082] Reference Figure 2The multi-phase clock circuit includes two mode switching units, namely mode switching unit 1 and mode switching unit 2. Mode switching unit 1 includes an injection buffer BUF1, and mode switching unit 2 includes an injection buffer BUF2. CKP is input to injection node IN1 through injection buffer BUF1, and CKN is input to injection node IN2 through injection buffer BUF2.

[0083] It should be understood that the size of the injection buffer can be set as needed, and the embodiments of the present disclosure do not limit this.

[0084] As one embodiment of the present disclosure, by setting a corresponding mode switching switch unit for each injection node, each mode switching switch unit can control the ring oscillator to be opened or closed at its corresponding injection node, thereby improving the flexibility of control; by setting an injection buffer at each mode switching switch, the enhancement of each phase clock signal to be injected can be achieved.

[0085] In some embodiments, for any one of the mode switching switch units, the mode switching switch unit includes a first switch, a second switch, and a third switch, wherein: the first end of the first switch is used to access the phase clock signal to be injected corresponding to the mode switching switch unit, and the second end is connected to the input end of the injection buffer in the mode switching switch unit; the first end of the second switch is connected to the injection node corresponding to the mode switching switch unit, and the second end is connected to the output node of the previous stage main ring inverter of the injection node corresponding to the mode switching switch unit; the first end of the third switch is connected to a main ring inverter input load and a coupling inverter input load, and the second end is connected to the output node of the previous stage main ring inverter of the injection node corresponding to the mode switching switch unit.

[0086] Any mode switching unit includes a first switch, a second switch and a third switch, wherein the first switch, the second switch and the third switch are configured to control the ring oscillator to be open or closed. Figure 2 The mode switching switch unit 1 includes a first switch S1, a second switch S2 and a third switch S3; the mode switching switch unit 2 includes a first switch S1, a second switch S2 and a third switch S3.

[0087] The first end of the first switch is configured to receive the phase clock signal to be injected corresponding to the mode switching switch unit to which it belongs, and the second end of the first switch is connected to the input end of the injection buffer in the mode switching switch unit to which it belongs. The first switch is configured such that, when closed, the phase clock signal to be injected corresponding to the mode switching switch unit to which it belongs is input into the input end of the injection buffer in the mode switching switch unit to which it belongs.

[0088] Reference Figure 2Taking mode switching unit 1 as an example, the corresponding phase clock signal to be injected is CKP, and the injection buffer is BUF1. The first end of the first switch S1 is connected to CKP, and the second end is connected to the input of the injection buffer BUF1. When the first switch S1 is closed, CKP is input to the input of the injection buffer BUF1.

[0089] The first end of the second switch is connected to the injection node corresponding to the mode switching switch unit to which it belongs, and the second end of the second switch is connected to the output node of the main ring inverter of the previous stage of the injection node corresponding to the mode switching switch unit to which it belongs. The second switch is configured such that: when closed, the injection node corresponding to the mode switching switch unit to which the second switch belongs is connected to the output node of the main ring inverter of the previous stage of the injection node, forming a closed loop of the ring oscillator; when open, the injection node corresponding to the mode switching switch unit to which the second switch belongs is disconnected from the output node of the main ring inverter of the previous stage of the injection node, forming a broken loop of the ring oscillator.

[0090] Reference Figure 2 Taking the mode switching unit 1 as an example, its corresponding injection node is IN1, and the output node of the main loop inverter before the injection node IN1 is CKO <0> The first end of the second switch S2 is connected to the injection node IN1, and the second end is connected to the output node CKO <0> The second switch S2 is configured to: when closed, the injection node IN1 and the output node CKO <0> When connected, the ring oscillator forms a closed loop; when disconnected, the injection node IN1 and the output node CKO <0> If not connected, the ring oscillator forms a broken ring.

[0091] As one embodiment of the present disclosure, the injection node corresponding to the mode switching switch unit to which it belongs is isolated from the output node of the main ring inverter of the previous stage of the injection node by a second switch. When the second switch is disconnected, the competition between the injection node and the output node can be eliminated, which greatly alleviates the pressure of the injection buffer on the injection strength. Thus, when the buffer size is small and the injection strength is low, the clock signal to be injected can be smoothly injected. Figure 2 In clockwise order, the second switch S2 in the mode switching unit 1 switches the output node CKO before injecting the node IN1. <0> The second switch S2 in the mode switching switch unit 2 is isolated from the injection node IN1 before the injection node IN2, and the output node CKO <8> In this way, by eliminating the output node CKO <0> The competition relationship between the injection node IN1 and the injection buffer BUF1 is small and the injection intensity is low, so the smooth injection of CKP is achieved. <8> The competition relationship between the CKN and the injection node IN2 enables smooth injection of the CKN when the injection buffer BUF2 is small and the injection intensity is low.

[0092] A first end of the third switch is connected to a main-ring inverter input load and a coupling inverter input load, and a second end of the third switch is connected to the output node of the main-ring inverter preceding the injection node corresponding to the mode switching switch unit to which the third switch belongs. The third switch is configured to, when closed, add a main-ring inverter input load and a coupling inverter input load to the output node of the main-ring inverter preceding the injection node corresponding to the mode switching switch unit to which the third switch belongs.

[0093] Reference Figure 2 Taking the mode switching switch unit 1 as an example, the first end of the third switch S3 is connected to the input end of a main ring inverter D and the input end of a coupling inverter F, and the second end of the third switch S3 is connected to the output node CKO <0> The third switch S3 is configured to: when closed, at the output node CKO <0> An input load of the main ring inverter D and an input load of the coupling inverter F are added.

[0094] It should be understood that the main ring inverter connected to the first end of the third switch can refer to the cascaded main ring inverters in the ring oscillator, and the coupling inverter connected to the first end of the third switch can refer to the coupling inverter connected to the output node of the main ring inverter in the ring oscillator.

[0095] As one method of an embodiment of the present disclosure, by connecting a main-loop inverter input load and a coupled inverter input load to the third switch, the load of the output node during a closed loop can be simulated, thereby reducing the impact of a broken loop on the output node load and reducing phase deviation.

[0096] In some embodiments, the first switch and the third switch are controlled by a first switch signal; and the second switch is controlled by a second switch signal.

[0097] The first switch signal can be used to control the access of the clock signal to be injected and the load. The second control signal can be used to control the opening and closing of the ring oscillator at the injection node, that is, the ring oscillator's ring breaking and closing. Since the ring oscillator is closed when the second switch is closed, the ring oscillator adjusts its own frequency without the need to access the phase clock signal to be injected and the load. Therefore, when the second switch is closed, the first switch and the third switch are disconnected. Since the ring oscillator is broken when the second switch is disconnected, the ring oscillator needs to inject the phase clock signal to be injected into the injection node and needs to connect the load to reduce the impact of the broken loop. Therefore, when the second switch is disconnected, the first switch and the third switch are closed.

[0098] It can be seen that the states of the first switch and the third switch are consistent, and the states of the first switch and the third switch are opposite to the states of the second switch. Therefore, the first switch signal and the second switch signal are opposite control signals.

[0099] Reference Figure 2 CKP is connected to the injection node IN1 via the first switch S1 and the injection buffer BUF1; a main ring inverter D and a coupling inverter F are connected to the output node CKO via the third switch S3 <0> ;Injection node IN1 and output node CKO <0> The first switch S1 and the third switch S3 are controlled by a first switching signal, and the second switch is controlled by a second switching signal.

[0100] It should be understood that the first switch and the third switch in each mode switching switch unit can be controlled by the same first switch signal, and the second switch in each mode switching switch unit can be controlled by the same second switch signal. This can ensure the consistency of each mode switching switch unit, so that each phase clock signal to be injected can be turned on and injected at the same time, thereby reducing the phase deviation.

[0101] As one embodiment of the present disclosure, the first switch, the second switch, and the third switch are controlled to be closed and opened by the first switch signal and the second switch signal, thereby controlling the closed loop and the broken loop of the ring oscillator.

[0102] Figure 3 Figure 2 shows the state of the mode switching unit when the ring oscillator is closed. Figure 3 When the ring oscillator is closed, the first switch S1 and the third switch S3 are disconnected (off), and the second switch S2 is closed (on). At this time, the output node CKO <0> Connected to the injection node IN1, the output node CKO <8> Connected to the injection node IN2, the ring oscillator forms a closed loop.

[0103] Figure 4 The figure shows the state of the mode switching unit when the ring oscillator is broken. Figure 4 When the ring oscillator is broken, the first switch S1 and the third switch S3 are closed (on), and the second switch S2 is open (off). At this time, the output node CKO <0> Not connected to the injection node IN1, output node CKO <8> It is not connected to the injection node IN2, and the ring oscillator is disconnected into two coupled delay chains.

[0104] In some embodiments, the ring oscillator is configured to: when in a closed loop, compare the self-oscillation frequency with the clock frequency of the clock signal to be injected, and adjust the self-oscillation frequency toward the clock frequency of the clock signal to be injected through negative feedback loop tuning.

[0105] In closed loop, negative feedback is used to adjust the ring oscillator's self-oscillation frequency fosc to a value close to the clock frequency finj of the clock signal to be injected (such as CKP and CKN). This process can be achieved by obtaining the output clock frequency finj through digital calibration or actual measurement. The frequency of is used as fosc, and the control bit of the ring oscillator is adjusted to tune until the self-oscillation frequency fosc matches the clock frequency finj of the clock signal to be injected.

[0106] In a ring oscillator, two adjacent output nodes and The transmission delay between the two adjacent output nodes can be expressed as td = 1 / (N × fosc). When the self-oscillation frequency fosc matches the clock frequency finj of the clock signal to be injected, it can be determined that fosc = finj. Therefore, the transmission delay between the two adjacent output nodes is td = 1 / (N × fosc). and The actual transmission delay td between the ring oscillator and the clock frequency finj is 1 / (N × finj). The ring oscillator's oscillation period T = 1 / fosc = 1 / finj. The ring oscillator's unit delay tui = T / N = T = 1 / finj. Therefore, when fosc = finj, the ring oscillator's transmission delay td is identical to its unit delay tui. Therefore, by comparing the self-oscillating frequency fosc with the injected clock frequency finj, we can indirectly determine whether the transmission delay td of the ring-time coupled delay chain matches the ring oscillator's unit delay tui. Furthermore, we can also determine whether the transmission delay td of the coupled delay chain in open-loop mode matches the unit delay tui.

[0107] As one method of an embodiment of the present disclosure, by adjusting the self-oscillation frequency fosc to match the clock frequency finj of the clock signal to be injected, the transmission delay td of the coupled delay chain can be matched with the unit delay tui of the ring oscillator, thereby ensuring that the ring oscillator will not affect the transmission delay of the injected clock signal due to a broken ring.

[0108] Figure 5 The connection relationship of the injection nodes in the related art is shown. Figure 6 FIG. 1 shows the connection relationship of the injection node in the embodiment of the present disclosure. Figure 5 and Figure 6 It can be seen that in the embodiment of the present disclosure, when the loop is broken, the first switch S1 and the third switch S3 are closed, and the second switch S2 is opened, thereby connecting the injection node and the output node CKO. <0> Isolated, while at the output node CKO <0> Connect the same load as other output nodes (a load at the input terminal of the main ring inverter D and a load at the input terminal of the coupled inverter F) to avoid the large injection phase deviation caused by the current capability difference between the injection buffer and the coupled delay chain and the load difference of the output node; In addition, due to CKO <n-1>and The connected main-loop inverter does not compete with the injection buffer, which greatly alleviates the pressure on the buffer's injection strength.

[0109] In the disclosed embodiments, a mode switching unit is added to an injection-locked ring oscillator to control the ring oscillator's loop opening and closing. When the ring oscillator is closed, it enters a ring oscillator tuning mode, in which it is in a self-oscillating state. By comparing its self-oscillating frequency fosc with the clock frequency finj of the clock signal to be injected, it indirectly determines whether the transmission delay td of the coupled delay chain when the loop is broken matches the unit delay tui of the ring oscillator when the loop is closed. Negative feedback is then used to tune the ring oscillator so that its self-oscillating frequency fosc approaches the clock frequency finj of the clock signal to be injected. When the ring oscillator is broken, it enters a coupled delay chain open-loop injection mode, in which the clock frequency finj of the clock signal to be injected is applied to the coupled delay chain to generate a multi-phase clock signal. For an N-stage ring oscillator with m-phase injection, the ring oscillator needs to be disconnected at the injection node and equally divided into m N / m-stage coupled delay chains. These m coupled delay chains are connected by coupling inverters F to ensure accurate phase relationships between the output nodes. Compared with the injection-locked ring oscillator in the related art, the embodiment of the present disclosure disconnects the ring oscillator at the injection node, isolates the injection node from the output node while ensuring that the phase and frequency information of the injected clock signal can be written through the ring oscillator and the coupled delay chain, thereby avoiding the injection phase deviation introduced by the injection node load and current difference, and at the same time eliminates the competition between the injection buffer and the delay unit, reducing the difficulty of injection.

[0110] Figure 7 FIG. 4 shows a waveform diagram of an output clock signal based on a small-size injection buffer in the related art. Figure 8 The waveform diagram of the output clock signal based on the small-size injection buffer in the embodiment of the present disclosure is shown. Figure 7 The waveform diagram of the clock signal outputted by each output node of the ring oscillator in the related art after the clock signal to be injected is injected into the ring oscillator via the injection buffer. Figure 8 This is a waveform diagram of the clock signals output by each output node of the ring oscillator according to the embodiment of the present disclosure after the clock signal to be injected is injected into the ring oscillator through the injection buffer. Figure 7 and Figure 8 The clock signal to be injected and the injection buffer used in the method are the same, and the size of the injection buffer is small. Figure 7 and Figure 8 In the waveform diagram shown, the horizontal axis represents time and the vertical axis represents voltage, and the curves therein represent how the voltage of the clock signal output by each output node of the ring oscillator changes over time.

[0111] In related technologies, the injection node is directly used as the output node. Figure 7 In the case where the injection buffer size is small, the voltage of the clock signal output by the injection node cannot reach the maximum value at some time, and the clock signal to be injected cannot be successfully injected into the ring oscillator. In the embodiment of the present disclosure, the injection node and the output node are connected through a second switch. Figure 7 , when the injection buffer size is small, the clock signal to be injected can be successfully injected into the ring oscillator. It can be seen that the embodiment of the present disclosure successfully injects the clock signal to be injected when the injection buffer size is small.

[0112] Figure 9 FIG. 4 shows a waveform diagram of an output clock signal based on a large-size injection buffer in the related art. Figure 10 The waveform diagram of the output clock signal based on the large-size injection buffer in the embodiment of the present disclosure is shown. Figure 9 The waveform diagram of the clock signal outputted from each output node of the ring oscillator in the related art after the captured clock signal is injected into the ring oscillator via the injection buffer. Figure 10 This is a waveform diagram of the clock signals output by each output node of the ring oscillator according to the embodiment of the present disclosure after the clock signal to be injected is injected into the ring oscillator through the injection buffer. Figure 9 and Figure 10 The clock signal to be injected and the injection buffer used in the method are the same, and the size of the injection buffer is larger. Figure 9 and Figure 10 In the waveform diagram shown, the horizontal axis represents time and the vertical axis represents voltage, and the curves therein represent how the voltage of the clock signal output by each output node of the ring oscillator changes over time.

[0113] In related technologies, the injection node is directly used as the output node. Figure 9 In the case of a large injection buffer size, the injection phase deviation is introduced due to the difference in injection node load and current, resulting in inconsistent clock signal waveforms output by the injection node and other clock nodes. In the embodiment of the present disclosure, the injection node and the output node are connected through a second switch. Figure 10 When the injection buffer size is large, the clock signal waveform output by the output node before the injection node is consistent with that output by other output nodes. It can be seen that the embodiment of the present disclosure reduces the phase deviation when the injection buffer size is large.

[0114] The disclosed embodiments, on the one hand, isolate the injection node from the clock signal output node, thereby reducing the clock injection phase deviation in an injection-locked ring oscillator, lowering the design burden and power consumption of subsequent clock deviation calibration circuits. On the other hand, by eliminating node competition between the injection buffer and the coupled delay chain, the injection difficulty is reduced, alleviating the design burden and power consumption of the injection buffer.

[0115] In a second aspect, an embodiment of the present disclosure provides a method for generating a multi-phase clock signal, which can be applied to the multi-phase clock circuit of any embodiment of the first aspect.

[0116] Reference Figure 11 , the multi-phase clock signal generation method provided by the embodiment of the present disclosure may include:

[0117] S801 , controlling the ring oscillator to close the loop by using the mode switching unit until the self-oscillation frequency of the ring oscillator matches the clock frequency of the clock signal to be injected.

[0118] S802 , controlling the ring oscillator to break the ring by using the mode switching unit to obtain m coupled delay chains, using each coupled delay chain to generate N / m phase clock signals and outputting them at N / m output nodes respectively.

[0119] The following combination Figure 2 The multi-phase clock signal generating method according to the embodiment of the present disclosure is described.

[0120] Reference Figure 2 Before the clock signal to be injected is injected into the ring oscillator, the mode switching unit controls the ring oscillator's closed loop (opening the first and third switches S1, S3 and closing the second switch S2), placing the multi-phase clock circuit in ring oscillator tuning mode. In this mode, negative feedback is used to adjust the ring oscillator's free-frequency frequency (fosc) until it matches the clock frequency (finj) of the clock signal to be injected (e.g., CKP / CKN).

[0121] Reference Figure 2 In the multi-phase clock signal generation stage, the ring oscillator is disconnected by controlling the mode switch (the first switch S1 and the third switch S3 are closed, and the second switch S2 is opened), so that the ring oscillator is disconnected into two coupled delay chains, and injection buffers (such as BUF1 and BUF2) and loads (such as the main ring inverter D and the coupled inverter F) are connected, and the clock frequency finj of CKP / CKN is injected into the two coupled delay chains. The two coupled delay chains will work at finj. and The transmission delay td between them is 1 / (16×fosc). After the first tuning step, fosc=finj, then the transmission delay td=1 / (16×finj)=unit delay tui. Therefore, the delay units of the two coupled delay chains (i.e., the main ring inverter D) divide the oscillation period T=(1 / finj) into 16 equal parts, thereby better generating a 16-phase clock signal.

[0122] In the embodiment of the present disclosure, a mode switching switch unit is added to an injection-locked ring oscillator to control the ring oscillator's loop opening or closing. When in the closed loop, the ring oscillator operates in a ring oscillator tuning mode, in which the ring oscillator is in a self-oscillating state and is used to adjust the unit delay through the self-oscillating frequency. When in the broken loop, the ring oscillator operates in a coupled delay chain open-loop injection mode, in which the m-phase is injected into the N-stage ring oscillator, disconnected at the injection node and divided into m N / m-stage coupled delay chains, thereby generating an N-phase clock signal with a small phase deviation.

[0123] It should be understood that the multi-phase clock circuit and multi-phase clock signal generation method of the embodiments of the present disclosure can be used in high-speed and high-precision communication systems such as high-speed multi-channel analog-to-digital converters and time-domain interleaved analog-to-digital converters.

[0124] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly indicated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A multi-phase clock circuit, characterized in that: A ring oscillator including a mode switching unit and m-phase injection and N-stage output; The mode switching unit is configured to control the ring oscillator to be open or closed; The ring oscillator is configured as: When the loop is closed, adjusting the self-oscillation frequency of the ring oscillator until the self-oscillation frequency matches the clock frequency of the clock signal to be injected, wherein adjusting the self-oscillation frequency of the ring oscillator includes increasing the value of the self-oscillation frequency when the self-oscillation frequency is less than the clock frequency of the clock signal to be injected, and decreasing the value of the self-oscillation frequency when the self-oscillation frequency is greater than the clock frequency of the clock signal to be injected; When the loop is broken, the m injection nodes are disconnected to form m coupled delay chains; each coupled delay chain is used to generate N / m phase clock signals and output them at N / m output nodes respectively.

2. The multi-phase clock circuit according to claim 1, wherein: The ring oscillator includes N main-ring inverters cascaded into a ring, each coupled delay chain includes N / m adjacent main-ring inverters, and the output end of each main-ring inverter is an output node; Each of the injection nodes is located between two adjacent stages of the main-ring inverters.

3. The multi-phase clock circuit according to claim 2, wherein: The output node of each main-ring inverter is further connected to the output nodes of subsequent j-stage main-ring inverters through a coupling inverter.

4. The multi-phase clock circuit according to claim 2, wherein: The clock signal to be injected includes m phase clock signals to be injected corresponding to the m injection nodes one by one, and each phase clock signal to be injected is used to be injected into a corresponding injection node.

5. The multi-phase clock circuit according to claim 4, wherein: Phase differential distribution of the m phase clock signals to be injected.

6. The multi-phase clock circuit according to claim 4, wherein: The multi-phase clock circuit includes m mode switching switch units corresponding one-to-one to m injection nodes, each of the mode switching switch units includes an injection buffer, and each of the injection buffers is used to inject one of the phase clock signals to be injected into the corresponding injection node.

7. The multi-phase clock circuit according to claim 6, wherein: For any one of the mode switching switch units, the mode switching switch unit includes a first switch, a second switch and a third switch, wherein: The first end of the first switch is used to access the phase clock signal to be injected corresponding to the mode switching switch unit, and the second end is connected to the input end of the injection buffer in the mode switching switch unit; A first end of the second switch is connected to the injection node corresponding to the mode switching switch unit, and a second end is connected to the output node of the main ring inverter before the injection node corresponding to the mode switching switch unit; The first end of the third switch is connected to a main ring inverter input load and a coupling inverter input load, and the second end is connected to the output node of the previous stage main ring inverter of the injection node corresponding to the mode switching switch unit.

8. The multi-phase clock circuit according to claim 7, wherein: The first switch and the third switch are controlled by a first switch signal; The second switch is controlled by a second switching signal.

9. The multi-phase clock circuit according to claim 1, wherein: The ring oscillator configuration is: In a closed loop, the self-oscillation frequency is compared with the clock frequency of the clock signal to be injected, and the self-oscillation frequency is adjusted toward the clock frequency of the clock signal to be injected through negative feedback loop tuning.

10. A method for generating a multi-phase clock signal, characterized in that: The method is applied to the multi-phase clock circuit according to any one of claims 1 to 9, and the method includes: Controlling the ring oscillator to close the loop by the mode switching unit until the self-oscillation frequency of the ring oscillator matches the clock frequency of the clock signal to be injected; The ring oscillator is controlled to break the ring by the mode switching unit to obtain m coupled delay chains, and each coupled delay chain is used to generate N / m phase clock signals and output them at N / m output nodes respectively.

Images