Ring oscillator and frequency trimming method thereof

Abstract

The invention discloses a ring oscillator which comprises M delay units, the M delay units are sequentially cascaded to form a loop, each delay unit comprises a second transistor and a first capacitor, the control end of each second transistor serves as the input end of the corresponding delay unit, and the control end of each first capacitor serves as the input end of the corresponding delay unit. The first power end of the second transistor is used as the output end of the delay unit, and M is an odd number greater than or equal to 3; and a current generation circuit for generating a control current and providing the control current to the M delay units, wherein the ring oscillator trims the frequency of the clock signal output by the ring oscillator by adjusting the numerical values of the first capacitor and the control current at the same time. The frequency of the clock signal is finely adjusted by trimming the control current, and the frequency of the clock signal is coarsely adjusted by trimming the first capacitor. Therefore, the power consumption and the area are greatly optimized, and a relatively good temperature drift characteristic can still be maintained.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and particularly to a ring oscillator and a method for trimming its frequency. Background Art

[0002] An oscillator is an important part of a chip, providing a clock signal for the chip. The frequency stability of the clock signal affects the performance, power consumption and reliability of the chip. The frequency of the clock signal is affected by factors such as PVT (Process, Voltage, Temperature). Therefore, an oscillator with low temperature drift and simple trimming is expected in this field. Summary of the Invention

[0003] According to one aspect of the embodiments of the present application, a ring oscillator is provided, including:

[0004] M delay units, the M delay units are cascaded in sequence to form a loop, the delay unit includes a second transistor and a first capacitor, the control terminal of the second transistor serves as the input terminal of the delay unit, the first power terminal of the second transistor serves as the output terminal of the delay unit, and M is an odd number greater than or equal to 3; and

[0005] a current generation circuit for generating a control current to be provided to the M delay units;

[0006] wherein, the ring oscillator trims the frequency of the clock signal output therefrom by simultaneously adjusting the values of the first capacitor and the control current.

[0007] Preferably, the frequency of the clock signal generated by the ring oscillator is determined by the effective capacitance value of the first capacitor and the effective current value of the control current, and the frequency change of the clock signal caused by adjusting the effective capacitance value of the first capacitor is greater than the frequency change of the clock signal caused by adjusting the effective current value of the control current.

[0008] Preferably, the adjustment signal for trimming the frequency of the clock signal includes a high-order part and a low-order part, the high-order part is used to adjust the effective capacitance value of the first capacitor, and the low-order part is used to adjust the effective current value of the control current.

[0009] Preferably, the current generation circuit includes a first transistor, a current source, a first resistor and a current mirror, wherein the current source and the first transistor are connected in series, the voltage across the first resistor is clamped to the gate-source voltage of the first transistor, and the current mirror generates the control current based on the current flowing through the first resistor.

[0010] Preferably, the current mirror includes a plurality of fourth transistors, the control terminals of the plurality of fourth transistors are connected together, the source electrodes of the plurality of fourth transistors are connected together, and the first power terminals of the plurality of fourth transistors are respectively coupled to M delay units.

[0011] Preferably, the first capacitor includes m trimming capacitors and m first switches. Each trimming capacitor and the corresponding first switch are connected in series to form a branch, and the m branches are connected in parallel, where m is a positive integer greater than 1.

[0012] Preferably, the m trimming capacitors have different capacitance values.

[0013] Preferably, the first resistor includes n trimming resistors and n second switches. The n trimming resistors are connected in series, and each trimming resistor is connected in parallel with the corresponding second switch, where n is a positive integer greater than 1.

[0014] Preferably, the n trimming resistors have different resistance values.

[0015] Preferably, the frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the effective resistance value of the first resistor. The change in the frequency of the clock signal caused by the change in the switching state of one or more of the m first switches is greater than the change in the frequency of the clock signal caused by the change in the switching state of one or more of the n second switches.

[0016] Preferably, the current mirror includes a plurality of fourth transistors, the control terminals of the plurality of fourth transistors are connected together, the source electrodes of the plurality of fourth transistors are connected together, the fourth transistor includes n trimming transistors and n second switches, the n trimming transistors are connected in parallel, and the control terminal of each trimming transistor is connected to a bias node through the corresponding second switch, where n is a positive integer greater than 1.

[0017] Preferably, the n trimming transistors have different aspect ratios.

[0018] Preferably, the frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the magnitude of the control current. The change in the frequency of the clock signal caused by the change in the switching state of one or more of the m first switches is greater than the change in the frequency of the clock signal caused by the change in the switching state of one or more of the n second switches.

[0019] Preferably, one end of the first capacitor is coupled to the first power terminal of the second power transistor, and the other end of the first capacitor is connected to the ground or the power supply terminal.

[0020] Preferably, the first transistor and the second transistor have the same type and temperature drift characteristics.

[0021] In a second aspect, a method for trimming the frequency of a ring oscillator is provided. The ring oscillator includes M delay units, and the M delay units are cascaded in sequence to form a loop. The delay unit includes a second transistor and a first capacitor. The control terminal of the second transistor serves as the input terminal of the delay unit, and the first power terminal of the second transistor serves as the output terminal of the delay unit. M is an odd number greater than or equal to 3; and

[0022] a current generation circuit for generating a control current and supplying it to the M delay units;

[0023] wherein, the ring oscillator adjusts the frequency of the clock signal output therefrom by simultaneously adjusting the values of the first capacitor and the control current.

[0024] Preferably, the frequency of the clock signal generated by the ring oscillator is determined by the effective capacitance value of the first capacitor and the effective current value of the control current. The change in the frequency of the clock signal caused by adjusting the effective capacitance value of the first capacitor is greater than the change in the frequency of the clock signal caused by adjusting the effective current value of the control current.

[0025] Preferably, the value of the adjustment signal for trimming the frequency of the clock signal is divided into a high-order part and a low-order part. The high-order part is used to adjust the effective capacitance value of the first capacitor, and the low-order part is used to adjust the effective current value of the control current.

[0026] Preferably, the current generation circuit includes a first transistor, a current source, a first resistor, and a current mirror. Among them, the current source and the first transistor are connected in series, the voltage across the first resistor is clamped to the gate-source voltage of the first transistor, and the current mirror generates the control current based on the current flowing through the first resistor.

[0027] Preferably, the current mirror includes a plurality of fourth transistors. The control terminals of the plurality of fourth transistors are connected together, the source terminals of the plurality of fourth transistors are connected together, and the first power terminals of the plurality of fourth transistors are respectively coupled to the M delay units.

[0028] Preferably, the first capacitor includes m trimming capacitors and m first switches. Each trimming capacitor and the corresponding first switch are connected in series to form a branch, and the m branches are connected in parallel, where m is a positive integer greater than 1.

[0029] Preferably, the first resistor includes n trimming resistors and n second switches. The n trimming resistors are connected in series, and each trimming resistor is connected in parallel with a corresponding second switch, where n is a positive integer greater than 1.

[0030] Preferably, the frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the effective resistance value of the first resistor. When one or more of the m first switches change their switching states, the change in the frequency of the clock signal is greater than the change in the frequency of the clock signal when one or more of the n second switches change their switching states.

[0031] Preferably, the current mirror includes a plurality of fourth transistors. The control terminals of the plurality of fourth transistors are connected together, and the source terminals of the plurality of fourth transistors are connected together. The fourth transistor includes n trimming transistors and n second switches. The n trimming transistors are connected in parallel, and the control terminal of each trimming transistor is connected to a bias node through the corresponding second switch, where n is a positive integer greater than 1.

[0032] Preferably, the frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the magnitude of the control current. When one or more of the m first switches change their switching states, the change in the frequency of the clock signal is greater than the change in the frequency of the clock signal when one or more of the n second switches change their switching states.

[0033] In this application, the frequency of the clock signal is finely adjusted by trimming the control current, and coarsely adjusted by trimming the first capacitor. In this way, the power consumption and area are greatly optimized, and good temperature drift characteristics can still be maintained. Description of the Drawings

[0034] Through the following description of the embodiments of the present application with reference to the drawings, the above and other objects, features, and advantages of the present application will become clearer. In the drawings:

[0035] Figure 1 is a schematic circuit diagram of a ring oscillator according to an embodiment of the present application;

[0036] Figure 2 is another schematic circuit diagram of a ring oscillator according to an embodiment of the present application;

[0037] Figure 3 is yet another schematic circuit diagram of a ring oscillator according to an embodiment of the present application;

[0038] Figure 4 is a schematic diagram of a chip according to an embodiment of the present application;

[0039] Figure 5 is a schematic circuit diagram of a first capacitor according to an embodiment of the present application;

[0040] Figure 6 is a schematic circuit diagram of a first resistor according to an embodiment of the present application;

[0041] Figure 7 is a schematic circuit diagram of a fourth transistor according to an embodiment of the present application;

[0042] Figure 8 is another schematic circuit diagram of a first resistor according to an embodiment of the present application;

[0043] Figure 9 is another schematic circuit diagram of a first capacitor according to an embodiment of the present application;

[0044] Figure 10 is another schematic circuit diagram of a fourth transistor according to an embodiment of the present application;

[0045] Figure 11 is another schematic circuit diagram of a first resistor according to an embodiment of the present application;

[0046] Figure 12 is another schematic circuit diagram of a first capacitor according to an embodiment of the present application. Detailed implementation manners

[0047] The following describes the present application based on embodiments, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0048] In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0049] Unless the context clearly requires otherwise, the words "including", "comprising", and the like in the entire application document should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense, that is, in the sense of "including but not limited to".

[0050] In the description of the present application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0051] Figure 1It is a schematic circuit diagram of a ring oscillator provided by an embodiment of the present application. The ring oscillator is used to generate a clock signal. The ring oscillator includes an oscillation loop 100 and a current generation circuit 200.

[0052] The oscillation loop 100 includes M delay units, where M is an odd number greater than or equal to 3. The M delay units are cascaded in sequence to form a ring loop. Specifically, the output terminal of the previous-stage delay unit is connected to the input terminal of the next-stage delay unit, and the output terminal of the last-stage delay unit is connected to the input terminal of the first-stage delay unit. The delay unit includes a second transistor and a first capacitor. The control terminal of the second transistor serves as the input terminal of the delay unit, the first power terminal of the second transistor serves as the output terminal of the delay unit, and the first capacitor is connected between the first power terminal of the second transistor and the ground. The first capacitor is, for example, a zero-temperature-drift metal-metal capacitor. In the embodiment of the present invention, since the second transistor is taken as an MOSFET (metal-oxide-semiconductor field-effect transistor) as an example, the control terminal of the second transistor is its gate, the first power terminal is its drain, and the second power terminal is its source.

[0053] In Figure 1 the illustrated exemplary embodiment, M = 3, and the ring oscillator includes a delay unit 101, a delay unit 102, and a delay unit 103. The delay unit 101 includes a second transistor N21 and a first capacitor C21. The delay unit 102 includes a second transistor N22 and a first capacitor C22. The delay unit 103 includes a second transistor N23 and a first capacitor C23. The first capacitor C21, the first capacitor C22, and the first capacitor C21 have the same capacitance value C.

[0054] The current generation circuit 200 is used to generate a control current I osc and provide the control current I osc to the M delay units. For example, the current generation circuit 200 is connected to the drain of the second transistor of the delay unit and provides the control current I osc to the output terminal of the delay unit.

[0055] The frequency f of the clock signal generated by the ring oscillator is proportional to the control current I osc inversely proportional to the capacitance value C of the first capacitor, and inversely proportional to the gate-source voltage Vgs2 of the second transistor N21.

[0056]

[0057] The amplitudes of the gate-source voltage Vgs2 of the second transistor N21, the gate-source voltage Vgs3 of the second transistor N22, and the gate-source voltage Vgs4 of the second transistor N23 are the same, but the phases are different. In the above formula, Vgs2 refers to the amplitude of the gate-source voltage of the second transistor N21.

[0058] The first transistor and the second transistor have the same or similar temperature drift characteristics, so the frequency f of the clock signal generated by the ring oscillator has low temperature drift characteristics.

[0059] In some embodiments, the ring oscillator further includes a shaping circuit ( Figure 1 not shown in the figure), the shaping circuit is connected to the output terminal OUT of the oscillation loop 100, and the shaping circuit is used to shape the oscillation signal generated by the oscillation loop 100 to obtain a clock signal.

[0060] Wherein, the ring oscillator adjusts the frequency of the clock signal output by simultaneously adjusting the values of the first capacitor and the control current.

[0061] In the embodiment of the present invention, the frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor C and the effective current value of the control current I osc The adjustment signal for adjusting the frequency f of the clock signal includes a high part and a low part. The high part is selected to adjust the effective capacitance value of the first capacitor C, and the low part is selected to adjust the effective current value of the control current I osc so that the change in the frequency f of the clock signal caused by adjusting the effective capacitance value of the first capacitor C is greater than the change in the frequency f of the clock signal caused by adjusting the effective current value of the control current I osc when adjusting the effective current value of the control current I.

[0062] Figure 2 is another schematic circuit diagram of a ring oscillator according to an embodiment of the present application. As Figure 2 shown, the current generation circuit 200 further includes: a current source 230, a first resistor R0, a current mirror 210, and a voltage clamping circuit 220. The current generation circuit 200 includes a first transistor N1. The current generation circuit 200 is used to generate a control current I osc and supply the control current I osc to M delay units. The magnitude of the control current I osc is proportional to the gate-source voltage Vgs1 of the first transistor N1.

[0063] The current source 230 is used to provide a bias current Iref to the first transistor N1. The bias current Iref has a zero temperature drift characteristic. The current source 230 is, for example, a Bandgap Reference current source. The Bandgap Reference current source includes a sub-circuit that generates a positive temperature coefficient (PTAT) current and a sub-circuit that generates a negative temperature coefficient (CTAT) current. By superimposing the positive temperature coefficient current and the negative temperature coefficient current, a bias current Iref with a zero temperature coefficient is obtained. As Figure 2 shown, the current source 230 and the first transistor N1 are connected in series between the power supply terminal VDD and the ground GND. The bias current Iref determines the gate-source voltage Vgs1 of the first transistor N1. The temperature drift characteristic of the gate-source voltage Vgs1 of the first transistor N1 is determined by the temperature drift characteristic of the NMOS transistor. More specifically, as Figure 2 shown, the drain of the first transistor N1 is connected to the current source 230, the gate and the drain of the first transistor N1 are connected together, and the source of the first transistor N1 is grounded.

[0064] The voltage clamping circuit 220 is connected to the gate of the first transistor N1 and the first end N of the first resistor R0. The second end of the first resistor R0 is grounded. The voltage clamping circuit 220 clamps the voltage at the first end N of the first resistor R0 to the gate-source voltage Vgs1 of the first transistor N1. The voltage clamping circuit 220 is, for example, a voltage follower. The first resistor R0 is, for example, a polysilicon resistor with zero temperature drift. Therefore, when the voltage at the first end N of the first resistor R0 is equal to the gate-source voltage Vgs1 of the first transistor N1, the second end of the first resistor R0 and the source of the first transistor N1 are grounded. Thus, the magnitude of the current I0 flowing through the first resistor R0 is Vgs1 / R0, and the temperature drift characteristic of this current depends on the temperature drift characteristic of the gate-source voltage Vgs1 of the first transistor N1.

[0065] The current mirror 210 generates a control current I osc based on the current I0 flowing through the first resistor R0. In this embodiment, as Figure 2 shown, the current mirror 210 includes a third transistor P10 whose drain is connected to the first end N of the first resistor R0, and a plurality of fourth transistors P11 - P13. The gates of the plurality of fourth transistors P11 - P13 are commonly connected to the bias voltage Vbias, and the sources of the plurality of fourth transistors P11 - P13 are connected to the power supply terminal VDD. The drains of the fourth transistors P11 - P13 are connected to the drain terminals of the second transistors of the corresponding delay units. The control current I osc is proportional to the current I0 flowing through the first resistor R0. The control current I oscThe ratio to the current I0 is determined by the ratio of the aspect ratios of the transistors P10 - P13. The aspect ratio of a transistor refers to the ratio of the distance between two adjacent electrodes of the transistor to the length of the transistor. When the aspect ratio of the transistor increases, the current gain of the transistor will increase. When a higher current gain is required, a transistor with a larger aspect ratio can be selected. In other embodiments, the current mirror can be in other forms, and the present invention does not limit this. Any method of converting Vgs1 / R0 into the control current I through a current mirror osc is within the protection scope of the present invention.

[0066] It should be noted that in the embodiments of the present invention, the first transistor and the second transistor are NMOS transistors, and the third transistor and the fourth transistor are PMOS transistors. In other embodiments, the first transistor and the second transistor can also be PMOS transistors, and the third transistor and the fourth transistor can also be NMOS transistors. As long as the first transistor and the second transistor are of the same type of transistors, and the third transistor and the fourth transistor are of the same type of transistors, the present invention does not make any limitations in this regard.

[0067] Figure 3 is another schematic circuit diagram of a ring oscillator according to an embodiment of the present application. As Figure 3 shown, the voltage clamping circuit 220 includes an operational amplifier OP. The first input terminal of the operational amplifier OP is connected to the gate of the first transistor N1, the second input terminal is connected to the first terminal N of the first resistor R0, and the output terminal is connected to the gates of a plurality of PMOS transistors P10 - P13. Optionally, the first input terminal of the operational amplifier OP is the inverting input terminal, and the second input terminal is the non-inverting input terminal. The operational amplifier OP clamps the voltage of the first terminal N of the first resistor R0 to the gate voltage Vgs1 of the first transistor N1 through negative feedback. The operational amplifier OP also provides a bias voltage for the plurality of PMOS transistors P10 - P13.

[0068] As Figure 3 shown, the voltage clamping circuit 220 further includes a resistor R1 and a capacitor C1. The resistor R1 and the capacitor C1 are connected in series between the output terminal of the operational amplifier OP and the first terminal N of the first resistor R0. The resistor R1 and the capacitor C1 are used for Miller compensation.

[0069] According to Figure 3 the ring oscillator shown, the magnitude of the current I0 flowing through the first resistor R0 is Vgs1 / R0, and the control current I osc is proportional to the current I0 flowing through the first resistor R0. The current mirror 210 mirrors the current I0, and the temperature drift characteristics of the transistors P10 - P13 do not affect the control current I oscThe temperature drift characteristic of the control current I osc The temperature drift characteristic of is determined by the temperature drift characteristic of the gate-source voltage Vgs1 of the first transistor N1. Taking I osc = I0 and M = 3 as an example, Figure 3 The expression of the frequency f of the clock signal generated by the ring oscillator shown is as follows.

[0070]

[0071] Since the first transistor and the second transistor have the same temperature drift characteristic, Vgs1 and Vgs2 also have the same temperature drift characteristic. Therefore, the frequency f of the clock signal generated by the ring oscillator has a low temperature drift characteristic. When designing the oscillator, by adjusting the ratio of Vgs1 and Vgs2, temperature compensation is performed to achieve the low temperature drift characteristic of the frequency at -40 to 150 degrees Celsius.

[0072] This application also provides a chip. The chip includes the ring oscillator of the above embodiment. The chip is, for example, a microprocessor MCU. Figure 4 is the structural diagram of an exemplary chip. The chip includes: a memory and the ring oscillator of the above embodiment.

[0073] Due to the influence of factors such as PVT, the actual frequency of the ring oscillator may deviate from the target frequency. Therefore, it is necessary to trim the frequency of the ring oscillator. According to the expression of the frequency f of the clock signal, trimming the control current I osc , the resistance value of the first resistor, and the capacitance value of the first capacitor can achieve trimming of the frequency f. This application provides the following several frequency trimming methods.

[0074] Exemplary Frequency Tuning Method 1

[0075] In some embodiments, the frequency of the ring oscillator is trimmed by trimming the first resistor R0 and the first capacitor. Each of the first capacitors C21, C22, C23 includes m trimming capacitors and m first switches, where m is a positive integer greater than 1. Each trimming capacitor and the corresponding first switch are connected in series to form a trimming branch. In Figure 3 the ring oscillator shown, when the second transistor is an NMOS, the m trimming branches are connected in parallel between the drain terminal of the corresponding second transistor and the ground. The effective capacitance value of the first capacitor depends on the switch states of the respective first switches. The first resistor R0 includes n trimming resistors and n second switches, where n is a positive integer greater than 1. The n trimming resistors are connected in series, and each trimming resistor is connected in parallel with the corresponding second switch. When the second switch is turned on, the corresponding trimming resistor is short-circuited. The n trimming resistors, for example, have different resistance values. The effective resistance value of the first resistor depends on the switch states of the respective second switches.

[0076] Figure 5 is a schematic circuit diagram of a first capacitor according to an embodiment of the present application, Figure 6 and is a schematic circuit diagram of a first resistor according to an embodiment of the present application. In Figure 5 and Figure 6 corresponding embodiments, m = 8, n = 2. The first capacitor includes eight trimming capacitors C 30 , C 40 , C 50 , C 60 , C 70 , C 80 , C 90 , C 100 , and eight first switches K3, K4, K5, K6, K7, K8, K9, K 10 . In some embodiments, the capacitance values of the trimming capacitors C 30 , C 40 , C 50 , C 60 , C 70 , C 80 , C 90 , C 100 are C0, 2C0, 4C0, 8C0, 16C0, 32C0, 64C0, and 128C0 respectively. Optionally, the eight first switches are respectively controlled by binary signals Bit<2>-Bit<9>.

[0077] The first resistor includes two trimming resistors R 10 and R 20 , and two second switches K1 and K2. In some embodiments, the resistance values of the trimming resistors R 10 and R 20 are R 00 and 2R 00 respectively. Optionally, the two second switches are respectively controlled by binary signals Bit<0> and Bit<1>.

[0078] By means of the tunable first capacitor and the first resistor, 2 10 candidate frequency values can be realized, and the candidate frequency value closest to the target frequency value is selected.

[0079] The first switch and the second switch can be a Zener diode, a fuse, a MOSFET switch, etc. Exemplarily, the first switch and the second switch are MOSFET switches, and the binary signals Bit<0>-Bit<9> are stored in the memory of the chip. When the chip is powered on, the first switch and the second switch are controlled to conduct or disconnect according to the binary signals Bit<0>-Bit<9>.

[0080] As described above, the frequency f of the clock signal generated by the ring oscillator is determined by the effective capacitance value of the first capacitor and the magnitude of the control current, and the magnitude of the control current is determined by the effective resistance value of the first resistor. In this embodiment, the change in the frequency f of the clock signal caused by the change in the switching state of one or more of the m first switches is greater than the change in the frequency f of the clock signal caused by the change in the switching state of one or more of the n second switches. That is, the first switch is used for coarse-tuning the frequency f, and the second switch is used for fine-tuning the frequency f. For example, the change in the frequency f of the clock signal caused by the conduction of any one of the first switches is greater than the change in the frequency f of the clock signal caused by the conduction of any one of the second switches. For example, trimming capacitor C 30 The change in the frequency f of the clock signal caused by the conduction of the corresponding first switch K3 is greater than the change in the frequency f of the clock signal caused by the conduction of all two second switches K1 and K2. The binary signals Bit<0> to Bit<9> form a 10-bit binary number. The upper 8 bits of the 10-bit binary number are used to control the first switch, and the lower 2 bits are used to control the second switch. As the value of the 10-bit binary number gradually increases, the frequency f gradually increases or gradually decreases.

[0081] Exemplary Frequency Tuning Method 2

[0082] In some embodiments, the frequency of the ring oscillator is trimmed by trimming the fourth transistor and the first capacitor. Each of the first capacitors C21, C22, and C23 includes m trimming capacitors and m first switches, where m is a positive integer greater than 1. Each trimming capacitor and the corresponding first switch are connected in series to form a trimming branch, and the m trimming branches are connected in parallel between the drain of the corresponding second transistor and the ground. The m trimming capacitors have different capacitance values, for example. The effective capacitance value of the first capacitor depends on the switching state of each first switch. The fourth transistor includes n PMOS trimming transistors and n second switches. The n PMOS trimming transistors are connected in parallel, and the gate of each PMOS trimming transistor is connected to the output terminal of the operational amplifier OP through the corresponding second switch, where n is a positive integer greater than 1. When the second switch is turned on, the PMOS trimming transistor provides a control current to the delay unit. When the second switch is turned off, the PMOS trimming transistor does not provide a control current to the delay unit. The n PMOS trimming transistors have different aspect ratios, for example. The magnitude of the control current provided to the delay unit depends on the switching state of each second switch.

[0083] Figure 5 is a schematic circuit diagram of the first capacitor according to an embodiment of the present application, Figure 7 is a schematic circuit diagram of the fourth transistor according to an embodiment of the present application. In Figure 5 and Figure 7In the corresponding embodiment, m = 8 and n = 2. The first capacitor includes eight trimming capacitors C 30 , C 40 , C 50 , C 60 , C 70 , C 80 , C 90 , C 100 , and eight first switches K3, K4, K5, K6, K7, K8, K9, K 10 . In some embodiments, the capacitance values of the trimming capacitors C 30 , C 40 , C 50 , C 60 , C 70 , C 80 , C 90 , C 100 are C0, 2C0, 4C0, 8C0, 16C0, 32C0, 64C0, and 128C0 respectively. Optionally, the eight first switches are respectively controlled by binary signals Bit<2> to Bit<9>.

[0084] Each of the fourth transistors P11 - P13 includes two PMOS trimming transistors P 100 and P 200 , and two second switches K1 and K2. In some embodiments, the PMOS trimming transistors P 100 and P 200 can respectively provide I0 and 2I0. Optionally, the two second switches are respectively controlled by binary signals Bit<0> and Bit<1>.

[0085] Two 10 candidate frequency values can be implemented through the tunable first capacitor and the fourth transistor, and the candidate frequency value closest to the target frequency value is selected. Exemplarily, the first switch and the second switch are MOSFET switches, and the binary signals Bit<0> - Bit<9> are stored in the memory of the chip. When the chip is powered on, the first switch and the second switch are controlled to conduct or disconnect according to the binary signals Bit<0> - Bit<9>.

[0086] As described above, the frequency f of the clock signal generated by the ring oscillator is determined by the effective capacitance value of the first capacitor and the magnitude of the control current. In this embodiment, the change in the frequency f of the clock signal caused by the change in the switching state of one or more of the m first switches is greater than the change in the frequency f of the clock signal caused by the change in the switching state of one or more of the n second switches. That is, the first switch is used for coarse-tuning the frequency f, and the second switch is used for fine-tuning the frequency f. For example, the change in the frequency f of the clock signal caused by the conduction of any one of the first switches is greater than the change in the frequency f of the clock signal caused by the conduction of any one of the second switches. The binary signals Bit<0> to Bit<9> form a 10-bit binary number. The high 8 bits of this 10-bit binary number are used to control the first switch, and the low 2 bits are used to control the second switch. As the value of this 10-bit binary number gradually increases, the frequency f gradually increases or gradually decreases.

[0087] Exemplary Frequency Tuning Method 3

[0088] In some embodiments, the frequency of the ring oscillator is trimmed by trimming the first resistor R0 and the first capacitor. In this embodiment, m = 7 and n = 3. Figure 8 is a schematic circuit diagram of the first resistor in this embodiment, Figure 9 is a schematic circuit diagram of the first capacitor in this embodiment. The first capacitor includes 7 trimming capacitors C 40 , C 50 , C 60 , C 70 , C 80 , C 90 , C 100 , and 7 first switches K4, K5, K6, K7, K8, K9, K 10 . The first resistor includes 3 trimming resistors R 10 , R 20 , and R 30 , and 3 second switches K1, K2, and K3. Optionally, the first switch and the second switch are controlled by the binary signals Bit<0> to Bit<9>.

[0089] Exemplary Frequency Tuning Method 4

[0090] In some embodiments, the magnitude of the control current is trimmed by trimming the fourth transistor, and thus the frequency of the ring oscillator is trimmed. Figure 10 is a schematic circuit diagram of the fourth transistor in this embodiment. Each of the fourth transistors P11 - P13 includes 10 trimming transistors, and 10 second switches K1 to K 10 . In some embodiments, the currents that the 10 trimming transistors can respectively provide are I0, 2I0... 2 8*I0, 2 9 *I0. Optionally, the ten second switches are respectively controlled by binary signals Bit<0> to Bit<9>. It can be trimmed so that the fourth transistor can provide 2 10 kinds of candidate control current magnitudes, and thus provide 2 10 kinds of frequency values.

[0091] Exemplary Frequency Tuning Method 5

[0092] In some embodiments, the magnitude of the control current is trimmed by trimming the first resistor, and thus the frequency of the ring oscillator is trimmed. Figure 11 is a schematic circuit diagram of the first resistor. The first resistor includes ten trimming resistors and ten second switches K1 to K 10 . In some embodiments, the resistance values of the ten trimming resistors are R0, 2R0, …, 9R0, 10R0 respectively. Optionally, the ten second switches are respectively controlled by binary signals Bit<0> to Bit<9>. Multiple candidate frequency values can be achieved through the trimable first resistor, and the candidate frequency value closest to the target frequency value is selected.

[0093] Exemplary Frequency Tuning Method 6

[0094] In some embodiments, the frequency of the ring oscillator is trimmed by trimming the first capacitor. Figure 12 is a schematic circuit diagram of the first capacitor. The first capacitor includes ten trimming capacitors C 10 to C 100 , and ten first switches K1 to K 10 . Optionally, the ten first switches are respectively controlled by binary signals Bit<0> to Bit<9>. Multiple candidate frequency values can be achieved through the trimable first resistor, and the candidate frequency value closest to the target frequency value is selected.

[0095] In Exemplary Method 4, the control current I osc is changed by trimming the fourth transistor, and thus the frequency of the clock signal is trimmed. In Exemplary Method 5, the control current I osc is changed by trimming the first resistor R0, and thus the frequency of the clock signal is trimmed. However, both of these trimming methods will change the gate-source voltage of the second transistor. If the control current I oscThe variation is relatively large, the variation of the gate-source voltage of the second transistor is relatively large, and the temperature characteristics of the second transistor will also change significantly, which will cause the oscillator to deviate seriously from the set optimal temperature compensation point, resulting in a deterioration of the overall temperature drift characteristic of the oscillator. In the exemplary frequency trimming methods 1-3, a method combining trimming the control current and trimming the first capacitor is adopted. Moreover, the frequency of the clock signal is finely tuned by trimming the control current, and the frequency of the clock signal is coarsely tuned by trimming the first capacitor. In this way, the frequency deviation caused by factors such as PVT can be trimmed, and the offset of the temperature compensation point is minimized as much as possible, ensuring the low temperature drift characteristic of the oscillator.

[0096] In the exemplary method 6, the frequency of the ring oscillator is trimmed by trimming the first capacitor. Trimming the first capacitor does not change the gate-source voltage of the second transistor and maintains the designed optimal temperature drift compensation point. However, the capacitance value of the minimum trimming capacitor in the first capacitor cannot be made very small. The designed minimum trimming capacitor cannot be close to the parasitic capacitance of the oscillator circuit. If the capacitance value of the minimum trimming capacitor is designed to be large, the capacitance values of other trimming capacitors will also increase accordingly, resulting in an increase in the area and power consumption of the trimming circuit. In the exemplary frequency trimming methods 1-3, a method combining trimming the control current and trimming the first capacitor is adopted. Moreover, the frequency of the clock signal is finely tuned by trimming the control current, and the frequency of the clock signal is coarsely tuned by trimming the first capacitor. In this way, the power consumption and area are greatly optimized, and a good temperature drift characteristic can still be maintained. For example, if the exemplary frequency trimming method 6 is used, the first capacitor includes 10 trimming capacitors, the minimum trimming capacitor is 10 fF, and the maximum trimming capacitor is 10240 fF. If the exemplary frequency trimming method 1 is used, the lower 2 bits correspond to the trimming of the first resistor, and the higher 8 bits correspond to the trimming of the first capacitor. The maximum trimming capacitor only needs 2560 fF, and the capacitor area is greatly reduced. When the oscillator circuit is working, the first capacitor is charged and discharged, the capacitor area is reduced, and the power consumption is also reduced.

[0097] Taking the design frequency of 262 KHz and the operating temperature range of -40 to 125 °C as an example, the ring oscillators using the exemplary trimming methods 1-6 are each subjected to 100 Monte Carlo simulations, and the simulation results are shown in Table 1.

[0098] Tuning Bits Minimum Tuning Capacitance Total Current Temperature Drift Exemplary Tuning Method 5 10 / 2.5 μA >1％ Exemplary Tuning Method 4 10 / 2.5 μA >1％ Exemplary Tuning Method 6 10 5 fF 24 μA 0.477％ Exemplary Tuning Method 6 8 10 fF 14 μA 0.638％ Exemplary Tuning Method 1 10 (m = 8, n = 2) 5 fF 6 μA 0.463％ Exemplary Tuning Method 3 10 (m = 7, n = 3) 5 fF 3 μA 0.487％

[0099] Table 1

[0100] As shown in Table 1, trimming the control current using trimming methods 4 and 5 will cause a large temperature drift. Trimming the first capacitor using trimming method 6 will result in a large capacitor area and power consumption. By using trimming methods 1-3, trimming the first capacitor to coarsely adjust the clock signal frequency and trimming the control current to finely adjust the clock signal frequency, better temperature drift characteristics and lower power consumption can be achieved.

[0101] The above are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various modifications and changes can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A ring oscillator, characterized in that, Including: M delay units, where the M delay units are cascaded in sequence to form a loop. The delay unit includes a second transistor and a first capacitor. The control terminal of the second transistor serves as the input terminal of the delay unit, and the first power terminal of the second transistor serves as the output terminal of the delay unit. M is an odd number greater than or equal to 3; and a current generation circuit for generating a control current and supplying it to the M delay units; wherein, the ring oscillator adjusts the frequency of the clock signal output therefrom by simultaneously adjusting the values of the first capacitor and the control current.

2. The ring oscillator according to claim 1, wherein The frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the effective current value of the control current. The change in the frequency of the clock signal caused by adjusting the effective capacitance value of the first capacitor is greater than the change in the frequency of the clock signal caused by adjusting the effective current value of the control current.

3. The ring oscillator according to claim 2, wherein The adjustment signal for adjusting the frequency of the clock signal includes a high-order part and a low-order part. The high-order part is used to adjust the effective capacitance value of the first capacitor, and the low-order part is used to adjust the effective current value of the control current.

4. The ring oscillator according to claim 1, characterized in that, The current generation circuit includes a first transistor, a current source, a first resistor, and a current mirror. Among them, the current source and the first transistor are connected in series, the voltage across the first resistor is clamped to the gate-source voltage of the first transistor, and the current mirror generates the control current based on the current flowing through the first resistor.

5. The ring oscillator according to claim 4, wherein The current mirror includes a plurality of fourth transistors. The control terminals of the plurality of fourth transistors are connected together, the source terminals of the plurality of fourth transistors are connected together, and the first power terminals of the plurality of fourth transistors are respectively coupled to the M delay units.

6. The ring oscillator according to claim 4, characterized in that, The first capacitor includes m trimming capacitors and m first switches. Each trimming capacitor and the corresponding first switch are connected in series to form a branch, and the m branches are connected in parallel, where m is a positive integer greater than 1.

7. The ring oscillator according to claim 6, wherein The m trimming capacitors have different capacitance values.

8. The ring oscillator according to claim 6, characterized in that, The first resistor includes n trimming resistors and n second switches. The n trimming resistors are connected in series, and each trimming resistor and the corresponding second switch are connected in parallel, where n is a positive integer greater than 1.

9. The ring oscillator according to claim 8, wherein, The n trimming resistors have different resistance values.

10. The ring oscillator according to claim 8, characterized in that, The frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the effective resistance value of the first resistor. The change in the frequency of the clock signal caused by the change in the switch state of one or more of the m first switches is greater than the change in the frequency of the clock signal caused by the change in the switch state of one or more of the n second switches.

11. The ring oscillator according to claim 6, wherein The current mirror includes a plurality of fourth transistors, the control terminals of the plurality of fourth transistors are connected together, the source terminals of the plurality of fourth transistors are connected together, the fourth transistor includes n trimming transistors and n second switches, the n trimming transistors are connected in parallel, and the control terminal of each trimming transistor is connected to a bias node through the corresponding second switch, where n is a positive integer greater than 1.

12. The ring oscillator according to claim 11, wherein The n trimming transistors have different aspect ratios.

13. The ring oscillator according to claim 11, characterized in that, The frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the magnitude of the control current. When one or more of the m first switches change their switching states, the change in the frequency of the clock signal is greater than the change in the frequency of the clock signal when one or more of the n second switches change their switching states.

14. The ring oscillator according to claim 1, characterized in that, One end of the first capacitor is coupled to the first power terminal of the second power transistor, and the other end of the first capacitor is connected to the ground or a power supply terminal.

15. The ring oscillator according to claim 4, characterized in that, The first transistor and the second transistor have the same type and temperature drift characteristics.

16. A method for trimming the frequency of a ring oscillator, the ring oscillator includes M delay units, the M delay units are cascaded in sequence to form a loop, the delay unit includes a second transistor and a first capacitor, the control terminal of the second transistor is used as the input terminal of the delay unit, the first power terminal of the second transistor is used as the output terminal of the delay unit, and M is an odd number greater than or equal to 3; and a current generation circuit, the current generation circuit is used to generate a control current and provide it to the M delay units; Among them, The ring oscillator adjusts the frequency of the clock signal output therefrom by simultaneously adjusting the values of the first capacitor and the control current.

17. The frequency trimming method according to claim 16, wherein The frequency of the clock signal generated by the ring oscillator is determined by the effective capacitance value of the first capacitor and the effective current value of the control current. When adjusting the effective capacitance value of the first capacitor, the change in the frequency of the clock signal is greater than the change in the frequency of the clock signal when adjusting the effective current value of the control current.

18. The frequency trimming method according to claim 17, characterized in that, The value of the adjustment signal for trimming the frequency of the clock signal is divided into a high-order part and a low-order part. The high-order part is used to adjust the effective capacitance value of the first capacitor, and the low-order part is used to adjust the effective current value of the control current.

19. The frequency trimming method according to claim 16, wherein The current generation circuit includes a first transistor, a current source, a first resistor, and a current mirror. Among them, the current source and the first transistor are connected in series, the voltage across the first resistor is clamped to the gate-source voltage of the first transistor, and the current mirror generates the control current based on the current flowing through the first resistor.

20. The frequency trimming method according to claim 19, wherein The current mirror includes a plurality of fourth transistors, the control terminals of the plurality of fourth transistors are connected together, the source terminals of the plurality of fourth transistors are connected together, and the first power terminals of the plurality of fourth transistors are respectively coupled to the M delay units.

21. The frequency trimming method according to claim 19, wherein The first capacitor includes m trimming capacitors and m first switches. Each trimming capacitor and the corresponding first switch are connected in series to form a branch, and the m branches are connected in parallel, where m is a positive integer greater than 1.

22. The frequency trimming method according to claim 21, characterized in that, The first resistor includes n trimming resistors and n second switches. The n trimming resistors are connected in series, and each trimming resistor is connected in parallel with the corresponding second switch, where n is a positive integer greater than 1.

23. The frequency trimming method according to claim 22, wherein The frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the effective resistance value of the first resistor. The change in the frequency of the clock signal caused by the change in the switch state of one or more of the m first switches is greater than the change in the frequency of the clock signal caused by the change in the switch state of one or more of the n second switches.

24. The frequency trimming method according to claim 21, wherein The current mirror includes a plurality of fourth transistors. The control terminals of the plurality of fourth transistors are connected together, and the source terminals of the plurality of fourth transistors are connected together. The fourth transistor includes n trimming transistors and n second switches. The n trimming transistors are connected in parallel, and the control terminal of each trimming transistor is connected to a bias node through the corresponding second switch, where n is a positive integer greater than 1.

25. The frequency trimming method according to claim 24, characterized in that, The frequency of the clock signal generated by the ring oscillator depends on the effective capacitance value of the first capacitor and the magnitude of the control current. The change in the frequency of the clock signal caused by the change in the switch state of one or more of the m first switches is greater than the change in the frequency of the clock signal caused by the change in the switch state of one or more of the n second switches.

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