Dynamic self-adaptive network-to-bus cross-network-segment integrated clock synchronization method

Abstract

The invention discloses a cross-network-segment integrated clock synchronization method from a dynamic adaptive network to a bus, which is applied to the technical field of clock synchronization of an airborne bus in an avionics system and aims to solve the problem of transmission uncertainty caused by relatively large jitter of cross-network-segment communication between an adaptive dynamic network and an adaptive bus in the prior art. According to the invention, the transmission from the synchronous clock of the adaptive dynamic network to the adaptive bus is realized by designing a master-slave time service mode of the pulse signal, and the adaptive bus synchronizes other equipment in the system by adopting a mode of transmitting the master clock, so that integrated global clock synchronization across the adaptive dynamic network / the adaptive bus is ensured; and a time reference is provided for cross-network-segment data communication based on time triggering.

Description

Technical Field

[0001] The present invention belongs to the technical field of clock synchronization of on-board buses in avionics systems, and particularly relates to a dynamic adaptive network-to-bus cross-network segment integrated clock synchronization technology. Background Art

[0002] In a network system based on event-triggered communication applied to the avionics field, transmission competition inevitably occurs due to random access of nodes to the transmission channel. The delay and jitter caused by the competition are uncontrollable. For some application scenarios with strict requirements for time safety criticality, this network system cannot be accepted. With the increasing demand for time-critical and safety-critical distributed communication applications in avionics systems, it is urgent to solve the uncertainty of traditional network communication transmission. Time-triggered communication based on network global clock synchronization can well solve the uncertainty and real-time performance of network transmission.

[0003] An adaptive dynamic network is a time-triggered network in a switched interconnection environment. It introduces a high-precision distributed clock synchronization mechanism on the basis of Ethernet, provides contention-free TT communication and efficient ET (Event-Triggered) communication, and ensures the real-time performance and determinacy of different levels of safety-critical tasks in the system. The adaptive dynamic network plans and guides the activities of the entire system according to the consistency arrangement of resource scheduling on the basis of time synchronization, realizes system resource sharing, effectively improves resource utilization rate, and greatly reduces the system design and maintenance costs; the adaptive bus, as one of the key network technologies of the avionics distributed control system, has proved its value in the application verification in the past decade or so. This technology has been widely applied in systems such as aeroengine control, cockpit systems, power management, and flight control. The contention-free time-division multiple access (TDMA) method of the adaptive bus, high-fault-tolerant time synchronization, fast member response, communication monitoring, fast fault detection and isolation, and redundant design solve the bottleneck problems such as weak anti-interference ability and poor fault tolerance of the avionics on-board control system, improve the efficiency and time determinacy of data communication, and make it the first choice for the bus of aircraft safety-critical / mission-critical systems.

[0004] The original mainstream design method of airborne combined network uses the AFDX bus as the avionics backbone network and the 429 bus as the control network, both of which use event-triggered data transmission. A new combined network architecture with an adaptive dynamic network and an adaptive bus is used to replace the above scheme. This new network architecture solves the problem of communication uncertainty within each network system, but there is still a large jitter in the cross-segment communication between the adaptive dynamic network and the adaptive bus, resulting in transmission uncertainty. In the context of the integration and data fusion of airborne systems, the demand for cross-segment data communication may experience a blowout development. Improving the real-time performance and certainty of cross-segment data communication is of great strategic significance. Summary of the Invention

[0005] To solve the above technical problems, the present invention proposes a cross-segment integrated clock synchronization method from a dynamic adaptive network to a bus, which realizes the transfer of the synchronous clock of the adaptive dynamic network to the adaptive bus by designing the master-slave time synchronization method of pulse signals. The adaptive bus uses the method of transmitting the master clock to synchronize other devices in the system, ensuring the integrated global clock synchronization across the adaptive dynamic network / adaptive bus, and providing a time reference for time-triggered data communication across segments.

[0006] The technical solution adopted by the present invention is: a cross-segment integrated clock synchronization method from a dynamic adaptive network to a bus, including an integrated gateway. The gateway includes an adaptive dynamic network controller and an adaptive bus controller. The adaptive dynamic network controller and the adaptive bus controller in the gateway device use the master-slave time synchronization method of pulse signals to transmit the synchronous clock of the adaptive dynamic network to the adaptive bus as the master clock for bus synchronization, and other devices of the adaptive bus are synchronized to this master clock source; the clocks of the adaptive dynamic network and the adaptive bus network are synchronized to a unified global clock across segments.

[0007] The airborne system includes adaptive dynamic network segments of various constructed synchronization domains; in the same adaptive dynamic network synchronization domain, the adaptive dynamic network controllers in all gateway devices maintain the same global clock;

[0008] The adaptive dynamic network controller and the adaptive bus controller are interconnected using the I / O of the FPGA.

[0009] The synchronous clock mechanism of the adaptive dynamic network is designed and implemented according to the SAE AS6802 standard.

[0010] The master-slave time synchronization includes three pulse mechanisms, specifically: a forward pulse for periodically transmitting synchronous time point information, a reverse pulse for trigger-based reverse measurement, and a forward response pulse for responding to the reverse pulse;

[0011] When the adaptive bus controller first collects a positive pulse, it starts the cycle counting of the local synchronous clock. The counting time point of the local synchronous clock is set to the zero time point of the synchronous clock counting + the average pulse delay + the statistical calculation delay, and the synchronous clock cycle counting begins;

[0012] The local synchronous clock starts cycle counting. Compare the counting time point of the local synchronous clock with (the average pulse delay + the statistical calculation delay). If they are equal, the local timing is not adjusted. If there is a difference, it will jump to the time point of (the average pulse delay + the statistical calculation delay + 1) in the next cycle.

[0013] The beneficial effects of the present invention: The present invention designs a unified clock synchronization design method for an adaptive dynamic network to an adaptive bus across network segments, realizing unified clock synchronization across network segments between an adaptive dynamic network as the backbone network of an avionics system and an adaptive bus as the bus of an airborne control system of an aircraft. It provides a unified global clock for time-triggered communication across network segments, which has great significance for realizing a unified network for time-triggered communication in an avionics system and promoting the strategic development of the integration of avionics bus networks. This design method greatly enriches the methods for users in the selection of airborne network clock synchronization and other links of an avionics system, and provides high-precision clock synchronization across network segments. At the same time, the application of the present invention is independent of the hardware platform, has a wide range of applications, and has significant market prospects and economic benefits. Brief Description of the Drawings

[0014] Figure 1 It is the unified clock source adopted by the adaptive dynamic network controller and the adaptive bus controller in the gateway;

[0015] Figure 2 It is the three pulse mechanisms between the designed adaptive dynamic network controller and the adaptive bus controller;

[0016] Figure 3 It is the processing schematic diagram of the positive pulse collected by the adaptive bus controller. Detailed Embodiment

[0017] To facilitate those skilled in the art to understand the technical content of the present invention, the content of the present invention will be further explained below with reference to the accompanying drawings.

[0018] In the traditional design method of cross-network communication in the field of airborne electronic communication, the AFDX bus is used as the avionics backbone network and the 429 bus is used as the control network, which can no longer meet the application requirements of high real-time and high-determinacy data communication in airborne systems. A new type of adaptive dynamic network is used to construct the avionics backbone network and the adaptive bus is used as the bus for control systems such as flight control, electromechanics, and power supply, which solves the problems of real-time and determinacy of communication within subsystems. However, there is still a large jitter in cross-network communication, resulting in transmission uncertainty. In the context of the integration and data fusion of airborne systems, there are a large number of application requirements for data communication between cross-network systems. Based on ensuring high-precision time synchronization within the adaptive dynamic network and adaptive bus network systems, a clock synchronization design method for cross-network of adaptive dynamic network / adaptive bus based on time-triggered architecture is proposed. This design method provides a global clock synchronization function for cross-network integration, providing a time basis for time-triggered communication across airborne buses. This design method can be transplanted into a combined network system of adaptive dynamic network and other time-triggered networks to achieve high-precision clock synchronization for cross-network integration, providing a global clock for time-triggered communication across such cross-networks, such as network systems combining adaptive dynamic network and TTCAN, and combining switched adaptive dynamic network and bus-type adaptive dynamic network.

[0019] The present invention designs a method for unified clock synchronization from an adaptive dynamic network to an adaptive bus across network segments. The core of this method is to use the synchronization clock constructed by the adaptive dynamic network and transfer it to the adaptive bus as the main clock source, and other devices of the adaptive bus are synchronized to this main clock source, synchronizing the respective clocks of the adaptive dynamic network and the adaptive bus network to a unified global clock across network segments, providing a time-triggered global clock basis for data transmission between the adaptive dynamic network and the adaptive bus across network segments. Through the master-slave timing method of pulse signals between two controllers in the gateway device in the present invention, the synchronization clock of the adaptive dynamic network is transferred to the adaptive bus as the main synchronization clock of this bus, and the adaptive bus uses the method of the present invention to achieve clock synchronization inside the adaptive dynamic network controller and the adaptive bus controller in the gateway device, achieving the global clock synchronization function across network segments.

[0020] The present invention does not innovate in the clock synchronization of the adaptive dynamic network. The synchronization clock mechanism of the adaptive dynamic network is designed and implemented according to the internationally released SAE AS6802 standard. Under this synchronization mechanism, the synchronization clock established and maintained by the adaptive dynamic network controller has a precision of microseconds and has fault tolerance, providing a highly reliable synchronization clock source for cross-network integrated clock synchronization. In an airborne system, various adaptive dynamic network segments of synchronization domains may be constructed, and all adaptive dynamic network controllers in gateways within the same adaptive dynamic network synchronization domain maintain the same global clock.

[0021] In the present invention, an integrated gateway design is proposed, and this gateway plays an important role in the present invention.

[0022] As Figure 1 shown, the adaptive dynamic network controller and the adaptive bus controller in the gateway adopt a unified clock source. Based on this same-source clock design, it is ensured that the rising edge and falling edge of each pulse are in-phase aligned, avoiding the situation that two controllers use different crystal oscillators as clock sources, where the clock drift rates are different, resulting in synchronous clock deviation, and the uncertainty of the pulse signal transmission delay between the two controllers.

[0023] In the gateway, the adaptive dynamic network controller and the adaptive bus controller are interconnected through the I / O of the FPGA. The synchronization period spans of the adaptive dynamic network and the adaptive bus are defined to be the same, and three pulse mechanisms between the adaptive dynamic network controller and the adaptive bus controller are designed, as Figure 2 shown:

[0024] 1) The forward pulse is a pulse that periodically transmits synchronous time point information;

[0025] 2) The reverse pulse is a trigger-type reverse measurement pulse;

[0026] 3) The forward response pulse is a forward pulse that responds to the reverse pulse.

[0027] The three positive and reverse pulses are designed with the same frequency; based on this same-frequency basis, a frequency multiplication design is used to achieve the sampling frequencies of the three pulses.

[0028] When the adaptive dynamic network is in a synchronous state, the adaptive dynamic network controller in the gateway generates periodic pulses to transmit the synchronous cycle timing time points. The synchronous clock of the adaptive dynamic network controller counts cyclically according to the synchronous cycle, and generates a pulse signal at the synchronous zero time point of each cycle timing period, that is, the forward pulse is transmitted to the adaptive bus controller through the I / O connection; the synchronous clock of the adaptive dynamic network controller then counts cyclically in the same cycle mode after receiving the forward pulse for the first time; before the adaptive bus controller powers on and collects the I / O pulse signal for the first time and during the periodic collection process during operation, the adaptive bus controller actively sends a reverse pulse, and the adaptive dynamic network controller collects the reverse pulse through the frequency multiplication collector, and triggers a forward response pulse within the same frequency multiplication cycle through the frequency multiplication trigger, realizing seamless connection of the collection and trigger in the same cycle. The adaptive bus controller collects the forward response pulse, statistically calculates the handshake response non-frequency multiplication clock cycle between the trigger reverse pulse edge and the collected forward response pulse edge, and the average pulse delay corresponding to this non-frequency multiplication clock cycle, as well as statistically calculates the consumed non-frequency multiplication clock cycle; when the adaptive bus controller collects the forward pulse, it is processed in two ways, asFigure 3 as shown in

[0029] 1) When a positive pulse is first collected, start the periodic cyclic timing of the local synchronous clock. The timing moment of the local synchronous clock is set as the synchronous clock timing zero moment + pulse delay average value + statistical calculation time delay, and start the synchronous clock cycle timing;

[0030] 2) The local synchronous clock starts periodic cyclic timing, compares the timing moment of the local synchronous clock with (pulse delay average value + statistical calculation time delay), if they are equal, do not adjust the local timing, if there is a difference, then jump to the moment of (pulse delay average value + statistical calculation time delay + 1) in the next cycle.

[0031] Through the master-slave time synchronization method in the form of the above pulses, set the synchronous clock of the adaptive dynamic network as the master clock source of the adaptive bus, and complete the clock transfer across network segments.

[0032] In the static configuration of the adaptive bus, set the adaptive bus controller in the gateway as the cold start node of the bus. The cold start node sends the master clock information to other nodes through the cold start frame for integrated synchronization. The cross-network segment clock synchronization method of the present invention does not limit the number of gateway devices. The master clock source information provided by different gateway devices all comes from the adaptive dynamic network of the same clock domain, which can be used for the average calculation of the adaptive bus clock slave device, improving the synchronization accuracy and synchronization fault tolerance ability. The clock information received by the slave device for averaging comes from the high-precision global clock of the same network.

[0033] Construct a time state update parameter model between the adaptive bus controller in the gateway device and other slave device nodes of the adaptive bus to indicate the clock offset and clock slope between the two devices:

[0034] 1) θ(t n +Δt) = θ(t n ) + γ(t n )·τ + ω θ (t n +ΔT) clock offset model

[0035] τ represents a certain period of time during operation;

[0036] 2) γ(t n +△T) = γ(t n ) + ω γ (t n +△T) clock slope

[0037] θ(t n ) and θ(t n +△T) represent the local clock and the clocks of other devices at the given synchronization moment point t in each cyclen and t n + △T clock deviation; γ(t n ) and γ(t n + △T) as t n and t n + △T time point of clock frequency drift;.ω θ (t n + △T) and ω γ (t n + △T) represent the noise of random offset and drift.

[0038] The reception time point of the gateway device (B) received from the slave clock device (A) can be expressed as follows:

[0039]

[0040] , t0 represents the pulse start time point, γ cp represents the clock slope, ω(Δt) represents the noise of random offset and drift, and represents the first time point within the synchronization period, Δcompcorr i represents the time calculation value of the received master clock pulse, represents the pulse processing technology delay of device B, δ BA,i represents the pulse transmission time between devices A and B, and f represents the number of tolerable failed pulses in different gateway devices.

[0041] According to the fact that the clock offset and skew of the slave clock device are time-varying, the tracking and optimal estimation of clock parameters are realized through distributed Kalman filtering. Based on the design of the clock synchronization periodic synchronization mode, sampling is designed at time intervals of the synchronization period:

[0042]

[0043] T1 represents the pulse period time.

[0044]

[0045] θ BA (n) and γ BA (n) represent the deviation and slope between the local clock of the slave clock device and the average clock of each gateway device.

[0046] Design a Kalman filtering algorithm for the gateway device and the slave device to obtain the above clock synchronization clock deviation. In each cycle synchronization of the system, the filtering calculation is repeated to evaluate the clock deviation, clock drift, and clock drift rate of change of the slave device. The clock deviation is compensated through the evaluation value, and at the same time, the clock model parameters of the slave device are corrected.

[0047] Based on the parameters obtained by the slave device through Kalman filtering during the synchronous operation cycle, the local clock parameter model is corrected, and a smaller precise clock deviation between the gateway device and the slave device is obtained within each synchronous cycle. The average algorithm for correcting the slave device clock can be simply designed as follows:

[0048] 1) Calculate the difference between the actual reception time point of the slave device and the predetermined reception time point. The predetermined reception time point is obtained from the transmission delay measurement of the adaptive bus controller and other slave device nodes on the adaptive bus. The predetermined reception time point is equal to the transmission time point plus the measured transmission delay, and calculate the difference Inputi between the local clocks of each gateway device and the slave device; when there is only a single gateway device connected, no averaging calculation is performed;

[0049] The transmission delay measurement, that is, the predetermined reception time point, is the average value of the transmission delays of the adaptive bus controller and other slave device nodes on the adaptive bus;

[0050] 2) Calculate the average value of the clock deviation:

[0051] Offsetavr1 = Input1;

[0052] Offsetavr2 = (Input1 + Input2) / 2;

[0053] Offsetavri = (Input1 + … + Inputi) / i.

[0054] 3) Perform slave clock correction according to Offset. The slave clock correction criterion:

[0055] When Offset is zero, it means that there is no deviation between the master and slave clocks, and no correction is required;

[0056] When Offset is positive, it means that the slave clock is faster than the master clock, and the local clock of the slave device is rolled back by Offset;

[0057] When Offset is negative, it means that the slave clock is slower than the master clock, and the local clock of the slave device is advanced by Offset.

[0058] This average algorithm has a certain fault tolerance function, allowing the clock synchronization of the network to be continued in the case of the failure of the gateway node of the adaptive bus network. When there is only one cold start node of the gateway in the adaptive bus network in the same clock synchronization domain, synchronization can be completed without averaging.

[0059] The original mainstream design method of airborne combined networks uses a new combined network architecture that adapts to dynamic networks and adaptive buses for data transmission. This network architecture solves the communication uncertainty problem within each network system, but there is still significant jitter in the communication between the adaptive dynamic network and the adaptive bus across network segments, resulting in transmission uncertainty.

[0060] Those of ordinary skill in the art will realize that the embodiments described herein are for helping the reader understand the principles of the present invention and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. For those skilled in the art, various changes and modifications can be made to the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of the claims of the present invention.

Claims

1. A dynamic adaptive network-to-bus cross-network segment integrated clock synchronization method, characterized in that It includes an integrated gateway, in which there is an adaptive dynamic network controller and an adaptive bus controller. The adaptive dynamic network controller and the adaptive bus controller in the gateway device use the master-slave timing method of pulse signals to transmit the synchronous clock of the adaptive dynamic network to the adaptive bus as the master clock source of the bus, and other devices on the adaptive bus are synchronized to this master clock source; thus, the clocks of the adaptive dynamic network and the adaptive bus network are synchronized to a unified global clock across network segments.

2. The dynamic adaptive network-to-bus cross-segment integrated clock synchronization method according to claim 1, wherein The adaptive dynamic network controller and the adaptive bus controller are interconnected using the I / O of FPGA.

3. The dynamic adaptive network-to-bus cross-network segment integrated clock synchronization method according to claim 2, characterized in that, It also includes the constructed adaptive dynamic network segments of various synchronization domains; in the same adaptive dynamic network synchronization domain, the adaptive dynamic network controllers in all gateway devices maintain the same global clock.

4. A dynamic adaptive network-to-bus cross-segment integrated clock synchronization method according to claim 3, characterized in that, The synchronous clock mechanism of the adaptive dynamic network is designed and implemented according to the SAE AS6802 standard.

5. A dynamic adaptive network-to-bus cross-segment integrated clock synchronization method according to claim 4, characterized in that The master-slave timing includes three pulse mechanisms, specifically: a forward pulse for periodically transmitting synchronous time point information, a reverse pulse for trigger-based reverse measurement, and a forward response pulse for responding to the reverse pulse; The adaptive bus controller's acquisition of the large forward pulse includes the following two processing methods: When the adaptive bus controller first acquires the forward pulse, it starts the periodic cycle timing of the local synchronous clock. The timing time point of the local synchronous clock is set to the synchronous clock timing zero time point + pulse delay average value + statistical calculation delay, and starts the synchronous clock cycle timing; Compare the timing time point of the local synchronous clock with (pulse delay average value + statistical calculation delay). If they are equal, do not adjust the local timing. Otherwise, jump to the time point of (pulse delay average value + statistical calculation delay + 1) in the next cycle.

6. A dynamic adaptive network-to-bus cross-segment integrated clock synchronization method according to claim 5, characterized in that, It also includes: Construct a time state update parameter model for the adaptive bus controller in the gateway device and other slave device nodes on the adaptive bus to indicate the clock offset and clock slope between the two devices; According to the fact that the clock offset and skew of the slave clock device are time-varying, use distributed Kalman filtering to achieve the tracking and optimal estimation of the clock parameters, and obtain the clock deviation, clock drift, and clock drift rate of change of the slave device; Compensate the clock deviation according to the estimated value, and at the same time correct the clock model parameters of the slave device.

7. A dynamic adaptive network-to-bus cross-segment integrated clock synchronization method according to claim 6, characterized in that The process of correcting the slave device clock is as follows: 1) Calculate the difference between the actual reception time point of the slave device and the predetermined reception time point. The predetermined reception time point is obtained from the transmission delay measurement between the adaptive bus controller and other slave device nodes on the adaptive bus. The predetermined reception time point is equal to the transmission time point plus the measured transmission delay, and calculate the difference Inputi between the local clocks of each gateway device and the slave device; when there is only a single gateway device connected, no average calculation is performed; 2) Calculate the average value of the clock deviation: Offsetavr1 = Input1; Offsetavr1 represents the clock deviation of the first slave device; Offsetavr2 = (Input1 + Input2) / 2; Offsetavr1 represents the clock deviation of the second slave device; Offsetavri = (Input1 + … + Inputi) / i; Offsetavr1 represents the clock deviation of the i-th slave device; 3) Perform slave clock correction according to Offset, and the slave clock correction criterion is as follows: A clock deviation of zero means that there is no deviation between the master and slave clocks, and no correction is required; A positive clock deviation means that the slave clock is faster than the master clock. Based on this clock deviation, the local clock of the slave device counts time backwards; A negative clock deviation means that the slave clock is slower than the master clock. Based on this clock deviation, the local clock of the slave device counts time forward.

Images