FPGA-based nuclear power multi-device time synchronization and soe recording system

Abstract

The application discloses a kind of nuclear power multi-device time synchronization and SOE recording system based on FPGA, it is related to time synchronization technical field, the system includes: control station, the equipment module in control station includes first controller, second controller and IO module, IO module includes DI module, DI module is divided into DI general acquisition module and DI-SOE module;First controller and second controller select a road from two-way time information as output time information;First controller or second controller updates local time according to the selected time information, sends time slot broadcast time information to IO module every bus cycle;After IO module receives time slot broadcast time information, update local time;DI-SOE module updates local time using the time information obtained in the last time slot of time slot broadcast time information, can realize nuclear power multi-device time synchronization, while improve the time accuracy of recording SOE event.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of time synchronization, in particular to a nuclear power multi-device time synchronization and SOE recording system based on FPGA. BACKGROUND

[0002] In a nuclear power plant digital instrument control system (DCS), the role of the sequence of event (SOE) is to record the time and sequence of switch actions when an accident occurs, providing an important basis for accident cause analysis. Through effective management and maintenance of SOE data, the sequence of each important signal can be distinguished, especially the first fault, so that faults can be diagnosed and eliminated in time to ensure normal operation of the system.

[0003] The resolution of a nuclear power plant digital instrument control system is generally 1ms. According to the conventional design method, a pulse source generates a pulse signal to the SOE acquisition module. The pulse source device records the time jump second level moment, and the SOE acquisition device records the data millisecond level moment. The actual signal occurrence time is obtained by adding the two data. The acquisition device records the millisecond level moment and data by acquiring the pulse per second (PPS) signal. After the acquisition data bus is transmitted to the controller, the controller module timestamps the acquisition data. Thus, there is a deviation in the time accuracy. If the sampling device does not receive the PPS pulse, there will be a problem of recording time error. At the same time, the time delay of the PPS pulse received by multiple devices makes the reference of multiple devices inconsistent, ultimately leading to inaccurate SOE recording time. SUMMARY

[0004] The purpose of the present application is to provide a nuclear power multi-device time synchronization and SOE recording system based on FPGA, which can realize nuclear power multi-device time synchronization and improve the time accuracy of SOE event recording.

[0005] To achieve the above purpose, the present application provides the following solutions:

[0006] The present application provides a nuclear power multi-device time synchronization and SOE recording system based on FPGA, which comprises a control station. The device modules in the control station comprise a first controller, a second controller and an IO module. The IO module comprises a DI module, which is divided into a DI general acquisition module and a DI-SOE module. Each device module adopts FPGA.

[0007] The first controller and the second controller both collect two time signals, and parse each time signal into time information; the first controller and the second controller both select one time information from the two time information, and send the selected time information through two local buses in each bus cycle by time slot broadcasting;

[0008] The first controller and the second controller both update local time according to the corresponding selected time information, and start local time self-keeping;

[0009] The IO module is used to select redundancy after receiving each time slot broadcasting time information, and update local time by time information of 0 time slot parsed from the selected time information, and start local time self-keeping;

[0010] The DI-SOE module is used to collect SOE events, and update local time by time information of the last time slot of the selected time information, and start local time self-keeping, and use local time after self-keeping as recording time when collecting SOE events.

[0011] Optionally, the FPGA-based nuclear power multi-device time synchronization and SOE recording system further comprises an engineer station.

[0012] The engineer station is used to send configuration information of multi-device module configuration to the control station; and the configuration information is used to distinguish each DI module into a DI general collection module or a DI-SOE module.

[0013] Optionally, the two time signals collected by the first controller and the second controller are both IRIG-B codes.

[0014] Optionally, in terms of selecting one time information from the two time signals, the first controller or the second controller is specifically used for:

[0015] judging whether the first time information is normal to obtain a first judgment result; the two time information are respectively the first time information and the second time information;

[0016] If the first judgment result is yes, the first time information is taken as the selected time signal;

[0017] If the first judgment result is no, a second judgment result is obtained by judging whether the second time information is normal;

[0018] If the second judgment result is yes, the second time information is taken as the selected time signal;

[0019] If the second determination result is no, the time information is not selected.

[0020] Optionally, the first controller, the second controller and the IO module are self-kept time by local crystal oscillator in terms of local time.

[0021] Optionally, the DI-SOE module includes a plurality of DI channels, and SOE events collected by each DI channel are stored in a first-in first-out queue according to the order of occurrence of the SOE events.

[0022] Optionally, the DI-SOE module and the DI general collection module share bus bandwidth of a local bus.

[0023] Optionally, the bus bandwidth is 64 bytes.

[0024] The 32 DI channels in the DI-SOE module occupy 64 bytes, the first 8 bytes are switch value and quality information of the 32 DI channels, and the last 56 bytes are SOE events.

[0025] The DI general collection module includes 32 channels, and each channel is stored according to 2 bytes.

[0026] Each SOE event is 8 bytes, and each SOE event includes time information, time mark, channel value, quality bit and channel number.

[0027] Optionally, the device module further includes a communication module.

[0028] The communication module is used to receive each time slot broadcast time information and perform redundancy selection, update local time by time information of 0 time slot parsed from the selected time information, and start local time self-keeping.

[0029] Optionally, the first controller and the second controller communicate by S_LINK synchronization.

[0030] According to the specific embodiments provided in the application, the application discloses the following technical effects: the application provides a nuclear power multi-device time synchronization and SOE recording system based on FPGA, the first controller and the second controller both collect two-way time signals, and analyze each way of time signals into time information; the first controller and the second controller both select one way of time information from the two-way time information, and send the selected one way of time information through two-way local buses in each bus cycle; the two controllers both update local time according to the corresponding selected one way of time information, and start local time self-keeping; so that the input output (Input Output, IO) module receives redundant time information, and improves the reliability of time synchronization; the DI-SOE module is used for collecting SOE events, the DI-SOE module obtains time information in the last time slot of the selected one way of time information, and updates local time, starts local time self-keeping, and collects SOE events by using local time after local time self-keeping, that is, the application improves the time accuracy of recording SOE events by using redundant time information, in addition, the system of the application realizes multi-device time synchronization based on the hardware architecture of field programmable gate array (Field Programmable Gate Array, FPGA) technology, does not depend on microprocessors and software, improves the reliability of time synchronization, and improves the time accuracy of recording SOE events. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed in the embodiments. Obviously, the drawings in the following description are only some embodiments of the application, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0032] Figure 1 A structure schematic diagram of a nuclear power multi-device time synchronization and SOE recording system based on FPGA provided by an embodiment of the application.

[0033] Figure 2 A redundant B code hardware design schematic diagram provided by an embodiment of the application.

[0034] Figure 3 A controller time collection and L-BUS sending schematic diagram provided by an embodiment of the application.

[0035] Figure 4 A time receiving and time synchronization schematic diagram of other modules in a control station provided by an embodiment of the application.

[0036] Figure 5A method for bus sharing of a nuclear power multi-device time synchronization and SOE recording system based on FPGA is provided for an embodiment of the present application.

[0037] Figure 6 A bus sharing allocation diagram of a DI-SOE module is provided for an embodiment of the present application.

[0038] Figure 7 A bus sharing allocation diagram of a DI general acquisition module is provided for an embodiment of the present application.

[0039] Figure 8 A bus sharing allocation example diagram of a DI-SOE module is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0041] The above purposes, features and advantages of the present application will be more apparent and understandable. The present application will be described in further detail below with reference to the drawings and specific embodiments.

[0042] In an exemplary embodiment, the present application provides a nuclear power multi-device time synchronization and SOE recording system based on FPGA, as shown in the following figure. Figure 1 The nuclear power multi-device time synchronization and SOE recording system based on FPGA includes a control station, wherein the device modules in the control station include a first controller, a second controller, a communication module and an IO module, the IO module includes a digital input (Digital Input, DI) module, the DI module is divided into a DI general acquisition module and a DI-SOE module, that is, the DI module is either a DI general acquisition module or a DI-SOE module. The first controller is a controller (0 slot) in Figure 1 , and the second controller is a controller (1 slot) in Figure 1 . Each of the device modules uses FPGA.

[0043] The IO module further includes a digital output (Digital Output, DO) module, an analog input (Analog Input, AI) module, an analog output (Analog Output, AO) module, a pulse input (Pulse Input, PI) module and a pulse output (Pulse Output, PO) module.

[0044] The first controller and the second controller both collect two time signals, and parse each time signal into time information; the first controller and the second controller both select one time information from the two time information, and send the selected time information through two local buses (L_BUS) in each bus cycle.

[0045] The first controller and the second controller both update local time according to the corresponding selected time information, and start local time self-keeping.

[0046] The IO module is used to receive each time slot broadcast time information, and update local time by using the time information of 0 time slot parsed from the selected time information, and start local time self-keeping. More specifically, the IO module receives two time information broadcast through two local buses, and receives four time information through the two local buses, and selects one time information from the four time information, and if there is no normal time information in the four time information, no time information is selected.

[0047] The communication module is used to receive each time slot broadcast time information, and update local time by using the time information of 0 time slot parsed from the selected time information, and start local time self-keeping.

[0048] The DI-SOE module is used to collect SOE events, and update local time by using the time information of the last time slot parsed from the selected time information, and start local time self-keeping, and use the local time after self-keeping as the recording time when collecting SOE events.

[0049] In an exemplary embodiment, the FPGA-based nuclear power multi-device time synchronization and SOE recording system further comprises an engineer station.

[0050] The engineer station is used to send configuration information of the multi-device module to the control station, and the configuration information is used to distinguish each DI module into a DI general collection module or a DI-SOE module.

[0051] In the download mode, the engineer station sends configuration information.

[0052] After the download is completed, the mode is switched to the running mode, and according to the configuration information, the DI module is configured into a DI general collection module or a DI-SOE module.

[0053] The application realizes DCS multi-device time synchronization, SOE event recording, general switch value acquisition and SOE acquisition bus sharing in the field of nuclear industry control. The method is a method for nuclear power DCS multi-device time synchronization based on FPGA technology, DI general acquisition module and DI-SOE module bandwidth sharing, that is, in the DCS control system in the field of nuclear industry control, users can configure through the engineer station according to application requirements to realize time synchronization of mixed plug-in configuration of all device modules (including general acquisition modules and SOE modules) in the control station.

[0054] The function of the FPGA-based nuclear power multi-device time synchronization and SOE recording system of the application is realized by using the hardware chip of FPGA and the corresponding programming language of FPGA.

[0055] In an exemplary embodiment, the two-way time signals collected by the first controller and the second controller are both IRIG-B codes.

[0056] In an exemplary embodiment, in terms of selecting one-way time information from the two-way time signals, the first controller or the second controller is specifically configured to: 1) determine whether the first-way time information is normal to obtain a first determination result; the two-way time information is respectively the first-way time information and the second-way time information. 2) If the first determination result is yes, the first-way time information is selected as the one-way time signal. 3) If the first determination result is no, determine whether the second-way time information is normal to obtain a second determination result. 4) If the second determination result is yes, the second-way time information is selected as the one-way time signal. 5) If the second determination result is no, no time information is selected.

[0057] Whether the first-way time information is normal and whether the second-way time information is normal is determined according to the width of the code source and whether there is a code source.

[0058] If there is no code source for the first-way time information, it is determined that the first-way time information is abnormal,

[0059] If there is a code source for the first-way time information and the code source of the first-way time information is within a preset width range, it is determined that the first-way time information is normal, otherwise it is determined that the first-way time information is abnormal. The method for determining whether the second-way time information is normal is the same as the method for determining the second-way time information.

[0060] In an exemplary embodiment, in terms of local time self-keeping, the first controller, the second controller, the communication module and the IO module are all self-kept by local crystal oscillators.

[0061] In an exemplary embodiment, the DI-SOE module includes a plurality of DI channels, and the SOE events collected by the DI channels are stored in a First Input First Output (FIFO) queue according to the order of occurrence of the SOE events.

[0062] In an exemplary embodiment, the DI-SOE module and the DI general collection module share bus bandwidth.

[0063] In an exemplary embodiment, the bus bandwidth is 64 bytes.

[0064] The 32 DI channels in the DI-SOE module occupy 64 bytes, the first 8 bytes are switch value collection values and quality information of the 32 DI channels, and the last 56 bytes are SOE events. The quality information is a quality bit.

[0065] The DI general collection module includes 32 channels, and each channel is stored according to 2 bytes.

[0066] In an exemplary embodiment, each SOE event is 8 bytes, and each SOE event includes time information, time mark, channel value, quality bit, and channel number.

[0067] In an exemplary embodiment, the online controller communicates with the IO module through a local bus, and the first controller and the second controller communicate synchronously through a redundant synchronization link (Synchronization Link, S_LINK).

[0068] The control station also includes a maintenance interface module. The engineer station communicates with the maintenance interface module through a maintenance link communication protocol (Maintenance Network, M-NET), and the engineer station is used to send a download package and a maintenance package to the maintenance interface module, and the download package includes configuration information. The modules in the control station communicate through a local maintenance communication bus (Maintenance-Bus, M-BUS).

[0069] In an exemplary embodiment, the application provides a working process of a nuclear power multi-device time synchronization and SOE recording system based on FPGA as follows.

[0070] First, after the system is powered on, the user performs mixed device module configuration on the engineer station according to system requirements, and the mixed device module includes a first controller, a second controller, a communication module, an IO module (DI, DO, AI, AO, PI, PO), wherein the DI module can be configured into a DI general collection module or a DI-SOE module (a module for collecting SOE events) through configuration, and configuration information is generated.

[0071] Second step, in the download mode, the engineer station issues the configuration information mentioned above,

[0072] Third step, after the download is completed, the mode is switched to the running mode, all modules in the system are powered on and initialized, and the configuration information of the engineer station mentioned above is obtained, wherein the DI module needs to judge whether it is a DI-SOE acquisition module or a DI general acquisition module, and the DI module has 32 channels.

[0073] Fourth step, after the initialization of all the modules mentioned above is completed, the redundant controller collects the redundant clock source signal, and the redundant controller includes a first controller and a second controller, as shown in Figure 2 That is, the redundant IRIGB code (IRIGB0 and IRIGB1) is connected to the controller A slot (0 slot) and the controller B slot (1 slot), and the physical layer is RS485. The time information analysis and sending of the first controller or the second controller is as shown in Figure 3 After the redundant controller receives the two-way IRIGB signal, it selects and processes the time information in each cycle and sends the time information in the time slot on the L-BUS (the communication bus of the controller module, the communication module and the IO module). The L-BUS is the communication bus of the controller and the communication module, and the controller and the IO module. The controller A is the first controller, and the controller B is the second controller.

[0074] 1. After the redundant controller receives the two-way IRIGB signal, the two-way IRIGB time information is analyzed by the IRIGB code (B code) analysis module.

[0075] 2. The analyzed time information is selected by the redundancy selection module, and the time information t0 is output. The selection and output principle is: the two-way time information is represented as A and B, if A is normal, A is selected, otherwise, B is checked, if B is normal, B is selected; if both are incorrect, no time information is output.

[0076] The time state information includes: 1) after power-on, no B code has been received so far. 2) after power-on, B code has been received, the normal or abnormal state of the current A and B.

[0077] 3. The time information t0 output by the first controller and the second controller enters the self-keeping time module, and the time and the self-keeping time t1 are updated. The self-keeping time module outputs two-way time information through two-way local bus, and the time information output by the self-keeping time module and the two-way local bus is accurate to the microsecond (us) level. Like other IO modules, the time information is ensured to be available and reliable through the redundant local bus.

[0078] 1) after power-on, no time information is received, the current time is all 0, and the output time information t1 is 0.

[0079] 2) After power on, receive time information t0, update according to B code second, update time is time information t0, start self-keeping time t1.

[0080] 3) After power on, receive time information sent by first controller and second controller, B code disconnection, output time is t1'.

[0081] 4, t1 time is sent on L-BUS sending end (TX) module.

[0082] Controller sends time information through L-BUS bus every period, when it is controller A, at time slot 0, get current self-keeping time information t1, send it on L-BUS ACK frame, that is, send it on L-BUS ACK0. When it is controller B, get current self-keeping time information t1, send it on L-BUS ACK frame at time slot 12. ACK frame is a control frame used for confirming successful reception of data frame in computer network. According to control station pre-defined time slot technology, sending time slot of a controller is 0~11, total 12 time slots; therefore, controller B is designed to send at the 12th time slot (L-BUS ACK12).

[0083] When time information sent by ACK frame is 0, it means not to time.

[0084] Fifth step, time information receiving and analysis synchronization of other modules (communication module, IO module) in control station, such as Figure 4 .

[0085] 1) After power on initial success of other modules (communication module, IO module) in control station, receive L-BUS data of controller, join token bus ring, and analyze received redundant L-BUS ACK time information t1 of controller A at time slot 0.

[0086] 2) Analyzed time information t1 is selected by redundant selection module, select one way of time information t1, and output time state information.

[0087] 3) The above time information t1 enters self-keeping time module (time information is accurate to us level), if time is valid, update current time as time information t1, start self-keeping time t2 with local crystal oscillator.

[0088] 4) For DI-SOE module, local time self-keeping time module gets time information t2 at the last time slot of L-BUS bus period, updates local time, starts local time self-keeping time t3, and provides time for SOE channel. Local time is accurate to us level.

[0089] The DI module is configured as a DI-SOE acquisition module, the DI channel is used for acquiring SOE events, and SOE events acquired by each channel are stored in a FIFO queue in the order of event occurrence.

[0090] The bus shared bandwidth is designed as 64 bytes, the first 8 bytes are acquisition values and quality information of 32 channels, that is, 2 bits are used for acquisition value of each switching value acquisition channel, and 8 bytes are occupied by 32 channels; and the last 56 bytes are SOE events, each SOE event is designed as 8 bytes, and a maximum of 7 SOE events are supported on a single cycle bus, as shown in Figure 5 The SOE event is designed to include time information, acquisition event information, channel information and valid information, as shown in Table 1.

[0091] Table 1 DI-SOE event (56 bit)

[0092]

[0093] Since the FPGA uses parallel processing, the resolution time us in the above table is used to ensure that the channel acquisition SOE event resolution can reach us.

[0094] The time flag is 0, indicating that the time information is normal.

[0095] The DI module is configured as a DI general acquisition module, the DI channel is used for general acquisition of switching values, and the bus shared bandwidth of 64 bytes is designed as 2 bytes for each channel, and 64 bytes for 32 channels, as shown in Figure 6 .

[0096] According to the pre-defined time slot technology of the control station, the bus transmission time slot of the DI module is reached, and the above-mentioned 64 bytes are transmitted on the bus to transmit the first controller or the second controller, so as to realize bus sharing of the DI general acquisition module and the DI-SOE module.

[0097] The above steps realize time synchronization of all device modules in the station and SOE recording.

[0098] The application uses FPGA technology, uses the parallel working principle, transmits us-level time information on the bus, all modules on the bus can obtain accurate time (the delay time on the bus is less than us level and can be ignored), and can realize time synchronization of all devices in the station, and the FPGA technology time synchronization can improve the resolution of SOE to us level. At the same time, the DI general acquisition module and the DI-SOE module have the same hardware, and do not depend on microprocessors and software, thereby improving the stability of system operation.

[0099] In an exemplary embodiment, the application provides a working process of a nuclear power multi-device time synchronization and SOE recording system based on FPGA.

[0100] The first step, after the system is powered on, the user configures the multi-module device mixed insertion on the engineer station according to the application requirements, such as Figure 1 , including the first controller, the second controller, the DI-SOE acquisition module of 8 DI-SOE channels, the DI-SOE acquisition module of 3 DI-SOE channels, the DI general module, the communication module, and other IO modules, to generate configuration information.

[0101] The second step, in the download mode, the engineer station downloads the above configuration information.

[0102] The third step, after the download is completed, the mode is switched to the running mode, and all modules in the station are initialized and loaded with the engineer station configuration information.

[0103] The fourth step, the first controller starts collecting redundant B code time for analysis and selection, selects the time information t0 as 78 days (March 19) 9:50:30.15 milliseconds, and the first controller performs self-keeping time from the self-keeping time module. According to the bus token ring time slot predefinition technology, the time information t1 of the self-keeping time is output on the ACK frame of the L-BUS 0 time slot as 78 days (March 19) 9:50:30.18 milliseconds 20 microseconds. The second controller has the same processing flow as the first controller in this step.

[0104] The fifth step, other modules (DI-SOE acquisition module of 8 DI-SOE channels, DI-SOE acquisition module of 3 DI-SOE channels, DI general module, communication module, and other IO modules) on the L-BUS bus in the station receive the 0 time slot redundant L-BUS ACK data (t1: 78 days (March 19) 9:50:30.18 milliseconds 20 microseconds) sent by the above controller, each module is independent, and respectively performs time synchronization and self-keeping time. The self-keeping time module judges that the time is valid, and then updates the time information t1 of the current time as 78 days (March 19) 9:50:30.18 milliseconds 20 microseconds, and starts the self-keeping time t2 from the local crystal oscillator.

[0105] The sixth step, for the DI-SOE acquisition module of 8 DI-SOE channels, the local time self-keeping time module acquires the time information t2 as 78 days (March 19) 9:50:30.33 milliseconds 20 microseconds in the last time slot of the L-BUS bus cycle 15 ms, updates the local time, and starts the local time self-keeping time t3. Assuming that in the next bus cycle, the 1st channel, the 12th channel, the 3rd channel, and the 1st channel occur SOE events in turn, each channel collects and acquires the time information t3 to record the SOE events of each channel, and stores them in the common FIFO in turn according to the order of event occurrence.

[0106] SOE1 (Channel 1): 78 days (March 19) 9:50:30.33 250 microseconds, time valid 0 (valid), channel value 1, channel quality bit 0 (good), channel number 1.

[0107] The specific byte information of SOE event 1 is (001001110 01001 110010 011110 00001000010011111010 0 1 0 000001).

[0108] SOE2 (Channel 12): 78 days (March 19) 9:50:30.34 751 microseconds, time valid 0 (valid), channel value 1, channel quality bit 0 (good), channel number 12.

[0109] The specific byte information of SOE event 2 is (001001110 01001 110010 011110 00001000101011101110 0 1 0 001100).

[0110] SOE3 (Channel 3): 78 days (March 19) 9:50:30.35 1 microseconds, time valid 0 (valid), channel value 1, channel quality bit 0 (good), channel number 3.

[0111] The specific byte information of SOE event 3 is (001001110 01001 110010 011110 00001000110000000001 0 1 0 000011).

[0112] SOE4 (Channel 1): 78 days (March 19) 9:50:30.35 100 microseconds, time valid 0 (valid), channel value 0, channel quality bit 0 (good), channel number 1.

[0113] The specific byte information of SOE event 4 is (001001110 01001 110010 011110 00001000110001100100 0 0 0 000001).

[0114] The 4 SOE events are stored in the FIFO in the order of occurrence, as shown in Figure 6 .

[0115] According to the pre-defined time slot technology, when it is the turn of the bus sending time slot of this module, the module reads the first 8 bytes of channel data and the first 7 SOE events in the FIFO, and sends 64 bytes to the bus, that is, 2 bits per channel, 8 bytes for 32 channels, 8 bytes for each SOE event, 32 bytes for 4 SOE events, and the remaining bytes are 0, and the data is as shown in Figure 8 .

[0116] The seventh step is to collect switch value data and store it for the DI universal acquisition module; the shared bandwidth is 64 bytes, 2 bytes of data per channel (1 byte of channel data and 1 byte of quality bit), 64 bytes for 32 channels; for example Figure 7 According to the predefined time slot technology, when the bus transmission time slot of the module is reached, the 64 bytes of data are read and transmitted on the bus.

[0117] The above steps achieve time synchronization, universal acquisition and SOE bus sharing for the mixed configuration of nuclear power devices.

[0118] The module controlled by the FPGA in the present application is a "hard" logic platform with high reliability and integrity. The system uses a hardware architecture based on FPGA technology to transmit us-level time information on a redundant bus, and the entire system is synchronized every 15 ms to achieve time synchronization of all devices (including DI-SOE) in the system. The stable operation of the system does not depend on microprocessors and software. The resolution of the DI-SOE generated based on FPGA control can reach us, which is more accurate than the resolution of 1 ms achieved by CPU.

[0119] The technical features of the above embodiments can be combined in any way. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not conflict, they should be considered within the scope of the present application.

[0120] The principles and implementation modes of the present application are described by specific examples in this paper, and the above descriptions of the embodiments are only used to help understand the method and its core idea of the present application; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed. In conclusion, the content of the present application should not be understood as a limitation.

Claims

1. An FPGA-based nuclear power multi-device time synchronization and SOE recording system, characterized in that, The FPGA-based nuclear power multi-device time synchronization and SOE recording system comprises a control station, wherein a device module in the control station comprises a first controller, a second controller and an IO module, the IO module comprises a DI module, the DI module is divided into a DI general acquisition module and a DI-SOE module; each device module adopts FPGA; The first controller and the second controller each acquire two-way time signals, analyze each way of time signals into time information; the first controller and the second controller each select one way of time information from two-way time information, and send the selected one way of time information through two-way local buses in each bus cycle; the first controller broadcasts and sends time information in 0 time slot, and the second controller broadcasts and sends time information in 12 time slot; The first controller and the second controller each update local time according to the corresponding selected one way of time information, and start local time self-keeping; The IO module is used for selecting redundantly after receiving each way of time slot broadcast time information, updating local time by using time information in 0 time slot analyzed from the selected one way of time information, and starting local time self-keeping; The DI-SOE module is used for acquiring SOE events, updating local time by using time information in the last time slot of the selected one way of time information, starting local time self-keeping, and using the local time after self-keeping as recording time when acquiring SOE events.

2. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, wherein, The FPGA-based nuclear power multi-device time synchronization and SOE recording system further comprises an engineer station; The engineer station is used for sending configuration configuration information of multi-device module configuration to the control station; the configuration configuration information is used for distinguishing each DI module as a DI general acquisition module or a DI-SOE module.

3. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, wherein, The two-way time signals acquired by the first controller and the second controller are each IRIG-B code.

4. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, wherein, In terms of selecting one way of time information from two-way time signals, the first controller or the second controller is specifically used for: judging whether the first way of time information is normal to obtain a first judgment result; the two-way time information is respectively the first way of time information and the second way of time information; if the first judgment result is yes, the first way of time information is selected as the selected one way of time signal; if the first judgment result is no, judging whether the second way of time information is normal to obtain a second judgment result; if the second judgment result is yes, the second way of time information is selected as the selected one way of time signal; if the second judgment result is no, no time information is selected.

5. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, wherein, In terms of local time self-keeping, the first controller, the second controller and the IO module are self-kept by local crystal oscillators.

6. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, wherein, The DI-SOE module comprises a plurality of DI channels, and SOE events acquired by each DI channel are stored in a first-in-first-out queue in the order of SOE event occurrence.

7. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, wherein, The DI-SOE module and the DI general acquisition module share bus bandwidth of a local bus.

8. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 7, characterized in that, The bus bandwidth is 64 bytes; The 32 DI channels in the DI-SOE module occupy 64 bytes, the first 8 bytes are switch value and quality information of the 32 DI channels, and the last 56 bytes are SOE events; The DI general acquisition module includes 32 channels, each channel is stored according to 2 bytes; Each SOE event is 8 bytes, and each SOE event includes time information, time mark, channel value, quality bit and channel number.

9. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, wherein, The device module further includes a communication module; The communication module is used for receiving time information of each time slot broadcast, selecting redundancy, updating local time by using time information of 0 time slot parsed from the selected time information, and starting local time self-keeping.

10. The FPGA-based nuclear power multi-device time synchronization and SOE recording system according to claim 1, wherein, The first controller and the second controller are in synchronous communication through S_LINK.

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