Analog demultiplexer and related device

Abstract

The embodiment of the invention discloses an analog demultiplexer and a related device, the analog demultiplexer comprises a first THA and a second THA, the first THA comprises a first input end, a first sampling and holding switch group and a first output end, and the second THA comprises a second input end, a second sampling and holding switch group and a second output end; the first output end is connected with the second input end through a first coupling capacitor group; the first THA receives a differential signal through a first input end; the second THA receives a differential signal through a second input end; the first THA samples the differential signal through a first sampling holding switch group in a sampling state, and outputs a first sampling signal at a first output end; sending a first sampling signal to a second input end through a first coupling capacitor group; and when the second sampling and holding switch group is in a holding state, the first sampling signal and the original sampling signal generate an offset effect at the second input end. According to the invention, the sampling signal quality can be improved.

Description

Technical Field

[0001] This application relates to the technical field of electronic circuits, and in particular, to an analog demultiplexer and related devices. Background Art

[0002] With the continuous advancement of the social informatization process, the development of emerging services such as ultra-high-definition video, cloud computing, big data, and the Internet of Things has led to a rapid increase in the demand for network bandwidth, resulting in a continuous increase in the single-channel transmission rate of optical transmission systems. It is currently evolving from 100 Gb / s to 400 Gb / s, 800 Gb / s, and may even reach above 1 Tb / s in the future. To increase the transmission capacity, higher-order modulation methods and an increased number of subcarriers are required. However, this also places more stringent requirements on the performance of analog-to-digital converters (ADCs) based on complementary metal-oxide semiconductor (CMOS) technology in optical receivers, which not only need to have a higher sampling rate but also a larger output analog bandwidth.

[0003] Currently, a bandwidth doubling technique can be achieved by using a 1:2 high-linearity analog demultiplexer (ADEMUX) to compensate for the deficiencies in the sampling rate and analog bandwidth of ADCs under CMOS technology due to process characteristics. Due to the severe attenuation and distortion (intersymbol interference) of ultra-high-speed signals transmitted in high-speed links affected by the non-ideality of the channel, in order to eliminate intersymbol interference and recover the ideal signal, an equalization technique can be introduced to obtain the best signal eye diagram opening and a better eye diagram quality output. At the same time, in the hold mode of the sampling and holding amplifier in the core module of the ADEMUX, the input signal will feed through the input signal to the sampling capacitor through the switching triode capacitor CBE, affecting the voltage on the sampling capacitor and thus the quality of the sampling signal. Therefore, it is very valuable to design an analog demultiplexing circuit that can be used in high-speed scenarios. Summary of the Invention

[0004] Embodiments of this application provide an analog demultiplexer and related devices to improve the quality of the sampling signal of the analog demultiplexer.

[0005] In a first aspect, an embodiment of the present application provides an analog demultiplexer. The analog demultiplexer includes a first track-and-hold amplifier (THA) and a second track-and-hold amplifier (THA). The first THA includes a first input terminal, a first track-and-hold switch group, and a first output terminal. The second THA includes a second input terminal, a second track-and-hold switch group, and a second output terminal. The first output terminal is connected to the second input terminal through a first coupling capacitor group. The first THA is configured to receive a differential signal through the first input terminal, and the first track-and-hold switch group is currently in a sampling state. The second THA is configured to receive a differential signal through the second input terminal, and the second track-and-hold switch group is currently in a holding state. The first THA is further configured to sample the differential signal through the first track-and-hold switch group in the sampling state and output a first sampling signal at the first output terminal, and send the first sampling signal to the second input terminal through the first coupling capacitor group. The second THA is further configured to keep the second track-and-hold switch group in the holding state, receive the first sampling signal through the second input terminal, wherein a cancellation effect is generated between the differential signal and the first sampling signal at the second input terminal. The second THA is further configured to control the second track-and-hold switch group to switch to the sampling state, sample the differential signal through the second track-and-hold switch group, and output a second sampling signal at the second output terminal.

[0006] In the embodiment of the present application, the analog demultiplexer can be used to slow down a received high-speed signal and divide the signal into multiple paths for output. During this process, the THA in the analog demultiplexer can sample the signal received by the analog demultiplexer to output multiple signals. During the sampling process of the THA, when the first THA is in the sampling state, the second THA is in the holding state. When the second track-and-hold switch group of the second THA is in the holding state, the second THA does not need to sample the received differential signal. However, since the second track-and-hold switch group includes parasitic capacitance, even when the second track-and-hold switch group is in the holding state, the differential signal will be fed through the parasitic capacitance to the second output terminal, causing the sampling signal output by the second THA to be interfered by the signal that does not need to be sampled in the differential signal, reducing the signal quality of the second sampling signal. In the present application, considering that the first THA and the second THA receive the same differential signal simultaneously, when the first THA is in the sampling state, the second THA is in the holding state, that is, the signal that the first THA needs to sample is exactly the signal that interferes with the second THA. Therefore, the first output terminal and the second input terminal can be connected by the first coupling capacitor group, so that the first THA can send the sampled first sampling signal to the second input terminal. Furthermore, a cancellation effect can be generated between the differential signal and the first sampling signal at the second input terminal, thereby eliminating the influence of signal feedthrough and improving the quality of the second sampling signal.

[0007] In some embodiments, the input end of the first sample-and-hold switch group is connected to the first input end, and the output end of the first sample-and-hold switch group is connected to the first output end; the input end of the second sample-and-hold switch group is connected to the second input end, and the output end of the second sample-and-hold switch group is connected to the second output end; the output end of the first sample-and-hold switch group and the input end of the second sample-and-hold switch group are connected through a first coupling capacitor group.

[0008] In the embodiments of the present application, considering that interference appears at the second sample-and-hold switch group, the first coupling capacitor group can be directly connected between the output end of the first sample-and-hold switch group and the input end of the second sample-and-hold switch group. Furthermore, when the second sample-and-hold switch group is in the hold state, at the input end of the second sample-and-hold switch group, the differential signal received at the input end of the second sample-and-hold switch group and the sampling signal output by the first sample-and-hold switch group can produce a cancellation effect, thereby eliminating the influence of signal feedthrough and improving the quality of the second sampling signal.

[0009] In some embodiments, the first THA is further configured to control the first sample-and-hold switch group according to the first clock cycle signal; when the first clock cycle signal is at the rising edge, the first THA is specifically configured to control the first sample-and-hold switch group to be in the sampling state; when the first clock cycle signal is at the falling edge, the first THA is specifically configured to control the first sample-and-hold switch group to be in the hold state.

[0010] In the embodiments of the present application, during the process of the analog demultiplexer reducing the speed of the received high-speed signal and dividing the signal into multiple paths for output, the state of the first sample-and-hold switch group can be controlled by the clock cycle signal. For example, when the first clock cycle signal is at the rising edge, the first THA can control the first sample-and-hold switch group to be in the sampling state; when the first clock cycle signal is at the falling edge, the first THA can control the first sample-and-hold switch group to be in the hold state, so that the first THA can sample at a preset sampling frequency.

[0011] In some embodiments, the differential signal is composed of a first signal and a second signal, and the first signal and the second signal are opposite in phase; the first input terminal includes a first signal input terminal and a second signal input terminal, and the first output terminal includes a first signal output terminal and a second signal output terminal; the second input terminal includes a third signal input terminal and a fourth signal input terminal, and the second output terminal includes a third signal output terminal and a fourth signal output terminal; the first THA is specifically configured to receive the first signal through the first signal input terminal and output a third signal through the first signal output terminal; receive the second signal through the second signal input terminal and output a fourth signal through the second signal output terminal; the first sampling signal includes the third signal and the fourth signal; the second THA is specifically configured to receive the first signal through the third signal input terminal and output a fifth signal through the third signal output terminal; receive the second signal through the fourth signal input terminal and output a sixth signal through the fourth signal output terminal; the second sampling signal includes the fifth signal and the sixth signal.

[0012] In the embodiments of the present application, since the signals input to the first THA and the second THA are differential signals, and the differential signal is composed of two signals with opposite phases, both the input terminal and the output terminal of the first THA and the second THA have two signal terminals. That is, the first input terminal includes a first signal input terminal and a second signal input terminal, and these two signal terminals respectively receive one signal in the differential signal to separately sample each signal and output a differential sampling signal. Therefore, the first output terminal also needs to include a first signal output terminal and a second signal output terminal. The second input terminal includes a third signal input terminal and a fourth signal input terminal, and these two signal terminals respectively receive one signal in the differential signal to separately sample each signal and output a differential sampling signal. Therefore, the second output terminal also needs to include a third signal output terminal and a fourth signal output terminal. Further, the first THA can obtain a first sampling signal by sampling the differential signal, and the second THA can obtain a second sampling signal by sampling the differential signal.

[0013] In some embodiments, the first coupling capacitor group includes a first capacitor and a second capacitor; the first signal output terminal is connected to the fourth signal input terminal through the first capacitor, and the second signal output terminal is connected to the third signal input terminal through the second capacitor.

[0014] In the embodiment of the present application, the third signal input terminal in the second input terminal receives the first signal, and the fourth signal input terminal receives the second signal. Since the first signal and the second signal are signals with opposite phases, and the phase of the first signal is the same as the phase of the third signal, and the phase of the second signal is the same as the phase of the fourth signal. When the second THA is in the hold state, since the first signal output terminal and the fourth signal input terminal are connected through the first capacitor, and the second signal output terminal and the third signal input terminal are connected through the second capacitor, the third signal can be sent to the fourth signal input terminal, and the fourth signal can be sent to the third signal input terminal. Then, at the second input terminal, a cancellation effect can be achieved between the third signal and the second signal, and a cancellation effect can be achieved between the fourth signal and the first signal, thereby eliminating the influence of signal feedthrough and improving the quality of the second sampling signal.

[0015] In some embodiments, the second output terminal and the first input terminal are connected through the second coupling capacitor bank. When the second sample and hold switch bank is in the sampling state and the first sample and hold switch bank is in the hold state; the second THA is further configured to send the second sampling signal to the first input terminal through the second coupling capacitor bank; the first THA is further configured to keep the first sample and hold switch bank in the hold state and receive the second sampling signal through the first input terminal, wherein the received differential signal and the second sampling signal generate a cancellation effect at the first input terminal.

[0016] In the embodiment of the present application, when the second THA is in the sampling state, the first THA is in the hold state. When the first sample and hold switch bank of the first THA is in the hold state, the first THA does not need to sample the received differential signal. Since the first sample and hold switch bank includes parasitic capacitance, even when the first sample and hold switch bank is in the hold state, the differential signal will feed through to the first output terminal through the parasitic capacitance, so that the first sampling signal output by the first THA is interfered by the signal that does not need to be sampled in the differential signal, reducing the signal quality of the first sampling signal. Considering that the first THA and the second THA receive the same differential signal at the same time, when the second THA is in the sampling state, the first THA is in the hold state, that is, the signal to be sampled by the second THA is exactly the signal that interferes with the first THA. Therefore, the second output terminal and the first input terminal can be connected through the second coupling capacitor bank, so that the second THA can send the sampled second sampling signal to the first input terminal. Furthermore, the first THA receives the second sampling signal sent by the second THA in the hold state, and the differential signal received by the first THA can generate a cancellation effect with the second sampling signal at the first input terminal, thereby eliminating the influence of signal feedthrough and improving the quality of the first sampling signal.

[0017] In some embodiments, the output terminal of the second sample and hold switch bank and the input terminal of the first sample and hold switch bank are connected through the second coupling capacitor bank.

[0018] In the embodiments of the present application, considering that interference appears at the first sample-and-hold switch group, the second coupling capacitor group can be directly connected between the output end of the second sample-and-hold switch group and the input end of the first sample-and-hold switch group. Furthermore, when the first sample-and-hold switch group is in the hold state, at the input end of the first sample-and-hold switch group, the differential signal received at the input end of the first sample-and-hold switch group and the sample signal output by the second sample-and-hold switch group can produce a cancellation effect, thereby eliminating the influence of signal feedthrough and improving the quality of the first sample signal.

[0019] In some embodiments, the second THA is further configured to control the second sample-and-hold switch group according to the second clock cycle signal; the second clock cycle signal has the same clock cycle as the first clock cycle signal and opposite phases; when the second clock cycle signal is at the rising edge, the second THA is specifically configured to control the second sample-and-hold switch group to be in the sampling state; when the second clock cycle signal is at the falling edge, the second THA is specifically configured to control the second sample-and-hold switch group to be in the hold state.

[0020] In the embodiments of the present application, during the process of the analog demultiplexer reducing the speed of the received high-speed signal and dividing the signal into multiple paths for output, the state of the second sample-and-hold switch group can be controlled by the clock cycle signal. For example, when the second clock cycle signal is at the rising edge, the second THA can control the second sample-and-hold switch group to be in the sampling state; when the second clock cycle signal is at the falling edge, the second THA can control the second sample-and-hold switch group to be in the hold state, so that the second THA can sample at a preset sampling frequency. Among them, the second clock cycle signal has the same clock cycle as the first clock cycle signal and opposite phases, so that when the first THA is in the sampling state, the second THA is in the hold state; when the first THA is in the hold state, the second THA is in the sampling state.

[0021] In some embodiments, the second coupling capacitor group includes a third capacitor and a fourth capacitor; the third signal output end is connected to the second signal input end through the third capacitor, and the fourth signal output end is connected to the first signal input end through the fourth capacitor.

[0022] In the embodiment of the present application, the second sampling signal output by the second THA is composed of a fifth signal and a sixth signal. Since the first signal and the second signal are signals with opposite phases, and the phase of the first signal is the same as the phase of the fifth signal, and the phase of the second signal is the same as the phase of the sixth signal. When the first THA is in the holding state, since the third signal output terminal and the second signal input terminal are connected through a third capacitor, and the fourth signal output terminal and the first signal input terminal are connected through a fourth capacitor, the fifth signal can be sent to the second signal input terminal, and the sixth signal can be sent to the first signal input terminal. Then, at the second input terminal, a cancellation effect can be achieved between the fifth signal and the second signal, and a cancellation effect can be achieved between the sixth signal and the first signal. When the first sample-and-hold switch group is in the holding state, at the input terminal of the first sample-and-hold switch group, the differential signal received at the input terminal of the first sample-and-hold switch group and the sampling signal output by the second sample-and-hold switch group can produce a cancellation effect, eliminating the influence of signal feedthrough and improving the quality of the first sampling signal.

[0023] In a second aspect, an embodiment of the present application provides an analog demultiplexing device, and the analog demultiplexing device includes the analog demultiplexer described in any one of the above first aspects.

[0024] In a third aspect, an embodiment of the present application provides a switch, and the switch includes the analog demultiplexer described in any one of the above first aspects, or the analog demultiplexing device in the above second aspect.

[0025] In a fourth aspect, a chip system is provided, and the chip system includes the analog demultiplexer described in any one of the above first aspects, or the analog demultiplexing device in the above second aspect. Description of the Drawings

[0026] Figure 1 It is a schematic diagram of a communication system provided by an embodiment of the present application.

[0027] Figure 2a It is an analog demultiplexer provided by an embodiment of the present application.

[0028] Figure 2b It is a schematic diagram of N-way outputs of an analog demultiplexer provided by an embodiment of the present application.

[0029] Figure 2c It is a schematic diagram of two-way outputs of an analog demultiplexer provided by an embodiment of the present application.

[0030] Figure 3 It is a schematic diagram of the sampling process of a sample-and-hold amplifier provided by an embodiment of the present application.

[0031] Figure 4Schematic diagram of a connection between a first switch group and a second switch group through a first coupling capacitor provided by an embodiment of the present application.

[0032] Figure 5 Schematic diagram of a circuit connection between a first THA and a second THA provided by an embodiment of the present application.

[0033] Figure 6 Another schematic diagram of an analog demultiplexer provided by an embodiment of the present application.

[0034] Figure 7 Another schematic diagram of a sampling process of a sample-and-hold amplifier provided by an embodiment of the present application.

[0035] Figure 8 Schematic diagram of a circuit connection of a second coupling capacitor group provided by an embodiment of the present application.

[0036] Figure 9 Another schematic diagram of a circuit connection of a second coupling capacitor group provided by an embodiment of the present application.

[0037] Figure 10 Another schematic diagram of an analog demultiplexer provided by an embodiment of the present application.

[0038] Figure 11 Schematic diagram of a sample-and-hold amplifier structure of a multipath feedback cancellation technique provided by an embodiment of the present application. Detailed implementation manners

[0039] Next, embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application.

[0040] Terms such as "first", "second", "third", and "fourth" in the specification and claims of the present application and the accompanying drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0041] Referring to "embodiment" herein means that a specific feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0042] In the description of the embodiments of the present application, it should be noted that unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. Among them, "fixed connection" means that the components are connected to each other and the relative positional relationship after connection remains unchanged. It should be understood that when component A is fixedly connected to component C through component B, a change in the relative positional relationship due to the deformation of component A, component B, and component C itself is allowed.

[0043] The following introduces a communication system provided by the embodiments of the present application.

[0044] Please refer to Figure 1 , Figure 1A schematic diagram of a communication system provided by an embodiment of the present application. In the figure, the communication system may include a first electronic device and a second electronic device. The first electronic device may be a switch and can serve as a sending end in this communication system; the second electronic device may also be a switch and can serve as a receiving end in this communication system. For example, the second electronic device is an optical receiver. Communication can occur between the first electronic device and the second electronic device. The first electronic device can send a signal to the second electronic device, and this signal can be an optical signal or an electrical signal. With the continuous advancement of the social informatization process, the development of emerging services such as ultra-high-definition video, cloud computing, big data, and the Internet of Things has led to a rapid increase in the demand for network bandwidth, causing the communication rate (i.e., the single-channel transmission rate) between the first electronic device and the second electronic device in a communication system (such as an optical transmission system) to continuously increase. It is currently evolving from 100 Gb / s towards 400 Gb / s, 800 Gb / s, and may even reach above 1 Tb / s in the future. To increase the transmission capacity, higher-order modulation methods and an increased number of subcarriers need to be adopted. However, this also places more stringent requirements on the performance of the analog-to-digital converter (ADC) based on complementary metal oxide semiconductor (CMOS) technology in the second electronic device (such as an optical receiver), which not only requires a higher sampling rate but also a larger output analog bandwidth. The analog demultiplexer can compensate for the deficiencies of the sampling rate and analog bandwidth of the ADC under CMOS technology being limited by process characteristics. The analog demultiplexer may include multiple track-hold-amplifier (THA) circuits, also known as sampling-hold circuits. The input of each track-hold-amplifier circuit in the multiple track-hold-amplifier circuits can be a high-speed differential signal, and the output can be a differential signal with a reduced speed. During the sampling process of the analog demultiplexer for the received high-speed differential signal in the hold mode, the input signal will be fed through the parasitic capacitance (such as capacitor CBE) of the sampling switch (such as a switching triode) to the sampling capacitor, affecting the sampling signal. The analog demultiplexer provided by the present application can divide a high-speed input signal obtained through optoelectronic conversion into multiple low-speed signals and send them to each corresponding ADC respectively, achieving the function of equivalently increasing the ADC bandwidth. Moreover, the analog demultiplexer provided by the present application integrates a multi-path data cancellation technology, which can obtain better ADC input signal quality. The multi-path data cancellation technology in the present application will be described in detail later and will not be elaborated here.

[0045] It can be understood that Figure 1 a communication system among them is only an exemplary implementation manner in the embodiments of the present application. The communication systems in the embodiments of the present application include but are not limited to the above communication systems.

[0046] Please refer to Figure 2a , Figure 2a , which is an analog de-multiplexer provided by an embodiment of the present application. The analog de-multiplexer (ADEMUX) includes a first sample and hold amplifier THA and a second sample and hold amplifier THA. The first THA 10 includes a first input terminal 102, a first sample and hold switch group 101, and a first output terminal 103. The second THA 20 includes a second input terminal 202, a second sample and hold switch group 201, and a second output terminal 203. The first output terminal 103 is connected to the second input terminal 202 through a first coupling capacitor group 30.

[0047] Specifically, as Figure 2b shown, Figure 2b is a schematic diagram of N outputs of an analog de-multiplexer provided by an embodiment of the present application. The analog de-multiplexer can be used to slow down the received high-speed signal and divide the signal into N output signals (N can be an integer greater than or equal to 2). During this process, the THA in the analog de-multiplexer can sample the signal received by the analog de-multiplexer to output N signals. Also as Figure 2c shown, Figure 2cSchematic diagram of two-way output of a simulated demultiplexer provided by an embodiment of this application. When the simulated demultiplexer includes a first THA10 and a second THA20, the first THA10 and the second THA20 can be used to sample the signal received by the simulated demultiplexer to output two signals. For example, the first THA10 outputs a first sampled signal, and the second THA20 outputs a second sampled signal. When the first sample-and-hold switch group 101 is in the sampling state, the first THA10 is in the sampling state, and the first THA10 can sample the received signal; when the first THA10 is in the hold state, the first THA10 can stop sampling the received signal. The first sample-and-hold switch group 101 can include one or more switches. If the signal received by the first THA10 is a multi-terminal signal, the first sample-and-hold switch group 101 can include multiple switches; if the signal received by the first THA10 is a single-terminal signal, the first sample-and-hold switch group 101 can include one switch. Each switch in the first sample-and-hold switch group 101 can be a triode, and the triode can include a field-effect transistor, a bipolar junction transistor, etc. For example, the switch can be a complementary metal-oxide semiconductor, and the switch can also be a silicon-germanium triode, etc., which are not specifically limited in this application. When the second sample-and-hold switch group 201 is in the sampling state, the second THA20 is in the sampling state, and the second THA20 can sample the received signal; when the second THA20 is in the hold state, the second THA20 can stop sampling the received signal. The second sample-and-hold switch group 201 can include one or more switches. If the signal received by the second THA20 is a multi-terminal signal, the second sample-and-hold switch group 201 can include multiple switches; if the signal received by the second THA20 is a single-terminal signal, the second sample-and-hold switch group 201 can include one switch. Each switch in the second sample-and-hold switch group 201 can be a triode, and the triode can include a field-effect transistor, a bipolar junction transistor, etc. For example, the switch can be a complementary metal-oxide semiconductor, and the switch can also be a silicon-germanium triode, etc., which are not specifically limited in this application. The first THA10 can receive a signal through the first input terminal 102 and output the sampled signal through the first output terminal 103; the second THA20 can receive a signal through the second input terminal 202 and output the sampled signal through the second output terminal 203.

[0048] The first THA10 is used to receive a differential signal through the first input terminal 102, and the first sample-and-hold switch group 101 is currently in the sampling state.

[0049] Specifically, when the signal received by the analog demultiplexer is a differential signal, the first THA10 can be used to receive the differential signal through the first input terminal 102. If the first sample-and-hold switch group 101 is in the sampling state and the second sample-and-hold switch group 201 is in the holding state, that is, when the first THA10 is in the sampling state, the second THA20 is in the holding state; if the first sample-and-hold switch group 101 is in the holding state and the second sample-and-hold switch group 201 is in the sampling state, that is, when the first THA10 is in the holding state, the second THA20 is in the sampling state.

[0050] The second THA20 is used to receive the differential signal through the second input terminal 202, and the second sample-and-hold switch group 201 is currently in the holding state.

[0051] Specifically, when the signal received by the analog demultiplexer is a differential signal, the second THA20 can be used to receive the differential signal through the second input terminal 202. It should be noted that the first THA10 and the second THA20 receive the same signal simultaneously.

[0052] The first THA10 is also used to sample the differential signal through the first sample-and-hold switch group 101 in the sampling state and output the first sampled signal at the first output terminal 103; send the first sampled signal to the second input terminal 202 through the first coupling capacitor group 30.

[0053] Specifically, the first THA10 can sample the received differential signal and output the first sampled signal at the first output terminal 103. At the same time, since the first output terminal 103 is connected to the second input terminal 202 through the first coupling capacitor group 30, the first THA10 can also send the first sampled signal to the second input terminal 202 through the first coupling capacitor group 30. It can be understood that during this process, the first THA is in the sampling state and the second THA20 is in the holding state.

[0054] The second THA20 is also used to keep the second sample-and-hold switch group 201 in the holding state and receive the first sampled signal through the second input terminal 202, where the differential signal and the first sampled signal produce a cancellation effect at the second input terminal 202.

[0055] Specifically, when the first THA 10 is in the sampling state and the second THA 20 is in the holding state, and the second sample-and-hold switch group 201 of the second THA 20 is in the holding state, the second THA 20 does not need to sample the received differential signal. Since the second sample-and-hold switch group 201 includes parasitic capacitance, even when the second sample-and-hold switch group 201 is in the holding state, the differential signal will be fed through the parasitic capacitance to the second output terminal 203, so that the second sampled signal output by the second THA 20 is interfered by the signal that does not need to be sampled in the differential signal, reducing the signal quality of the second sampled signal. In this application, considering that the first THA 10 and the second THA 20 receive the same differential signal at the same time, when the first THA 10 is in the sampling state, the second THA 20 is in the holding state, that is, the signal that the first THA 10 needs to sample is exactly the signal that interferes with the second THA 20. Therefore, the first coupling capacitor group 30 can be used to connect the first output terminal 103 and the second input terminal 202, so that the first THA 10 can send the first sampled signal obtained by sampling to the second input terminal 202. Furthermore, the second THA 20 receives the first sampled signal sent by the first THA 10 in the holding state, and the differential signal received by the second THA 20 can generate a cancellation effect with the first sampled signal at the second input terminal 202, thereby eliminating the influence of signal feedthrough and improving the quality of the second sampled signal.

[0056] For example, as Figure 3 shown, Figure 3 is a schematic diagram of the sampling process of a sample-and-hold amplifier provided by an embodiment of the present application. The signal input to the input analog demultiplexer can be a differential signal, and the input data of the differential signal can be Figure 3 shown. Exemplarily, the differential signal can be composed of D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, and D11. When the first THA 10 samples D1, the second THA 20 is in the holding stage, and D1 in the differential signal will be fed through the parasitic capacitance to the second output terminal 203, affecting D0 collected by the second THA 20. Therefore, the first coupling capacitor group 30 can be used to connect the first output terminal 103 and the second input terminal 202, so that the first THA 10 can send the sampled D1 to the second input terminal 202. Furthermore, the second THA 20 receives D1 sent by the first THA 10 in the holding state, and D1 in the differential signal received by the second THA 20 can generate a cancellation effect with D1 sent by the first THA 10 at the second input terminal 202, thereby eliminating the influence of signal feedthrough and improving the quality of the second sampled signal.

[0057] The second THA 20 is further configured to control the second sample-and-hold switch group 201 to switch to the sampling state, sample the differential signal through the second sample-and-hold switch group 201, and output a second sampled signal at the second output terminal 203.

[0058] Specifically, when the second sampling and holding switch group 201 switches to the sampling state, the second THA 20 can sample the received differential signal and output a second sampling signal through the second output terminal 203. Since the second THA 20 receives the first sampling signal sent by the first THA 10 during the holding stage, the differential signal received by the second THA 20 can generate a cancellation effect with the first sampling signal at the second input terminal 202, thereby eliminating the signal feedthrough effect and improving the quality of the second sampling signal. In addition, the output stage signal swing of the first THA 10 is large and the driving force is strong, and the requirement for the size of the coupling capacitor is low, which can improve the influence of the coupling capacitor on the bandwidth.

[0059] In some embodiments, please refer to Figure 4 , Figure 4 FIG. is a schematic diagram of a connection between a first switch group and a second switch group through a first coupling capacitor provided by an embodiment of the present application. The input terminal of the first sampling and holding switch group 101 is connected to the first input terminal 102, and the output terminal of the first sampling and holding switch group 101 is connected to the first output terminal 103; the input terminal of the second sampling and holding switch group 201 is connected to the second input terminal 202, and the output terminal of the second sampling and holding switch group 201 is connected to the second output terminal 203; the output terminal of the first sampling and holding switch group 101 and the input terminal of the second sampling and holding switch group 201 are connected through the first coupling capacitor group 30.

[0060] Specifically, when the first THA 10 is in the sampling state and the second THA 20 is in the holding state. When the second sampling and holding switch group 201 of the second THA 20 is in the holding state, the second THA 20 does not need to sample the received differential signal. Since the second sampling and holding switch group 201 includes parasitic capacitance, even when the second sampling and holding switch group 201 is in the holding state, the differential signal will be fed through the parasitic capacitance to the second output terminal 203, so that the second sampling signal output by the second THA 20 is interfered by the signal that does not need to be sampled in the differential signal, reducing the signal quality of the second sampling signal. In the embodiment of the present application, considering that the interference occurs at the second sampling and holding switch group 201, the first coupling capacitor group 30 can be directly connected between the output terminal of the first sampling and holding switch group 101 and the input terminal of the second sampling and holding switch group 201. Furthermore, when the second sampling and holding switch group 201 is in the holding state, at the input terminal of the second sampling and holding switch group 201, the differential signal received by the input terminal of the second sampling and holding switch group 201 and the sampling signal output by the first sampling and holding switch group 101 can generate a cancellation effect, thereby eliminating the signal feedthrough effect and improving the quality of the second sampling signal.

[0061] In some embodiments, the first THA 10 is further configured to control the first sample-and-hold switch group 101 according to the first clock cycle signal. When the first clock cycle signal is at the rising edge, the first THA 10 is specifically configured to control the first sample-and-hold switch group 101 to be in the sampling state. When the first clock cycle signal is at the falling edge, the first THA 10 is specifically configured to control the first sample-and-hold switch group 101 to be in the holding state.

[0062] Specifically, during the process of the analog demultiplexer reducing the speed of the received high-speed signal and dividing the signal into multiple paths for output, the state of the first sample-and-hold switch group 101 can be controlled by the clock cycle signal. For example, when the first clock cycle signal is at the rising edge, the first THA 10 can control the first sample-and-hold switch group 101 to be in the sampling state. When the first clock cycle signal is at the falling edge, the first THA 10 can control the first sample-and-hold switch group 101 to be in the holding state, so that the first THA 10 can sample at a preset sampling frequency.

[0063] In some embodiments, the differential signal is composed of a first signal and a second signal, and the first signal and the second signal are opposite in phase. As Figure 5 shown, Figure 5 FIG. 10 is a schematic circuit connection diagram of a first THA and a second THA provided by an embodiment of the present application. The first input terminal 102 includes a first signal input terminal 1021 and a second signal input terminal 1022, and the first output terminal 103 includes a first signal output terminal 1031 and a second signal output terminal 1032. The second input terminal 202 includes a third signal input terminal 2021 and a fourth signal input terminal 2022, and the second output terminal 203 includes a third signal output terminal 2031 and a fourth signal output terminal 2032. The first THA 10 is specifically configured to receive the first signal through the first signal input terminal 1021 and output a third signal through the first signal output terminal 1031. Receive the second signal through the second signal input terminal 1022 and output a fourth signal through the second signal output terminal 1032. The first sampling signal includes the third signal and the fourth signal. The second THA 20 is specifically configured to receive the first signal through the third signal input terminal 2021 and output a fifth signal through the third signal output terminal 2031. Receive the second signal through the fourth signal input terminal 2022 and output a sixth signal through the fourth signal output terminal 2032. The second sampling signal includes the fifth signal and the sixth signal.

[0064] Specifically, since the signals input to the first THA 10 and the second THA 20 are differential signals, and a differential signal is composed of two signals with opposite phases, both the input and output terminals of the first THA 10 and the second THA 20 have two signal terminals. That is, the first input terminal 102 includes a first signal input terminal 1021 and a second signal input terminal 1022. These two signal terminals respectively receive one signal in the differential signal to separately sample each signal and output a differential sampling signal. Therefore, the first output terminal 103 also needs to include a first signal output terminal 1031 and a second signal output terminal 1032. The second input terminal 202 includes a third signal input terminal 2021 and a fourth signal input terminal 2022. These two signal terminals respectively receive one signal in the differential signal to separately sample each signal and output a differential sampling signal. Therefore, the second output terminal 203 also needs to include a third signal output terminal 2031 and a fourth signal output terminal 2032. Further, the first THA 10 can sample the received differential signal to obtain a first sampling signal, and this first sampling signal is a differential sampling signal; the second THA 20 can sample the received differential signal to obtain a second sampling signal, and this second sampling signal is a differential sampling signal.

[0065] In some embodiments, for another example Figure 5 As shown, the first coupling capacitor group 30 includes a first capacitor and a second capacitor; the first signal output terminal 1031 is connected to the fourth signal input terminal 2022 through the first capacitor, and the second signal output terminal 1032 is connected to the third signal input terminal 2021 through the second capacitor.

[0066] Specifically, the first sampling signal output by the first THA 10 is composed of a third signal and a fourth signal. Optionally, the first sampling switch in the first sample-and-hold switch group 101 can sample the first signal received by the first signal input terminal 1021 and output the third signal from the first signal output terminal 1031. Optionally, the second sampling switch in the first sample-and-hold switch group 101 can sample the second signal received by the second signal input terminal 1022 and output the fourth signal from the second signal output terminal 1032. The third signal input terminal 2021 in the second input terminal 202 receives the first signal, and the fourth signal input terminal 2022 receives the second signal. Since the first signal and the second signal are signals with opposite phases, and the phase of the first signal is the same as the phase of the third signal, and the phase of the second signal is the same as the phase of the fourth signal. When the second THA 20 is in the hold state, since the first signal output terminal 1031 and the fourth signal input terminal 2022 are connected by a first capacitor, and the second signal output terminal 1032 and the third signal input terminal 2021 are connected by a second capacitor, the third signal can be sent to the fourth signal input terminal 2022, and the fourth signal can be sent to the third signal input terminal 2021. Then, at the second input terminal 202, a cancellation effect can be achieved between the third signal and the second signal, and between the fourth signal and the first signal. When the second sample-and-hold switch group 201 is in the hold state, at the input terminal of the second sample-and-hold switch group 201, the differential signal received by the input terminal of the second sample-and-hold switch group 201 and the sampling signal output by the first sample-and-hold switch group 101 can produce a cancellation effect, eliminating the influence of signal feedthrough and improving the quality of the second sampling signal.

[0067] In some embodiments, as Figure 6 shown, Figure 6 is a schematic diagram of another analog demultiplexer provided by an embodiment of the present application. The second output terminal 203 is connected to the first input terminal 102 through a second coupling capacitor group 40. When the second sample-and-hold switch group 201 is in the sampling state and the first sample-and-hold switch group 101 is in the hold state; the second THA 20 is further configured to send the second sampling signal to the first input terminal 102 through the second coupling capacitor group 40; the first THA 10 is further configured to keep the first sample-and-hold switch group 101 in the hold state and receive the second sampling signal through the first input terminal 102, where a cancellation effect is generated between the differential signal and the second sampling signal at the first input terminal.

[0068] Specifically, when the second THA 20 is in the sampling state, the first THA 10 is in the holding state. When the first sampling and holding switch group 101 of the first THA 10 is in the holding state, the first THA 10 does not need to sample the received differential signal. Since the first sampling and holding switch group 101 includes parasitic capacitance, even when the first sampling and holding switch group 101 is in the holding state, the differential signal will be fed through the parasitic capacitance to the first output terminal 103, so that the first sampling signal output by the first THA 10 is interfered by the signal that does not need to be sampled in the differential signal, reducing the signal quality of the first sampling signal. In this application, considering that the first THA 10 and the second THA 20 receive the same differential signal at the same time, when the second THA 20 is in the sampling state, the first THA 10 is in the holding state, that is, the signal that the second THA 20 needs to sample is exactly the signal that interferes with the first THA 10. Therefore, the second coupling capacitor group 40 can be used to connect the second output terminal 203 and the first input terminal 102, so that the second THA 20 can send the sampled second sampling signal to the first input terminal 102. Furthermore, the first THA 10 receives the second sampling signal sent by the second THA 20 in the holding state, and the differential signal received by the first THA 10 and the second sampling signal can generate a cancellation effect at the first input terminal 102, thereby eliminating the influence of signal feedthrough and improving the quality of the first sampling signal. In addition, the output stage signal swing of the second THA 20 is large and the driving force is strong, and the requirement for the size of the coupling capacitor is low, which can improve the influence of the coupling capacitor on the bandwidth.

[0069] For example, as Figure 7 shown, Figure 7 is a schematic diagram of the sampling process of another sampling and holding amplifier provided by an embodiment of the present application. The signal input to the input analog demultiplexer can be a differential signal, and the input data of the differential signal can be Figure 7 shown. Exemplarily, the differential signal can be composed of D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, and D11. Exemplarily, the clock frequency can be half of the input data baud rate. When the second THA 20 samples D2, the first THA 10 is in the holding stage, and D2 in the differential signal will be fed through the parasitic capacitance to the first output terminal 103, affecting D1 collected by the first THA 10. Therefore, the second coupling capacitor group 40 can be used to connect the second output terminal 203 and the first input terminal 102, so that the second THA 20 can send the sampled D2 to the first input terminal 102. Furthermore, the first THA 10 receives D2 sent by the second THA 20 in the holding state, and D2 in the differential signal received by the first THA 10 and D2 sent by the second THA 20 can generate a cancellation effect at the first input terminal 102, thereby eliminating the influence of signal feedthrough and improving the quality of the first sampling signal.

[0070] In some embodiments, such asFigure 8 As shown Figure 8 This is a schematic diagram of the circuit connection of a second coupling capacitor bank provided by an embodiment of the present application. The output end of the second sample-and-hold switch bank 201 is connected to the input end of the first sample-and-hold switch bank 101 through the second coupling capacitor bank 40.

[0071] Specifically, when the second THA 20 is in the sampling state, the first THA 10 is in the holding state. When the first sample-and-hold switch bank 101 of the first THA 10 is in the holding state, the first THA 10 does not need to sample the received differential signal. Since the first sample-and-hold switch bank 101 includes parasitic capacitance, even when the first sample-and-hold switch bank 101 is in the holding state, the differential signal will be fed through the parasitic capacitance to the first output end 103, so that the first sample signal output by the first THA 10 is interfered by the signal that does not need to be sampled in the differential signal, reducing the signal quality of the first sample signal. In the embodiment of the present application, considering that the interference occurs at the first sample-and-hold switch bank 101, the second coupling capacitor bank 40 can be directly connected between the output end of the second sample-and-hold switch bank 201 and the input end of the first sample-and-hold switch bank 101. Furthermore, when the first sample-and-hold switch bank 101 is in the holding state, at the input end of the first sample-and-hold switch bank 101, the differential signal received by the input end of the first sample-and-hold switch bank 101 and the sample signal output by the second sample-and-hold switch bank 201 can produce a cancellation effect, thereby eliminating the influence of signal feedthrough and improving the quality of the first sample signal.

[0072] In some embodiments, the second THA 20 is further configured to control the second sample-and-hold switch bank 201 according to a second clock cycle signal; the second clock cycle signal has the same clock cycle as the first clock cycle signal and the opposite phase; when the second clock cycle signal is at the rising edge, the second THA 20 is specifically configured to control the second sample-and-hold switch bank 201 to be in the sampling state; when the second clock cycle signal is at the falling edge, the second THA 20 is specifically configured to control the second sample-and-hold switch bank 201 to be in the holding state.

[0073] Specifically, during the process of the analog demultiplexer reducing the speed of the received high-speed signal and dividing the signal into multiple output signals, the state of the second sample-and-hold switch group 201 can be controlled by a clock cycle signal. For example, when the second clock cycle signal is at the rising edge, the second THA20 can control the second sample-and-hold switch group 201 to be in the sampling state; when the second clock cycle signal is at the falling edge, the second THA20 can control the second sample-and-hold switch group 201 to be in the holding state, so that the second THA20 can sample at a preset sampling frequency. Among them, the second clock cycle signal has the same clock cycle as the first clock cycle signal and the opposite phase, so that when the first THA10 is in the sampling state, the second THA20 is in the holding state; when the first THA10 is in the holding state, the second THA20 is in the sampling state.

[0074] In some embodiments, please refer to Figure 9 , Figure 9 which is a schematic circuit connection diagram of another second coupling capacitor group provided by the embodiment of the present application. The second coupling capacitor group 40 includes a third capacitor and a fourth capacitor; the third signal output terminal 2031 is connected to the second signal input terminal 1022 through the third capacitor, and the fourth signal output terminal 2032 is connected to the first signal input terminal 1021 through the fourth capacitor.

[0075] Specifically, the second sampling signal output by the second THA 20 is composed of a fifth signal and a sixth signal. Optionally, the third sampling switch in the second sample-and-hold switch group 201 can sample the first signal received by the third signal input terminal 2021 and output the fifth signal from the third signal output terminal 2031. Optionally, the fourth sampling switch in the second sample-and-hold switch group 201 can sample the second signal received by the fourth signal input terminal 2022 and output the sixth signal from the fourth signal output terminal 2032. The first signal input terminal 1021 in the first input terminal 102 receives the first signal, and the second signal input terminal 1022 receives the second signal. Since the first signal and the second signal are signals with opposite phases, and the phase of the first signal is the same as the phase of the fifth signal, and the phase of the second signal is the same as the phase of the sixth signal. When the first THA 10 is in the hold state, since the third signal output terminal 2031 and the second signal input terminal 1022 are connected through a third capacitor, and the fourth signal output terminal 2032 and the first signal input terminal 1021 are connected through a fourth capacitor, the fifth signal can be sent to the second signal input terminal 1022, and the sixth signal can be sent to the first signal input terminal 1021. Then, at the second input terminal 202, a cancellation effect can be achieved between the fifth signal and the second signal, and a cancellation effect can be achieved between the sixth signal and the first signal. When the first sample-and-hold switch group 101 is in the hold state, at the input terminal of the first sample-and-hold switch group 101, the differential signal received at the input terminal of the first sample-and-hold switch group 101 and the sampling signal output by the second sample-and-hold switch group 201 can produce a cancellation effect, eliminating the influence of signal feedthrough and improving the quality of the first sampling signal.

[0076] For example, as Figure 10 shown, Figure 10 FIG. is a schematic diagram of another analog demultiplexer provided by an embodiment of the present application. The analog demultiplexer can be equipped with an equalization technique and an on-chip clock module. Next, an analog demultiplexer with a 130 GB (original input speed) and a coding form of four-level pulse amplitude modulation (4 Pulse Amplitude Modulation, PAM4) will be used as an example for illustration. The clock module can introduce an on-chip quadrupling module (high-speed clock), obtain a low-speed clock from the outside, and then obtain a high-speed sampling clock through on-chip frequency doubling technology. In addition, through the on-chip gating module, an on-chip clock or a sampling clock obtained from the outside can be selected. The input and output paths of the data can both increase the equalization function, and the channel loss can be compensated by a continuous-time linear equalization (CTLE). For the core module of the analog demultiplexer, the sample-and-hold amplifier, a multi-path feedback cancellation technology is introduced: by introducing cross-coupling capacitors between two stages of THA, feedthrough cancellation is achieved.

[0077] For another example Figure 11 as shown Figure 11 FIG. is a schematic diagram of a sample-and-hold amplifier structure of a multi-path feedback cancellation technique provided by an embodiment of the present application. The THA uses an SEF (switch emitter follower) as a sampling switch, and two inverted clock signals respectively control two THAs, so that when one path is in the sampling mode, the other path is in the hold mode. In the sampling mode, the clock sampling signal is at a high level, the clock hold signal is at a low level, and the switching triode is closed. At this time, the circuit is similar to an emitter follower, and the voltage on the sampling capacitor follows the change of the input signal. In the hold mode, the clock hold signal is at a high level, the clock sampling signal is at a low level, the output design follower is turned off, and the voltage on the sampling capacitor remains unchanged. Different from the traditional hold-mode feedthrough cancellation technique that uses the internal cross-coupling capacitor of the THA, that is, the positive-terminal input signal and the negative-terminal input signal are respectively coupled to the negative-terminal sampling capacitor through the coupling capacitor and the parasitic capacitor to cancel the signal feedthrough, instead, a cross-coupling capacitor is introduced between the two THAs: the sampling signals output by the two THAs are respectively coupled to the input of the emitter follower of the other THA circuit through the capacitor, so that the charge injection of the inverted signal of the THA in the introduced sampling mode and the leakage signal of the other THA in the hold mode cancel each other, reducing the influence of the input feedthrough signal in the hold mode.

[0078] An embodiment of the present application provides an analog demultiplexing device, and the analog demultiplexing device includes the analog demultiplexer described in any one of the above.

[0079] An embodiment of the present application provides a switch, and the switch includes the analog demultiplexer described in any one of the above, or the above analog demultiplexing device.

[0080] An embodiment of the present application provides a chip system, and the chip system includes the analog demultiplexer described in any one of the above, or the above analog demultiplexing device.

[0081] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For the parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0082] It should be noted that, for the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present application is not limited by the described action sequence, because according to the present application, certain steps may be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0083] In several embodiments provided by the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the above division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be electrical or other forms.

[0084] The units described above as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0085] In addition, in each embodiment of the present application, each functional unit can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0086] If the above integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc., specifically, the processor in the computer device) to execute all or part of the steps of the above methods in each embodiment of the present application. Among them, the aforementioned storage medium can include: USB flash drives, mobile hard disks, magnetic disks, optical disks, read-only memories (ROM) or random access memories (RAM), etc., all kinds of media that can store program codes.

[0087] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An analog demultiplexer, characterized in that, The analog demultiplexer includes a first sample-and-hold amplifier THA and a second sample-and-hold amplifier THA. The first THA includes a first input terminal, a first sample-and-hold switch group, and a first output terminal. The second THA includes a second input terminal, a second sample-and-hold switch group, and a second output terminal. The first output terminal is connected to the second input terminal through a first coupling capacitor group. The first THA is configured to receive a differential signal through the first input terminal, and the first sample-and-hold switch group is currently in the sampling state. The second THA is configured to receive the differential signal through the second input terminal, and the second sample-and-hold switch group is currently in the hold state. The first THA is further configured to sample the differential signal through the first sample-and-hold switch group in the sampling state, and output a first sampled signal at the first output terminal; and send the first sampled signal to the second input terminal through the first coupling capacitor group. The second THA is further configured to, when the second sample-and-hold switch group is in the hold state, receive the first sampled signal through the second input terminal, wherein the first sampled signal and the differential signal generate a cancellation effect at the second input terminal. The second THA is further configured to control the second sample-and-hold switch group to switch to the sampling state, sample the differential signal through the second sample-and-hold switch group, and output a second sampled signal at the second output terminal.

2. The analog demultiplexer according to claim 1, wherein The input terminal of the first sample-and-hold switch group is connected to the first input terminal, and the output terminal of the first sample-and-hold switch group is connected to the first output terminal; the input terminal of the second sample-and-hold switch group is connected to the second input terminal, and the output terminal of the second sample-and-hold switch group is connected to the second output terminal; the output terminal of the first sample-and-hold switch group is connected to the input terminal of the second sample-and-hold switch group through the first coupling capacitor group.

3. The analog demultiplexer according to claim 1 or 2, characterized in that, The first THA is further configured to control the first sample-and-hold switch group according to a first clock period signal; when the first clock period signal is at the rising edge, the first THA is specifically configured to control the first sample-and-hold switch group to be in the sampling state; when the first clock period signal is at the falling edge, the first THA is specifically configured to control the first sample-and-hold switch group to be in the hold state.

4. The analog demultiplexer according to any one of claims 1 to 3, characterized in that, The differential signal is composed of a first signal and a second signal, and the first signal and the second signal are in opposite phases; the first input terminal includes a first signal input terminal and a second signal input terminal, the first output terminal includes a first signal output terminal and a second signal output terminal; the second input terminal includes a third signal input terminal and a fourth signal input terminal, and the second output terminal includes a third signal output terminal and a fourth signal output terminal. The first THA is specifically configured to receive the first signal through the first signal input terminal and output a third signal through the first signal output terminal; receive the second signal through the second signal input terminal and output a fourth signal through the second signal output terminal; the first sampled signal includes the third signal and the fourth signal. The second THA is specifically configured to receive the first signal through the third signal input terminal and output a fifth signal through the third signal output terminal; receive the second signal through the fourth signal input terminal and output a sixth signal through the fourth signal output terminal; the second sampling signal includes the fifth signal and the sixth signal.

5. The analog demultiplexer according to claim 4, wherein The first coupling capacitor group includes a first capacitor and a second capacitor; the first signal output terminal is connected to the fourth signal input terminal through the first capacitor, and the second signal output terminal is connected to the third signal input terminal through the second capacitor.

6. The analog demultiplexer according to any one of claims 1-5, characterized in that, The second output terminal is connected to the first input terminal through a second coupling capacitor group. When the second sample-and-hold switch group is in the sampling state, the first sample-and-hold switch group is in the holding state. The second THA is further configured to send the second sampling signal to the first input terminal through the second coupling capacitor group. The first THA is further configured to, when the first sample-and-hold switch group is in the holding state, receive the second sampling signal through the first input terminal, wherein the second sampling signal and the differential signal produce a cancellation effect at the first input terminal.

7. The analog demultiplexer according to claim 6, wherein The output terminal of the second sample-and-hold switch group is connected to the input terminal of the first sample-and-hold switch group through the second coupling capacitor group.

8. The analog demultiplexer according to claim 6 or 7, characterized in that, The second THA is further configured to control the second sample-and-hold switch group according to a second clock cycle signal; the second clock cycle signal has the same clock cycle as the first clock cycle signal and opposite phases; when the second clock cycle signal is at the rising edge, the second THA is specifically configured to control the second sample-and-hold switch group to be in the sampling state; when the second clock cycle signal is at the falling edge, the second THA is specifically configured to control the second sample-and-hold switch group to be in the holding state.

9. The analog demultiplexer according to any one of claims 6-8, characterized in that The second coupling capacitor group includes a third capacitor and a fourth capacitor; the third signal output terminal is connected to the second signal input terminal through the third capacitor, and the fourth signal output terminal is connected to the first signal input terminal through the fourth capacitor.

10. A simulation demultiplexing device, characterized in that, The analog demultiplexing device includes the analog demultiplexer according to any one of claims 1-9.

11. A switch, characterized in that, The switch includes the analog demultiplexer according to any one of claims 1-9.

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