CGRA-based software defined protocol controller and multi-protocol exchange chip

Abstract

The invention provides a software defined protocol controller based on CGRA and a multi-protocol exchange chip. The software defined protocol controller comprises a coarse particle reconfigurable array CGRA module, an embedded field programmable gate array module eFPGA and an application specific integrated circuit module ASIC. The coarse grain reconfigurable array CGRA module consists of a coarse grain reconfigurable network processing unit PE and is used for realizing partial control logic in a protocol layer in the software defined protocol controller; the embedded field programmable gate array module eFPGA is used for realizing partial control logic in a data link layer in the software defined protocol controller; and the ASIC is used for realizing a public part of a standard protocol and a user-defined protocol in the software defined protocol controller and public processing logic irrelevant to the protocol. According to the invention, unified processing of various heterogeneous protocols is realized, redundant logic in the protocol controller is reduced, and maximum utilization of hardware resources is realized.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a software-defined protocol controller based on CGRA and a multi-protocol switching chip. Background Art

[0002] Currently, most of the existing multi-protocol controllers adopt a technical route that combines an Embedded Field-Programmable Gate Array (eFPGA) and an Application Specific Integrated Circuit (ASIC). Referring to the patent number CN110535788A, the approach is to implement the multi-protocol data link layer function processing units with large functional differences in the eFPGA, and implement the common processing units that can be merged in the form of ASIC.

[0003] At present, although the above solution realizes the reuse of the logic circuits of different protocol controllers to a certain extent, limited by the inconsistencies in routing table lookup, cache read / write, and traffic control of multiple protocols, it is still necessary to regard this part of the functions as the private computing grains of each protocol controller and implement them independently, and the reuse of this part of the logic cannot be achieved. And this part of the logic overhead cannot be underestimated. While increasing the overall chip area and power consumption, it also limits the types of access protocols and cannot achieve flexible reconfiguration. Summary of the Invention

[0004] In order to solve the incompatibility problems of multiple protocols in aspects such as protocol parsing, traffic management, and routing table lookup, the present invention provides a software-defined protocol controller based on CGRA and a multi-protocol switching chip, which can realize the unified processing of multiple heterogeneous protocols, reduce the redundant logic in the protocol controller, maximize the utilization of hardware resources, effectively reduce the possibility of routing errors and network congestion, and more effectively manage network traffic and path selection.

[0005] In a first aspect, the present invention provides a software-defined protocol controller based on CGRA, including a coarse-grained reconfigurable array CGRA module, an embedded field-programmable gate array module eFPGA, and an application specific integrated circuit module ASIC;

[0006] The coarse-grained reconfigurable array module CGRA is composed of coarse-grained reconfigurable network processing units PE, and is used to implement part of the control logic in the protocol layer of the software-defined protocol controller;

[0007] The embedded field-programmable gate array module eFPGA is used to implement part of the control logic in the data link layer of the software-defined protocol controller;

[0008] The dedicated application-specific integrated circuit module ASIC is used to implement the common part of the standard protocol and the custom protocol in the software-defined protocol controller and the protocol-independent common processing logic.

[0009] Further, the coarse-grained reconfigurable array module CGRA includes a software-defined protocol processing unit;

[0010] The software-defined protocol processing unit is used to configure the coarse-grained reconfigurable network processing unit PE to execute the logic of protocol parsing, message processing, and traffic management.

[0011] Further, the coarse-grained reconfigurable array module CGRA further includes a converged routing unit;

[0012] The converged routing unit is used to integrate the routing information from different routing protocols into a converged routing table.

[0013] Further, the converged routing unit includes a field extraction subunit and a table lookup subunit;

[0014] The field extraction subunit is used to extract the content of the message software protocol field to obtain the routing table lookup key value corresponding to the protocol;

[0015] The table lookup subunit is used to obtain the table lookup result in the converged routing table based on the routing table lookup key value of the message software protocol.

[0016] Further, the table lookup subunit is specifically used for:

[0017] For complex protocols, perform a hash operation on the routing table lookup key value, use the hash operation result to index the hash address mapping table to obtain the index address of the converged routing table, and obtain the routing table lookup result;

[0018] For simple protocols, directly obtain the routing table lookup result according to the routing table lookup key value;

[0019] Among them, the complex protocol refers to a protocol in which there is a conflict between the routing table lookup key value and the table entry configuration in the converged routing table; the simple protocol refers to a protocol in which there is no conflict between the routing table lookup key value and the table entry configuration in the converged routing table.

[0020] Further, some control logic in the data link layer is used to implement the reconfigurability requirements of the data link layer;

[0021] The reconfigurability requirements of the data link layer at least include frame synchronization processing, data message reception processing, and CRC operation.

[0022] Further, the dedicated application-specific integrated circuit module ASIC at least includes a protocol physical layer processing module and a configuration management module;

[0023] The protocol physical layer processing module consists of a physical medium adaptation layer PMA and a physical coding sublayer PCS.

[0024] Furthermore, the coarse-grained reconfigurable network processing unit PE includes an input routing module, a network processing ALU module, a local instruction sequence storage module, a local SRAM module, and an output routing module;

[0025] Among them, the input routing module is used to receive network packet data, obtain packet descriptor data, or obtain routing lookup table key values according to preset priorities and rules;

[0026] The local instruction sequence storage module is used to store multiple instructions; the instructions support multiple execution methods;

[0027] The network processing ALU module executes a series of operations according to the instructions stored in the local instruction sequence storage module;

[0028] The local SRAM module is used to store and process data; the storing and processing of data include packet access operations or lookup table operations;

[0029] The output routing module is used to output the processed data packets or control information of the current coarse-grained reconfigurable network processing unit PE to the outside;

[0030] The output of the processed data packets or control information of the current coarse-grained reconfigurable network processing unit PE includes outputting packet data according to the dequeue priority scheduling, outputting the processed packet descriptor data, or outputting the routing lookup table result.

[0031] In a second aspect, the present invention provides a multi-protocol switching chip, including: a peripheral interface, and a CGRA-based software-defined protocol controller provided by one of the first aspect and its possible implementation manners above.

[0032] Advantages of the present invention:

[0033] The software-defined protocol controller provided by the present invention adopts a technical route combining ASIC, eFPGA, and CGRA. Compared with the implementation method using pure ASIC, the flexibility and reconfigurability of the protocol controller are greatly improved; compared with the implementation method using pure eFPGA, while effectively reducing the area of the protocol controller, the power consumption is reduced; the introduction of CGRA technology effectively solves the incompatibility problems of multiple protocols in aspects such as protocol parsing, traffic management, and routing lookup, realizes the unified processing of multiple heterogeneous protocols, reduces the redundant logic in the protocol controller, and realizes the maximum utilization of hardware resources.

[0034] The software-defined protocol controller provided by the present invention implements heterogeneous protocol fusion routing technology, integrates routing information from different routing protocols into a fusion routing table, and realizes the function of unified routing table lookup for different protocols. The heterogeneous protocol fusion routing technology can effectively reduce the possibility of routing errors and network congestion, and can manage network traffic and path selection more effectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0036] Figure 1 FIG. is a schematic structural diagram of a software-defined protocol controller based on CGRA provided by an embodiment of the present invention;

[0037] Figure 2 FIG. is a schematic structural diagram of a coarse-grained reconfigurable array module CGRA provided by an embodiment of the present invention;

[0038] Figure 3 FIG. is a block diagram of the configuration structure of a software-defined protocol processing unit provided by an embodiment of the present invention;

[0039] Figure 4 FIG. is a software-defined routing forwarding framework diagram provided by an embodiment of the present invention;

[0040] Figure 5 FIG. is a block diagram of the PE architecture in a coarse-grained reconfigurable array provided by an embodiment of the present invention;

[0041] Figure 6 FIG. is a schematic structural diagram of a multi-protocol switching chip provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0043] Such as Figure 1As shown in the figure, an embodiment of the present invention provides a software-defined protocol controller based on a CGRA, which includes a coarse-grained reconfigurable array module CGRA, an embedded field-programmable gate array module eFPGA, and an application-specific integrated circuit module ASIC;

[0044] The coarse-grained reconfigurable array module CGRA is composed of coarse-grained reconfigurable network processing units PE, and is used to implement part of the control logic in the protocol layer of the software-defined protocol controller;

[0045] The embedded field-programmable gate array module eFPGA is used to implement part of the control logic in the data link layer of the software-defined protocol controller. Specifically, this part of the control logic is mainly used to implement the reconfigurable requirements of the data link layer such as frame synchronization processing, data packet sending and receiving processing, and CRC operation, to support port-level and bit-level reconfiguration, and can process user-defined protocols.

[0046] The application-specific integrated circuit module ASIC is used to implement the common part of the standard protocol and the custom protocol in the software-defined protocol controller and the common processing logic independent of the protocol. Specifically, it includes general logic such as protocol physical layer processing and configuration management to save the circuit implementation area and reduce power consumption.

[0047] As Figure 2 shown, the coarse-grained reconfigurable array module CGRA includes a software-defined protocol processing unit; the software-defined protocol processing unit is used to configure the coarse-grained reconfigurable network processing unit PE so that it executes the logic of protocol parsing, message processing, and traffic management.

[0048] The coarse-grained reconfigurable array module CGRA further includes a fusion routing unit; the fusion routing unit is used to integrate routing information from different routing protocols into a fusion routing table.

[0049] The fusion routing unit includes a field extraction subunit and a lookup table subunit; the field extraction subunit is used to extract the content of the message software protocol field to obtain the routing lookup key value corresponding to the protocol; the lookup table subunit is used to obtain the lookup result in the fusion routing table based on the routing lookup key value of the message software protocol.

[0050] The lookup table subunit is specifically used for: for complex protocols, performing a hash operation on the routing lookup key value, using the hash operation result to index the hash address mapping table to obtain the index address of the fusion routing table, and obtaining the routing lookup result; for simple protocols, directly obtaining the routing lookup result according to the routing lookup key value;

[0051] Among them, the complex protocol refers to a protocol in which there is a conflict between the routing lookup table key value and the entry configuration in the fusion routing table; the simple protocol refers to a protocol in which there is no conflict between the routing lookup table key value and the entry configuration in the fusion routing table.

[0052] Specifically, the coarse-grained reconfigurable array module CGRA is composed of coarse-grained reconfigurable network processing elements (Processing Element, PE) and is used to implement the protocol layer partial control logic in the software-defined protocol controller. This partial control logic is mainly applied in two aspects. The first aspect is to use the software-defined protocol processing unit to perform protocol parsing, message processing, and traffic management; the second aspect is to use the fusion routing unit to integrate routing information from different routing protocols into a fusion routing table to achieve the function of unified routing lookup for different protocols.

[0053] Specifically, an implementable manner of the software-defined protocol processing unit in the first aspect of the coarse-grained reconfigurable array module CGRA is as Figure 3 shown. The coarse-grained reconfigurable array is a two-dimensional structure with a built-in transmission network. According to different application requirements, the network processing elements PE of the coarse-grained reconfigurable array can be configured differently to implement different software-defined protocol processing functions. As Figure 3 shown, the coarse-grained reconfigurable array is divided into three parts to implement the functions of protocol parsing, message processing, and traffic management respectively. It should be noted that the PE ratio and the interconnection relationship of various configuration modes in this implementation manner do not limit this application.

[0054] Specifically, an implementable manner of the fusion routing unit in the second aspect of the coarse-grained reconfigurable array module CGRA is as Figure 4 shown, Figure 4 which is a block diagram of the software-defined routing forwarding architecture.

[0055] Specifically, in order to meet the routing lookup requirements of different protocols, the fusion routing unit is applied. The fusion routing unit includes a field extraction subunit and a lookup subunit.

[0056] Specifically, the field extraction subunit is used to complete the comparison, judgment, and extraction of the lookup table key values, and adopts the CGRA technology to extract the content of the software-defined fields of the message. For the Ethernet protocol, it will complete the extraction of information such as the MAC address, Vlan, number of tag layers, and protocol type of the message; the lookup table subunit is used to send a lookup table request and obtain the lookup table result. After the messages of different protocols pass through the field extraction subunit, the key values (Key) for the protocol routing lookup are extracted from the messages. The key values (Key) are calculated through the hash module. The hash operation output of the key values (Key) of each protocol is generally a random but definite value. Subsequently, the hash operation result is used to index the hash address mapping table to obtain the index address of the fusion routing table, and thus the routing lookup result is obtained. Compared with the direct routing lookup of traditional protocols, software-defined routing increases the hash operation and the hash address mapping table query time, increasing its lookup latency.

[0057] Specifically, for the protocols where there is no conflict between the routing lookup key value and the table entry configuration in the fusion routing table, they are defined as simple protocols, and the routing lookup result is directly obtained according to the routing lookup key value, which is the same as the traditional routing lookup; for the protocols where there is a conflict between the routing lookup key value and the table entry configuration in the fusion routing table, they are defined as complex protocols. The routing lookup key value is calculated through the hash operation, and then the hash operation result is used to index the hash address mapping table to obtain the index address of the fusion routing table to obtain the final routing lookup result.

[0058] Further, as Figure 5 shown, the coarse-grained reconfigurable network processing unit PE includes an input routing module, a network processing ALU module, a local instruction sequence storage module, a local SRAM module, and an output routing module.

[0059] The input routing module is used to receive network message data, message descriptor data, or obtain routing lookup key values according to the preset priorities and rules. Specifically, in the queue management mode or the switching mode, it obtains messages from the external routing bus; in the message processing mode, it realizes the acquisition of message descriptors; in the TCAM mode, it realizes the acquisition of lookup table key values.

[0060] The network processing ALU module executes a series of operations according to the instructions stored in the local instruction sequence storage module. Specifically, an input message triggers an operation to judge the Nth byte, and according to the judgment result, a storage or forwarding operation is performed, or a hash operation is performed on the N - M bytes, and the SRAM is searched with the hash value.

[0061] The local instruction sequence storage module is used to store multiple instructions, and the instructions support multiple execution modes. Specifically, this module is a storage block that can store 16 - 256 instructions. The instructions in this storage module support multiple execution modes. Specifically, they can be executed sequentially or according to jumps; each module can process only one instruction and perform pipelining operations between modules; or one PE can support multiple cycles for multiple judgments and operations. When configured as complex instructions for deep packet parsing, the local SRAM can also be used as the instruction storage space to further expand the instruction depth.

[0062] The output routing module is used to output the processed data packets or control information of the current coarse-grained reconfigurable network processing unit PE to the outside. Specifically, in the queue management mode or the switching mode, the packet data is scheduled for output according to the dequeue priority; in the packet processing mode, the output of the processed packet descriptor data is realized; in the TCAM mode, the output of the routing lookup result is realized. Specifically, the output routing module needs to operate according to certain instructions, such as the status information of the input routing module of other PEs or the bus occupancy information.

[0063] The local SRAM module is used to store and process data; the storing and processing of data include packet access operations or lookup operations. Specifically, the local SRAM module is the core of each PE. In the queue management mode, the switching mode or the packet processing mode, it can be used for packet access operations; in the TCAM mode or the packet processing mode, it can be used for lookup operations; in the complex packet processing mode, it can also be used as a complex instruction storage space to further expand the instruction depth.

[0064] Furthermore, the application-specific integrated circuit module ASIC at least includes a protocol physical layer processing module and a configuration management module; the protocol physical layer processing module is composed of a physical medium attachment layer PMA and a physical coding sublayer PCS.

[0065] Specifically, the protocol physical layer processing module consists of a Physical Medium Attachment (PMA) and a Physical Coding Sublayer (PCS); the Physical Medium Attachment PMA is mainly used to implement serialization and deserialization functions. The Physical Medium Attachment PMA integrates SerDes, transmit and receive buffers, a clock generator, and a clock recovery circuit, etc. The functions of the Physical Medium Attachment PMA between different protocol interfaces are basically the same, and can be implemented through simple normalization processing, so as to realize the logical multiplexing of the Physical Medium Attachment PMA. The Physical Coding Sublayer PCS is mainly used to implement functions such as encoding and decoding, scrambling and descrambling, polarity control, PRBS generation and detection, etc. Extract the greatest common divisor of the functional requirements of mainstream protocols in the Physical Coding Sublayer PCS to make general logic, and make the differential functions into configurable logic to finally realize the design of the general Physical Coding Sublayer PCS.

[0066] Specifically, the configuration management module is a channel for receiving and transmitting software-defined configuration flows, which has nothing to do with the processing process of the protocol itself, and is used to implement the parameter configuration of the software-defined protocol controller.

[0067] An embodiment of the present invention also provides a multi-protocol switching chip, as Figure 6 shown, which is a schematic structural diagram, and consists of Figure 6 It can be seen that the multi-protocol switching chip includes a peripheral interface and the multi-protocol controller 100 provided by one of the above embodiments and its possible implementation manners. In actual operation, the multi-protocol switching chip needs to cooperate with an external master and combine its own SPI interface to flexibly configure the working protocol mode of the multi-protocol controller 100, so as to simultaneously meet the functional requirements of supporting multiple protocol specifications.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A software-defined protocol controller based on CGRA, characterized in that, It includes a coarse-grained reconfigurable array module CGRA, an embedded field-programmable gate array module eFPGA, and an application-specific integrated circuit module ASIC; The coarse-grained reconfigurable array module CGRA is composed of coarse-grained reconfigurable network processing units PE, which is used to implement part of the control logic in the protocol layer of the software-defined protocol controller; The embedded field-programmable gate array module eFPGA is used to implement part of the control logic in the data link layer of the software-defined protocol controller; The application-specific integrated circuit module ASIC is used to implement the common part of the standard protocol and the custom protocol in the software-defined protocol controller and the common processing logic independent of the protocol.

2. The software-defined protocol controller based on CGRA according to claim 1, wherein The coarse-grained reconfigurable array module CGRA includes a software-defined protocol processing unit; The software-defined protocol processing unit is used to configure the coarse-grained reconfigurable network processing unit PE so that it executes the logic of protocol parsing, message processing, and traffic management.

3. The software-defined protocol controller based on CGRA according to claim 1, characterized in that, The coarse-grained reconfigurable array module CGRA also includes a fusion routing unit; The fusion routing unit is used to integrate routing information from different routing protocols into a fusion routing table.

4. The software-defined protocol controller based on CGRA according to claim 3, wherein The fusion routing unit includes a field extraction sub-unit and a look-up table sub-unit; The field extraction sub-unit is used to extract the content of the message software protocol field to obtain the routing look-up table key value corresponding to the protocol; The look-up table sub-unit is used to obtain the look-up table result in the fusion routing table based on the routing look-up table key value of the message software protocol.

5. The software-defined protocol controller based on CGRA according to claim 4, characterized in that, The look-up table sub-unit is specifically used for: For complex protocols, perform a hash operation on the routing look-up table key value, use the hash operation result to index the hash address mapping table to obtain the index address of the fusion routing table, and obtain the routing look-up table result; For simple protocols, directly obtain the routing look-up table result according to the routing look-up table key value; Among them, the complex protocol refers to a protocol in which there is a conflict between the routing look-up table key value and the table entry configuration in the fusion routing table; the simple protocol refers to a protocol in which there is no conflict between the routing look-up table key value and the table entry configuration in the fusion routing table.

6. The software-defined protocol controller based on CGRA according to claim 1, characterized in that, Part of the control logic in the data link layer is used to implement the reconfigurable requirements of the data link layer; The reconfigurable requirements of the data link layer at least include frame synchronization processing, data message reception processing, and CRC operation.

7. A software-defined protocol controller based on CGRA according to claim 1, characterized in that, The application-specific integrated circuit module ASIC at least includes a protocol physical layer processing module and a configuration management module; The protocol physical layer processing module is composed of a physical medium attachment layer PMA and a physical coding sub-layer PCS.

8. The software-defined protocol controller based on CGRA according to claim 1, characterized in that The coarse-grained reconfigurable network processing unit PE includes an input routing module, a network processing ALU module, a local instruction sequence storage module, a local SRAM module, and an output routing module; Among them, the input routing module is used to receive network message data, obtain message descriptor data, or obtain routing look-up table key values according to preset priorities and rules; The local instruction sequence storage module is used to store multiple instructions; the instructions support multiple execution methods; The network processing ALU module executes a series of operations according to the instructions stored in the local instruction sequence storage module; The local SRAM module is used for storing and processing data; the storing and processing of data includes packet access operations or look-up table operations; The output routing module is used for outputting the processed data packets or control information that have passed through the current coarse-grained reconfigurable network processing unit PE to the outside; The output of the processed data packets or control information of the current coarse-grained reconfigurable network processing unit PE includes outputting packet data scheduled according to the dequeue priority, outputting processed packet descriptor data, or outputting routing look-up table results.

9. A multi-protocol switching chip, characterized in that, Comprising: A peripheral interface, and a CGRA-based software-defined protocol controller according to any one of claims 1 to 8.

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