Image sensing apparatus and control method thereof

Abstract

The invention relates to an image sensing apparatus and a control method thereof. An image sensing apparatus may include: a test control switch configured to selectively connect a test reset line for transmitting a test reset signal and a test image line for transmitting a first test image signal; and a first correlated double sampling (CDS) circuit configured to receive the test reset signal through the test reset line and to receive the first test image signal through the test image line. When the test control switch is closed, the first CDS circuit may receive a second test image signal through the test image line.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to an image sensing device and an imaging device including the same. Background Art

[0002] An image sensing device is a device that captures an optical image by using the properties of a photosensitive semiconductor material that responds to light. With the development of the vehicle, medical, computer, and communication industries, the demand for high-performance image sensing devices is increasing in various fields such as smart phones, digital cameras, gaming devices, the Internet of Things, robots, security cameras, and medical micro cameras.

[0003] Recently, in order to provide high-quality images, various schemes for detecting defects in an image sensing device have been developed. Among various schemes, research and development have been conducted on interpolating pixels that have omitted information or detecting defective pixels by using information of adjacent pixels in the image sensing device. Summary of the Invention

[0004] In an embodiment of the present disclosure, an image sensing device may include: a test control switch configured to selectively connect a test reset line for transmitting a test reset signal and a test image line for transmitting a first test image signal; and a first correlated double sampling (CDS) circuit configured to receive the test reset signal through the test reset line and receive the first test image signal through the test image line. When the test control switch is closed, the first CDS circuit may receive a second test image signal through the test image line.

[0005] In an embodiment of the present disclosure, an image sensing device may include: a test control switch configured to selectively connect a test reset line for transmitting a test reset signal generated from a test circuit and a test image line for transmitting a test image signal generated from the test circuit; and a correlated double sampling (CDS) circuit configured to receive the test image signal through the test image line and receive the test reset signal through the test reset line. The test control switch may control the difference between the test image signal and the test reset signal input to the CDS circuit.

[0006] In an embodiment of the present disclosure, a method of controlling an image sensing device may include the steps of: transmitting a test image signal and a test reset signal to a first correlated double sampling (CDS) circuit included in the image sensing device through a first test image line and a first test reset line, respectively; transmitting the test image signal and the test reset signal to a second CDS circuit included in the image sensing device through a second test image line and a second test reset line, respectively; and controlling the difference between the test image signal and the test reset signal input to the first CDS circuit by selectively connecting the first test image line and the first test reset line. Description of the Drawings

[0007] Figure 1 is a block diagram showing the configuration of an imaging device according to an embodiment of the present disclosure.

[0008] Figure 2 is a circuit diagram showing the detailed configuration of pixels included in the pixel array according to an embodiment of the present disclosure Figure 1 thereof.

[0009] Figure 3 is a block diagram showing the detailed configuration of an ADC according to an embodiment of the present disclosure Figure 1 thereof.

[0010] Figure 4 is a block diagram showing the configuration of a test circuit connected to the ADC according to an embodiment of the present disclosure Figure 1 thereof.

[0011] Figure 5A is a graph showing the difference in power between a test image signal and a test reset signal according to an embodiment of the present disclosure.

[0012] Figure 5B is an image output according to the difference in power between a test image signal and a test reset signal in Figure 5A according to an embodiment of the present disclosure.

[0013] Figure 6A is a graph showing the difference in power between a test image signal and a test reset signal according to an embodiment of the present disclosure.

[0014] Figure 6B is an image output according to the difference in power between a test image signal and a test reset signal in Figure 6A according to an embodiment of the present disclosure.

[0015] Figure 7 is a diagram for describing the operation of a test circuit corresponding to an image according to an embodiment of the present disclosure Figure 6B thereof Figure 4 in accordance with the present disclosure.

[0016] Figure 8 is a timing diagram of a test circuit according to an embodiment of the present disclosure. Detailed Description of the Embodiments

[0017] Hereinafter, various embodiments of the present disclosure will be described with reference to the drawings. However, it should be noted that the present disclosure is not limited to specific embodiments, but includes various modifications, equivalents, and / or alternatives of the embodiments. The embodiments of the present disclosure may provide various effects that can be directly and indirectly recognized through the present disclosure.

[0018] Various embodiments of the present disclosure are directed to an image sensing device for detecting defects in an image data output operation and an imaging device including the same.

[0019] The technical problems of the present disclosure are not limited to the above technical problems, and those skilled in the art will clearly understand other technical problems not mentioned herein from the following description.

[0020] Figure 1 is a block diagram showing the configuration of an imaging device 10 according to an embodiment of the present disclosure.

[0021] Referring to Figure 1 , the imaging device 10 may be a device such as a digital still camera for capturing still images or a digital video camera for capturing moving images. For example, the imaging device 10 may be implemented as a digital single-lens reflex (DSLR) camera, a mirrorless camera, or a smartphone, but the embodiments are not limited thereto. The imaging device 10 may be a device capable of photographing an object and generating an image, including an image pickup device.

[0022] The imaging device 10 may include an image sensing device 100 and an image signal processor (ISP) 200.

[0023] The image sensing device 100 may be a complementary metal oxide semiconductor image sensor (CIS) for converting incident light into an electrical signal. The image sensing device 100 may include a pixel array 110, a row driver 120, a ramp generator 130, an analog-to-digital converter (ADC) 140, an output buffer 150, a column driver 160, and a timing controller 170. In this case, each component of the image sensing device 100 may be merely an example, and at least some components may be added to the image sensing device 100 or at least some components of the image sensing device 100 may be omitted if necessary.

[0024] The pixel array 110 may include a plurality of pixels arranged in multiple rows and multiple columns. In an embodiment, the plurality of pixels may be arranged in the form of a two-dimensional (2-D) pixel array including rows and columns. In another embodiment, the plurality of unit image pixels may be arranged in the form of a 3-D pixel array. The plurality of pixels may convert an optical signal into an electrical signal in units of pixels or in units of pixel groups. The pixels within a pixel group may share at least one internal circuit. The pixel array 110 may receive driving signals from the row driver 120, including a row selection signal, a pixel reset signal, and a transfer signal. The corresponding pixels of the pixel array 110 may be enabled by the driving signals to perform operations corresponding to the row selection signal, the pixel reset signal, and the transfer signal.

[0025] Each pixel of the pixel array 110 may have two or more different sensitivities. In this case, the sensitivity may refer to an increment of the image data IDATA (or an increment of the response) for an increment of the intensity of incident light. That is, as the sensitivity increases, the increment of the image data IDATA for an increment of the intensity of incident light may increase. As the sensitivity decreases, the increment of the image data IDATA for an increment of the intensity of incident light may decrease. In the present disclosure, the sensitivity may be determined by a conversion gain.

[0026] The row driver 120 may enable the pixel array 110 based on instructions and / or control signals supplied by the timing controller 170 such that the pixel array 110 performs a specific operation on pixels included in a corresponding row. In an embodiment, the row driver 120 may select at least one pixel arranged in at least one row of the pixel array 110. The row driver 120 may generate a row selection signal to select at least one row among multiple rows. The row driver 120 may sequentially enable a pixel reset signal and a transfer signal for pixels corresponding to the selected at least one row. Accordingly, reference signals and image signals in an analog form generated from respective pixels of the selected row may be sequentially transmitted to the ADC 140. In this case, the reference signal may be an electrical signal provided to the ADC 140 when a sensing node (e.g., a floating diffusion region) of a pixel is reset. The image signal may be an electrical signal provided to the ADC 140 when photo charges generated by a pixel are accumulated in the sensing node. The reference signal indicating reset noise specific to a pixel and the image signal indicating the intensity of incident light may be collectively referred to as pixel signals.

[0027] The CMOS image sensor may use correlated double sampling (CDS) such that an unwanted offset value (e.g., fixed pattern noise) of a pixel may be removed by sampling a pixel signal twice to remove a difference between two samples. For example, through CDS, an unwanted offset value may be removed by comparing pixel output voltages obtained before and after photo charges generated by incident light are accumulated in a sensing node, thereby measuring a pixel output voltage based only on incident light. In an embodiment, the ADC 140 may sequentially sample and hold reference signals and image signals provided from the pixel array 110 through each of multiple column lines.

[0028] Under the control of the timing controller 170, the ramp generator 130 may generate a ramp signal required for an ADC operation of the ADC 140 and supply the ramp signal to the ADC 140.

[0029] The ADC 140 can sample and hold the pixel signals of each column output from each column line of the pixel array 110, and can output the pixel signals by converting the pixel signals into digital signals. In an embodiment, the ADC 140 can be implemented as a ramp comparison type ADC. The ramp comparison type ADC can include a comparison circuit for comparing a ramp signal that rises or falls over time with a pixel signal in analog form and a counter for performing a counting operation until the ramp signal matches the analog pixel signal.

[0030] The output buffer 150 can temporarily hold and output the image data in column units (i.e., the data IDATA obtained by digitally converting the pixel signals) supplied by the ADC 140. The output buffer 150 can temporarily store the image data IDATA output by the ADC 140 based on the control of the timing controller 170. The output buffer 150 can operate as an interface to compensate for the difference in the transmission (or processing) speeds of the devices connected to the image sensing device 100.

[0031] The column driver 160 can select a column of the output buffer 150 based on the control of the timing controller 170, and can control the output buffer 150 so that the image data IDATA temporarily stored in the selected column of the output buffer 150 is sequentially output. In an embodiment, the column driver 160 can receive an address signal from the timing controller 170. The column driver 160 can select a column of the output buffer 150 by generating a column selection signal based on the address signal, so as to control the output of the image data IDATA from the selected column of the output buffer 150 to the outside.

[0032] The timing controller 170 can control at least one of the row driver 120, the ramp generator 130, the ADC 140, the output buffer 150, and the column driver 160.

[0033] The timing controller 170 can provide a clock signal required for the operation of each component of the image sensing device 100, a control signal for timing control, and an address signal for selecting a row or a column to at least one of the row driver 120, the ramp generator 130, the ADC 140, the output buffer 150, and the column driver 160. According to an embodiment, the timing controller 170 can include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, and a communication interface circuit.

[0034] The ISP 200 can perform image signal processing on the image data IDATA received from the image sensing device 100. The ISP 200 can reduce the noise of the image data IDATA and can perform image signal processing for picture quality improvement, such as interpolation, synthesis, and gamma correction of the image data IDATA, interpolation of the color filter array, color matrix, color correction, color enhancement, and lens distortion correction. In addition, the ISP 200 can generate an image file by compressing and processing the image data generated by performing image signal processing for picture quality improvement, or can restore the image data from the image file. The compression format of the image can be a reversible form or an irreversible form. As an example of the compression format, in the case of a still image, the Joint Photographic Experts Group (JPEG) format or the JPEG 2000 format can be used. In addition, in the case of a moving image, a moving image file can be generated by compressing a plurality of frames according to the Moving Picture Experts Group (MPEG) standard. For example, an image file can be generated according to the Exchangeable Image File Format (Exif) standard.

[0035] The ISP 200 can send the image data for which the image processing operation has been completed to a host device (not shown). The host device (not shown) can be a processor (e.g., an application processor) for processing the image data for which the image processing has been performed received from the ISP 200, a memory (e.g., a non-volatile memory) for storing the image data, or a display device (e.g., a liquid crystal display (LCD)) for visually outputting the image data.

[0036] In addition, the ISP 200 can send a control signal for controlling the operation of the image sensing device 100 (e.g., whether to operate the image sensing device 100, the operation timing of the image sensing device 100, or the operation mode of the image sensing device 100) to the image sensing device 100.

[0037] Figure 2 is a circuit diagram showing the detailed configuration of the pixel PX included in the pixel array 110 Figure 1 according to an embodiment of the present disclosure.

[0038] Referring to Figure 2 , the pixel PX can be one of the plurality of pixels included in the pixel array 110. Figure 2 One pixel PX is shown in

[0039] but other pixels among the plurality of pixels can have substantially the same configuration and operation as the pixel PX. Figure 3 The pixel PX can include a photoelectric conversion element PD, a transfer transistor TX, a reset transistor RX, a floating diffusion region FD, a source follower transistor SF, and a selection transistor SX. Figure 3It is shown that pixel PX includes a photoelectric conversion element PD. However, according to another embodiment of the present disclosure, pixel PX may be a shared pixel having a plurality of photoelectric conversion elements. In this case, a plurality of transfer transistors may be provided according to the plurality of photoelectric conversion elements.

[0040] The photoelectric conversion element PD can generate and accumulate photo charges corresponding to the intensity of incident light. For example, the photoelectric conversion element PD can be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0041] If the photoelectric conversion element PD is implemented as a photodiode, the photoelectric conversion element PD may be a region where a substrate of a first conductivity type (e.g., P-type) is doped with an impurity of a second conductivity type (e.g., N-type).

[0042] The transfer transistor TX may be connected between the photoelectric conversion element PD and the floating diffusion region FD. The transfer transistor TX may be turned on or off in response to a transfer signal TG. The turned-on transfer transistor TX may transfer the photo charges accumulated in the photoelectric conversion element PD to the floating diffusion region FD.

[0043] The reset transistor RX may be connected between the power supply voltage VDD and the floating diffusion region FD, and may reset the voltage of the floating diffusion region FD to the power supply voltage VDD in response to a pixel reset signal RG.

[0044] The floating diffusion region FD may receive photo charges from the transfer transistor TX. The floating diffusion region FD may be connected to the gate of the source follower transistor SF, and may correspond to a region where signal electrons are input and appear as a voltage. In an example, the floating diffusion region FD may be referred to as a sensing node.

[0045] In the present disclosure, a logic high level may mean a voltage level for enabling (e.g., turning on) a corresponding element (e.g., a transistor). A logic low level may mean a voltage level for disabling (e.g., turning off) a corresponding element (e.g., a transistor).

[0046] The source follower transistor SF may be connected between the power supply voltage VDD and the selection transistor SX, and may transmit a corresponding electrical signal to the selection transistor SX by amplifying the change in the potential of the floating diffusion region FD that has received the photo charges accumulated in the photoelectric conversion element PD.

[0047] The selection transistor SX may be connected between the source follower transistor SF and the output signal line, may be turned on by a selection control signal SEL, and may output the electrical signal received from the source follower transistor SF as a pixel signal PS.

[0048] Figure 3 is shown according to an embodiment of the present disclosureFigure 1 Block diagram of the detailed configuration of the ADC 140.

[0049] Referring to Figure 3 , the ADC 140 can receive a ramp signal Vramp from a ramp generator 130, can receive a pixel signal PS from a pixel PX, can generate ADC data ADC_OUT based on the ramp signal Vramp and the pixel signal PS, and can output the ADC data ADC_OUT. In an example, the ADC 140 can receive a ramp signal Vramp from a ramp generator 130, can receive a test reset signal and a test image signal from a test circuit, can generate ADC data ADC_OUT based on the ramp signal Vramp, the test reset signal, and the test image signal, and can output the ADC data ADC_OUT.

[0050] The ADC 140 can include a first capacitor C1 and a second capacitor C2, a comparator 142, and a counter 144.

[0051] The first capacitor C1 can receive the ramp signal Vramp and send the ramp signal Vramp to the comparator 142. The second capacitor C2 can receive the pixel signal PS and send the pixel signal PS to the comparator 142.

[0052] The comparator 142 can compare the ramp signal Vramp and the pixel signal PS, can generate comparison data CDS_OUT based on the result of the comparison, and can send the comparison data CDS_OUT to the counter 144. According to an embodiment, when the ramp signal Vramp is greater than the pixel signal PS, the comparator 142 can generate comparison data CDS_OUT with a logic high level. In addition, when the ramp signal Vramp is less than the pixel signal PS, the comparator 142 can generate comparison data CDS_OUT with a logic low level. That is, the comparison data CDS_OUT can indicate the magnitude relationship between the ramp signal Vramp and the pixel signal PS.

[0053] The counter 144 can be enabled in response to a counter enable signal CNT_EN. The enabled counter 144 can perform counting in response to comparison data CDS_OUT with a logic high level, and can output the result of the counting as ADC data ADC_OUT. The ADC data ADC_OUT can correspond to the image data IDATA described with reference to Figure 1 .

[0054] The CDS circuit 146 may correspond to a component among the components of the ADC 140 that includes a first capacitor C1, a second capacitor C2, and a comparator 142. In an example, the CDS circuit 146 may correspond to at least some regions of the pixel array 110. In this case, the CDS circuit 146 may generate CDS data CDS_OUT corresponding to at least some regions of the pixel array 110 to which the CDS circuit 146 corresponds. For example, the CDS circuit 146 may correspond to the first column of the pixel array 110. The CDS data CDS_OUT generated by the CDS circuit 146 may correspond to the first column of the pixel array 110.

[0055] According to an embodiment, the CDS circuit 146 may perform a CDS operation. The CMOS image sensor may use CDS so that an unwanted offset value (e.g., fixed pattern noise) of a pixel can be removed by sampling the pixel signal twice to remove the difference between the two samples. The CDS circuit 146 may remove the unwanted offset value by performing a CDS operation to compare the pixel output voltage obtained before and after the optical charge generated by incident light is accumulated in the sensing node, so that the pixel output voltage based only on the incident light can be measured.

[0056] The test circuit 300 may generate a test image signal and a test reset signal that are sent to the CDS circuit 146. The test image signal may correspond to the image signal used in the CDS operation. The test reset signal may correspond to the reference signal used in the CDS operation. In an example, in the wafer test step, the test circuit 300 may generate test signals for detecting defects in the image sensing device 100. For example, in the wafer test step for the image sensing device 100, the test circuit 300 may generate a test reset signal and a test image signal and send the test reset signal and the test image signal to the CDS circuit 146. The CDS circuit 146 may generate the CDS data CDS_OUT based on the comparison result between the difference between the test reset signal and the test image signal and the ramp signal Vramp.

[0057] According to an embodiment, the test circuit 300 may control the timing at which the test reset signal and the test image signal are sent to the CDS circuit 146. In an example, the test circuit 300 may include a test reset control switch and a test image control switch. The test circuit 300 may send the test reset signal to the CDS circuit by closing the test reset control switch and opening the test image control switch, and may send the test image signal to the CDS circuit by opening the test reset control switch and closing the test image control switch. In an example, since the sending timing of the test reset signal and the test image signal is controlled by the test circuit 300, the CDS circuit 146 may perform a CDS operation between the test reset signal and the test image signal.

[0058] According to an embodiment, the ADC 140 may generate ADC data ADC_OUT based on the generated CDS data CDS_OUT. The ADC data ADC_OUT may correspond to the image data IDATA. For example, the CDS circuit 146 may correspond to the first column of the pixel array 110. In this case, the CDS circuit 146 may generate CDS data CDS_OUT corresponding to the first column of the pixel array 110 to which the CDS circuit 146 corresponds. The ADC 140 may generate ADC data ADC_OUT corresponding to the first column based on the generated CDS data CDS_OUT. The generated ADC data ADC_OUT may correspond to the image data IDATA corresponding to the first column.

[0059] According to an embodiment, the CDS circuit 146 may sequentially sample and hold a reference signal and an image signal provided to each of a plurality of column lines from the pixel array 110. That is, the CDS circuit 146 may sample and hold the levels of the reference signal and the image signal corresponding to each column of the pixel array 110. In this case, the reference signal may be an electrical signal provided to the CDS circuit 146 when a sensing node (e.g., a floating diffusion node) of a pixel is reset. The image signal may be an electrical signal provided to the CDS circuit 146 when photo charges generated by the pixel accumulate in the sensing node.

[0060] When a relatively small value of the difference between the reference signal and the image signal is input to some of the plurality of CDS circuits and a relatively large value of the difference between the reference signal and the image signal is input to some of the plurality of CDS circuits, band noise (BN) in the form of a band may occur due to signal leakage from the CDS circuit having a relatively large difference between the reference signal and the image signal. The band noise may be noise having a linear band form that occurs in the readout step of the ADC 140 due to transistor characteristics, and may include trailing horizontal band noise (SHBN) that occurs in operations of signal amplification and enabling pixels in the same row or column. In an embodiment, when the difference between the reference signal and the image signal input to the first CDS circuit corresponding to the first column of the pixel array 110 is large and the difference between the reference signal and the image signal input to the second CDS circuit corresponding to the second column of the pixel array 110 is small, band noise may occur in the row region connected to the first CDS circuit, and a noisy image with horizontal stripes may occur in the output image 600 (refer to Figure 6B ).

[0061] Figure 4 is a block diagram showing a configuration of an embodiment of a test circuit connected to an ADC according to an embodiment of the present disclosure Figure 1 of.

[0062] Refer to Figure 4, the CDS circuit 146 can be selectively connected to the test circuit 300 and perform a CDS operation based on the signal sent by the test circuit 300. That is, in order for the CDS circuit 146 to perform a CDS operation, the CDS circuit 146 can sample and hold the test reset signal and the test image signal generated by the test circuit 300 in sequence, just like in the operation of sampling and holding the reference signal and the image signal provided from the pixel array 110 to each of the multiple column lines in sequence.

[0063] The test circuit 300 can generate a test image signal and a test reset signal sent to the CDS circuit 146. The test image signal can correspond to the image signal used in the CDS operation. The test reset signal can correspond to the reference signal used in the CDS operation. The CDS circuit 146 can receive the test image signal and the test reset signal from the test circuit 300 and generate image data IDATA based on the CDS data CDS_OUT generated by the comparator 142 based on the calculation result of the difference between the two signals.

[0064] The test reset line 410 can be connected to the test reset switch 440 operating based on the first control signal SC_1 and can connect the relatively thick lines included in the CDS circuit 146 and the test circuit 300. In an example, when the test reset switch 440 is closed based on the first control signal SC_1, the CDS circuit 146 can receive the test reset signal through the test reset line 410.

[0065] The test image line 420 can be connected to the test image switch 450 operating based on the second control signal SC_2 and can be connected between the relatively thin line connected to the test circuit 300 and the CDS circuit 146. In an example, when the test image switch 450 is closed based on the second control signal SC_2, the CDS circuit 146 can receive the test image signal through the test image line 420. At this time, the voltage value of the test image signal sent to the CDS circuit 146 through the test image line 420 can correspond to a voltage value relatively lower than that of the test reset signal.

[0066] According to an embodiment, the first voltage value corresponding to the test reset signal and the second voltage value corresponding to the test image signal can be determined based on the resistance value of the circuit to which the test reset signal and the test image signal are sent. The first voltage value corresponding to the test reset signal can be greater than the second voltage value corresponding to the test image signal. In an example, Figure 4The embodiments show that the first voltage value and the second voltage value are determined differently due to the difference in the thickness between the line to which the test reset signal is sent and is connected to the test reset switch 440 (e.g., the relatively thick line included in the test circuit 300) and the line to which the test image signal is sent and is connected to the test image switch 450 (e.g., the relatively thin line included in the test circuit 300), but this is only an embodiment, and the embodiments of the present disclosure are not limited thereto. For example, the first voltage value and the second voltage value may be determined by passive elements (e.g., additionally included resistors).

[0067] The test control switch 430 may be connected between the test reset line 410 and the test image line 420, and may control the test reset signal and the test image signal sent to the CDS circuit 146 based on the test control signal SC_T. In an example, when the test control switch 430 is turned off, the test reset signal and the test image signal may each have a voltage value corresponding to the voltage value set in the test circuit 300. In an example, the first voltage value corresponding to the test reset signal and the second voltage value corresponding to the test image signal may be adjusted based on the voltage value VDD set in the test circuit 300. In an example, the voltage value VDD set in the test circuit 300 may be turned on or off by at least one transistor included in the test circuit 300. In an example, at least one transistor included in the test circuit 300 corresponds to the enable switch En.Sw. The voltage value VDD set in the test circuit 300 may be applied to the test circuit 300, or the supply of the voltage value VDD may be blocked by the test circuit 300. For example, in a state where the test control switch 430 has been turned off by the test control signal SC_T, the test reset signal may have a first voltage value, and the test image signal may have a second voltage value, and the second voltage value undergoes a voltage drop of a predetermined value compared to the first voltage value due to the line resistance. The CDS circuit 146 may generate the CDS data CDS_OUT based on the difference between the first voltage value corresponding to the test reset signal and the second voltage value corresponding to the test image signal.

[0068] According to an embodiment, the test reset line 410 and the test image line 420 may correspond to the first column area of the output image. In an example, the test circuit 300 may include a second test reset line and a second test image line. The second test reset line and the second test image line may correspond to the second column area of the output image. In an example, the signal corresponding to the second test reset line may be determined according to the point where the second test reset line is connected to the relatively thick line of the test circuit 300. In an example, the signal corresponding to the second test image line may be determined according to the point where the second test image line is connected to the relatively thin line of the test circuit 300.

[0069] In the example, when the test control switch 430 is closed, since the test reset line 410 and the test image line 420 are connected, the test reset signal and the test image signal may have the same voltage value. For example, if the test circuit 300 sets a first voltage value in the test reset signal and the test control switch 430 connected between the test reset line 410 and the test image line 420 is closed based on the test control signal SC_T, then although the test circuit 300 sets a second voltage value in the test image signal, the test image signal input to the CDS circuit 146 still has the first voltage value. In this case, the CDS circuit 146 may generate the CDS data CDS_OUT based on the difference between the first voltage value corresponding to the test reset signal and the first voltage value corresponding to the test image signal. The CDS data CDS_OUT may correspond to a dark image because there is no difference between the test reset signal and the test image signal input to the CDS circuit 146.

[0070] According to an embodiment, the test circuit 300 may set a test reference voltage and may set the voltage value of the test reset signal and the voltage value of the test image signal by using the test reference voltage and the line resistance included in the test circuit 300. In the example, the test circuit 300 may set the value of the power supply voltage to VDD. The voltage value corresponding to the test reset signal and the voltage value corresponding to the test image signal may each be a voltage value that undergoes a predetermined voltage drop from the power supply voltage VDD. In the example, the test circuit 300 may set the test reference current to a value I by using a current source. At this time, the voltage value of the test reset signal transmitted to the CDS circuit 146 through the test reset line 410 may correspond to a voltage value that undergoes a voltage drop based on the value of the power supply voltage VDD, and the voltage drop is a value obtained by multiplying the resistance value of the line through which the test reset signal passes by the value I.

[0071] According to an embodiment, when the resistance value of the line through which the test reset signal passes is R_RST, the voltage value of the test reset signal received by the CDS circuit 146 may correspond to the value "VDD - I*R_RST". In addition, the voltage value of the test image signal sent to the CDS circuit 146 through the test image line 420 may correspond to the voltage value that undergoes a voltage drop based on the power supply voltage VDD, and the voltage drop is a value obtained by multiplying the resistance value of the line through which the test image signal passes by the value I. For example, when the resistance value of the line through which the test reset signal passes is R_SIG, the voltage value of the test reset signal received by the CDS circuit 146 may correspond to the value "VDD - I*R_SIG". In the example, since the test reset line 410 may be connected to a relatively thick line and the test image line 420 may be connected to a relatively thin line, the resistance value R_RST may be less than the resistance value R_SIG. In the example, since the path through which the test reset signal passes may be shorter than the path through which the test image signal passes, the resistance value R_RST may be less than the resistance value R_SIG. In the example, the test reset line 410 may be connected to a line corresponding to a relatively small resistance, and the test image line 420 may be connected to a line corresponding to a relatively large resistance. Therefore, the resistance value R_RST may be less than the resistance value R_SIG.

[0072] According to an embodiment, the test circuit 300 may send a test reset signal to the CDS circuit 146 by disconnecting the test control switch 430 and the test image switch 450 and closing the test reset switch 440. At this time, the voltage value corresponding to the test reset signal may correspond to the value "VDD - I*R_RST". In the example, the test circuit 300 may send a test image signal to the CDS circuit 146 by disconnecting the test control switch 430 and the test reset switch 440 and closing the test image switch 450. At this time, the voltage value corresponding to the test image signal may correspond to the value "VDD - I*R_SIG".

[0073] According to an embodiment, the test circuit 300 may send a test image signal to the CDS circuit 146 by disconnecting the test reset switch 440 and closing the test control switch 430 and the test image switch 450. At this time, since the test image signal may be sent through a relatively thick line (instead of a relatively thin line), the voltage value corresponding to the test image signal may correspond to the value "VDD - I*R_RST". In an example, the test circuit 300 may send a test reset signal to the CDS circuit 146 by disconnecting the test image switch 450 and closing the test control switch 430 and the test reset switch 440. At this time, since the test reset signal may be sent through a relatively thick line, the voltage value corresponding to the test reset signal may correspond to the value "VDD - I*R_RST". When writing the voltage values of the respective signals according to the example, the resistance values generated when the resistance value passes through each switch (e.g., 430, 440, or 450) may be regarded as negligible values.

[0074] According to an embodiment, according to the disconnection or closing of the test control switch 430, the test image signal sent to the CDS circuit 146 through the test image line 420 may be divided into a first test image signal corresponding to the value "VDD - I*R_SIG" when the test control switch 430 is disconnected and a second test image signal corresponding to the value "VDD - I*R_RST" when the test control switch 430 is closed. In an example, the image sensing device 100 may include a CDS circuit 146 corresponding to a test circuit 300 that does not include a test control switch. The CDS circuit 146 corresponding to the test circuit 300 that does not include a test control switch may operate as in the case where the test control switch 430 is disconnected.

[0075] A CDS control switch (not shown) may be connected to the CDS circuit 146 to control the input of the reference signal and the image signal generated by the pixel array 110. The operation of the image sensing device 100 may include an operation of generating image data IDATA based on the signals generated by the pixel array 110 and an operation of generating test image data based on the signals generated by the test circuit 300. If the operation of generating test image data based on the signals generated by the test circuit 300 is performed, the CDS control switch (not shown) may prevent the signals generated by the pixel array 110 from being sent to the ADC 140. In an example, if the operation of generating test image data is performed, the signals generated by the pixel array 110 may be prevented from being sent to the ADC 140 based on the on / off state or the disconnection / closing state of the CDS control switch (not shown). The CDS circuit 146 may perform a CDS operation based on the signals generated by the test circuit 300.

[0076] According to an embodiment, the image input mode or the test mode of the image sensing device 100 may be determined based on a CDS control switch (not shown), a test reset switch 440, and a test image switch 450. In an example, when the mode of the image sensing device 100 is the image input mode, since the pixel signals generated by the pixel array 110 need to be input to the ADC 140, the test reset switch 440 and the test image switch 450 may be set to off based on a first control signal SC_1 and a second control signal SC_2. In an example, when the mode of the image sensing device 100 is the test mode, since the test signals (e.g., a test reset signal or a test image signal) generated by the test circuit 400 need to be input to the ADC 140, the CDS control switch (not shown) may be set to off.

[0077] According to an embodiment, the operation of generating test image data may be performed in the wafer test step of the image sensing device 100. In an example, the set voltages of the test reset signal and the test image signal may be applied to the test circuit based on test pads connected to a test device or test probes.

[0078] According to an embodiment, the test circuit 300 may be connected to a plurality of CDS circuits 146. For example, the test circuit 300 may be connected to a first CDS circuit and a second CDS circuit. In this case, the first CDS circuit may correspond to a first region of the pixel array 110, and the second CDS circuit may correspond to a second region of the pixel array 110. The test image signal generated by the test circuit 300 may be sent to the first CDS circuit through a first test image line. The test reset signal generated by the test circuit 300 may be sent to the first CDS circuit through a first test reset line. In addition, the test image signal generated by the test circuit 300 may be sent to the second CDS circuit through a second test image line. The test reset signal generated by the test circuit 300 may be sent to the second CDS circuit through a second test reset line.

[0079] According to an embodiment, one or more CDS circuits may generate different CDS data CDS_OUT according to the open / closed state of a test control switch connected between a test reset line connected to a CDS circuit and a test image line connected to the CDS circuit. For example, when a first test control switch connected between a first test reset line and a first test image line is open, a first CDS circuit may receive a test reset signal corresponding to a first voltage value and a test image signal corresponding to a second voltage value, and may generate first CDS data based on a difference between the first voltage value and the second voltage value. In addition, when a second test control switch connected between a second test reset line and a second test image line is closed, a second CDS circuit may receive a test reset signal and a test image signal corresponding to a voltage value identical to the first voltage value, and may generate second CDS data based on a difference between the identical voltage values. At this time, image data IDATA corresponding to a bright image may be generated based on the first CDS data, and image data IDATA corresponding to a dark image may be generated based on the second CDS data.

[0080] According to an embodiment, the test circuit 300 may further include a switch control circuit (not shown) that controls the test control switch 430. In an example, the switch control circuit (not shown) may control the opening or closing of the test control switch 430 based on which region of the pixel array 110 the CDS circuit 146 selectively connected to the test control switch 430 corresponds to.

[0081] According to an embodiment, a user may determine whether there is a defect of a noise type of the image sensing device 100 by recognizing noise in the output image 600 in a wafer test step. In an embodiment, since a test reset signal and a test image signal in an existing wafer test step are uniformly input to each CDS circuit 146 of the image sensing device 100, bright images are uniformly distributed in the output image 600. However, if the test control switch 430 connected to the test reset line and the test image line is used, since a difference between the test reset signal and the test image signal can be controlled, the test reset signal and the test image signal may be partially input to each CDS circuit 146 of the image sensing device 100.

[0082] Figure 5A is a diagram showing a difference between the power of a test image signal and the power of a test reset signal according to an embodiment of the present disclosure.

[0083] Figure 5AThe power TEST_RST of the test reset signal received by each of the plurality of CDS circuits 146 and the power TEST_SIG of the test image signal can be shown based on the respective columns corresponding to the CDS circuits 146. In an example, the test circuit 300 can send a test reset signal with a relatively small power to the CDS circuit 146 corresponding to the left column of the pixel array 110, and can send a test reset signal with a relatively large power to the CDS circuit 146 corresponding to the right column of the pixel array 110. In addition, the test circuit 300 can send a test image signal with a relatively large power to the CDS circuit 146 corresponding to the left column of the pixel array 110, and can send a test reset signal with a relatively small power to the CDS circuit 146 corresponding to the right column of the pixel array 110. In this case, the power TEST_RST of the test reset signal generated by the test circuit 300 can be greater than the power TEST_SIG of the test image signal.

[0084] According to an embodiment, Figure 5A It can correspond to a wafer test environment in which test reset signals with gradually increasing powers are sent to the respective corresponding CDS circuits 146 from the left column to the right column of the pixel array 110, and can correspond to a wafer test environment in which test image signals with gradually decreasing powers are sent to the respective corresponding CDS circuits 146 from the left column to the right column of the pixel array 110. In an example, when the power TEST_RST of the test reset signal is greater than the power TEST_SIG of the test image signal, test reset signals with gradually increasing powers and test image signals with gradually decreasing powers can be sent to the respective corresponding CDS circuits 146 corresponding to the respective column positions of the pixel array 110 from the left column to the right column of the pixel array 110. The difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal can be gradually increased in the respective corresponding CDS circuits 146 corresponding to the respective column positions of the pixel array 110 from the left column to the right column of the pixel array 110.

[0085] According to an embodiment, if the test circuit 300 sets the power TEST_RST of the test reset signal input to the CDS circuit 146 to high and sets the power TEST_SIG of the test image signal input to the CDS circuit 146 to low, the bright image data corresponding to the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal may correspond to the output image. In an example, the test circuit 300 may adjust the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal by adjusting the reference voltage values of the test reset signal and the test image signal. For example, the test circuit 300 may set the difference between the power TEST_RST of the test reset signal input to the CDS circuit 146 and the power TEST_SIG of the test image signal to be larger by setting the reference voltage value of the test reset signal to high and setting the reference voltage value of the test image signal to low. In this case, as the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal increases, the output image may correspond to a bright image.

[0086] Figure 5B is an image output according to the difference between the power of the test image signal and the power of the test reset signal according to an embodiment of the present disclosure. Figure 5A between the power of the test image signal and the power of the test reset signal in

[0087] Referring to Figure 5B , the CDS circuit 146 may generate CDS data CDS_OUT based on the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal. In this case, the ADC 140 may output the CDS data CDS_OUT of each column output by the CDS circuit 146 by converting the CDS data CDS_OUT into a digital signal. In an example, as the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal increases, CDS data CDS_OUT corresponding to the bright image data IDATA may be generated. For example, when the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit 146 corresponding to the left column of the pixel array 110 are relatively small, the dark image data may correspond to the left side of the output image. When the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit 146 corresponding to the right column of the pixel array 110 are relatively large, the bright image data may correspond to the right side of the output image.

[0088] According to an embodiment, if the test circuit 300 sets the power TEST_RST of the test reset signal input to the CDS circuit 146 to be large and sets the power TEST_SIG of the test image signal input to the CDS circuit 146 to be small, the bright image data corresponding to the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal may correspond to the output image. For example, as the test circuit 300 sets the power TEST_RST of the test reset signal input to the CDS circuit 146 to be larger and sets the power TEST_SIG of the test image signal input to the CDS circuit 146 to be smaller, brighter image data may correspond to the output image.

[0089] Figure 6A is a graph showing the difference between the power of the test image signal and the power of the test reset signal according to an embodiment of the present disclosure. Figure 6B is according to an embodiment of the present disclosure according to Figure 6A the image output according to the difference between the power of the test image signal and the power of the test reset signal in

[0090] Figure 6A The power TEST_RST of the test reset signal received by each CDS circuit 146 and the power TEST_SIG of the test image signal may be shown based on each column corresponding to the plurality of CDS circuits 146. In an example, the test circuit 300 may send a test reset signal with relatively small power to the CDS circuit 146 corresponding to the left column of the pixel array 110, may send a test reset signal with medium power to the CDS circuit 146 corresponding to the middle column (i.e., the central column) of the pixel array 110, and may send a test reset signal with relatively large power to the CDS circuit 146 corresponding to the right column of the pixel array 110. At this time, the test control switch connected to the CDS circuit 146 corresponding to the left column of the pixel array 110 may be closed, the test control switch connected to the CDS circuit 146 corresponding to the middle column of the pixel array 110 may be opened, and the test control switch connected to the CDS circuit 146 corresponding to the right column of the pixel array 110 may be closed.

[0091] According to an embodiment, if the test circuit 300 sets the power TEST_RST of the test reset signal input to the CDS circuit 146 to be large and sets the power TEST_SIG of the test image signal input to the CDS circuit 146 to be small, the bright image data corresponding to the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal may correspond to the output image. In an example, the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal may be adjusted by turning on or off the test control switch 430.

[0092] According to an embodiment, after the test circuit 300 sets the reference voltage value of the test reset signal to be large and sets the reference voltage value of the test image signal to be small, the test control switch connected to the CDS circuit 146 corresponding to the left column of the pixel array 110 may be turned on, the test control switch connected to the CDS circuit 146 corresponding to the middle column of the pixel array 110 may be turned off, and the test control switch connected to the CDS circuit 146 corresponding to the right column of the pixel array 110 may be turned on. At this time, in the CDS circuit 146 corresponding to the left column of the pixel array 110, the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal may be small. In the CDS circuit 146 corresponding to the middle column of the pixel array 110, the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal may be large. In the CDS circuit 146 corresponding to the right column of the pixel array 110, the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal may be small.

[0093] Figure 7 is for describing the operation of a test circuit corresponding to Figure 6B the image according to an embodiment of the present disclosure Figure 4 is a diagram.

[0094] Refer to Figure 7, the CDS circuit 146 can generate CDS data CDS_OUT based on the difference between the test reset signal and the test image signal. In this case, the ADC 140 can output the CDS data CDS_OUT of each column output by the CDS circuit 146 by converting the CDS data CDS_OUT into a digital signal. In the example, as the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal increases, the CDS data CDS_OUT corresponding to the bright image data IDATA can be generated. For example, when the power TEST_RST of the test reset signal input to the CDS circuit corresponding to the left column of the pixel array 110 and the power TEST_SIG of the test image signal are relatively small, the dark image data can correspond to the left side of the output image. When the power TEST_RST of the test reset signal input to the CDS circuit corresponding to the middle column of the pixel array 110 and the power TEST_SIG of the test image signal are relatively large, the bright image data can correspond to the middle (center) of the output image. When the power TEST_RST of the test reset signal input to the CDS circuit corresponding to the right column of the pixel array 110 and the power TEST_SIG of the test image signal are relatively small, the dark image data can correspond to the right side of the output image.

[0095] According to an embodiment, if the test circuit 300 sets the power TEST_RST of the test reset signal input to the CDS circuit 146 to be relatively large and sets the power TEST_SIG of the test image signal input to the CDS circuit 146 to be relatively small, the bright image data corresponding to the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal can correspond to the output image. For example, when the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit corresponding to the left column of the pixel array 110 is relatively small, the dark image data can correspond to the left side of the output image. When the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit corresponding to the middle column of the pixel array 110 is relatively small, the dark image data can correspond to the middle of the output image. When the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit corresponding to the right column of the pixel array 110 is relatively small, the dark image data can correspond to the right side of the output image.

[0096] According to an embodiment, when the test circuit 300 operates, the image data of the output image 600 in the row direction can be adjusted by controlling the row circuit connected to the CDS circuit 146. In an example, when the test circuit 300 operates, the row circuit corresponding to the CDS circuit 146 may include a row control switch. If the row circuit corresponding to the CDS circuit 146 corresponds to the central portion of the pixel array, the row control switch may be set to open. If the row circuit corresponding to the CDS circuit 146 corresponds to the edge portion of the pixel array, the row control switch may be set to closed.

[0097] According to an embodiment, the test control switch connected to the CDS circuit corresponding to the middle column of the pixel array 110 may be closed. The test control switches connected to the CDS circuits corresponding to the left and right columns of the pixel array 110 may be open. Further, if the row switch corresponding to the CDS circuit corresponds to the central portion (e.g., the middle row) of the pixel array, the row control switch may be set to open. If the row switch corresponding to the CDS circuit corresponds to the edge portion (e.g., the upper row and the lower row) of the pixel array, the row control switch may be set to closed. In this case, the bright image data may correspond to only some regions in the center of the output image, and the dark image data may correspond to the edge regions of the output image.

[0098] According to an embodiment, the CDS circuit may generate CDS data CDS_OUT based on the difference between the test reset signal and the test image signal. In this case, the ADC may output the CDS data CDS_OUT of each row output by the CDS circuit by converting the CDS data CDS_OUT into a digital signal. In an example, as the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal increases, the CDS data CDS_OUT corresponding to the bright image data IDATA may be generated. For example, when the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit corresponding to the upper row of the pixel array 110 are relatively small, the dark image data may correspond to the upper side of the output image. When the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit corresponding to the middle row of the pixel array 110 are relatively large, the bright image data may correspond to the middle of the output image. When the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit corresponding to the lower row of the pixel array 110 are relatively small, the dark image data may correspond to the lower side of the output image. In an example, different from the column CDS circuit, the CDS circuit that outputs the CDS data CDS_OUT of each row of the pixel array by converting the CDS data CDS_OUT into a digital signal may correspond to the row CDS circuit.

[0099] According to an embodiment, if the test circuit 300 sets the power TEST_RST of the test reset signal input to the CDS circuit 146 to be large and sets the power TEST_SIG of the test image signal input to the CDS circuit 146 to be small, the bright image data corresponding to the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal may correspond to the output image. For example, when the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit corresponding to the upper row of the pixel array 110 is small, the dark image data may correspond to the upper side of the output image. When the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit corresponding to the middle row (i.e., the central row) of the pixel array 110 is small, the dark image data may correspond to the middle of the output image. When the difference between the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit corresponding to the lower row of the pixel array 110 is small, the dark image data may correspond to the lower side of the output image.

[0100] According to an embodiment, in the wafer test step, the test circuit 300 may create a noisy environment by controlling the difference between the test reset signal and the test image signal input to each of the plurality of CDS circuits by using the test control switch 430. In an example, the test circuit 300 may make the dark image data correspond to the left side of the output image 600 by making the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit corresponding to the left column of the pixel array 110 relatively small. The test circuit 300 may make the bright image data correspond to the middle of the output image 600 by making the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit corresponding to the middle column of the pixel array 110 relatively large. The test circuit 300 may make the dark image data correspond to the right side of the output image by making the power TEST_RST of the test reset signal and the power TEST_SIG of the test image signal input to the CDS circuit corresponding to the right column of the pixel array 110 relatively small.

[0101] According to an embodiment, since noise can be detected in an environment where light is incident on some regions of the pixel array, noise is determined based on an output image output based on pixel signals rather than signals input from a test circuit. If the test control switch 430 connected to the test reset line and the test image line is used, noise can be determined based on the signals input from the test circuit, because the different differences between the test reset signal and the test image signal can be input to each of the plurality of CDS circuits 146. For example, in the wafer test step, the user can input a signal with a relatively small difference between the test reset signal and the test image signal to the first CDS circuit by closing the test control switch connected to the first CDS circuit, and input a signal with a relatively large difference between the test reset signal and the test image signal to the second CDS circuit by closing the test control switch connected to the second CDS circuit to determine whether there is noise in the output image 600. In this case, the user can determine whether the image sensing device 100 includes a defect based on whether there is noise in the determined output image 600.

[0102] According to an embodiment, the test circuit 300 may further include a switch control circuit (not shown) that controls the test control switch 430. The switch control circuit may close the test control switch when the test control switch is a CDS circuit corresponding to the left region of the pixel array, may open the test control switch when the test control switch is a CDS circuit corresponding to the middle (central) region of the pixel array, and may close the test control switch when the test control switch is a CDS circuit corresponding to the right region of the pixel array.

[0103] According to an embodiment, after the test circuit 300 sets the reference voltage value of the test reset signal to high and the reference voltage value of the test image signal to low, the test circuit 300 can send the test reset signal and the test image signal to the CDS circuit (e.g., 706, 716, or 726) by adjusting the test reset switch (e.g., 707, 717, or 727) and the test image switch (e.g., 708, 718, or 728) connected to the test reset line (e.g., 700, 710, or 720) and the test image line (e.g., 702, 712, or 722). In the example, the test control switch 704 connected to the CDS circuit 706 corresponding to the left column of the pixel array 110 may be closed. The test control switch 714 connected to the CDS circuit 716 corresponding to the middle column of the pixel array 110 may be opened. The test control switch 724 connected to the CDS circuit 726 corresponding to the right column of the pixel array 110 may be closed. In this case, the dark image data may correspond to the left side of the output image 600, the bright image data may correspond to the middle of the output image 600, and the dark image data may correspond to the right side of the output image 600.

[0104] According to an embodiment, the test circuit 300 may reduce the difference between the test reset signal and the test image signal input to the first CDS circuit 706 by closing the test control switch 704 connected to the first CDS circuit 706 corresponding to the left column of the pixel array 110. In addition, the test circuit 300 may adjust the timing of the test reset signal and the test image signal sent to the first CDS circuit 706 by adjusting the first test reset switch 707 and the first test image switch 708. For example, the test circuit 300 may send a test reset signal to the first CDS circuit 706 through the first test reset line 700, and may send a test image signal to the first CDS circuit 706 through the first test image line 702. In this case, the difference between the power of the test reset signal and the power of the test image signal input to the first CDS circuit 706 may be reduced by closing the test control switch 704 corresponding to the first CDS circuit 706. Based on the reduction in the difference between the power of the test reset signal and the power of the test image signal input to the first CDS circuit 706, the dark image data may correspond to the left region of the output image 600 corresponding to the first CDS circuit 706.

[0105] According to an embodiment, the test circuit 300 may disconnect the test control switch 714 connected to the second CDS circuit 716 corresponding to the middle column of the pixel array 110, may send a test reset signal to the second CDS circuit 716 through the second test reset line 710, and may send a test image signal to the second CDS circuit 716 through the second test image line 712. In addition, the test circuit 300 may adjust the timing of the test reset signal and the test image signal sent to the second CDS circuit 716 by adjusting the second test reset switch 717 and the second test image switch 718. At this time, the difference between the power of the test reset signal and the power of the test image signal input to the second CDS circuit 716 by disconnecting the test control switch 714 corresponding to the second CDS circuit 716 may correspond to the difference between the power of the test reset signal and the power of the test image signal preset in the test circuit 300. Based on the difference between the power of the test reset signal and the power of the test image signal input to the second CDS circuit 716, the relatively bright image data may correspond to the middle region of the output image 600 corresponding to the second CDS circuit 716.

[0106] According to an embodiment, the test circuit 300 may reduce the difference between the test reset signal and the test image signal input to the third CDS circuit 726 by closing the test control switch 724 connected to the third CDS circuit 726 corresponding to the right column of the pixel array 110. In addition, the test circuit 300 may adjust the timing of the test reset signal and the test image signal sent to the third CDS circuit 726 by adjusting the third test reset switch 727 and the third test image switch 728. For example, the test circuit 300 may send a test reset signal to the third CDS circuit 726 through the third test reset line 720, and may send a test image signal to the third CDS circuit 726 through the third test image line 722. In this case, the difference between the power of the test reset signal and the power of the test image signal input to the third CDS circuit 726 may be reduced by closing the test control switch 724 corresponding to the third CDS circuit 726. Based on the reduction of the difference between the power of the test reset signal and the power of the test image signal input to the third CDS circuit 726, the dark image data may correspond to the right region of the output image 600 corresponding to the third CDS circuit 726.

[0107] According to an embodiment, by closing the test control switches (e.g., 704 or 724) connected to each of the first CDS circuit 706 and the third CDS circuit 726, regardless of the difference between the test reset signal and the test image signal set by the test circuit 300, the difference between the test reset signal and the test image signal input to each of the first CDS circuit 706 and the third CDS circuit 726 may be relatively small. For example, referring to Figure 7 and Figure 6B , when the test control switches (e.g., 704 and 724) connected to the first CDS circuit 706 and the third CDS circuit 726 are closed respectively, the test image signals input to the first CDS circuit 706 and the third CDS circuit 726 may correspond to Figure 6B the left and right figures in respectively. In the example, the test image signals input to the first CDS circuit 706 and the third CDS circuit 726 may have the same magnitude as the test reset signals input to the first CDS circuit 706 and the third CDS circuit 726.

[0108] According to an embodiment, by disconnecting the test control switch 714 connected to the second CDS circuit 716, the difference between the test reset signal and the test image signal input to the second CDS circuit 716 may have a value corresponding to the difference between the test reset signal and the test image signal set by the test circuit 300. For example, referring to Figure 7 and Figure 6B , when the test control switch 714 connected to the second CDS circuit 716 is disconnected, the test image signal input to the second CDS circuit 716 may correspond toFigure 6B The middle part of the figure in

[0109] Figure 8 is a timing diagram of a test circuit according to an embodiment of the present disclosure.

[0110] Referring to Figure 8 , when the first control signal SC_1 is at a logic high level from t1 to t2, the test reset signal TEST_RST may be at a logic high level from t1 to t2. When the first control signal SC_1 is at a logic low level from t2 to t5, the test reset signal TEST_RST may be at a logic low level from t2 to t5. In the example, when the second control signal SC_2 is at a logic high level from t7 to t8, the test image signal TEST_SIG may be at a logic high level from t7 to t8. When the second control signal SC_2 is at a logic low level from t4 to t7, the test image signal TEST_SIG may be at a logic low level from t4 to t7.

[0111] According to the embodiment, when the test control switch is at a logic low level from t1 to t4, the test reset signal TEST_RST and the test image signal TEST_SIG may have a difference in voltage values. Accordingly, the test image TEST_IDATA may be output as a bright image. For example, when the test control switch is at a logic low level from t1 to t4, the test control switch may be turned off, the test reset signal TEST_RST may have a relatively high voltage value, and the test image signal TEST_SIG may have a relatively low voltage value. Accordingly, the test image TEST_IDATA may be output as a bright image corresponding to the difference in voltage values between the test reset signal TEST_RST and the test image signal TEST_SIG.

[0112] According to an embodiment, when the test control switch is at a logic high level from t5 to t8, the test reset signal TEST_RST and the test image signal TEST_SIG may have the same voltage value. Accordingly, the test image TEST_IDATA may be output as a dark image. For example, when the test control switch is at a logic high level from t5 to t8, the test control switch may be closed, and the test reset signal TEST_RST and the test image signal TEST_SIG may have the same voltage value or the difference between their voltage values may be relatively small. Accordingly, the test image TEST_IDATA may be output as a relatively dark image. In the example, after calculating the voltage value of the test reset signal TEST_RST and then calculating the voltage value of the test image signal TEST_SIG, the brightness of the test image TEST_IDATA may be determined based on the difference between the voltage value of the test reset signal TEST_RST and the voltage value of the test image signal TEST_SIG.

[0113] Although multiple exemplary embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments may be conceived based on what is described and / or shown in the present disclosure. In addition, these embodiments may be combined to form additional embodiments.

[0114] Cross-reference to related applications

[0115] This patent application claims the priority of Korean Application No. 10-2024-0000926, filed on January 3, 2024, which is incorporated herein by reference in its entirety.

Claims

1. An image sensing device, the image sensing device comprising: A test control switch, the test control switch selectively connecting a test reset line for sending a test reset signal and a test image line for sending a first test image signal; And A first correlated double sampling (CDS) circuit, the first CDS circuit receiving the test reset signal through the test reset line and receiving the first test image signal through the test image line, Wherein, when the test control switch is closed, the first CDS circuit receives a second test image signal through the test image line.

2. The image sensing device according to claim 1, wherein, The first CDS circuit includes a column CDS circuit corresponding to at least one column of the pixel array.

3. The image sensing device according to claim 1, wherein, The first CDS circuit corresponds to at least some regions of the pixel array.

4. The image sensing device according to claim 3, wherein, When the first CDS circuit corresponds to a first region of the pixel array, the test control switch is closed; And When the first CDS circuit corresponds to a second region of the pixel array, the test control switch is open.

5. The image sensing device according to claim 4, wherein, The first region corresponds to a central portion of the pixel array; and The second region corresponds to an edge portion of the pixel array.

6. The image sensing device according to claim 3, wherein, When a row circuit corresponding to the first CDS circuit corresponds to a central portion of the pixel array, the test control switch is closed; And When the row circuit corresponding to the first CDS circuit corresponds to an edge portion of the pixel array, the test control switch is open.

7. The image sensing device according to claim 6, wherein, The row circuit includes at least one of a row control switch and a row CDS circuit.

8. The image sensing device according to claim 1, the image sensing device further comprising a test circuit, the test circuit generating the test reset signal and the first test image signal.

9. The image sensing device according to claim 8, the image sensing device further comprising a second CDS circuit, the second CDS circuit receiving the test reset signal and the first test image signal.

10. The image sensing device according to claim 1, the image sensing device further comprising a switch control circuit, the switch control circuit identifying a CDS circuit corresponding to the test control switch and controlling the opening or closing of the test control switch according to a region of the pixel array corresponding to the identified CDS circuit.

11. The image sensing device according to claim 1, the image sensing device further comprising a CDS control switch, the CDS control switch connected to the CDS circuit and preventing a pixel signal generated from the pixel array from being sent to the CDS circuit.

12. An image sensing device, the image sensing device comprising: A test control switch, the test control switch selectively connecting a test reset line for sending a test reset signal generated from a test circuit and a test image line for sending a test image signal generated from the test circuit; And A correlated double sampling (CDS) circuit that receives the test image signal through the test image line and receives the test reset signal through the test reset line. Wherein, the test control switch controls the difference between the test image signal and the test reset signal input to the CDS circuit.

13. A method of controlling an image sensing device, the method comprising the steps of: Sending a test image signal and a test reset signal to a first correlated double sampling (CDS) circuit included in the image sensing device through a first test image line and a first test reset line, respectively; Sending a test image signal and a test reset signal to a second CDS circuit included in the image sensing device through a second test image line and a second test reset line, respectively; and Controlling the difference between the test image signal and the test reset signal input to the first CDS circuit by selectively connecting the first test image line and the first test reset line.

14. The method according to claim 13, wherein The first CDS circuit corresponds to a first region of the pixel array; and The second CDS circuit corresponds to a second region of the pixel array.

15. The method according to claim 14, wherein The first region includes a first column of the pixel array; and The second region includes a second column of the pixel array.

16. The method according to claim 13, the method further comprising the steps of: Generating first CDS data by the first CDS circuit based on the difference between the test image signal and the test reset signal; And Generating second CDS data by the second CDS circuit based on the difference between the test image signal and the test reset signal.

17. The method according to claim 16, the method further comprising the steps of: Generating image data based on the first CDS data and the second CDS data; And Detecting the band noise (BN) of the image data.

18. The method according to claim 13, wherein, The step of controlling the difference between the test image signal and the test reset signal includes the steps of: changing the voltage level of the test image signal input to the first CDS circuit to the same voltage level as the test reset signal by connecting the first test image line and the first test reset line.

19. The method according to claim 13, wherein Generating the test reset signal and the test image signal from a test circuit.

20. The method according to claim 13, the method further comprising the steps of: Selectively connecting the first test image line and the first test reset line according to the region of the pixel array corresponding to the first CDS circuit.

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