Semiconductor memory device

Abstract

A semiconductor memory device having a peripheral upper cell (COP) structure includes a first semiconductor structure and a second semiconductor structure disposed on an underside of the first semiconductor structure. The first semiconductor structure includes a memory region, a first region, a memory cell array disposed in the memory region and including a vertical channel transistor, and a first peripheral circuit disposed in the first region and including a vertical channel transistor or a horizontal channel transistor. The second semiconductor structure includes a second region on a lower side of the first region, a third region on a lower side of the first region, a second peripheral circuit disposed in the second region and including a horizontal channel transistor, and a third peripheral circuit disposed in the third region and including a horizontal channel transistor, the third region is on a lower side of the memory region.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0001162, filed on January 3, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Background Art

[0003] Embodiments of the present disclosure described herein relate to a semiconductor device, and more particularly, to a semiconductor memory device.

[0004] Semiconductor memory devices can be classified into volatile memory devices or non - volatile memory devices. A volatile memory device can hold data stored therein while power is supplied, and a non - volatile memory device can hold data stored therein even when the power is turned off. The volatile memory device provides fast operation, and the non - volatile memory device provides excellent security and durability.

[0005] To increase the storage capacity of a semiconductor memory device and make the integration degree of the semiconductor memory device higher, a cell - on - periphery (COP) structure is being developed, in which memory cells are arranged three - dimensionally rather than two - dimensionally, and peripheral circuits for the memory cells are provided below the memory cells. Summary of the Invention

[0006] Embodiments of the present disclosure provide a semiconductor memory device that optimizes a chip size by appropriately arranging peripheral circuits in the semiconductor memory device.

[0007] According to an embodiment, a semiconductor memory device having a cell - on - periphery (COP) structure includes a first semiconductor structure and a second semiconductor structure disposed on a lower side of the first semiconductor structure. The first semiconductor structure includes a memory region, a first region, a memory cell array disposed in the memory region and including vertical channel transistors (VCTs), and a first peripheral circuit disposed in the first region and including VCTs or horizontal channel transistors (HCTs). The second semiconductor structure includes a second region, a third region, a second peripheral circuit, and a third peripheral circuit. The second peripheral circuit is disposed in the second region and includes HCTs, the second region is located on a lower side of the first region, the third peripheral circuit is disposed in the third region and includes HCTs, and the third region is located on a lower side of the memory region.

[0008] According to an embodiment, a semiconductor memory device having a chip-on-periphery (COP) structure includes a first semiconductor structure and a second semiconductor structure disposed on a lower side of the first semiconductor structure. The first semiconductor structure includes a memory region, a first region, a memory cell array, and a first peripheral circuit. The memory cell array includes a plurality of first sub-memory cell arrays and a plurality of second sub-memory cell arrays disposed in the memory region and implemented by using vertical channel transistors (VCTs). The first peripheral circuit is disposed in the first region and implemented by using a VCT or a horizontal channel transistor (HCT). The second semiconductor structure includes a second region, a third region, a second peripheral circuit disposed in the second region located on a lower side of the first region, and a third peripheral circuit disposed in the third region located on a lower side of the memory region.

[0009] According to an embodiment, a semiconductor memory device having a chip-on-periphery (COP) structure includes a first semiconductor structure and a second semiconductor structure disposed on a lower side of the first semiconductor structure. The first semiconductor structure includes a memory region, a first region, a memory cell array disposed in the memory region and including vertical channel transistors (VCTs), and a first peripheral circuit disposed in the first region. The first peripheral circuit includes a VCT or a horizontal channel transistor and has a first timing margin associated with an operation of the semiconductor memory device. The second semiconductor structure includes a second region and a second peripheral circuit disposed in the second region and having a second timing margin associated with an operation of the semiconductor memory device. The second region is located on a lower side of the first region. The first timing margin is greater than the second timing margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0011] Figure 1 is a perspective view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0012] Figure 2 is a block diagram showing a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figure 3 is a block diagram showing an embodiment of a semiconductor memory device according to an exemplary embodiment Figure 1 of

[0014] Figure 4A is a cross-sectional view of a semiconductor memory device taken along line X-X' according to an exemplary embodiment Figure 1 of

[0015] Figure 4B is a diagram for describing a memory cell array and a peripheral circuit disposed in a region of Figure 4A .

[0016] Figure 4C is a diagram for describing characteristics of a first peripheral circuit and a second peripheral circuit disposed in a region of Figure 4A .

[0017] Figure 5A is a cross-sectional view of a semiconductor memory device taken along line X-X' of Figure 1 .

[0018] Figure 5B is a diagram for describing a memory cell array and a peripheral circuit disposed in a region of Figure 5A .

[0019] Figure 6A is a cross-sectional view of a semiconductor memory device taken along line X-X' of Figure 1 .

[0020] Figure 6B is a diagram for describing a memory cell array and a peripheral circuit disposed in a region of Figure 6A .

[0021] Figure 7A is a cross-sectional view of a semiconductor memory device taken along line X-X' of Figure 1 .

[0022] Figure 7B is a diagram for describing a memory cell array and a peripheral circuit disposed in a region of Figure 7A .

[0023] Figure 8A is a cross-sectional view of a semiconductor memory device taken along line X-X' of Figure 1 .

[0024] Figure 8B is a diagram for describing a memory cell array and a peripheral circuit disposed in a region of Figure 8A .

[0025] Figure 9 is a plan view of a first semiconductor structure according to an exemplary embodiment of Figure 1 .

[0026] Figure 10 is a plan view of a first semiconductor structure according to an exemplary embodiment of Figure 1Planar view of the second semiconductor structure.

[0027] Figure 11A and Figure 11B is a diagram for describing the reduction of chip size by a semiconductor memory device according to an embodiment of the present disclosure.

[0028] Figure 12 is a diagram showing Figure 1 a part of the semiconductor memory device according to an exemplary embodiment.

[0029] Figure 13A is a diagram for describing a plurality of sub - memory cell arrays provided in the memory region of the semiconductor memory device according to an exemplary embodiment in Figure 1 the semiconductor memory device.

[0030] Figure 13B is a diagram for describing the peripheral circuit provided on the lower side of a plurality of sub - memory cell arrays provided in Figure 13A the semiconductor memory device according to an exemplary embodiment.

[0031] Figure 14 is a diagram showing the semiconductor memory device according to an embodiment of the present disclosure.

[0032] Figure 15 is a planar view showing a pad array included in the semiconductor memory device in Figure 14 the semiconductor memory device according to an exemplary embodiment.

[0033] Figure 16A is a cross - sectional view of the semiconductor memory device taken along line A - A' of Figure 15 in Figure 14 the semiconductor memory device according to an exemplary embodiment.

[0034] Figure 16B is a cross - sectional view of the semiconductor memory device taken along line B - B' of Figure 15 in Figure 14 the semiconductor memory device according to an exemplary embodiment. Detailed Description

[0035] Hereinafter, embodiments of the present disclosure will be described in detail and clearly to such an extent that those skilled in the art can easily implement the present disclosure.

[0036] Figure 1 is a perspective view showing the semiconductor memory device according to an embodiment of the present disclosure.

[0037] Referring to Figure 1 , the semiconductor memory device 100 may include a first semiconductor structure SEMS1 and a second semiconductor structure SEMS2. In an embodiment, Figure 1It is shown that the second semiconductor structure SEMS2 can be disposed below the first semiconductor structure SEMS1, but this is merely an example. In another embodiment, the first semiconductor structure SEMS1 can be disposed below the second semiconductor structure SEMS2. In an embodiment, the first semiconductor structure SEMS1 can be formed of a first semiconductor wafer, and the second semiconductor structure SEMS2 can be formed of a second semiconductor wafer different from the first semiconductor wafer. The semiconductor memory device 100 can include a dynamic random access memory (DRAM), a double data rate 4 (DDR4) synchronous DRAM (SDRAM), a low power DDR4 (LPDDR4) SDRAM, an LPDDR5 SDRAM, a graphics double data rate 5 (GDDR5) SDRAM, a GDDR6 SDRAM, a high bandwidth memory 2 (HBM2), an HBM2E, or an HBM3, but the present invention is not limited thereto.

[0038] In an embodiment, the semiconductor memory device 100 can have a cell-on-periphery (COP) structure, in which the peripheral circuits are disposed below the memory cells. As the COP structure is applied to the semiconductor memory device 100, the storage capacity of the semiconductor memory device 100 can be increased, and the integration degree of the semiconductor memory device 100 can become higher, the utilization of space can be improved, and the manufacturing cost can be reduced.

[0039] The semiconductor memory device 100 can include a memory cell array and peripheral circuits associated with the memory cell array. For example, the memory cell array can include a plurality of memory cells for storing data, and the peripheral circuits can include a plurality of circuits for writing, reading, and managing the data of the memory cells.

[0040] The semiconductor memory device 100 can include therein regions RGNa, RGNb, RGNc, and RGNd. Each of the regions RGNa and RGNb can be a region in the first semiconductor structure SEMS1, and each of the regions RGNc and RGNd can be a region in the second semiconductor structure SEMS2.

[0041] In an embodiment, each of the regions RGNa, RGNb, RGNc, and RGNd can include one or more regions as Figure 1 shown (for example, the region RGNa can include two regions RGNa, and the region RGNd includes two regions RGNd), and each of the regions RGNa, RGNb, RGNc, and RGNd can include with reference to Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B ,Figure 7A , Figure 7B , Figure 8A and Figure 8B one or more of the plurality of regions described, and may be referred to based on components typically included in each region or based on the location of each region. For example, since a plurality of memory cells can be disposed in region RGNa, region RGNa may be referred to as a "memory cell array region", and region RGNd may be referred to as the "lower side of the memory cell array region". In an embodiment, region RGNa may overlap region RGNd in the vertical direction VD. For example, since region RGNb can be disposed between one memory cell array region and another memory cell array region, and region RGNc can be disposed on the lower side of region RGNb, region RGNb and region RGNc may be referred to as "intermediate regions", region RGNb may be referred to as an "upper intermediate region", and region RGNc may be referred to as a "lower intermediate region". In an embodiment, region RGNb may overlap region RGNc in the vertical direction VD.

[0042] The semiconductor memory device 100 may include a memory cell array, a first peripheral circuit, a second peripheral circuit, and a third peripheral circuit.

[0043] In an embodiment, the memory cell array may be disposed in the memory cell array region in the first semiconductor structure SEMS1, the first peripheral circuit may be disposed in the "upper intermediate region" in the first semiconductor structure SEMS1, the second peripheral circuit may be disposed in the "lower intermediate region" in the second semiconductor structure SEMS2, and the third peripheral circuit may be disposed on the "lower side of the memory cell array region" in the second semiconductor structure SEMS2. In an embodiment, the third peripheral circuit may overlap the memory cell array region in the vertical direction VD.

[0044] In an embodiment, the memory cell array may include vertical channel transistors (VCTs). The first peripheral circuit may include vertical channel transistors or horizontal channel transistors (HCTs). The second peripheral circuit and the third peripheral circuit may include horizontal channel transistors. For example, the memory cell array may be implemented by using vertical channel transistors, the first peripheral circuit may be implemented by using vertical channel transistors or horizontal channel transistors, and each of the second peripheral circuit and the third peripheral circuit may be implemented by using horizontal channel transistors.

[0045] In an embodiment, a horizontal channel transistor may include a planar field effect transistor (FET), a fin field effect transistor (FinFET), a recessed channel array transistor (RCAT), a spherical RCAT (S-RCAT), a buried channel array transistor (BCAT), etc., and a vertical channel transistor may refer to a transistor including a channel grown in a vertical channel after a horizontal channel transistor as semiconductor manufacturing process technology develops.

[0046] The first peripheral circuit and the second peripheral circuit provided in the “middle area” may have a given relationship.

[0047] In an embodiment, each of the first peripheral circuits may have heat resistance under given conditions associated with a manufacturing process of the semiconductor memory device 100. For example, under given conditions, the heat resistance of each of the first peripheral circuits may be higher than the heat resistance of the second peripheral circuit. For example, under given conditions, each of the first peripheral circuits may be less sensitive than the second peripheral circuit with respect to heat resistance.

[0048] In an embodiment, each of the first peripheral circuits may have a timing margin of a given level or more associated with the operation of the semiconductor memory device 100. For example, during a data input / output operation of the semiconductor memory device 100, the timing margin of each of the first peripheral circuits may be greater than the timing margin of each of the second peripheral circuits.

[0049] exist Figure 1 In the embodiment, the memory cell array, the first peripheral circuit, the second peripheral circuit, and the third peripheral circuit may be disposed in the regions RGNa, RGNb, RGNc, and RGNd of the semiconductor memory device 100, but the present invention is not limited thereto. In other embodiments, the semiconductor memory device 100 may further include regions, and additional peripheral circuits may be further disposed in the regions further included in the semiconductor memory device 100. Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A Various embodiments of the semiconductor memory device 100 are described.

[0050] Figure 1The vertical direction VD, the first horizontal direction HD1, and the second horizontal direction HD2 perpendicular to each other are shown. In the following drawings, the vertical direction VD, the first horizontal direction HD1, and the second horizontal direction HD2 can be used in common. For example, the vertical direction VD can be the direction away from the upper surface of the first semiconductor structure SEMS1 or the second semiconductor structure SEMS2, the first horizontal direction HD1 can be the direction from the memory cell array region to the upper intermediate region or the direction from the lower side of the memory cell array region to the lower intermediate region, and the second horizontal direction HD2 can be the direction perpendicular to the first horizontal direction HD1.

[0051] According to the above configuration, the semiconductor memory device of the present disclosure may include a peripheral circuit provided in the upper intermediate region between one memory cell array region and another memory cell array region. In a semiconductor memory device having a COP structure, the upper intermediate region may be a region in the first semiconductor structure forming the memory cell array, and considering the process of manufacturing the memory cell array or the operation of the semiconductor memory device, the peripheral circuits having characteristics at a given level or higher among all the peripheral circuits of the semiconductor memory device may be provided only in the upper intermediate region. Since all the peripheral circuits of the semiconductor memory device are appropriately distributed and provided in the upper intermediate region and the lower intermediate region, the chip size of the semiconductor memory device can be optimized.

[0052] Figure 2 is a block diagram showing a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

[0053] Refer to Figure 2 , the memory system 300 may include a memory controller 310 and a memory device 350. The memory device 350 may correspond to Figure 1 the semiconductor memory device 100.

[0054] The memory controller 310 may generally control the operation of the memory system 300 and may generally control the data exchange between the external host device and the memory device 350. For example, the memory controller 310 may generate a command CMD and an address ADDR depending on the request of the host device. Based on the command CMD and the address ADDR, the memory controller 310 may write the data indicated by the data signal DQ into the memory device 350 or read data from the memory device 350. For example, the memory controller 310 may provide a clock signal CLK for a write operation or a read operation to the memory device 350.

[0055] The memory device 350 may include a memory cell array 351 and peripheral circuits 353. The memory cell array 351 may include a plurality of memory cells for storing data, and the plurality of memory cells may be grouped into a plurality of sub-memory cell arrays (e.g., SMCAx) (x is an integer greater than or equal to 2). The peripheral circuits 353 (e.g., PERICKTy) (y is an integer greater than or equal to 2) may include various circuits for writing, reading, and managing data associated with the plurality of memory cells.

[0056] Figure 3 is a block diagram showing an embodiment of a Figure 1 semiconductor memory device according to an exemplary embodiment.

[0057] Referring to Figure 3 , the memory device 400 may include a control logic circuit 410, an address register 420, a bank control logic 431, a row address multiplexer 433, a column address latch 435, a repair control circuit 441, a power supply circuit 445, a row decoder 450, a column decoder 460, a memory cell array 490, an input / output strobe circuit 470, an error correction code (ECC) circuit 471, a data input / output buffer 473, an on-die termination (ODT) circuit 475, an equalizer circuit 477, data input / output pads 479, a sense amplifier unit 480, a temperature sensor 491, a refresh controller 493, and a row hammer handler 495. The memory device 400 may correspond to Figure 1 the semiconductor memory device 100 or Figure 2 the memory device 350.

[0058] The memory cell array 490 may include a first memory bank 490a to an eighth memory bank 490h. The row decoder 450 may include a first bank row decoder 450a to an eighth bank row decoder 450h respectively connected to the first memory bank 490a to the eighth memory bank 490h, the column decoder 460 may include a first bank column decoder 460a to an eighth bank column decoder 460h respectively connected to the first memory bank 490a to the eighth memory bank 490h, and the sense amplifier unit 480 may include a first bank sense amplifier 480a to an eighth bank sense amplifier 480h respectively connected to the first memory bank 490a to the eighth memory bank 490h.

[0059] The first bank 490a to the eighth bank 490h, the first bank sense amplifier 480a to the eighth bank sense amplifier 480h, the first bank row decoder 450a to the eighth bank row decoder 450h, and the first bank column decoder 460a to the eighth bank column decoder 460h may constitute the first bank to the eighth bank. Each of the first bank 490a to the eighth bank 490h may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC formed at the intersections of the word lines WL and the bit lines BL. Each of the first bank 490a to the eighth bank 490h may include a plurality of repair word lines WLr, a plurality of repair bit lines BLr, and a plurality of repair memory cells MCr formed at the intersections of the repair word lines WLr and the repair bit lines BLr.

[0060] Figure 3 The memory device 400 including eight banks is shown in , but the present invention is not limited thereto. In other embodiments, the memory device 400 may include any number of banks, that is, two or more banks.

[0061] The address register 420 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a memory controller (e.g., Figure 2 310). The address register 420 may provide the received bank address BANK_ADDR to the bank control logic 431, may provide the received row address ROW_ADDR to the row address multiplexer 433, and may provide the received column address COL_ADDR to the column address latch 435.

[0062] The bank control logic 431 may generate bank control signals in response to the bank address BANK_ADDR. The bank row decoder corresponding to the bank address BANK_ADDR among the first bank row decoder 450a to the eighth bank row decoder 450h may be activated in response to the bank control signal, and the bank column decoder corresponding to the bank address BANK_ADDR among the first bank column decoder 460a to the eighth bank column decoder 460h may be activated in response to the bank control signal.

[0063] The row address multiplexer 433 may receive the row address ROW_ADDR from the address register 420, and may receive a refresh row address REF_ADDR from the refresh controller 493 or the row hammer handler 495. The row address multiplexer 433 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA output from the row address multiplexer 433 may be applied to each of the first bank row decoder 450a to the eighth bank row decoder 450h.

[0064] The bank row decoders activated by the bank control logic 431 among the first bank row decoder 450a to the eighth bank row decoder 450h can decode the row address RA output from the row address multiplexer 433, and can activate the word line corresponding to the row address RA. For example, the activated bank row decoder can apply a word line drive voltage to the word line corresponding to the row address RA. The activated bank row decoder can generate the word line drive voltage by using a power supply voltage, and can supply the word line drive voltage to the corresponding word line.

[0065] The column address latch 435 can receive the column address COL_ADDR from the address register 420, and can temporarily store the received column address COL_ADDR. In addition, in burst mode, the column address latch 435 can gradually (or sequentially) increase the received column address COL_ADDR. The column address latch 435 can apply the temporarily stored column address COL_ADDR or the gradually increased column address COL_ADDR to each of the first bank column decoders 460a to the eighth bank column decoders 460h through the repair control circuit 441.

[0066] The bank column decoders activated by the bank control logic 431 among the first bank column decoder 460a to the eighth bank column decoder 460h can activate the sense amplifiers corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input / output strobe circuit 470.

[0067] Together with the circuit for strobing the input / output data, the input / output strobe circuit 470 can include the following: input data mask logic, a read data latch for storing the data output from the first bank 490a to the eighth bank 490h, and a write driver for writing data into the first bank 490a to the eighth bank 490h.

[0068] The data read from one of the first bank 490a to the eighth bank 490h can be read out by a sense amplifier corresponding to one of the first bank sense amplifiers 480a to the eighth bank sense amplifiers 480h, and can be stored in the read data latch.

[0069] The data stored in the read data latch can be provided to the memory controller through the ECC circuit 471, the data input / output buffer 473, the equalizer circuit 477, and the data input / output pad 479. The data to be written into one of the first bank 490a to the eighth bank 490h can be provided from the memory controller to the data input / output buffer 473 through the data input / output pad 479 and the equalizer circuit 477. The data provided to the data input / output buffer 473 can be provided to the input / output strobe circuit 470 through the ECC circuit 471.

[0070] The control logic circuit 410 can control the operation of the memory device 400. For example, the control logic circuit 410 can generate control signals such that the memory device 400 performs a write operation or a read operation. The control logic circuit 410 can include a command decoder 411 that decodes a command CMD received from the memory controller and a mode register 413 for setting the operation mode of the memory device 400.

[0071] In an embodiment, the control logic circuit 410 can output a control signal for controlling the ODT circuit 475, and the ODT circuit 475 can turn on / off one or more switches that can be included in the ODT circuit 475 based on the control signal.

[0072] The repair control circuit 441 can receive a column address COL_ADDR from the column address latch 435, compare the received column address COL_ADDR with a defective cell address indicating defective cells of the first bank 490a to the eighth bank 490h, and provide a repair control signal to the column decoder 460. In an embodiment, the repair control circuit 441 can include a defective cell memory that stores defective cell information for identifying a cell region to which a defective cell belongs, and the column decoder 460 can perform a column repair operation based on the repair control signal.

[0073] The power supply circuit 445 can provide various powers for the operation of various components included in the memory device 400.

[0074] The ECC circuit 471 can encode multiple write data to be written into the first bank 490a to the eighth bank 490h to generate parity symbols, and can provide a codeword CW including the multiple write data and the parity symbols to the input / output strobe circuit 470. The ECC circuit 471 can decode the codeword CW read from the first bank 490a to the eighth bank 490h to generate multiple read data, and can provide the multiple read data to the data input / output buffer 473.

[0075] The ODT circuit 475 can perform impedance matching and can prevent the quality of the transmission line from degrading, that is, prevent a data signal DQ included in the data transmitted through the data input / output pad 479 from being reflected as a noise signal at the end of the transmission line.

[0076] The equalizer circuit 477 can compensate for losses caused during the high-speed transmission of the data signal DQ.

[0077] The refresh controller 493 may provide a refresh address REF_ADDR for performing a refresh operation for compensating leakage current of a plurality of memory cells MC or a plurality of repaired memory cells MCr included in the first bank 490a to the eighth bank 490h.

[0078] The temperature sensor 491 may detect a predetermined temperature and may provide a temperature signal corresponding to the detected temperature to the refresh controller 493. The refresh controller 493 may change a refresh period depending on the detected temperature. For example, the refresh controller 493 may perform a temperature compensated self-refresh (TCSR) operation.

[0079] The row hammer handler 495 may provide a refresh address REF_ADDR for performing a hammer refresh operation for memory cells at a sacrificial row address adjacent to an attacker row address that is frequently accessed.

[0080] In an embodiment, the first bank 490a to the eighth bank 490h may correspond to the plurality of sub-memory cell arrays described in the reference Figure 2 For example, each of the first bank 490a to the eighth bank 490h may correspond to one sub-memory cell array.

[0081] Figure 3 FIG. shows various components 410, 411, 413, 420, 431, 433, 435, 441, 445, 450, 460, 470, 471, 473, 475, 477, 480, 490, 491, 493 and 495 included in the memory device 400, but the memory device 400 may further include Figure 3 any other components not shown in FIG.

[0082] For example, the memory device 400 may further include a sub-word line driver for driving a plurality of memory cells MC or a plurality of repaired memory cells MCr or a bit line sense amplifier for reading a voltage level of a bit line BL or a repaired bit line BLr.

[0083] For example, the memory device 400 may further include an input / output line driving circuit for driving local input / output lines and global input / output lines that transfer a voltage level read by the bit line sense amplifier to the input / output strobe circuit 470.

[0084] For example, the memory device 400 may further include a pre-decoder that is connected to the address register 420 and decodes a row address ROW_ADDR or a column address COL_ADDR to provide additional information to the row decoder 450 or the column decoder 460.

[0085] For example, the memory device 400 may further include an antifuse circuit for various settings associated with the operation of the memory device 400, a power / signal pad for transmitting power or signals provided from the outside, and an electrostatic protection circuit for protecting against an electric shock from the outside.

[0086] Figure 4A is a cross-sectional view of a semiconductor memory device taken along line X-X' according to an exemplary embodiment. Figure 1 is a cross-sectional view of a semiconductor memory device taken along line X-X' according to an exemplary embodiment. Figure 4B is a diagram for describing a memory cell array and a peripheral circuit disposed in a region according to an exemplary embodiment. Figure 4A is a diagram for describing a memory cell array and a peripheral circuit disposed in a region according to an exemplary embodiment. Figure 4C is a graph for describing characteristics of a first peripheral circuit and a second peripheral circuit disposed in a region according to an exemplary embodiment. Figure 4A is a graph for describing characteristics of a first peripheral circuit and a second peripheral circuit disposed in a region according to an exemplary embodiment.

[0087] Figure 4A The semiconductor memory device 100a of may correspond to Figure 1 the semiconductor memory device 100, and the semiconductor memory device 100a may include a first semiconductor structure SEMS1 and a second semiconductor structure SEMS2 disposed below (or on the lower side of) the first semiconductor structure SEMS1. In an embodiment, the first semiconductor structure SEMS1 may overlap the second semiconductor structure SEMS2 in the vertical direction VD.

[0088] Figure 4A A memory region MRGN, a first region RGN1, a second region RGN2, and a third region RGN3 are shown in, and the memory region MRGN may be an internal region of the first semiconductor structure SEMS1, and the second region RGN2 and the third region RGN3 may be internal regions of the second semiconductor structure SEMS2. In the semiconductor memory device 100a, each of the memory region MRGN and the third region RGN3 may include two or more regions.

[0089] In an embodiment, the memory region MRGN, the first region RGN1, the second region RGN2, and the third region RGN3 may respectively correspond to Figure 1 the regions RGNa, RGNb, RGNc, and RGNd of.

[0090] For example, the memory region MRGN may be included in Figure 1 the memory cell array region of, the first region RGN1 may be included in Figure 1 the "upper middle region" of, the second region RGN2 may be included in Figure 1 the "lower middle region" of, and the third region RGN3 may be included (or disposed) inFigure 1 on the "lower side of the memory cell array region". In an embodiment, the second region RGN2 may overlap with a part of the first region RGN1 in the vertical direction VD.

[0091] In an embodiment, the memory region MRGN and the first region RGN1 may be sequentially arranged in the first semiconductor structure SEMS1 along the first horizontal direction HD1 or in a direction away from the first horizontal direction HD1, and the third region RGN3 and the second region RGN2 may be sequentially arranged in the second semiconductor structure SEMS2 along the first horizontal direction HD1 or in a direction away from the first horizontal direction HD1.

[0092] Refer to Figure 4B , as in the semiconductor memory device 100 of Figure 1 , the semiconductor memory device 100a may include a memory cell array MCA, a first peripheral circuit PERICKT1, a second peripheral circuit PERICKT2, and a third peripheral circuit PERICKT3. Accordingly, the memory cell array MCA may be arranged in the memory region MRGN, the first peripheral circuit PERICKT1 may be arranged in the first region RGN1, the second peripheral circuit PERICKT2 may be arranged in the second region RGN2, and the third peripheral circuit PERICKT3 may be arranged in the third region RGN3.

[0093] In an embodiment, the memory cell array MCA may include vertical channel transistors VCT. The first peripheral circuit PERICKT1 may include vertical channel transistors VCT or horizontal channel transistors HCT. Each of the second peripheral circuit PERICKT2 and the third peripheral circuit PERICKT3 may include horizontal channel transistors.

[0094] Refer to Figure 4C , because the first peripheral circuit PERICKT1 is included in the "upper middle region" of Figure 1 , and the second peripheral circuit PERICKT2 is included in the "lower middle region" of Figure 1 , so the first peripheral circuit PERICKT1 and the second peripheral circuit PERICKT2 may be arranged in the "middle region" of Figure 1 , and the peripheral circuits arranged in the "middle region" may have a given relationship.

[0095] In an embodiment, each of the first peripheral circuits PERICKT1 may have heat resistance under a first condition associated with the process of manufacturing the semiconductor memory device 100a.

[0096] For example, the first condition may be associated with the process of manufacturing each memory cell included in the memory cell array MCA. Each memory cell may include a cell transistor and a cell capacitor, and the first condition may represent a physical or chemical shock applied to the semiconductor memory device 100a in the process of forming the cell capacitor on the upper side of the cell transistor after the cell transistor is formed. The first peripheral circuit provided in the "upper middle region" may be more exposed to the physical or chemical shock under the first condition than the second peripheral circuit provided in the "lower middle region". In particular, the peripheral temperature of the first peripheral circuit may rise to a temperature higher than the peripheral temperature of the second peripheral circuit. This may mean that a circuit vulnerable to the physical or chemical shock under the first condition can be selected as the second peripheral circuit instead of the first peripheral circuit. For example, under the first condition, the heat resistance of each of the first peripheral circuits PERICKT1 may be greater than the heat resistance of the second peripheral circuit PERICKT2. For example, as Figure 4C shown, under the first condition, the average (Avg.) heat resistance of the first peripheral circuit PERICKT1 may be greater than the average (Avg.) heat resistance of the second peripheral circuit PERICKT2. In this case, the reference value REFV may be a reference temperature associated with the first condition, and the first peripheral circuit PERICKT1 and the second peripheral circuit PERICKT2 may be determined based on the reference value REFV.

[0097] In an embodiment, each of the first peripheral circuits PERICKT1 may have a timing tolerance at a given level or greater level associated with the operation of the semiconductor memory device 100a. For example, during the data input / output operation of the semiconductor memory device 100a, the timing tolerance of each of the first peripheral circuits PERICKT1 may be greater than the timing tolerance of each of the second peripheral circuits PERICKT2. The timing tolerance may include the operating speed of each of the first peripheral circuit PERICKT1 and the second peripheral circuit PERICKT2, and may include the setup time or hold time of various signals. The timing tolerance may be associated with the signal integrity of the signals transmitted / received by the first peripheral circuit. For example, the timing tolerance of each of the first peripheral circuits PERICKT1 may be greater than the timing tolerance of each of the second peripheral circuits PERICKT2. For example, as Figure 4CAs shown, the average (Avg.) timing tolerance of the first peripheral circuit PERICKT1 can be greater than that of the second peripheral circuit PERICKT2. In this case, the reference value REFV can be the reference timing tolerance, and the first peripheral circuit PERICKT1 and the second peripheral circuit PERICKT2 can be determined based on the reference value REFV. For other examples, the operating speed of each of the first peripheral circuits PERICKT1 can be slower than that of each of the second peripheral circuits PERICKT2.

[0098] In an embodiment, the first peripheral circuit PERICKT1 may include one or more of the mode register 413, refresh controller 493, row hammer handler 495, and power supply circuit 445 described in reference Figure 3 However, this is only an example. For example, the first peripheral circuit PERICKT1 may include at least one of the mode register 413, refresh controller 493, row hammer handler 495, and power supply circuit 445 described in reference Figure 3 In another embodiment, the first peripheral circuit PERICKT1 may further include an antifuse circuit, a power / signal pad, and a pre-decoder described in reference Figure 3

[0099] In an embodiment, the second peripheral circuit PERICKT2 may include one or more of the command decoder 411, data input / output buffer 473, and ODT circuit 475 described in reference Figure 3 However, this is only an example. For example, the second peripheral circuit PERICKT2 may include at least one of the command decoder 411, data input / output buffer 473, and ODT circuit 475 described in reference Figure 3 In another embodiment, the second peripheral circuit PERICKT2 may further include an equalizer circuit 477 described in reference Figure 3

[0100] In an embodiment, the third peripheral circuit PERICKT3 may include one or more of the bit line sense amplifier, sub-word line driver, row decoder 450, and column decoder 460 described in reference Figure 3 However, this is only an example. For example, the third peripheral circuit PERICKT3 may include at least one of the bit line sense amplifier, sub-word line driver, row decoder 450, and column decoder 460 described in reference Figure 3 In another embodiment, the third peripheral circuit PERICKT3 may further include an input / output line driver circuit for driving local input / output lines and global input / output lines to transfer the voltage level read by the bit line sense amplifier to the input / output strobe circuit. ​​

[0101] Figure 5A is a cross-sectional view of a semiconductor memory device taken along the line X-X' according to an exemplary embodiment. Figure 1 of Figure 5B is a diagram for describing a memory cell array and a peripheral circuit provided in a region of Figure 5A according to an exemplary embodiment.

[0102] Figure 5A The semiconductor memory device 100b of Figure 1 may correspond to the semiconductor memory device 100 of

[0103] Figure 5A and the semiconductor memory device 100b may include a first semiconductor structure SEMS1 and a second semiconductor structure SEMS2 provided below (or on the lower side of) the first semiconductor structure SEMS1. In an embodiment, the first semiconductor structure SEMS1 may overlap the second semiconductor structure SEMS2 in a vertical direction VD.

[0104] Figure 5A The semiconductor memory device 100b of Figure 4A may be the same as or similar to the semiconductor memory device 100a of

[0105] except that it further includes a fourth region RGN4, and thus, additional description will be omitted to avoid redundancy. The fourth region RGN4 may be provided between the memory region MRGN and the first region RGN1.

[0106] Referring to Figure 5B as shown in Figure 4AIn the semiconductor memory device 100a, the semiconductor memory device 100b may further include a memory cell array MCA, a first peripheral circuit PERICKT1, a second peripheral circuit PERICKT2, a third peripheral circuit PERICKT3, and a fourth peripheral circuit PERICKT4. Accordingly, the memory cell array MCA may be disposed in a memory region MRGN, the first peripheral circuit PERICKT1 may be disposed in a first region RGN1, the second peripheral circuit PERICKT2 may be disposed in a second region RGN2, and the third peripheral circuit PERICKT3 may be disposed in a third region RGN3. The fourth peripheral circuit PERICKT4 may be disposed in a fourth region RGN4.

[0107] In an embodiment, such as in the first peripheral circuit PERICKT1, the fourth peripheral circuit PERICKT4 may include a vertical channel transistor VCT or a horizontal channel transistor HCT.

[0108] In an embodiment, such as in the first peripheral circuit PERICKT1, the fourth peripheral circuit PERICKT4 may have heat resistance under a first condition associated with a process of manufacturing the semiconductor memory device 100b and may have a timing tolerance at a given level or greater level associated with an operation of the semiconductor memory device 100b. However, the present invention is not limited thereto.

[0109] In an embodiment, the fourth peripheral circuit PERICKT4 may include a repair control circuit 441 as described in Figure 3 and this is only an example.

[0110] Figure 6A is a cross-sectional view of a semiconductor memory device taken along the line X-X' according to an exemplary embodiment. Figure 1 is a diagram for describing a memory cell array and peripheral circuits disposed in a region according to an exemplary embodiment. Figure 6B is for describing Figure 6A a memory cell array and peripheral circuits disposed in a region according to an exemplary embodiment.

[0111] Figure 6A The semiconductor memory device 100c may correspond to Figure 1 the semiconductor memory device 100, and the semiconductor memory device 100c may include a first semiconductor structure SEM S1 and a second semiconductor structure SEM S2 disposed below (or on a lower side of) the first semiconductor structure SEM S1. In an embodiment, the first semiconductor structure SEM S1 may overlap the second semiconductor structure SEM S2 in a vertical direction VD.

[0112] Figure 6AThe memory region MRGN, the first region RGN1, the second region RGN2, the third region RGN3, the fourth region RGN4, and the fifth region RGN5 are shown. The memory region MRGN, the first region RGN1, and the fourth region RGN4 may be internal regions of the first semiconductor structure SEMS1, and the second region RGN2, the third region RGN3, and the fifth region RGN5 may be internal regions of the second semiconductor structure SEMS2. In the semiconductor memory device 100c, each of the memory region MRGN, the third region RGN3, the fourth region RGN4, and the fifth region RGN5 may include two or more regions.

[0113] Except for further including the fifth region RGN5, Figure 6A the semiconductor memory device 100c may be the same as or similar to Figure 5A the semiconductor memory device 100b, and thus, additional descriptions will be omitted to avoid redundancy. The fifth region RGN5 may be disposed on the lower side of the fourth region RGN4. In an embodiment, the fifth region RGN5 may overlap the fourth region RGN4 in the vertical direction VD.

[0114] In an embodiment, the third region RGN3, the fifth region RGN5, and the second region RGN2 may be sequentially disposed in the second semiconductor structure SEMS2 along the first horizontal direction HD1 or in a direction away from the first horizontal direction HD1, and this is only an example.

[0115] Referring to Figure 6B as in Figure 5A the semiconductor memory device 100b, the semiconductor memory device 100c may include a memory cell array MCA, a first peripheral circuit PERICKT1, a second peripheral circuit PERICKT2, a third peripheral circuit PERICKT3, and a fourth peripheral circuit PERICKT4, and further include a fifth peripheral circuit PERICKT5. Accordingly, the memory cell array MCA may be disposed in the memory region MRGN, the first peripheral circuit PERICKT1 may be disposed in the first region RGN1, the second peripheral circuit PERICKT2 may be disposed in the second region RGN2, and the third peripheral circuit PERICKT3 may be disposed in the third region RGN3. The fourth peripheral circuit PERICKT4 may be disposed in the fourth region RGN4. The fifth peripheral circuit PERICKT5 may be disposed in the fifth region RGN5.

[0116] In an embodiment, as in the second peripheral circuit PERICKT2 or the third peripheral circuit PERICKT3, the fifth peripheral circuit PERICKT5 may include a horizontal channel transistor HCT.

[0117] In an embodiment, the characteristics of the fifth peripheral circuit PERICKT5 may be similar to those of the second peripheral circuit PERICKT2 or the third peripheral circuit PERICKT3.

[0118] In an embodiment, the fifth peripheral circuit PERICKT5 may include a reference Figure 3 ECC circuit 471 described, and this is only an example.

[0119] Figure 7A is a cross-sectional view of a semiconductor memory device taken along line X-X' according to an exemplary embodiment. Figure 1 of Figure 7B is a diagram for describing a memory cell array and peripheral circuits provided in a region of Figure 7A according to an exemplary embodiment.

[0120] Figure 7A The semiconductor memory device 100d of Figure 1 may correspond to the semiconductor memory device 100 of

[0121] Figure 7A and the semiconductor memory device 100d may include a first semiconductor structure SEMS1 and a second semiconductor structure SEMS2 provided below (or on the lower side of) the first semiconductor structure SEMS1. In an embodiment, the first semiconductor structure SEMS1 may overlap the second semiconductor structure SEMS2 in the vertical direction VD.

[0122] A memory region MRGN, a first region RGN1, a second region RGN2, a third region RGN3, a fourth region RGN4, a fifth region RGN5, and a sixth region RGN6 are shown in Figure 7A and the memory region MRGN, the first region RGN1, and the fourth region RGN4 may be internal regions of the first semiconductor structure SEMS1, and the second region RGN2, the third region RGN3, the fifth region RGN5, and the sixth region RGN6 may be internal regions of the second semiconductor structure SEMS2. In the semiconductor memory device 100d, each of the memory region MRGN, the third region RGN3, the fourth region RGN4, the fifth region RGN5, and the sixth region RGN6 may include two or more regions.

[0122] Except for further including a sixth region RGN6, Figure 7A the semiconductor memory device 100d of Figure 6A may be the same as or similar to the semiconductor memory device 100c of

[0123] In an embodiment, the third region RGN3, the sixth region RGN6, the fifth region RGN5, and the second region RGN2 may be sequentially disposed in the second semiconductor structure SEMS2 along the first horizontal direction HD1 or in a direction away from the first horizontal direction HD1, and this is merely an example.

[0124] Reference Figure 7B , as in Figure 6A In the semiconductor memory device 100c of, the semiconductor memory device 100d may include a memory cell array MCA, a first peripheral circuit PERICKT1, a second peripheral circuit PERICKT2, a third peripheral circuit PERICKT3, a fourth peripheral circuit PERICKT4, and a fifth peripheral circuit PERICKT5, and may further include a sixth peripheral circuit PERICKT6. Accordingly, the memory cell array MCA may be disposed in a memory region MRGN, the first peripheral circuit PERICKT1 may be disposed in a first region RGN1, the second peripheral circuit PERICKT2 may be disposed in a second region RGN2, and the third peripheral circuit PERICKT3 may be disposed in a third region RGN3. The fourth peripheral circuit PERICKT4 may be disposed in a fourth region RGN4, and the fifth peripheral circuit PERICKT5 may be disposed in a fifth region RGN5. The sixth peripheral circuit PERICKT6 may be disposed in a sixth region RGN6.

[0125] In an embodiment, such as in the second peripheral circuit PERICKT2, the third peripheral circuit PERICKT3, or the fifth peripheral circuit PERICKT5, the sixth peripheral circuit PERICKT6 may include a horizontal channel transistor HCT.

[0126] In an embodiment, the characteristics of the sixth peripheral circuit PERICKT6 may be the same as those of the second peripheral circuit PERICKT2, the third peripheral circuit PERICKT3, or the fifth peripheral circuit PERICKT5.

[0127] In an embodiment, the sixth peripheral circuit PERICKT6 may include a reference Figure 3 input / output line driving circuit described, and this is merely an example.

[0128] Figure 8A is a cross-sectional view of a semiconductor memory device taken along Figure 1 line X-X' according to an exemplary embodiment. Figure 8B is a diagram for describing a memory cell array and peripheral circuits disposed in a Figure 8A region according to an exemplary embodiment.

[0129] Figure 8AThe semiconductor memory device 100e can correspond to Figure 1 the semiconductor memory device 100, and the semiconductor memory device 100e can include a first semiconductor structure SEMS1 and a second semiconductor structure SEMS2 disposed below (or on the lower side of) the first semiconductor structure SEMS1. In an embodiment, the first semiconductor structure SEMS1 can overlap the second semiconductor structure SEMS2 in the vertical direction VD.

[0130] Figure 8A The memory region MRGN, the first region RGN1, the second region RGN2, the third region RGN3, the fourth region RGN4, the fifth region RGN5, the sixth region RGN6, and the seventh region RGN7 are shown in Figure 8A . The memory region MRGN, the first region RGN1, and the fourth region RGN4 can be internal regions of the first semiconductor structure SEMS1, and the second region RGN2, the third region RGN3, the fifth region RGN5, the sixth region RGN6, and the seventh region RGN7 can be internal regions of the second semiconductor structure SEMS2. In the semiconductor memory device 100e, each of the memory region MRGN, the third region RGN3, the fourth region RGN4, the fifth region RGN5, the sixth region RGN6, and the seventh region RGN7 can include two or more regions.

[0131] Except for further including the seventh region RGN7, Figure 8A the semiconductor memory device 100e can be the same as or similar to Figure 7A the semiconductor memory device 100d, and thus, additional descriptions will be omitted to avoid redundancy. The seventh region RGN7 can be disposed on the lower side of the first region RGN1. In an embodiment, the seventh region RGN7 can overlap a part of the first region RGN1 in the vertical direction VD.

[0132] In an embodiment, the third region RGN3, the sixth region RGN6, the seventh region RGN7, and the second region RGN2 can be sequentially disposed in the second semiconductor structure SEMS2 along the first horizontal direction HD1 or in a direction away from the first horizontal direction HD1, and this is only an example.

[0133] Referring to Figure 8B as in Figure 7AIn the semiconductor memory device 100d, the semiconductor memory device 100e may include a memory cell array MCA, a first peripheral circuit PERICKT1, a second peripheral circuit PERICKT2, a third peripheral circuit PERICKT3, a fourth peripheral circuit PERICKT4, a fifth peripheral circuit PERICKT5, and a sixth peripheral circuit PERICKT6, and may further include a seventh peripheral circuit PERICKT7. Accordingly, the memory cell array MCA may be disposed in a memory region MRGN, the first peripheral circuit PERICKT1 may be disposed in a first region RGN1, the second peripheral circuit PERICKT2 may be disposed in a second region RGN2, and the third peripheral circuit PERICKT3 may be disposed in a third region RGN3. The fourth peripheral circuit PERICKT4 may be disposed in a fourth region RGN4, the fifth peripheral circuit PERICKT5 may be disposed in a fifth region RGN5, and the sixth peripheral circuit PERICKT6 may be disposed in a sixth region RGN6. The seventh peripheral circuit PERICKT7 may be disposed in a seventh region RGN7.

[0134] In an embodiment, as in the second peripheral circuit PERICKT2, the third peripheral circuit PERICKT3, the fifth peripheral circuit PERICKT5, or the sixth peripheral circuit PERICKT6, the seventh peripheral circuit PERICKT7 may include a horizontal channel transistor HCT.

[0135] In an embodiment, the characteristics of the seventh peripheral circuit PERICKT7 may be similar to those of the second peripheral circuit PERICKT2, the third peripheral circuit PERICKT3, the fifth peripheral circuit PERICKT5, or the sixth peripheral circuit PERICKT6.

[0136] In an embodiment, the seventh peripheral circuit PERICKT7 may include a reference Figure 3 described electrostatic protection circuit, and this is only an example.

[0137] Figure 9 is a plan view of a first semiconductor structure for describing an example embodiment of Figure 1 of.

[0138] Reference Figure 9 , the first semiconductor structure SEMS1 may include a plurality of sub-memory cell arrays SMCA, a body repair control circuit RPCTL, a mode register, a refresh controller, a row hammer handler, and a power supply circuit.

[0139] Reference Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A andFigure 9 , a plurality of sub - memory cell arrays SMCA can be disposed in a memory region MRGN, a bulk repair control circuit RPCTL can be disposed in a fourth region RGN4, and a mode register, a refresh controller, a row - hammer handler, and a power circuit can be disposed in a first region RGN1. The plurality of sub - memory cell arrays SMCA can respectively correspond to the bulk repair control circuit RPCTL.

[0140] In an embodiment, the plurality of sub - memory cell arrays SMCA can form Figure 9 a memory cell array 490, and the bulk repair control circuit RPCTL can form Figure 3 a repair control circuit 441. The mode register, the refresh controller, the row - hammer handler, and the power circuit can correspond to a first peripheral circuit.

[0141] In an embodiment, the memory cell array 490 can include a plurality of first sub - memory cell arrays and a plurality of second sub - memory cell arrays. The plurality of first sub - memory cell arrays can be sub - memory cell arrays SMCA disposed at a first row ROWa in the memory cell array, and the plurality of second sub - memory cell arrays can be sub - memory cell arrays SMCA disposed at a second row ROWb in the memory cell array. For example, the plurality of first sub - memory cell arrays can be disposed at the first row ROWa in the memory cell array so as to be adjacent to each other in a second horizontal direction HD2, and the plurality of second sub - memory cell arrays can be disposed at the second row ROWb in the memory cell array so as to be adjacent to each other in the second horizontal direction HD2.

[0142] In an embodiment, the first peripheral circuit can be disposed between the plurality of first sub - memory cell arrays and the plurality of second sub - memory cell arrays in a first horizontal direction HD1.

[0143] Figure 10 is a plan view of a second semiconductor structure for describing Figure 1 according to an exemplary embodiment.

[0144] Referring to Figure 10 , the second semiconductor structure SEMS2 can include a bit - line sense amplifier BLSA, a sub - word - line driver SWD, a row decoder, a column decoder, an input / output line driver circuit, an ECC circuit, a command decoder, a data input / output buffer, an ODT circuit, and an EQ circuit.

[0145] Referring to Figure 8A and Figure 10, the bit line sense amplifier BLSA, sub-word line driver SWD, row decoder, and column decoder can be disposed in the third region RGN3, the input / output line driver circuit can be disposed in the sixth region RGN6, and the ECC circuit can be disposed in the fifth region RGN5. The command decoder, data input / output buffer, ODT circuit, and EQ circuit can be disposed in the second region RGN2. Although not shown in Figure 10 , the electrostatic protection circuit can be disposed in the seventh region RGN7.

[0146] Figure 11A and Figure 11B are diagrams for describing reducing the chip size by a semiconductor memory device according to an embodiment of the present disclosure.

[0147] In Figure 11A , the semiconductor structure SEMSa is shown, and in Figure 11B , the semiconductor structure SEMSb is shown. The semiconductor structure SEMSa can show the placement of components of a conventional semiconductor memory device without a COP structure, and the semiconductor structure SEMSb can show the placement of some components of a semiconductor memory device having a COP structure according to an embodiment of the present disclosure. For example, the semiconductor structure SEMSb can be the first semiconductor structure SEMS1 described with reference to Figure 1 , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9 .

[0148] Referring to Figure 11A , the semiconductor structure SEMSa can include a plurality of sub-memory cell arrays SMCAs, a row decoder ROWDEC, a column decoder COLDEC, a bulk repair control circuit RPCTL, a first peripheral circuit PERICKT1, a second peripheral circuit PERICKT2, a third peripheral circuit PERICKT3, etc. As shown in Figure 11A , one row decoder ROWDEC can be disposed between two sub-memory cell arrays SMCAs, and one column decoder COLDEC and one bulk repair control circuit RPCTL can operate for one sub-memory cell array SMCA.

[0149] Referring to Figure 11B , the semiconductor structure SEMSb can include a plurality of sub-memory cell arrays SMCAs, a bulk repair control circuit RPCTL, a first peripheral circuit PERICKT1, etc. As shown in Figure 11BAs shown, the row decoder ROWDEC and the column decoder COLDEC may be disposed on the lower side of a plurality of sub - memory cell arrays SMCA, and the second peripheral circuit PERICKT2, the third peripheral circuit PERICKT3, etc. may also be disposed on the lower side of the plurality of sub - memory cell arrays SMCA or the first peripheral circuit PERICKT1.

[0150] In the semiconductor structure SEMSa, the region where the first to third peripheral circuits PERICKT1, PERICKT2, PERICKT3,... etc. are provided may correspond to the "intermediate region" described in the reference. Figure 1 In the semiconductor structure SEMSb, the region where the first peripheral circuit PERICKT1 is provided may correspond to the "intermediate region". Comparing the "intermediate regions" of the semiconductor structures SEMSa and SEMSb, the width of the "intermediate region" of the semiconductor structure SEMSa in the first horizontal direction HD1 may be w1, the width of the "intermediate region" of the semiconductor structure SEMSb in the first horizontal direction HD1 may be w2, and w2 may be reduced to less than half of w1. In addition, in the semiconductor structure SEMSb, the row decoder ROWDEC and the column decoder COLDEC of the semiconductor structure SEMSa may be removed.

[0151] Therefore, compared with the semiconductor structure SEMSa, the area of the semiconductor structure SEMSb may be reduced by as much as the Figure 11B shadow area, and thus, the chip size of the semiconductor memory device according to the embodiments of the present disclosure can be optimized. The shadow area may be 20% or more of the total area occupied by the semiconductor structure SEMSa.

[0152] Figure 12 is a diagram showing a part of the Figure 1 semiconductor memory device according to an exemplary embodiment. Figure 12 The semiconductor memory device 100 - 1 may correspond to the Figure 1 semiconductor memory device 100.

[0153] Figure 12 The sub - memory cell array region MRGN - 1 and regions RGN3 - 11, RGN3 - 12, RGN4 - 1, RGN5 - 1, and RGN6 - 1 are shown in.

[0154] Referring to Figure 12 , the sub - memory cell array region MRGN - 1 may be within the first semiconductor structure SEM S1 and may include one sub - memory cell array SMCA.

[0155] The region RGN4 - 1 may be within the first semiconductor structure SEM S1 and may be for reference including Figure 5Aa part of the fourth region RGN4 described in the above drawings, and may be a region adjacent to the sub-memory cell array region MRGN-1 in the first horizontal direction HD1. In an embodiment, the region RGN4-1 may be a reference including Figure 6A , Figure 7A , Figure 8A and Figure 9 a part of the fourth region RGN4 described in the above drawings.

[0156] The regions RGN3-11 and RGN3-12 may be within the second semiconductor structure SEMS2, may be a part of the third region RGN3 described in the above drawings with reference to including Figure 4A , and may be a region located on the lower side of the sub-memory cell array region MRGN-1. The region RGN3-12 may be a region located at the edge of the region RGN3-11 and extending in the first horizontal direction HD1.

[0157] The region RGN5-1 may be within the second semiconductor structure SEMS2, may be a part of the fifth region RGN5 described in the above drawings with reference to including Figure 6A , and may be a region located on the lower side of the region RGN4-1. In an embodiment, the region RGN5-1 may overlap with the region RGN4-1 in the vertical direction VD.

[0158] The region RGN6-1 may be within the second semiconductor structure SEMS2, may be a part of the sixth region RGN6 described in the above drawings with reference to including Figure 7A , and may be a region located on the lower side of the sub-memory cell array region MRGN-1. In an embodiment, the region RGN6-1 may overlap with a part of the sub-memory cell array region MRGN-1 in the vertical direction VD.

[0159] In an embodiment, the sub-memory cell array SMCA may include unit memory cells MC, and bit line sense amplifiers BLSAx and BLSAy for reading the voltage levels of bit lines or repaired bit lines connected to the unit memory cells MC, and sub-word line drivers SWDx and SWDy for driving word lines connected to the unit memory cells MC may be provided in the region RGN3-11.

[0160] In an embodiment, various control circuits and drive circuits capable of controlling the input / output line drive circuit that can be provided in the region RGN6-1 or controlling the operations of the bit line sense amplifiers BLSAx and BLSAy and the sub-word line drivers SWDx and SWDy may be provided in the region RGN3-12.

[0161] Figure 13A is for describing the setting according to an exemplary embodiment inFigure 1 A diagram of a plurality of sub - memory cell arrays in a memory region of a semiconductor memory device. Figure 13B is a diagram for describing a peripheral circuit provided on the lower side of a plurality of sub - memory cell arrays according to an exemplary embodiment. Figure 13A A diagram of a plurality of sub - memory cell arrays in a memory region of a semiconductor memory device.

[0162] Referring to Figure 13A , the memory region MRGN - 2 may include a plurality of sub - memory cell arrays SMCAa, SMCAb, SMCAc, SMCAd, SMCAe, SMCAf, SMCAg, SMCAh, SMCAi, and SMCAj. Each of the plurality of sub - memory cell arrays SMCAa to SMCAj may include a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, and may correspond to the sub - memory cell array SMCAx described in reference Figure 2 .

[0163] The sub - memory cell arrays SMCAa to SMCAe may be provided in the first row, and the sub - memory cell arrays SMCAf to SMCAj may be provided in the second row.

[0164] Referring to Figure 13B , the peripheral circuits corresponding to the plurality of sub - memory cell arrays SMCAa to SMCAj may be provided in the region RGN3 - 1. For example, the bit - line sense amplifiers BLSA1a and BLSA2a and the sub - word - line driver SWDay corresponding to the sub - memory cell array SMCAa may be provided in the region RGN3 - 1. The bit - line sense amplifiers BLSA1b and BLSA2b and the sub - word - line drivers SWDbx and SWDby corresponding to the sub - memory cell array SMCAb may be provided in the region RGN3 - 1. The bit - line sense amplifiers BLSA1c and BLSA2c and the sub - word - line drivers SWDcx and SWDcy corresponding to the sub - memory cell array SMCAc may be provided in the region RGN3 - 1. As described above, the bit - line sense amplifiers and the sub - word - line drivers corresponding to the remaining sub - memory cell arrays SMCAd to SMCAj may be provided in the region RGN3 - 1.

[0165] Figure 13A and Figure 13B The sub - memory cell arrays SMCAa to SMCAj and the peripheral circuits may be in the shape of a matrix having two rows and five columns, but this is only an example. The number of rows or the number of columns of the sub - memory cell arrays may be increased or decreased.

[0166] Figure 14 is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0167] Referring toFigure 14 , the semiconductor memory device 1000 may include a memory cell array structure MCS and a core peripheral circuit structure CPS.

[0168] The memory cell array structure MCS may be formed on a first substrate 1010. The memory cell array structure MCS may include a data storage structure DSS and a signal routing structure SRS. The data storage structure DSS may include a plurality of memory cells, a plurality of bit lines, and a plurality of word lines, and each memory cell includes a capacitor "C" and a cell transistor TR. The signal routing structure SRS may include a plurality of upper metal pads UMP and a plurality of metal lines ML. The plurality of metal lines ML may provide electrical connections between the plurality of upper metal pads UMP and the data storage structure DSS. For example, the plurality of metal lines ML may provide electrical connections between some of the plurality of upper metal pads UMP and the bit lines or between some of the plurality of upper metal pads UMP and the word lines.

[0169] The core peripheral circuit structure CPS may be formed on a second substrate 1020. The core peripheral circuit structure CPS may include a transistor layer TRL. A plurality of transistors for driving the memory cell array structure MCS may be provided on the transistor layer TRL. Some of the plurality of transistors provided in the transistor layer TRL may constitute a bit line sense amplifier. Other transistors among the plurality of transistors provided in the transistor layer TRL may constitute a sub-word line driver. Other transistors among the plurality of transistors provided in the transistor layer TRL may constitute any other peripheral circuits for the operation of the semiconductor memory device 1000.

[0170] The plurality of upper metal pads UMP and the plurality of lower metal pads LMP may be provided at corresponding positions and provide electrical connections between each component formed in the first substrate 1010 and each component formed in the second substrate 1020. The plurality of upper metal pads UMP and the plurality of lower metal pads LMP may constitute a pad array PDA.

[0171] Figure 15 is a plan view showing a pad array included in the Figure 14 semiconductor memory device.

[0172] Referring to Figure 15 , the pad array PDA may include a plurality of bit line pads BL_PAD and a plurality of word line pads WL_PAD. The pad array PDA may include Figure 14 one of the plurality of upper metal pads UMP or the plurality of lower metal pads LMP shown in Figure 14 Each of the plurality of circles in the pad array PDA may indicate

[0173] Multiple bit line pads BL_PAD can be distributed and arranged such that multiple word line pads WL_PAD are inserted therebetween. The multiple bit line pads BL_PAD can be electrically connected to a bit line connection region BLC through one or more metal layers. The bit line pads BL_PAD disposed on one side of the multiple word line pads WL_PAD can be routed to an adjacent bit line connection region BLC, and the bit line pads BL_PAD disposed on the other side of the multiple word line pads WL_PAD can be routed to an adjacent bit line connection region BLC.

[0174] The multiple word line pads WL_PAD can be electrically connected to a word line connection region WLC through one or more metal layers.

[0175] The bit line connection region BLC can provide an electrical connection between the multiple bit line pads BL_PAD and bit lines included in a memory cell array. The word line connection region WLC can provide an electrical connection between the multiple word line pads WL_PAD and word lines included in the memory cell array.

[0176] Figure 16A is a cross-sectional view of a semiconductor memory device taken along Figure 15 line A-A' according to an exemplary embodiment. Figure 14

[0177] Referring to Figure 16A , a bit line sense amplifier disposed in a transistor layer TRL can be electrically connected to a bit line BL.

[0178] For ease of description, in Figure 16A , remaining components (e.g., adjacent metal pads) other than components that provide an electrical connection between the bit line sense amplifier disposed in the transistor layer TRL and the bit line BL will be omitted. The bit line sense amplifier disposed in the transistor layer TRL can be electrically connected to a lower metal pad LMP0 through metal layers M0, M1, M2, M3, M4, and M5. The lower metal pad LMP0 can physically and electrically contact an upper metal pad UMP0. The upper metal pad UMP0 can be electrically connected to multiple metal lines LM3, LM2, LM1, and LM0. The metal line LM0 can be connected to the bit line BL through a metal contact MC0. The metal contact MC0 can be formed in Figure 15In the bit line connection region BLC. The potential change of the bit line BL caused by the capacitor "C" and the cell transistor TR is applied (or transmitted) to the transistor layer TRL through a plurality of metal lines LM0 to LM3, an upper metal pad UMP0, a lower metal pad LMP0, and a plurality of metal layers M0 to M5. A bit line sense amplifier provided in the transistor layer TRL can read the data stored in the capacitor "C" by amplifying the potential change of the bit line BL. The data storage structure DSS can include a plurality of capacitors "C", cell transistors TR, and a plurality of bit lines BL. The signal routing structure SRS can include a plurality of metal lines LM0 to LM3 and an upper metal pad UMP0.

[0179] Figure 16B is along an example embodiment Figure 15 taken along line B-B' Figure 14 of a cross-sectional view of a semiconductor memory device.

[0180] Referring to Figure 16B , a sub-word line driver provided in the transistor layer TLR can be electrically connected to the word line WL.

[0181] For ease of description, in Figure 16B will omit the remaining components (e.g., adjacent metal pads) other than the components that provide the electrical connection between the sub-word line driver provided in the transistor layer TRL and the word line WL. The sub-word line driver provided in the transistor layer TRL can be electrically connected to the lower metal pad LMP1 through the metal layers M0, M1, M2, M3, M4, and M5. The lower metal pad LMP1 can physically and electrically contact the upper metal pad UMP1. The upper metal pad UMP1 can be electrically connected to a plurality of metal lines LM3, LM2, LM1, and LM0. The metal line LM0 can be connected to the word line WL through a metal contact MC0. The metal contact MC0 can be formed in Figure 15 the word line connection region WLC. The word line drive voltage output by the sub-word line driver can be applied to the word line WL through a plurality of metal layers M0 to M5, the lower metal pad LMP1, the upper metal pad UMP1, a plurality of metal lines LM0 to LM3, and the metal contact MC0. The cell transistor TR can be switched by the word line drive voltage applied to the word line WL, and thus, the bit line BL and the capacitor "C" can be electrically connected. The data storage structure DSS can include a plurality of capacitors "C", cell transistors TR, a plurality of bit lines BL, and a plurality of word lines WL. The signal routing structure SRS can include a plurality of metal lines LM0 to LM3 and an upper metal pad UMP1.

[0182] As described above, a semiconductor memory device according to an embodiment of the present disclosure may include a peripheral circuit disposed in an upper intermediate region between one memory cell array region and another memory cell array region. In a semiconductor memory device having a COP structure, the upper intermediate region may be a region in a first semiconductor structure forming the memory cell array, and considering the process of manufacturing the memory cell array or the operation of the semiconductor memory device, peripheral circuits having characteristics at a given level or higher among all the peripheral circuits of the semiconductor memory device may be disposed only in the upper intermediate region. Since all the peripheral circuits of the semiconductor memory device are appropriately distributed and disposed in the upper intermediate region and the lower intermediate region, the chip size of the semiconductor memory device can be optimized.

[0183] Although the present disclosure has been described with reference to embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor memory device having a peripheral upper cell COP structure, the semiconductor memory device comprising: A first semiconductor structure; And A second semiconductor structure disposed on the lower side of the first semiconductor structure, Wherein the first semiconductor structure includes: A memory region and a first region; A memory cell array disposed in the memory region and including vertical channel transistors VCT; and A first peripheral circuit disposed in the first region and including VCT or horizontal channel transistors HCT, and Wherein the second semiconductor structure includes: A second region and a third region; A second peripheral circuit disposed in the second region and including HCT, the second region being located on the lower side of the first region; and A third peripheral circuit disposed in the third region and including HCT, the third region being located on the lower side of the memory region.

2. The semiconductor memory device according to claim 1, wherein, Each of the first peripheral circuits has heat resistance under a first condition associated with the process of manufacturing the semiconductor memory device.

3. The semiconductor memory device according to claim 2, wherein, The memory cell array includes a plurality of first sub-memory cell arrays and a plurality of second sub-memory cell arrays, Wherein the plurality of first sub-memory cell arrays are disposed adjacent to each other at a first row in the memory cell array, Wherein the plurality of second sub-memory cell arrays are disposed adjacent to each other at a second row in the memory cell array, and Wherein the first peripheral circuit is disposed between the plurality of first sub-memory cell arrays and the plurality of second sub-memory cell arrays.

4. The semiconductor memory device according to claim 2, wherein, The first peripheral circuit includes at least one of a mode register, a refresh controller, a row hammer handler, and a power supply circuit.

5. The semiconductor memory device according to claim 4, wherein, The second peripheral circuit includes at least one of a command decoder, a data input / output buffer, an on-die termination circuit, and an equalizer circuit.

6. The semiconductor memory device according to claim 5, wherein, The third peripheral circuit includes at least one of a bit line sense amplifier, a sub-word line driver, a row decoder, and a column decoder.

7. The semiconductor memory device according to claim 6, wherein, The memory region and the first region are sequentially disposed in the first semiconductor structure along a first direction, and Wherein the third region and the second region are sequentially disposed in the second semiconductor structure along the first direction.

8. The semiconductor memory device according to claim 1, wherein, The first semiconductor structure further includes: A repair control circuit disposed in a fourth region in the first semiconductor structure.

9. The semiconductor memory device according to claim 8, wherein, The memory region, the fourth region, and the first region are sequentially disposed in the first semiconductor structure along a first direction or a direction opposite to the first direction.

10. The semiconductor memory device according to claim 8, wherein, The second semiconductor structure further includes: An error correction code ECC circuit disposed in a fifth region, the fifth region being in the second semiconductor structure and on the lower side of the fourth region.

11. The semiconductor memory device according to claim 10, wherein, The third region, the fifth region, and the second region are sequentially disposed in the second semiconductor structure along a first direction or a direction opposite to the first direction.

12. The semiconductor memory device according to claim 10, wherein, The second semiconductor structure further includes: An input / output line driving circuit disposed in a sixth region, the sixth region being in the second semiconductor structure, located on the lower side of the memory region, and between the third region and the fifth region.

13. The semiconductor memory device according to claim 12, wherein, The third region, the sixth region, the fifth region, and the second region are sequentially disposed in the second semiconductor structure along a first direction or a direction opposite to the first direction.

14. The semiconductor memory device according to claim 12, wherein, The second semiconductor structure further includes: An electrostatic protection circuit disposed in a seventh region, the seventh region being in the second semiconductor structure, located on the lower side of the first region, and between the second region and the fifth region.

15. The semiconductor memory device according to claim 14, wherein, The third region, the sixth region, the fifth region, the seventh region, and the second region are sequentially disposed in the second semiconductor structure along a first direction or a direction opposite to the first direction.

16. A semiconductor memory device having a peripheral on-cell COP structure, the semiconductor memory device including: A first semiconductor structure; And A second semiconductor structure disposed on the lower side of the first semiconductor structure, Wherein, the first semiconductor structure includes: A memory region and a first region; A memory cell array including a plurality of first sub-memory cell arrays and a plurality of second sub-memory cell arrays, the plurality of first sub-memory cell arrays and the plurality of second sub-memory cell arrays being disposed in the memory region and implemented by using vertical channel transistors VCTs; and A first peripheral circuit disposed in the first region and implemented by using VCTs or horizontal channel transistors HCTs, and Wherein, the second semiconductor structure includes: A second region and a third region; A second peripheral circuit disposed in the second region, the second region being located on the lower side of the first region; and A third peripheral circuit disposed in the third region, the third region being located on the lower side of the memory region.

17. The semiconductor memory device according to claim 16, wherein, Each of the first peripheral circuits has heat resistance under a first condition associated with the process of manufacturing the semiconductor memory device.

18. The semiconductor memory device according to claim 17, wherein The plurality of first sub-memory cell arrays are disposed adjacent to each other at a first row in the memory region, Wherein, the plurality of second sub-memory cell arrays are disposed adjacent to each other at a second row in the memory region, and Wherein, the first peripheral circuit is disposed between the plurality of first sub-memory cell arrays and the plurality of second sub-memory cell arrays.

19. The semiconductor memory device according to claim 18, wherein, The first peripheral circuit includes a refresh controller.

20. A semiconductor memory device having a peripheral on-cell COP structure, the semiconductor memory device including: A first semiconductor structure; And A second semiconductor structure disposed on the lower side of the first semiconductor structure, Wherein, the first semiconductor structure includes: A memory region and a first region; A memory cell array, the memory cell array being disposed in the memory region and including vertical channel transistors VCTs; and A first peripheral circuit, the first peripheral circuit being disposed in the first region, including VCTs or horizontal channel transistors, and having a first timing tolerance associated with the operation of the semiconductor memory device, wherein the second semiconductor structure includes: A second region; A second peripheral circuit, the second peripheral circuit being disposed in the second region and having a second timing tolerance associated with the operation of the semiconductor memory device, the second region being located on the lower side of the first region, and wherein the first timing tolerance is greater than the second timing tolerance.

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