Semiconductor device

Abstract

There is provided a semiconductor device including: a lower structure including a substrate and a lower transistor on the substrate; an intermediate structure on the lower structure; and an upper structure on the intermediate structure, the upper structure including an upper transistor and a data storage structure, in which the intermediate structure includes: an intermediate interlayer insulating layer, on the lower structure, an intermediate interconnect structure including an intermediate plug and an intermediate interconnect portion on the intermediate plug, in which the intermediate plug penetrates the intermediate interlayer insulating layer, the intermediate stopper layer, and the intermediate stopper layer; a middle stopper including a middle stopper horizontal portion on the middle interlayer insulating layer and a middle stopper extension portion extending from the middle stopper horizontal portion and covering a side surface and an upper surface of the middle interconnection portion, and a middle gap filling insulating layer on an outer side surface of the middle stopper extension portion, the middle stopper extending portion extending from the middle stopper horizontal portion and covering a side surface and an upper surface of the middle interconnection portion. And on an intermediate stopper horizontal portion of the intermediate stopper layer.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0000200, filed on Jan. 2, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The disclosure relates to a semiconductor device. Background Art

[0003] As the demand for high performance, high speed, and / or multi-functionality of semiconductor devices has increased, the integration density of semiconductor devices has increased. In manufacturing semiconductor devices having fine patterns in response to the trend of high integration density of semiconductor devices, it may be required to implement patterns having a fine width or a fine pitch. Summary of the Invention

[0004] Provided is a semiconductor device in which at least one intermediate structure including an intermediate interconnect structure is disposed on a lower structure including an interconnect structure, and each of the upper intermediate structures includes a plurality of insulating layers.

[0005] According to one aspect of the disclosure, a semiconductor device includes: a lower structure including a substrate and a lower transistor on the substrate; an intermediate structure on the lower structure; and an upper structure on the intermediate structure, the upper structure including an upper transistor and a data storage structure, wherein the intermediate structure includes: an intermediate interlayer insulating layer on the lower structure, an intermediate interconnect structure including an intermediate plug and an intermediate interconnect portion on the intermediate plug, wherein the intermediate plug penetrates the intermediate interlayer insulating layer, an intermediate stopper layer including an intermediate stopper horizontal portion and an intermediate stopper extension portion, the intermediate stopper horizontal portion on the intermediate interlayer insulating layer, the intermediate stopper extension portion extending from the intermediate stopper horizontal portion and covering side and upper surfaces of the intermediate interconnect portion, and an intermediate gap-fill insulating layer on an outer surface of the intermediate stopper extension portion and on the intermediate stopper horizontal portion of the intermediate stopper layer.

[0006] According to one aspect of the disclosure, a semiconductor device includes: a lower structure including a lower transistor; an intermediate structure on the lower structure; and an upper structure on the intermediate structure, the upper structure including a data storage structure, wherein the intermediate structure includes: a first interlayer insulating layer, a first intermediate interconnect structure penetrating the first interlayer insulating layer, the first intermediate interconnect structure including a first intermediate plug and a first intermediate interconnect portion on the first intermediate plug, a first intermediate stopper layer including a first horizontal portion on the first interlayer insulating layer and a first extending portion extending from the first horizontal portion, wherein the first extending portion is on a side surface and an upper surface of the first intermediate interconnect structure, a first intermediate gap-fill insulating layer on an upper surface of the first horizontal portion and on an outer side surface of the first extending portion, a second interlayer insulating layer on an upper surface of the first extending portion and on an upper surface of the first intermediate gap-fill insulating layer, and a second intermediate interconnect structure including a second intermediate plug and a second intermediate interconnect portion on the second intermediate plug, wherein the second intermediate plug penetrates the second interlayer insulating layer and the first extending portion and is connected to the first intermediate interconnect portion, wherein the first interlayer insulating layer, the first intermediate stopper layer, and the second interlayer insulating layer include insulating nitride, and wherein the first intermediate gap-fill insulating layer includes insulating oxide.

[0007] According to one aspect of the disclosure, a semiconductor device includes: a lower structure including a substrate; at least one intermediate structure on the lower structure; and an upper structure on the at least one intermediate structure, the upper structure including an upper transistor and a data storage structure on the upper transistor, wherein the lower structure includes: a peripheral transistor on the substrate, the peripheral transistor including a peripheral source / drain and a peripheral gate; a lower interlayer insulating layer on the substrate, wherein the lower interlayer insulating layer at least covers a side surface of the peripheral gate; a lower interconnect structure including a lower plug penetrating the lower interlayer insulating layer and a lower interconnect portion on the lower plug; a lower stopper layer on the lower interlayer insulating layer and on the lower interconnect structure, the lower stopper layer including a lower stopper horizontal portion and a lower stopper extension portion, the lower stopper horizontal portion on the lower interlayer insulating layer, the lower stopper extension portion extending from the lower stopper horizontal portion and covering a side surface and an upper surface of the lower interconnect portion; and a lower gap-fill insulating layer on the lower stopper extension portion, wherein the at least one intermediate structure includes: an intermediate interlayer insulating layer on the lower stopper extension portion and on the lower gap-fill insulating layer; an intermediate interconnect structure including an intermediate plug and an intermediate interconnect portion on the intermediate plug, wherein the intermediate plug penetrates the intermediate interlayer insulating layer and the lower stopper layer; an intermediate stopper layer on the intermediate interlayer insulating layer and on the intermediate interconnect structure, the intermediate stopper layer including an intermediate stopper horizontal portion and an intermediate stopper extension portion, the intermediate stopper horizontal portion on the intermediate interlayer insulating layer, the intermediate stopper extension portion extending from the intermediate stopper horizontal portion and covering a side surface and an upper surface of the intermediate interconnect portion; and an intermediate gap-fill insulating layer on the intermediate stopper horizontal portion, wherein the upper structure includes: an upper interlayer insulating layer on the intermediate stopper extension portion and on the intermediate gap-fill insulating layer; an upper interconnect structure including a contact plug and a bit line on the contact plug, wherein the contact plug penetrates the upper interlayer insulating layer and is connected to the intermediate plug; and an upper stopper layer on the upper interlayer insulating layer and on the upper interconnect structure, and wherein the upper transistor includes: a vertical channel portion on the bit line; a word line facing a side surface of the vertical channel portion; and a dielectric structure between the side surface of the vertical channel portion and the word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features, and advantages of the example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure.

[0010] Figure 2A is a vertical cross-sectional view showing the semiconductor device shown in Figure 1 taken along line I-I'.

[0011] Figure 2B is a view showing Figure 2AAn enlarged view of a part of the semiconductor device shown.

[0012] Figure 3 is a vertical cross-sectional view of the semiconductor device shown taken along line II-II'. Figure 1 An enlarged view of a part of the semiconductor device shown according to an exemplary embodiment of the present disclosure.

[0013] Figure 4A 、 Figure 4B and Figure 4C is a vertical cross-sectional view of a part of the semiconductor device according to an exemplary embodiment of the present disclosure.

[0014] Figure 5 is a vertical cross-sectional view of the semiconductor device shown according to an exemplary embodiment of the present disclosure. Figure 1 An enlarged view of a part of the semiconductor device shown according to an exemplary embodiment of the present disclosure.

[0015] Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A 、 Figure 16B 、 Figure 17A 、 Figure 17B 、 Figure 18A 、 Figure 18B 、 Figure 19A 、 Figure 19B 、 Figure 20A 、 Figure 20B 、 Figure 21A and Figure 21B is a vertical cross-sectional view of a process of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure.

[0016] Figure 22A 、 Figure 22B 、 Figure 23A 、 Figure 23B 、 Figure 24A and Figure 24B is a vertical cross-sectional view of a process of a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. Detailed Description

[0017] Hereinafter, embodiments in exemplary embodiments will be described with reference to the accompanying drawings as follows.

[0018] In the following description, throughout the specification, the same reference numerals denote the same elements. As used herein, a plurality of "units", "modules", "components", and "blocks" may be implemented as a single component, or a single "unit", "module", "component", and "block" may include a plurality of components.

[0019] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly or indirectly connected to the other element.

[0020] In addition, when a component "comprises" or "includes" an element, unless there is a specific description to the contrary, the component may also include other elements without excluding other elements.

[0021] Throughout the specification, when a member is "on" another member, this includes not only when the member is in contact with the other member, but also when there are additional members between the two members.

[0022] Here, the expressions "at least one of a, b, or c" and "at least one of a, b, and c" indicate "only a", "only b", "only c", "both a and b", "both a and c", "both b and c", and "all of a, b, and c".

[0023] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, the disclosure should not be limited by these terms. These terms are only used to distinguish one element from another.

[0024] As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0025] Regarding any method or process described herein, for ease of description, identification codes may be used, but are not intended to indicate the order of each step or operation. Unless the context clearly indicates otherwise, each step or operation may be implemented in an order different from the order shown. Unless the context of the disclosure clearly indicates otherwise, one or more steps or operations may be omitted.

[0026] Figure 1 is a plan view showing a semiconductor device according to an exemplary embodiment. Figure 2A is a vertical cross-sectional view showing the semiconductor device taken along line I-I'. Figure 1 as shown in. Figure 2B is a view showing Figure 2A an enlarged view of a part of the semiconductor device shown in. Figure 3 is a view showing the semiconductor device taken along line II-II'.Figure 1 Vertical cross-sectional view of the semiconductor device shown in

[0027] Referring to Figures 1 to 3 , the semiconductor device 1 according to an exemplary embodiment may include a lower structure LS, an intermediate structure MS, and an upper structure US.

[0028] The lower structure LS may include a substrate 3 and peripheral transistors TR (or "lower transistors") disposed on the substrate 3. The peripheral transistors TR may include word line drivers, sense amplifiers, row decoders, column decoders, and control circuits. The substrate 3 may include a cell array region MCA and a connection region EA.

[0029] The substrate 3 may include a semiconductor material (such as a Group-IV semiconductor, a Group-III-V compound semiconductor, or a Group-II-VI compound semiconductor). For example, the Group-IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate 3 may be configured as a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0030] The peripheral transistors TR may be disposed in the cell array region MCA and the connection region EA. The peripheral transistors TR may include a gate structure 7 and peripheral source / drain regions 9, the gate structure 7 being disposed on a peripheral active region 5a defined by a device isolation region 5b in the substrate 3, and the peripheral source / drain regions 9 being disposed in the peripheral active region 5a on both sides of the gate structure 7.

[0031] The gate structure 7 may include a peripheral gate electrode 7b and a peripheral gate dielectric layer 7a between the peripheral gate electrode 7b and the peripheral active region 5a. The peripheral gate electrode 7b may include at least two conductive layers (e.g., a first conductive layer 7b1 and a second conductive layer 7b2 on the first conductive layer 7b1). The gate structure 7 may further include an insulating liner 7c disposed on the substrate 3 and covering side surfaces of the peripheral gate dielectric layer 7a and the peripheral gate electrode 7b.

[0032] The lower structure LS may further include a lower interconnect structure 11 and a lower insulating structure 12. The lower interconnect structure 11 may include a peripheral interconnect portion 13 (also referred to herein as a lower interconnect portion 13) and peripheral plugs 15 (also referred to herein as lower plugs 15), and the lower insulating structure 12 may include a lower interlayer insulating layer 14, a lower stopper layer (or referred to as a stop layer) 16, and a lower gap-fill insulating layer 18.

[0033] The peripheral plug 15 can be connected to the peripheral source / drain region 9 and can extend vertically, and the peripheral interconnect 13 can be disposed on the peripheral plug 15. The peripheral interconnect 13 can be electrically connected to the peripheral transistor TR through the peripheral plug 15. The peripheral interconnect 13 and the peripheral plug 15 can be configured as a metal layer including a metal material (such as W or Mo).

[0034] The interlayer insulating layer 14 can surround the side surfaces of the peripheral gate electrode 7b and the peripheral plug 15. The lower stopper layer 16 can include a stopper horizontal portion (or referred to as a stop horizontal portion) and a stopper extension portion (or referred to as a stop extension portion). The stopper horizontal portion is disposed on the interlayer insulating layer 14, and the stopper extension portion extends to cover the side surface and the upper surface of the peripheral interconnect 13. The height of the upper surface of the stopper extension portion can be higher than the height of the upper surface of the stopper horizontal portion. The lower gap-fill insulating layer 18 can be disposed on the lower stopper layer 16. For example, the lower gap-fill insulating layer 18 can be disposed on the stopper horizontal portion of the lower stopper layer 16, and the side surface of the lower gap-fill insulating layer 18 can be disposed on the side surface of the stopper extension portion. The upper surface of the stopper extension portion and the upper surface of the lower gap-fill insulating layer 18 can be coplanar with each other. Alternatively, according to an exemplary embodiment, the upper surface of the stopper extension portion can be at a height higher than the height of the upper surface of the lower gap-fill insulating layer 18 (see Figure 4A )

[0035] The interlayer insulating layer 14 and the lower gap-fill insulating layer 18 can include a silicon oxide material, and the lower stopper layer 16 can include a silicon nitride material. For example, the silicon oxide material can include silicon oxide (SiO2), and the silicon nitride material can include silicon nitride (SiN), silicon carbonitride (SiCN), or silicon boron nitride (SiBN), but the disclosure is not limited thereto.

[0036] The lower interconnect structure 11 can further include a barrier layer 17 that covers the lower surface of the lower interconnect 13 and the side surface and the lower surface of the lower plug 15. The portion of the barrier layer 17 that covers the lower surface of the lower interconnect 13 can be in contact with the lower stopper layer 16. The portion of the barrier layer 17 that covers the side surface of the lower plug 15 can be in contact with the interlayer insulating layer 14. The barrier layer 17 can include at least one of TiN, TaN, WN, TiSiN, TaSiN, and RuTiN.

[0037] The intermediate structure MS can be disposed on the lower structure LS. The intermediate structure MS can include a first intermediate structure MS1 and a second intermediate structure MS2.

[0038] The first intermediate structure MS1 may include a first intermediate interconnect structure 21 and a first intermediate insulating structure 22. The first intermediate interconnect structure 21 may include a first intermediate interconnect portion 23 and a first intermediate plug 25, and the first intermediate insulating structure 22 may include a first interlayer insulating layer 24, a first intermediate stop layer 26, and a first intermediate gap-fill insulating layer 28.

[0039] The first intermediate plug 25 may penetrate the first interlayer insulating layer 24, and the lower stop layer 16 may contact an upper region of the lower interconnect portion 13. The first intermediate interconnect portion 23 may be disposed on the first intermediate plug 25. The first intermediate interconnect portion 23 may be electrically connected to the peripheral transistor TR through the first intermediate plug 25 and the lower interconnect structure 11. The first intermediate interconnect portion 23 and the first intermediate plug 25 may be configured as a metal layer including a metal material (such as, W or Mo).

[0040] The first interlayer insulating layer 24 may be disposed on the lower stop layer 16 and the lower gap-fill insulating layer 18. For example, the first interlayer insulating layer 24 may be disposed to cover an upper surface of a lower stop extension of the lower stop layer 16 and an upper surface of the lower gap-fill insulating layer 18. The first intermediate stop layer 26 may be disposed on the first interlayer insulating layer 24 and the first intermediate interconnect portion 23. For example, the first intermediate stop layer 26 may include a first intermediate stop horizontal portion and a first intermediate stop extension. The first intermediate stop horizontal portion is disposed on the first interlayer insulating layer 24, and the first intermediate stop extension covers a side surface and an upper surface of the first intermediate interconnect portion 23. The first intermediate gap-fill insulating layer 28 may be disposed on the first intermediate stop layer 26. For example, the first intermediate gap-fill insulating layer 28 may be disposed on the first intermediate stop horizontal portion of the first intermediate stop layer 26, and a side surface of the first intermediate gap-fill insulating layer 28 may contact a side surface of the first intermediate stop extension. An upper surface of the first intermediate stop extension and an upper surface of the first intermediate gap-fill insulating layer 28 may be coplanar. Optionally, according to an exemplary embodiment, an upper surface of the first intermediate stop extension may be disposed at a height higher than a height of an upper surface of the first intermediate gap-fill insulating layer 28 (see Figure 4A )

[0041] The first interlayer insulating layer 24 and the first intermediate stop layer 26 may include a material the same as or similar to that of the lower stop layer 16. For example, the first interlayer insulating layer 24 and the first intermediate stop layer 26 may include an insulating nitride (such as, silicon nitride) material. The first intermediate gap-fill insulating layer 28 may include a material the same as or similar to that of the lower gap-fill insulating layer 18. For example, the first intermediate gap-fill insulating layer 28 may include an insulating oxide (such as, silicon oxide) material.

[0042] The first intermediate interconnect structure 21 may further include a barrier layer 27 that covers the lower surface of the first intermediate interconnect portion 23 and the side and lower surfaces of the first intermediate plug 25. The portion of the barrier layer 27 that covers the lower surface of the first intermediate interconnect portion 23 may contact the first intermediate stopper layer 26. The portion of the barrier layer 27 that covers the side surface of the first intermediate plug 25 may contact the intermediate gap-fill insulating layer 28 and the lower stopper layer 16. The barrier layer 27 may include a material that is the same as or similar to the material of the barrier layer 17.

[0043] The second intermediate structure MS2 may be disposed on the first intermediate structure MS1. The second intermediate structure MS2 may include a second intermediate interconnect structure 31 and a second intermediate insulating structure 32. The second intermediate interconnect structure 31 may include a second intermediate interconnect portion 33 and a second intermediate plug 35, and the second intermediate insulating structure 32 may include a second interlayer insulating layer 34, a second intermediate stopper layer 36, and a second intermediate gap-fill insulating layer 38.

[0044] The second intermediate plug 35 may penetrate the second interlayer insulating layer 34 and the first intermediate stopper layer 26 and may contact an upper region of the first intermediate interconnect portion 23. The second intermediate interconnect portion 33 may be disposed on the second intermediate plug 35. The second intermediate interconnect portion 33 may be electrically connected to the peripheral transistor TR through the second intermediate plug 35, the first intermediate interconnect structure 21, and the lower interconnect structure 11. The second intermediate interconnect portion 33 and the second intermediate plug 35 may be configured as metal layers including a metal material such as W or Mo.

[0045] The second intermediate interlayer insulating layer 34 may be disposed on the first intermediate stop layer 26 and the first intermediate gap-fill insulating layer 28. For example, the second intermediate interlayer insulating layer 34 may be disposed to cover the upper surface of the first intermediate stop extension of the first intermediate stop layer 26 and the upper surface of the first intermediate gap-fill insulating layer 28. The second intermediate stop layer 36 may be disposed on the second intermediate interlayer insulating layer 34 and the second intermediate interconnect portion 33. For example, the second intermediate stop layer 36 may include a second intermediate stop horizontal portion and a second intermediate stop extension. The second intermediate stop horizontal portion is disposed on the second intermediate interlayer insulating layer 34, and the second intermediate stop extension covers the side surface and the upper surface of the second intermediate interconnect portion 33. The second intermediate gap-fill insulating layer 38 may be disposed on the second intermediate stop layer 36. For example, the second intermediate gap-fill insulating layer 38 may be disposed on the second intermediate stop horizontal portion of the second intermediate stop layer 36, and the side surface of the second intermediate gap-fill insulating layer 38 may be in contact with the side surface of the second intermediate stop extension. The upper surface of the second intermediate stop extension and the upper surface of the second intermediate gap-fill insulating layer 38 may be coplanar with each other. Optionally, according to an exemplary embodiment, the upper surface of the second intermediate stop extension may be disposed at a height higher than the height of the upper surface of the second intermediate gap-fill insulating layer 38 (see Figure 4A ).

[0046] The second intermediate interlayer insulating layer 34 and the second intermediate stop layer 36 may include the same or similar materials as the first intermediate interlayer insulating layer 24 and the first intermediate stop layer 26. For example, the second intermediate interlayer insulating layer 34 and the second intermediate stop layer 36 may include an insulating nitride (e.g., silicon nitride material). The second intermediate gap-fill insulating layer 38 may include the same or similar materials as the first intermediate gap-fill insulating layer 28. For example, the second intermediate gap-fill insulating layer 38 may include an insulating oxide (e.g., silicon oxide) material.

[0047] The second intermediate interconnect structure 31 may further include a barrier layer 37 that covers the lower surface of the second intermediate interconnect portion 33 and the side surface and the lower surface of the second intermediate plug 35. The portion of the barrier layer 37 that covers the lower surface of the second intermediate interconnect portion 33 may be in contact with the second intermediate stop layer 36. The portion of the barrier layer 37 that covers the side surface of the second intermediate plug 35 may be in contact with the intermediate gap-fill insulating layer 28 and the first intermediate stop layer 26. The barrier layer 37 may include the same or similar materials as the barrier layer 27.

[0048] The thicknesses of the lower interconnect portion 13, the first intermediate interconnect portion 23, and the second intermediate interconnect portion 33 may be different. For example, the thickness of the second intermediate interconnect portion 33 may be larger than the thicknesses of the lower interconnect portion 13 and the first intermediate interconnect portion 23. Accordingly, the level of the resistance of the interconnect portions 13, 23, and 33 (e.g., the lower interconnect portion 13, the first intermediate interconnect portion 23, and the second intermediate interconnect portion 33) or the level of the current flowing through the interconnect portions 13, 23, and 33 can be adjusted. However, the thicknesses between the interconnect portions 13, 23, 33 and the bit line 53 are not limited to Figure 2A , Figure 2B and Figure 3 the example embodiments shown in

[0049] and may be varied. In other words, by disposing at least one intermediate structure including an intermediate interconnect structure on a lower structure including an interconnect structure, various interconnect structures can be implemented, thereby increasing the design flexibility.

[0050] In addition, since each of the intermediate structures includes an insulating structure including a plurality of insulating layers, the level of warpage occurring in other processes in Figures 6A to 21B can be alleviated.

[0051] The upper structure US may be disposed on the intermediate structure MS. The upper structure US may include an upper interconnect structure 51 and an upper insulating structure 52. The upper interconnect structure 51 may include a bit line 53 and a contact plug 55, and the upper insulating structure 52 may include an upper interlayer insulating layer 54 and an upper stopper layer 56. The upper interconnect structure 51 may further include a barrier layer 57 that covers the lower surface of the bit line 53 and the side and lower surfaces of the contact plug 55. The barrier layer 57 may include a material the same as or similar to the materials of the barrier layers 27 and 37.

[0052] The contact plug 55 may penetrate the upper interlayer insulating layer 54 and the second intermediate stopper layer 36 and may contact an upper region of the second intermediate interconnect portion 33. The bit line 53 may be disposed on the contact plug 55. The bit line 53 may extend in a first horizontal direction X and may be spaced apart from each other in a second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other. The bit line 53 may be electrically connected to the peripheral transistor TR through the contact plug 55, the first intermediate interconnect structure 21, the second intermediate interconnect structure 31, and the lower interconnect structure 11. The bit line 53 may include doped polysilicon, metal, conductive metal nitride, metal semiconductor compound, metal compound, conductive metal oxide, graphene, carbon nanotube, or a combination thereof.

[0053] The semiconductor device 1 in the cell array region MCA may further include a shielding pattern that extends in the first horizontal direction X and is spaced apart from each other in the second horizontal direction Y. The shielding pattern may be alternately disposed with the bit line 53 in the second horizontal direction Y. The shielding pattern may reduce the capacitance between the bit lines 53.

[0054] The upper interlayer insulating layer 54 may be disposed on the second intermediate stopper layer 36 and the second intermediate gap-fill insulating layer 38. For example, the upper interlayer insulating layer 54 may be disposed to cover the upper surface of the second intermediate stopper extension of the second intermediate stopper layer 36 and the upper surface of the second intermediate gap-fill insulating layer 38. The upper stopper layer 56 may be disposed on the upper interlayer insulating layer 54 and the bit line 53. For example, the upper stopper layer 56 may include an upper stopper horizontal portion and an upper stopper extension portion, the upper stopper horizontal portion being disposed on the upper interlayer insulating layer 54, and the upper stopper extension portion covering the upper surface and the side surface of the bit line 53.

[0055] The upper structure US may further include a channel structure 73, a word line 79, an upper gap-fill insulating layer 84, an upper interconnect 81p, and an upper plug 83p disposed on the bit line 53.

[0056] The channel structure 73 may be disposed on the bit line 53. The channel structure 73 may include a horizontal portion 73L, a first vertical channel portion 73S1, and a second vertical channel portion 73S2, the horizontal portion 73L being in contact with and electrically connected to the bit line 53, and the first vertical channel portion 73S1 and the second vertical channel portion 73S2 extending in the vertical direction Z on both sides in the horizontal direction of the horizontal portion 73L. The vertical direction Z may be perpendicular to the upper surface of the substrate 3.

[0057] The channel structure 73 may be formed of a semiconductor material such as silicon. The channel structure 73 may be formed of single-crystalline silicon or polycrystalline silicon. However, the channel structure 73 is not limited to a semiconductor material such as silicon, and may be formed of another semiconductor material used as a channel region of a transistor. For example, the channel structure 73 may include an oxide semiconductor layer or a two-dimensional material layer used as a channel region of a transistor. Here, the transistor may be referred to as an upper transistor disposed at a height higher than the height of the lower transistor TR.

[0058] The oxide semiconductor layer may be indium gallium zinc oxide (IGZO). However, the disclosure is not limited thereto. For example, the oxide semiconductor layer may include at least one of indium tungsten oxide (IWO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAGO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), ZnO, indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), indium zinc oxide (InZnO), indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and indium gallium silicon oxide (InGaIO).

[0059] The two-dimensional material layer may include at least one of a transition metal dichalcogenide material layer (TMD material layer) that may have semiconductor characteristics, a black phosphorous material layer, and a hexagonal boron nitride material layer (hBN material layer). For example, the two-dimensional material layer may include at least one of BiOSe, CrI, WSe2, MoS2, TaS, WS, SnSe, ReS, β-SnTe, MnO, AsS, P(black), InSe, h-BN, GaSe, GaN, SrTiO, MXene, and Janus 2D materials that may form two-dimensional materials.

[0060] Each of the word lines 79 may extend in the second horizontal direction Y. A pair of word lines 79a and 79b among the word lines 79 may be vertically stacked with the horizontal portion 73L of the channel structure 73, and may be disposed between the first vertical channel portion 73S1 and the second vertical channel portion 73S2 of the channel structure 73. The pair of word lines 79a and 79b may include a first word line 79a facing the first vertical channel portion 73S1 and a second word line 79b facing the second vertical channel portion 73S2.

[0061] The upper structure US may further include a dielectric structure 76 between the word line 79 and the channel structure 73. The dielectric structure 76 may include a first dielectric structure 76a and a second dielectric structure 76b. The first dielectric structure 76a is disposed between the first word line 79a and the first vertical channel portion 73S1 and between the first word line 79a and the horizontal portion 73L, and the second dielectric structure 76b is disposed between the second word line 79b and the second vertical channel portion 73S2 and between the second word line 79b and the horizontal portion 73L.

[0062] In one example, each of the dielectric structures 76 may be configured as a tunneling dielectric layer that does not include a data storage layer. For example, each of the dielectric structures 76 may include at least one of silicon oxide and a high-κ dielectric. The high-κ dielectric may include a metal oxide or a metal oxynitride. For example, the high-κ dielectric may be formed of HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but the disclosure is not limited thereto. Each of the dielectric structures 76 may include a single layer or multiple layers formed of the materials mentioned above.

[0063] In another example, each of the dielectric structures 76 may include a data storage layer and a dielectric layer. For example, each of the dielectric structures 76 may have polarization characteristics that depend on an electric field and may include a ferroelectric layer that may have a remanent polarization through dipoles even in the absence of an external electric field. Data may be written using the polarization state in the ferroelectric layer. Thus, each of the dielectric structures 76 may include a ferroelectric layer that may be referred to as a data storage layer. The ferroelectric layer that may be configured as a data storage layer may include an Hf-based compound, a Zr-based compound, and / or an Hf-Zr-based compound. For example, the Hf-based compound may include an HfO-based ferroelectric material, the Zr-based compound may include a ZrO-based ferroelectric material, and the Hf-Zr-based compound may include a hafnium zirconium oxide (HZO) ferroelectric material. The ferroelectric layer that may be configured as a data storage layer may include a ferroelectric material doped with an impurity (such as at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr). For example, the ferroelectric layer that may be used as a data storage layer may be a material formed of at least one of HfO2, ZrO2, and HZrO "doped with at least one of C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr".

[0064] In the dielectric structure 76, the data storage layer is not limited to the materials mentioned above and may include materials that can store data.

[0065] The upper structure US may further include bonding pads 81 that are respectively in contact with the first vertical channel portion 73S1 and the second vertical channel portion 73S2 on the channel structure 73 and are electrically connected to the first vertical channel portion 73S1 and the second vertical channel portion 73S2. The bonding pads 81 may be formed of a conductive material.

[0066] The upper gap-fill insulating layer 84 may be disposed on the bit line 53 and the upper stop layer 56. The upper gap-fill insulating layer 84 may cover the side surfaces of the upper interconnect 81p and the upper plug 83p in the connection region EA. The upper gap-fill insulating layer 84 may cover the side surfaces of the structures including the channel structure 73, the word line 79, and the bonding pad 81 in the cell array region MCA.

[0067] The upper interconnect 81p may be disposed at the same height as the bonding pad 81 in the connection region EA. For example, the upper surface of the upper interconnect 81p may be disposed at the same height as the upper surface of the bonding pad 81. The upper plug 83p may extend in the vertical direction Z, and one of the upper interconnects 81p may be connected to the bit line 53. The upper interconnect 81p may include the same material as the bonding pad 81. The upper gap-fill insulating layer 84 may surround the side surfaces of the upper interconnect 81p and the upper plug 83p in the connection region EA. The upper gap-fill insulating layer 84 may include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or a combination thereof. For example, the upper gap-fill insulating layer 84 may include silicon oxide.

[0068] The upper structure US may further include a data storage structure 87 disposed on the upper gap-fill insulating layer 84 and the bonding pad 81. The data storage structure 87 may include a first electrode 88a electrically connected to and in contact with the bonding pad 81, a second electrode 88c on the first electrode 88a, and a dielectric layer 88b between the first electrode 88a and the second electrode 88c.

[0069] In one example, the data storage structure 87 may be configured to store data in a capacitor in a DRAM. For example, the dielectric layer 88b of the data storage structure 87 may be configured as the capacitor dielectric layer of the DRAM, and the dielectric layer 88b may include a high-κ dielectric, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0070] In another example, the data storage structure 87 may be configured to store data in a memory other than a DRAM. For example, the data storage structure 87 may be configured as a capacitor of a ferroelectric memory (FeRAM). For example, the dielectric layer 88b may be configured as a ferroelectric layer in which data can be written using a polarization state. In another example, the dielectric layer 88b may include a lower dielectric layer and a ferroelectric layer on the lower dielectric layer. Here, the lower dielectric layer may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a high-κ dielectric (high-k dielectric).

[0071] In one exemplary embodiment, when the dielectric structure 76 includes a data storage layer, the data storage structure 87 may not be provided.

[0072] The upper structure US may further include an upper insulating structure 90. The upper insulating structure 90 may cover the data storage structure 87 in the cell array region MCA and the upper interconnect 81p in the connection region EA. The upper insulating structure 90 may include silicon oxide, silicon nitride, silicon oxynitride, a low-κ dielectric material, or a combination thereof. For example, the upper insulating structure 90 may include silicon oxide.

[0073] The upper structure US may further include a cell contact plug CCP that extends in the vertical direction Z from the cell array region MCA, penetrates the upper insulating structure 90, and contacts the data storage structure 87. For example, the cell contact plug CCP may contact the second electrode 88c.

[0074] The upper structure US may further include a peripheral contact plug PCP that extends in the vertical direction Z from the connection region EA, penetrates the upper insulating structure 90, and is connected to at least a part of the upper interconnect 81p. For example, the peripheral contact plug PCP may contact an upper region of at least a part of the upper interconnect 81p.

[0075] In one exemplary embodiment, the cell contact plug CCP and the peripheral contact plug PCP may be formed simultaneously and may include the same material. For example, each of the cell contact plug CCP and the peripheral contact plug PCP may include a metal layer 93 and a barrier layer 96 that covers the lower surface and the side surfaces of the metal layer 93. The metal layer 93 may include a conductive material such as tungsten, and the barrier layer 96 may include a conductive material such as TiN. The upper surfaces of the cell contact plug CCP and the peripheral contact plug PCP may be coplanar with the upper surface of the upper insulating structure 90. The cell contact plug CCP and the peripheral contact plug PCP may have a tapered shape with a horizontally decreasing width downward.

[0076] A back-end-of-line (BEOL) interconnect structure may be disposed on the upper insulating structure 90, and at least a part of the cell contact plug CCP and the peripheral contact plug PCP may be electrically connected to each other through the BEOL interconnect structure. Figure 2A The arrangement structure and the number of the intermediate interconnects 21 and 31 (e.g., the first intermediate interconnect 21 and the second intermediate interconnect 31) and the peripheral contact plug PCP shown are merely examples, and the disclosure is not limited thereto. In some exemplary embodiments, one or three or more intermediate interconnects may be provided.

[0077] Figures 4A to 4C is an enlarged view showing a part of a semiconductor device according to an exemplary embodiment.

[0078] Referring to Figure 4A , except that the upper surfaces of at least a part of the lower interconnect portion 13, the first intermediate interconnect portion 23, and the second intermediate interconnect portion 33 may have a groove structure, the semiconductor device 1a may be constructed in the same or similar manner as the example described with reference to Figures 1 to 3 is described.

[0079] Referring to Figure 4A, the upper surface of the lower interconnect portion 13 may have a groove portion 13g. For example, the groove portion 13g may be deeper from both ends of the upper surface toward the center of the upper surface. Therefore, the thickness of the lower interconnect portion 13 may not be uniform. For example, the thickness of the lower interconnect portion 13 may decrease from both ends of the lower interconnect portion 13 toward the center of the lower interconnect portion 13. In one embodiment, the lower interconnect portion 13 may be recessed downward.

[0080] The upper surfaces of the first intermediate interconnect portion 23 and the second intermediate interconnect portion 33 may also have groove portions 23g and 33g respectively (i.e., may be recessed downward). When the vertical thickness of the interconnect portion is formed to be relatively thick, the groove portion may be formed to have a relatively reduced depth. For example, when the thickness of the second intermediate interconnect portion 33 is larger than the thickness of the first intermediate interconnect portion 23, the groove portion 33g of the second intermediate interconnect portion 33 is formed to have a length relatively reduced compared to the length of the groove portion 23g of the first intermediate interconnect portion 23.

[0081] The upper surface of the bit line 53 of the upper structure US may have a flat surface.

[0082] Referring to Figure 4A , each of the lower plug 15, the first intermediate plug 25, the second intermediate plug 35, and the contact plug 55 may have an inclined side surface such that the width of each lower region of the plurality of plugs 15, 25, 35, and the contact plug 55 may be smaller than the width of the upper region.

[0083] In addition, each of the lower interconnect portion 13, the first intermediate interconnect portion 23, and the second intermediate interconnect portion 33 may have an inclined side surface. For example, the lower interconnect portion 13 may have an inclined side surface such that the width of the lower region may be larger than the width of the upper region, and alternatively, the lower interconnect portion 13 may have an inclined side surface such that the width of the upper region may be smaller than the width of the lower region. Since the side surfaces of each of the first intermediate interconnect portion 23 and the second intermediate interconnect portion 33 may also be constructed to be the same as or similar to the shape of the side surface of the lower interconnect portion 13, a detailed description of the side surfaces of each of the first intermediate interconnect portion 23 and the second intermediate interconnect portion 33 will not be provided.

[0084] Referring to Figure 4A , the upper surface of the extension portion of each of the lower stopper layer 16, the first intermediate stopper layer 26, and the second intermediate stopper layer 36 may be provided at a height higher than the height of the upper surface of each of the lower gap-fill insulating layer 18, the first intermediate gap-fill insulating layer 28, and the second intermediate gap-fill insulating layer 38. For example, the upper surface of the extension portion of the lower stopper layer 16 may not have a flat surface and may have a curved shape in the vertical direction (Z direction). Therefore, the upper surface of the extension portion of the lower stopper layer 16 may not be coplanar with the upper surface of the lower gap-fill insulating layer 18. Therefore, the upper region of the extension portion of the lower stopper layer 16 may be inserted into the lower region of the first interlayer insulating layer 24.

[0085] Refer to Figure 4A , the lower surface of each of the first intermediate stopper layer 26, the second intermediate stopper layer 36, and the upper stopper layer 56 may be provided at a height lower than the height of the lower surfaces of the first intermediate interconnect 23, the second intermediate interconnect 33, and the bit line 53.

[0086] Refer to Figure 4A , the lower interconnect structure 11 may further include a metal-semiconductor compound layer 19 under the lower region of the barrier layer 17. The metal-semiconductor compound layer 19 may include at least one of metal silicides (such as, WSi, TiSi, TaSi, NiSi, and CoSi).

[0087] Refer to Figure 4B , the semiconductor device 1b may be constructed the same as or similarly to a configuration in which the film quality of one of the intermediate interconnects 23 and 33 may be different from the film quality of the other.

[0088] Refer to Figure 4B , one of the first intermediate interconnect 23 and the second intermediate interconnect 33 may have a denser film quality than the film quality of the other interconnect. For example, the film quality of the second intermediate interconnect 33 may be denser than the film quality of the first intermediate interconnect 23. In this case, the resistance of the second intermediate interconnect 33 may be smaller than the resistance of the first intermediate interconnect 23.

[0089] Refer to Figure 4C , except for a configuration in which the lower stopper layer 16 may contact at least a part of the lower transistor TR, the semiconductor device 1c may be constructed the same as or similarly to the example described with reference to Figures 1 to 4B .

[0090] Refer to Figure 4C , the lower surface of the lower stopper layer 16 may contact the upper region of the lower transistor TR. For example, the lower stopper layer 16 may be provided to contact the second conductive layer 7b2 and the insulating layer 7c of the lower transistor TR.

[0091] Figure 5 is a vertical cross-sectional view of a semiconductor device shown in Figure 1 according to an exemplary embodiment.

[0092] Refer to Figure 5 , except for a configuration in which the peripheral contact plug PCP may directly contact the bit line 53 in the connection region EA, the semiconductor device 2 may be constructed the same as or similarly to the example described with reference to Figures 1 to 4C .

[0093] Refer to Figure 5, the peripheral contact plug PCP can penetrate the upper insulating structure 90, the upper gap-fill insulating layer 84, and the upper stopper layer 56, and can be in direct contact with the bit line 53. In other words, the peripheral contact plug PCP can be electrically connected to the peripheral transistor TR without passing through the upper interconnect 81p and the upper plug 83p.

[0094] Figures 6A to 21B is a vertical cross-sectional view showing a process of manufacturing a semiconductor device in sequence according to an exemplary embodiment.

[0095] Figures 6A to 8B is a vertical cross-sectional view showing a process of forming the lower interconnect structure 11 in sequence.

[0096] Referring to Figure 6A and Figure 6B , an interlayer insulating layer 14 covering the peripheral transistor TR can be formed on the substrate 3. The interlayer insulating layer 14 can include a silicon oxide material. In the exemplary embodiment, the interlayer insulating layer 14 can include silicon oxide (SiO2).

[0097] Thereafter, a plurality of holes H1 penetrating the interlayer insulating layer 14 and exposing the upper surface of the source / drain region 9 can be formed.

[0098] Referring to Figure 7A and Figure 7B , a preliminary lower interconnect structure 11' can be formed on the interlayer insulating layer 14.

[0099] Forming the preliminary lower interconnect structure 11' can include forming a barrier layer 17 and depositing a conductive material on the barrier layer 17. The conductive material can be deposited by chemical vapor deposition (CVD).

[0100] For example, a barrier layer 17 conformally covering the surfaces of the plurality of holes H1 and the upper surface of the interlayer insulating layer 14 can be formed. Thereafter, a preliminary lower interconnect portion 13' and a preliminary lower plug 15' can be formed by depositing a conductive material on the barrier layer 17. The preliminary lower plug 15' can fill the plurality of holes H1.

[0101] Referring to Figure 8A and Figure 8B , the lower interconnect structure 11 can be formed.

[0102] Forming the lower interconnect structure 11 can include patterning the preliminary lower interconnect structure 11'. Patterning can include forming a mask pattern on the preliminary lower interconnect structure 11' and forming a recessed region R1 exposing the upper surface of the interlayer insulating layer 14 through an etching process. The lower surface of the recessed region R1 can be formed at a height lower than the height of the lower surface of the barrier layer 17. Thus, the lower interconnect portion 13 and the lower plug 15 can be formed.

[0103] According to an exemplary embodiment, the peripheral transistor TR can be exposed through an etching process (seeFigure 5 The upper region of ( ). Thus, at least a part of the insulating layer 7c of the peripheral transistor TR and the second conductive layer 7b2 can be exposed.

[0104] Figures 9A to 15B is a process diagram showing the first cycle of the process of forming the first intermediate interconnect structure 21 after the process in Figure 8A and Figure 8B .

[0105] Referring to Figure 9A and Figure 9B , the lower stop layer 16 can be formed.

[0106] The lower stop layer 16 can be formed to have a horizontal portion and an extension portion. The horizontal portion covers the surface of the lower interlayer insulating layer 14 exposed by the recessed region R1, and the extension portion covers the side surface of the barrier layer 17 and the side surface and the upper surface of the lower interconnect portion 13. The lower stop layer 16 can be used as an etch stop film. The lower stop layer 16 can include a silicon nitride material. In an exemplary embodiment, the lower stop layer 16 can include silicon nitride (SiN).

[0107] According to an exemplary embodiment, the lower stop layer 16 can be formed to contact the upper region of the peripheral transistor TR (see Figure 5 ). For example, the lower stop layer 16 can be formed to contact the insulating layer 7c and the second conductive layer 7b2 of the peripheral transistor TR.

[0108] Referring to Figure 10A and Figure 10B , a preliminary lower gap-fill insulating layer 18' can be formed on the lower stop layer 16.

[0109] The preliminary lower gap-fill insulating layer 18' can include a silicon oxide material. In an exemplary embodiment, the preliminary lower gap-fill insulating layer 18' can include silicon oxide (SiO2).

[0110] Referring to Figure 11A and Figure 11B , the lower gap-fill insulating layer 18 can be formed.

[0111] The preliminary lower gap-fill insulating layer 18' according to Figure 10A and Figure 10B can be formed into the lower gap-fill insulating layer 18 through a planarization process such as chemical mechanical polishing (CMP). Thus, the upper surface of the extension portion of the lower stop layer 16 can be exposed, and the lower gap-fill insulating layer 18 having an upper surface at the same height as the upper surface of the lower stop layer 16 can be formed.

[0112] Referring to Figure 12A and Figure 12B, an insulating layer 18 and a lower stopper layer 16 can be formed on the lower gap filling layer, and a first interlayer insulating layer 24 can be formed thereon.

[0113] The first interlayer insulating layer 24 can be deposited on the upper surface of the lower gap filling insulating layer 18 and the upper surface of the extension of the lower stopper layer 16. The first interlayer insulating layer 24 can include a silicon nitride material. In an exemplary embodiment, the first interlayer insulating layer 24 can include a silicon nitride material different from that of the lower stopper layer 16, and even when the first interlayer insulating layer 24 includes the same material, the boundary between the first interlayer insulating layer 24 and the lower stopper layer 16 can be distinguished by differences in physical properties.

[0114] Referring to Figure 13A and Figure 13B , a plurality of holes H2 can be formed to penetrate the first interlayer insulating layer 24 and the lower stopper layer 16 and expose the upper surface of the lower interconnect portion 13.

[0115] Referring to Figure 14A and Figure 14B , a first preliminary intermediate interconnect structure 21' can be formed on the first interlayer insulating layer 24.

[0116] Forming the first preliminary intermediate interconnect structure 21' can be the same as or similar to that of the preliminary lower interconnect structure 11' described with reference to Figure 7A and Figure 7B .

[0117] For example, forming the first preliminary intermediate interconnect structure 21' can include forming a barrier layer 27 and depositing a conductive material on the barrier layer 27. The conductive material can be deposited by chemical vapor deposition (CVD).

[0118] Specifically, a barrier layer 27 can be formed to conformally cover the surfaces of the plurality of holes H2 and the upper surface of the first interlayer insulating layer 24. Thereafter, a first preliminary intermediate interconnect portion 23' and a first preliminary intermediate plug 25' can be formed by depositing a conductive material on the barrier layer 27. The first preliminary intermediate plug 25' can be a part that fills the plurality of holes H2.

[0119] Referring to Figure 15A and Figure 15B , a first intermediate interconnect structure 21 can be formed.

[0120] Forming the first intermediate interconnect structure 21 can be the same as or similar to that of the lower interconnect structure 11 described with reference to Figure 8A and Figure 8B .

[0121] For example, forming the first intermediate interconnect structure 21 may include patterning a first preliminary intermediate interconnect structure 21'. The patterning may include forming a mask pattern on the first preliminary intermediate interconnect structure 21', and forming a recessed area R2 that exposes the upper surface of the first interlayer insulating layer 24 through an etching process. Accordingly, a first intermediate interconnect portion 23 and a first intermediate plug 25 may be formed.

[0122] As described above, referring to Figures 9A to 15B the process for forming the first intermediate interconnect structure 21 described may be referred to as the "first cycle".

[0123] Figures 16A to 17B is a process diagram showing a second cycle of a process for forming a second intermediate interconnect structure 31 after the processes in Figure 15A and Figure 15B . The second cycle may include processes that are the same as or similar to the processes of the first cycle described with reference to Figures 9A to 15B .

[0124] Referring to Figure 16A and Figure 16B , a second preliminary intermediate interconnect structure 31' may be formed on the first intermediate interconnect structure 21.

[0125] Similar to the example described with reference to Figures 9A to 12B , a first intermediate stopper layer 26 covering the first interlayer insulating layer 24 and the first intermediate interconnect portion 23, a first intermediate gap-fill insulating layer 28 on the first intermediate stopper layer 26, and a second intermediate stopper layer 26 on the first intermediate stopper layer 26 and a second interlayer insulating layer 34 may be formed. In an exemplary embodiment, the second interlayer insulating layer 34 may include a silicon nitride material different from that of the first intermediate stopper layer 26, and even when the second interlayer insulating layer 34 may include the same material, the boundary between the second interlayer insulating layer 34 and the first intermediate stopper layer 26 may be distinguishable by a difference in physical properties.

[0126] Thereafter, similar to the example described with reference to Figure 13A and Figure 13B , a plurality of holes penetrating the second interlayer insulating layer 34 and the first intermediate stopper layer 26 and exposing the upper surface of the first intermediate interconnect portion 23 may be formed.

[0127] Thereafter, similar to the example described with reference to Figure 14A and Figure 14B , a barrier layer 37 conformally covering the surfaces of the plurality of holes and the upper surface of the second interlayer insulating layer 34, and a second preliminary intermediate interconnect portion 33' and a second preliminary intermediate plug 35' on the barrier layer 37 may be formed.

[0128] Referring to Figure 17A andFigure 17B , the second intermediate interconnection structure 31 can be formed.

[0129] Forming the second intermediate interconnection structure 31 can be the same as or similar to forming the first intermediate interconnection structure 21 described with reference to Figure 15A and Figure 15B description.

[0130] Figure 18A and Figure 18B are diagrams showing the process of the third cycle for forming the bit line 53 after the processes in Figure 17A and Figure 17B . The third cycle may also include the same or similar processes as the first cycle described with reference to Figures 9A to 15B description.

[0131] With reference to Figure 18A and Figure 18B , the upper interconnection structure 51 can be formed on the second intermediate interconnection structure 31, and the upper stop layer 56 can be formed on the upper interconnection structure 51.

[0132] The second intermediate stop layer 36 covering the second intermediate interlayer insulation layer 34 and the second intermediate interconnection portion 33, the second intermediate gap filling insulation layer 38 on the second intermediate stop layer 36, the upper interlayer insulation layer 54 on the second intermediate gap filling insulation layer 38, a plurality of holes penetrating the upper interlayer insulation layer 54 and the second intermediate stop layer 36 and exposing the upper surface of the second intermediate interconnection portion 33, the upper interconnection structure 51 including the barrier layer 57, the contact plug 55 and the bit line 53 on the upper interlayer insulation layer 54, and the upper stop layer 56 on the upper interconnection structure 51 can be formed.

[0133] According to an exemplary embodiment, the upper stop layer 56 may not be formed on the upper interconnection structure 51.

[0134] Figures 19A to 21B is a vertical cross-sectional view showing the process for forming the upper transistor and the data storage structure 87 after the processes in Figure 18A and Figure 18B .

[0135] With reference to Figure 19A and Figure 19B , the upper transistor can be formed on the bit line 53.

[0136] In the cell array region MCA, as shown in Figure 3 , the channel structure 73, the dielectric structure 76, the word line 79, the bonding pad 81 and the upper gap filling insulation layer 84 can be formed on the bit line 53.

[0137] In the connection region EA, upper interconnect 81p and upper plug 83p can be formed on bit line 53 and upper stopper layer 56. In one exemplary embodiment, upper interconnect 81p and upper plug 83p can be formed simultaneously with bonding pad 81 and can include the same material as that of bonding pad 81. Upper gap-fill insulating layer 84 can surround bonding pad 81, upper interconnect 81p, and upper plug 83p.

[0138] Referring to Figure 20A and Figure 20B , a data storage structure 87 can be formed on the upper transistor.

[0139] In the cell array region MCA, a data storage structure 87 can be formed on the upper transistor. As referring to Figure 3 as described, data storage structure 87 can include a first electrode 88a electrically connected to and in contact with bonding pad 81, a second electrode 88c on the first electrode 88a, and a dielectric layer 88b between the first electrode 88a and the second electrode 88c.

[0140] In the cell array region MCA, an upper insulating structure 90 can be formed to cover the data storage structure 87. The upper insulating structure 90 can cover the upper interconnect 81p in the connection region EA.

[0141] Referring to Figure 21A and Figure 21B , a cell contact hole HC can be formed in the cell array region MCA, and a peripheral contact hole HP can be formed in the connection region EA.

[0142] The cell contact hole HC can penetrate the upper insulating structure 90 and can expose the second electrode 88c. The peripheral contact hole HP can penetrate the upper insulating structure 90 and can expose the upper surface of the upper interconnect 81p. The cell contact hole HC and the peripheral contact hole HP can be formed simultaneously by performing an anisotropic etching process.

[0143] Returning to referring Figure 2A and Figure 3 , a barrier layer 96 can be conformally formed in the cell contact hole HC and the peripheral contact hole HP, and a metal layer 93 can be filled in the barrier layer 96 to form each of the cell contact plug CCP and the peripheral contact plug PCP.

[0144] Figures 22A to 24B is a vertical cross-sectional view of a process showing a method of manufacturing a semiconductor device 1b in sequence according to an exemplary embodiment. Figures 22A to 24A is a process diagram showing a process continuing from the process in Figure 16A , and Figures 22B to 24B is a process diagram showing a process continuing from the process in Figure 16B .

[0145] Referring toFigure 22A and Figure 22B , the second preliminary intermediate interconnect 33' in Figure 16A and Figure 16B can be removed by a planarization process such as chemical mechanical polishing (CMP).

[0146] Accordingly, the upper surface of the second interlayer insulating layer 34 and the upper surface of the second preliminary intermediate plug 35' can be exposed. The upper surface of the second interlayer insulating layer 34 and the upper surface of the second preliminary intermediate plug 35' can be formed at the same height.

[0147] Referring to Figure 23A and Figure 23B , the second preliminary intermediate interconnect 33' can be formed on the second interlayer insulating layer 34 and the second preliminary intermediate plug 35'.

[0148] Forming the second preliminary intermediate interconnect 33' can include depositing a conductive material on the second interlayer insulating layer 34 and the second preliminary intermediate plug 35'. Here, the conductive material can be deposited by physical vapor deposition (PVD).

[0149] Accordingly, according to Figure 24A and Figure 24B , the second intermediate interconnect 33 can have a film quality denser than that of the lower interconnect 13 and the first intermediate interconnect 23. Accordingly, the second intermediate interconnect 33 can have a lower resistance than that of the lower interconnect 13 and the first intermediate interconnect 23.

[0150] Referring to Figure 24A and Figure 24B , similar to Figure 15A and Figure 15B , the second intermediate interconnect 33 can be formed. A detailed description of the second intermediate interconnect 33 will not be provided.

[0151] According to the foregoing exemplary embodiments, by providing at least one intermediate structure including an intermediate interconnect structure on a lower structure including an interconnect structure, various interconnect structures can be implemented and the design flexibility can be increased. Accordingly, the area of the connection region can be reduced. In addition, since each of the intermediate structures includes a plurality of insulating layers, the level of warping occurring in the manufacturing process can be resolved or alleviated.

[0152] Although the exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the exemplary embodiments defined by the appended claims.

Claims

1. A semiconductor device, comprising: A lower structure, including a substrate and a lower transistor on the substrate; An intermediate structure, on the lower structure; And An upper structure, on the intermediate structure, the upper structure including an upper transistor and a data storage structure, Wherein, the intermediate structure includes: An intermediate interlayer insulating layer, on the lower structure, An intermediate interconnect structure, including an intermediate plug and an intermediate interconnect portion on the intermediate plug, wherein the intermediate plug penetrates the intermediate interlayer insulating layer, An intermediate stopper layer, including an intermediate stopper horizontal portion and an intermediate stopper extension portion, the intermediate stopper horizontal portion is on the intermediate interlayer insulating layer, the intermediate stopper extension portion extends from the intermediate stopper horizontal portion and covers the side surface and the upper surface of the intermediate interconnect portion, and An intermediate gap-fill insulating layer, on the outer surface of the intermediate stopper extension portion of the intermediate stopper layer, and on the intermediate stopper horizontal portion of the intermediate stopper layer.

2. The semiconductor device according to claim 1, Among them, The intermediate interlayer insulating layer and the intermediate stopper layer include a first insulating material, and Wherein, the intermediate gap-fill insulating layer includes a second insulating material different from the first insulating material.

3. The semiconductor device according to claim 2, Among them, The intermediate interlayer insulating layer and the intermediate stopper layer include insulating nitride, and Wherein, the intermediate gap-fill insulating layer includes insulating oxide.

4. The semiconductor device according to claim 1, wherein, The upper structure further includes: An upper interlayer insulating layer, on the intermediate stopper extension portion of the intermediate stopper layer, and on the intermediate gap-fill insulating layer; An upper interconnect structure, including a contact plug penetrating the upper interlayer insulating layer, wherein the contact plug is connected to the intermediate plug and connected to a bit line on the contact plug; and An upper stopper layer, on the upper interlayer insulating layer, and on the upper interconnect structure.

5. The semiconductor device according to claim 4, Among them, The side surface of the intermediate gap-fill insulating layer contacts the outer surface of the intermediate stopper extension portion, and Wherein, the upper surface of the intermediate stopper extension portion and the upper surface of the intermediate gap-fill insulating layer contact the lower surface of the upper interlayer insulating layer.

6. The semiconductor device according to claim 4, wherein, The upper transistor includes: A vertical channel portion, on the bit line; A word line, facing the side surface of the vertical channel portion; and A dielectric structure, between the side surface of the vertical channel portion and the word line.

7. The semiconductor device according to claim 6, Among them, The upper structure further includes a bonding pad on the vertical channel portion, and Wherein, the data storage structure is on the bonding pad.

8. The semiconductor device according to claim 4, Among them, The upper structure further includes: An upper gap-fill insulating layer, on the upper stopper layer; An upper plug, penetrating the upper gap-fill insulating layer, wherein the upper plug is connected to the bit line; An upper interconnect, on the upper plug; An upper insulating structure, on the upper gap-fill insulating layer and on the upper interconnect; and A peripheral plug, and Wherein, the peripheral plug penetrates the upper insulating structure and is connected to the upper interconnect.

9. The semiconductor device according to claim 4, Among them, The upper structure further includes an upper insulating structure on the upper stopper layer, the upper insulating structure including a peripheral plug, and Wherein, the peripheral plug penetrates the upper insulating structure and is connected to the bit line.

10. The semiconductor device according to any one of claims 1 to 9, Among them, The intermediate interconnection structure further includes a barrier layer, the barrier layer includes a first portion and a second portion, the first portion is on the lower surface of the intermediate interconnection portion, and the second portion extends along the side surface and the lower surface of the intermediate plug, wherein, the side surface of the first portion of the barrier layer contacts the intermediate stop layer, and wherein, at least a portion of the second portion of the barrier layer is surrounded by the intermediate gap-fill insulating layer and the intermediate interlayer insulating layer.

11. A semiconductor device, comprising: a lower structure including a lower transistor; an intermediate structure on the lower structure; and an upper structure on the intermediate structure, the upper structure including a data storage structure, wherein, the intermediate structure includes: a first intermediate interlayer insulating layer, a first intermediate interconnection structure penetrating the first intermediate interlayer insulating layer, the first intermediate interconnection structure including a first intermediate plug and a first intermediate interconnection portion on the first intermediate plug, a first intermediate stop layer including a first horizontal portion on the first intermediate interlayer insulating layer and a first extension portion extending from the first horizontal portion, wherein, the first extension portion is on the side surface and the upper surface of the first intermediate interconnection structure, a first intermediate gap-fill insulating layer on the upper surface of the first horizontal portion and on the outer side surface of the first extension portion, a second intermediate interlayer insulating layer on the upper surface of the first extension portion and on the upper surface of the first intermediate gap-fill insulating layer, and a second intermediate interconnection structure including a second intermediate plug and a second intermediate interconnection portion on the second intermediate plug, wherein, the second intermediate plug penetrates the second intermediate interlayer insulating layer and the first extension portion and is connected to the first intermediate interconnection portion, wherein, the first intermediate interlayer insulating layer, the first intermediate stop layer and the second intermediate interlayer insulating layer include insulating nitrides, and wherein, the first intermediate gap-fill insulating layer includes insulating oxide.

12. The semiconductor device according to claim 11, Among them, the first intermediate interconnection portion extends to the first intermediate plug, and wherein, the second intermediate interconnection portion extends to the second intermediate plug.

13. The semiconductor device according to claim 11, wherein, The lower surface of the first horizontal portion is at a height lower than the height of the lower surface of the first intermediate interconnection portion.

14. The semiconductor device according to claim 13, Among them, the intermediate structure further includes a second intermediate stop layer, the second intermediate stop layer includes a second horizontal portion on the second intermediate interlayer insulating layer and a second extension portion extending from the second horizontal portion, wherein, the second extension portion is on the side surface and the upper surface of the second intermediate interconnection structure, and wherein, the lower surface of the second horizontal portion is at a height lower than the height of the lower surface of the second intermediate interconnection portion.

15. The semiconductor device according to claim 11, wherein, The upper surface of the first extension portion is at a height higher than the height of the upper surface of the first intermediate gap-fill insulating layer.

16. The semiconductor device according to claim 11, Among them, the upper surface of the first intermediate interconnection portion is recessed downward, and wherein, the second intermediate plug contacts at least a portion of the upper surface of the first intermediate interconnection portion.

17. The semiconductor device according to any one of claims 11 to 16, wherein, The film quality of one of the first intermediate interconnection portion and the second intermediate interconnection portion is denser than the film quality of the other of the first intermediate interconnection portion and the second intermediate interconnection portion.

18. A semiconductor device, comprising: a lower structure including a substrate; at least one intermediate structure on the lower structure; and an upper structure, on the at least one intermediate structure, the upper structure including an upper transistor and a data storage structure on the upper transistor, wherein, the lower structure includes: peripheral transistors, on a substrate, the peripheral transistors including peripheral source / drain and a peripheral gate, a lower interlayer insulating layer, on the substrate, wherein the lower interlayer insulating layer covers at least a side surface of the peripheral gate, a lower interconnect structure, including a lower plug penetrating the lower interlayer insulating layer and a lower interconnect portion on the lower plug, a lower stopper layer, on the lower interlayer insulating layer and on the lower interconnect structure, the lower stopper layer including a lower stopper horizontal portion and a lower stopper extension portion, the lower stopper horizontal portion on the lower interlayer insulating layer, the lower stopper extension portion extending from the lower stopper horizontal portion and covering a side surface and an upper surface of the lower interconnect portion, and a lower gap-fill insulating layer, on the lower stopper extension portion, wherein, the at least one intermediate structure includes: an intermediate interlayer insulating layer, on the lower stopper extension portion and on the lower gap-fill insulating layer, an intermediate interconnect structure, including an intermediate plug and an intermediate interconnect portion on the intermediate plug, wherein the intermediate plug penetrates the intermediate interlayer insulating layer and the lower stopper layer, an intermediate stopper layer, on the intermediate interlayer insulating layer and on the intermediate interconnect structure, the intermediate stopper layer including an intermediate stopper horizontal portion and an intermediate stopper extension portion, the intermediate stopper horizontal portion on the intermediate interlayer insulating layer, the intermediate stopper extension portion extending from the intermediate stopper horizontal portion and covering a side surface and an upper surface of the intermediate interconnect portion, and an intermediate gap-fill insulating layer, on the intermediate stopper horizontal portion, wherein, the upper structure includes: an upper interlayer insulating layer, on the intermediate stopper extension portion and on the intermediate gap-fill insulating layer, an upper interconnect structure, including a contact plug and a bit line on the contact plug, wherein the contact plug penetrates the upper interlayer insulating layer and is connected to the intermediate plug, and an upper stopper layer, on the upper interlayer insulating layer and on the upper interconnect structure, and wherein, the upper transistor includes: a vertical channel portion, on the bit line; a word line, facing a side surface of the vertical channel portion, and a dielectric structure, between the side surface of the vertical channel portion and the word line.

19. The semiconductor device according to claim 18, Among them, the peripheral transistors further include an insulating liner covering the peripheral gate on the substrate, and wherein, a lower surface of the lower stopper horizontal portion is at a height lower than a height of an upper surface of the insulating liner.

20. The semiconductor device according to claim 18 or claim 19, Among them, the lower gap-fill insulating layer and the intermediate gap-fill insulating layer include silicon oxide, and wherein, the lower stopper layer, the intermediate interlayer insulating layer, the intermediate stopper layer, the upper interlayer insulating layer and the upper stopper layer include silicon nitride.

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