Semiconductor memory device

Abstract

A semiconductor memory device includes: a first semiconductor structure including a first sub-memory cell array, the first sub-memory cell array including a plurality of word lines; and a second semiconductor structure under the first semiconductor structure, in which the second semiconductor structure includes: a first sub-word line driver configured to supply a word line driving voltage to a first end of a first word line among the plurality of word lines; a second sub word line driver configured to supply the word line driving voltage to a second end of the first word line; a third sub word line driver configured to supply the word line driving voltage to a first end of a second word line among the plurality of word lines; and a fourth sub word line driver configured to supply the word line driving voltage to a second end of the second word line.

Description

Technical Field

[0001] The present disclosure described herein relates to semiconductor devices, and more particularly, to semiconductor memory devices. Background Art

[0002] Semiconductor memories can be classified as: volatile memories, which lose the data stored therein when power is cut off, such as static random access memories (SRAMs) or dynamic random access memories (DRAMs); or non-volatile memory devices, which retain the data stored therein even when power is cut off, such as flash memories, phase change RAMs (PRAMs), magnetic RAMs (MRAMs), resistive RAMs (RRAMs), or ferroelectric RAMs (FRAMs).

[0003] DRAM devices may include memory cells connected to word lines and bit lines. Through the bit lines, a DRAM device can store data in the memory cells or read the data stored in the memory cells. To drive the word lines, the word lines can be divided into a plurality of sub-word lines, and each sub-word line can be driven using a sub-word line driver. To increase the integration degree of DRAM devices, the thickness of the word lines can become thinner and thinner, and the number of memory cells connected to the word lines can increase. However, this may increase the resistance of the word lines, and may thereby reduce the operation performance of DRAM devices. Summary of the Invention

[0004] A semiconductor memory device having improved operation performance by providing an operation voltage to opposite ends of a word line is provided.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0006] According to one aspect of the present disclosure, a semiconductor memory device includes: a first semiconductor structure including a first sub-memory cell array and a plurality of upper metal pads, the first sub-memory cell array including a first plurality of word lines, a plurality of bit lines, and a plurality of memory cells, and the plurality of upper metal pads being electrically connected to the first plurality of word lines and the plurality of bit lines; and a second semiconductor structure disposed under the first semiconductor structure and including a plurality of sub-word line drivers and a plurality of lower metal pads electrically connected to the plurality of sub-word line drivers, wherein the plurality of sub-word line drivers includes: a first sub-word line driver configured to supply a word line driving voltage to a first end of a first word line among the first plurality of word lines; a second sub-word line driver configured to supply the word line driving voltage to a second end of the first word line; a third sub-word line driver configured to supply the word line driving voltage to a first end of a second word line among the first plurality of word lines; and a fourth sub-word line driver configured to supply the word line driving voltage to a second end of the second word line, and wherein each of the plurality of upper metal pads is bonded to a corresponding one of the plurality of lower metal pads one-to-one.

[0007] According to one aspect of the present disclosure, a semiconductor memory device includes: a memory cell array structure located on a first substrate and including a plurality of sub-memory cell arrays, the plurality of sub-memory cell arrays including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; a core peripheral circuit structure located on a second substrate under the first substrate, wherein the core peripheral circuit structure includes a first sub-word line driver block, a second sub-word line driver block, a third sub-word line driver block, and a fourth sub-word line driver block, the first sub-word line driver block being configured to supply a word line driving voltage to a first end of a first odd-numbered word line among a first plurality of word lines in a first sub-memory cell array among the plurality of sub-memory cell arrays, the second sub-word line driver block being configured to supply the word line driving voltage to a second end of the first odd-numbered word line, the third sub-word line driver block being configured to supply the word line driving voltage to a first end of a first even-numbered word line among the first plurality of word lines, and the fourth sub-word line driver block being configured to supply the word line driving voltage to a second end of the first even-numbered word line; and a plurality of metal pad junctions electrically connecting the memory cell array structure and the core peripheral circuit structure.

[0008] According to one aspect of the present disclosure, a semiconductor memory device includes: a first substrate; a first sub memory cell array located on the first substrate and including a first plurality of word lines; a plurality of upper metal pads arranged in a matrix array shape on the first sub memory cell array; one or more first metal layers electrically connecting the plurality of upper metal pads to opposite ends of each of the first plurality of word lines; a second substrate located below the first substrate; a transistor layer located on the second substrate and including a plurality of sub word line drivers; a plurality of lower metal pads arranged in the matrix array shape on the upper side of the transistor layer, wherein each of the plurality of lower metal pads is bonded to a corresponding upper metal pad among the plurality of upper metal pads; and one or more second metal layers electrically connecting the plurality of lower metal pads to the transistor layer, wherein each of a plurality of first sub word line drivers included in the plurality of sub word line drivers is electrically connected to a first metal contact formed at a first end of each of a plurality of odd numbered word lines included in the first plurality of word lines, wherein each of a plurality of second sub word line drivers included in the plurality of sub word line drivers is electrically connected to a second metal contact formed at a second end of each of the odd numbered word lines, wherein each of a plurality of third sub word line drivers included in the plurality of sub word line drivers is electrically connected to a third metal contact formed at a first end of each of a plurality of even numbered word lines included in the first plurality of word lines, and wherein each of a plurality of fourth sub word line drivers included in the plurality of sub word line drivers is electrically connected to a fourth metal contact formed at an opposite second end of each of the even numbered word lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present disclosure; Figure 2 is a diagram showing a part of a semiconductor memory device according to an embodiment of the present disclosure; Figure 3 is a diagram showing a plurality of word lines and sub word line drivers included in a sub memory cell array according to an embodiment of the present disclosure; Figure 4 is a circuit diagram showing a word line and a sub word line driver according to an embodiment of the present disclosure; Figure 5 is a perspective view showing a sub - memory cell array of a semiconductor memory device according to an embodiment of the present disclosure; Figure 6 is a vertical cross - sectional view showing a semiconductor memory device according to an embodiment of the present disclosure; Figure 7 is a plan view showing the layout of metal pad junctions in a sub - memory cell array according to an embodiment of the present disclosure; Figure 8 is a view showing the vertical layout of a plurality of sub - memory cell arrays and a plurality of sub - word line drivers when observed in a cross - sectional view according to an embodiment of the present disclosure; Figure 9 is a view showing a part of a memory cell array structure according to an embodiment of the present disclosure; Figure 10 is a view showing a word line and a sub - word line driver according to an embodiment of the present disclosure; Figure 11 is a circuit diagram showing the configuration of a sub - word line driver according to an embodiment of the present disclosure; Figure 12 is a view showing another example of a memory cell array structure according to an embodiment of the present disclosure; Figure 13 is a view showing another example of a word line and a sub - word line driver according to an embodiment of the present disclosure; Figure 14 is a view showing the slope of the driving voltage at each position according to an embodiment of the present disclosure; Figure 15A is a view showing the layout of a sub - memory cell array of a semiconductor memory device according to an embodiment of the present disclosure; Figure 15B is a view showing according to an embodiment of the present disclosure and Figure 15A the layout of the core peripheral circuit corresponding to the sub - memory cell array; Figure 16 is a view depicting an integrated circuit device according to an embodiment of the present disclosure; Figure 17 is a view showing according to an embodiment of the present disclosure Figure 16 the plan view of the pad array PDA of the integrated circuit device; Figure 18A is a view showing according to an embodiment of the present disclosure along Figure 17 the vertical cross - section of the integrated circuit device taken along line A - A'; Figure 18B is a view showing according to an embodiment of the present disclosure along Figure 17 the vertical cross - section of the integrated circuit device taken along line B - B'. Detailed Description

[0010] Hereinafter, embodiments of the present disclosure will be described in detail and clearly so that those of ordinary skill in the art can easily implement the present disclosure.

[0011] As is conventional in the art, embodiments are described and illustrated in the drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will recognize that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing technologies or other manufacturing technologies. In the case where the blocks, units, and / or modules are implemented by a microprocessor or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein and can optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. Additionally, without departing from the scope hereof, each block, unit, and / or module of an embodiment can be physically divided into two or more interacting and discrete blocks, units, and / or modules. Furthermore, without departing from the scope hereof, the blocks, units, and / or modules of an embodiment can be physically combined into more complex blocks, units, and / or modules.

[0012] Figure 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present disclosure. Referring to Figure 1 , the semiconductor memory device 100 may include a memory cell array 110, a row decoder 120, a column decoder 130, a sense amplifier and write driver 140 (shown as "SW / WD"), an input / output circuit 150 (shown as "I / O circuit"), and a control logic circuit 160. The semiconductor memory device 100 may be a dynamic random access memory (DRAM) device. However, the embodiments are not limited thereto. For example, the semiconductor memory device 100 may include at least one of various memory devices such as SRAM, SDRAM, MRAM, FRAM, ReRAM, PRAM, and flash memory.

[0013] The memory cell array 110 may include memory cells MC connected to a plurality of word lines WL and a plurality of bit lines BL. Each memory cell MC may include a select transistor TR and a storage capacitor C. The select transistor TR may be connected between the storage capacitor C and the bit line BL and may operate based on the voltage of the word line WL. The storage capacitor C may be connected to the select transistor TR and may store data in accordance with the operation of the select transistor TR and the level of the bit line BL.

[0014] The row decoder 120 can be connected to the memory cell array 110 through a plurality of word lines WL. The row decoder 120 can decode the row address provided from an external device (e.g., a memory controller), and can control the voltage of the word line WL based on the decoding result.

[0015] The column decoder 130 can be connected to the memory cell array 110 through a plurality of bit lines BL. The column decoder 130 can decode the column address provided from an external device (e.g., a memory controller), and can control the plurality of bit lines BL based on the decoding result.

[0016] Through the plurality of bit lines BL, the sense amplifier and write driver 140 can read the data stored in the memory cell array 110, or can write the data into the memory cell array 110.

[0017] The input / output circuit 150 can send data to an external device (e.g., a memory controller) or can receive data from an external device. The input / output circuit 150 can provide the data received from the external device to the sense amplifier and write driver 140, or can provide the data received from the sense amplifier and write driver 140 to the external device.

[0018] The control logic circuit 160 can control various components included in the semiconductor memory device 100 based on commands or control signals from an external device.

[0019] During a read operation or a write operation of the semiconductor memory device 100, a select voltage, a word line enable voltage, or a high voltage (e.g., a voltage for turning on the select transistor TR of the memory cell MC) can be applied to the word line WL included in the plurality of word lines WL.

[0020] According to an embodiment, as the thickness of the word line WL on the memory cell array 110 decreases, the number of memory cells MC connected to one word line WL can increase. In addition, a structure in which a voltage is applied only to one end of the word line WL and the opposite end of the word line WL is floating can be adopted. In this case, as the resistance of the word line WL increases, the slope of the voltage applied to the word line WL may become worse. This can mean that the performance of the semiconductor memory device 100 may deteriorate.

[0021] The semiconductor memory device 100 according to an embodiment of the present disclosure can improve the slope of the voltage applied to the word line WL by applying a driving voltage to the opposite end of the word line WL, and thus can improve the performance of the semiconductor memory device 100. Examples of the semiconductor memory device 100 according to an embodiment of the present disclosure are described in detail with reference to the accompanying drawings.

[0022] Figure 2is a diagram showing a part of a semiconductor memory device according to an embodiment of the present disclosure. Refer to Figure 2 , a memory cell array 110 according to an embodiment of the present disclosure may include a plurality of sub-memory cell arrays SMA (e.g., a first sub-memory cell array SMA1, a second sub-memory cell array SMA2, and a third sub-memory cell array SMA3) and a plurality of sub-word line drivers SWD (e.g., a first sub-word line driver SWD1, a second sub-word line driver SWD2, …, and a sixteenth sub-word line driver SWD16).

[0023] In the present disclosure, for simplicity of the drawings and for ease of description, components that may not be necessary for describing the embodiments of the present disclosure (e.g., bit lines and memory cells) may be omitted in the drawings. However, the embodiments are not limited thereto. Additionally, although each sub-memory cell array is shown as including 8 or fewer word lines, the embodiments are not limited thereto, and in some embodiments, the number of word lines included in each sub-memory cell array may be increased and / or decreased.

[0024] The first sub-memory cell array SMA1 may include a first plurality of word lines WL1 (e.g., word line WL11, word line WL12, …, word line WL18). Opposite ends of each word line in the first plurality of word lines WL1 may be respectively connected to different sub-word line drivers SWD. For example, a first end of word line WL11 may be connected to the first sub-word line driver SWD1, and a second end of word line WL11 may be connected to the second sub-word line driver SWD2. Opposite ends of word line WL12 may be respectively connected to the third sub-word line driver SWD3 and the fourth sub-word line driver SWD4.

[0025] The plurality of sub-word line drivers SWD may be grouped into a plurality of sub-word line driver blocks SDB (e.g., a first sub-word line driver block SDB1, a second sub-word line driver block SDB2, a third sub-word line driver block SDB3, and a fourth sub-word line driver block SDB4). For example, the first sub-word line driver block SDB1 may include the first sub-word line driver SWD1, the fifth sub-word line driver SWD5, the ninth sub-word line driver SWD9, and the thirteenth sub-word line driver SWD13. The second sub-word line driver block SDB2 may include the second sub-word line driver SWD2, the sixth sub-word line driver SWD6, the tenth sub-word line driver SWD10, and the fourteenth sub-word line driver SWD14. The third sub-word line driver block SDB3 may include the third sub-word line driver SWD3, the seventh sub-word line driver SWD7, the eleventh sub-word line driver SWD11, and the fifteenth sub-word line driver SWD15, and the fourth sub-word line driver block SDB4 may include the fourth sub-word line driver SWD4, the eighth sub-word line driver SWD8, the twelfth sub-word line driver SWD12, and the sixteenth sub-word line driver SWD16.

[0026] Multiple sub - word - line driver blocks SDB can operate based on the word - line control signal PXI. According to an embodiment, the first sub - word - line driver block SDB1 and the second sub - word - line driver block SDB2 can drive word lines WL11, WL13, WL15, and WL17 which can be odd - numbered word lines. The third sub - word - line driver block SDB3 and the fourth sub - word - line driver block SDB4 can drive word lines WL12, WL14, WL16, and WL18 which can be even - numbered word lines. The first sub - word - line driver block SDB1 and the second sub - word - line driver block SDB2 can drive the odd - numbered word lines WL11, WL13, WL15, and WL17 based on the odd - numbered word - line control signal PXI_odd of the word - line control signal PXI. The third sub - word - line driver block SDB3 and the fourth sub - word - line driver block SDB4 can drive the even - numbered word lines WL12, WL14, WL16, and WL18 based on the even - numbered word - line control signal PXI_even of the word - line control signal PXI.

[0027] One side of the first sub - memory cell array SMA1 can be adjacent to the second sub - memory cell array SMA2, and the opposite side of the first sub - memory cell array SMA1 facing away from the second sub - memory cell array SMA2 can be adjacent to the third sub - memory cell array SMA3. For example, the first sub - memory cell array SMA1 can be disposed between the second sub - memory cell array SMA2 and the third sub - memory cell array SMA3. The second sub - memory cell array SMA2 can include multiple word lines WL2 (e.g., word line WL21, word line WL22, word line WL23, …, word line WL28). The third sub - memory cell array SMA3 can include multiple word lines WL3 (e.g., word line WL31, word line WL32, …, word line WL38).

[0028] The second sub - word - line driver SWD2 can be connected to the word line WL11 included in the first sub - memory cell array SMA1 and can be simultaneously connected to the word line WL21 included in the second sub - memory cell array SMA2. The first sub - word - line driver SWD1 can be connected to the word line WL11 and can be simultaneously connected to the word line WL31 included in the third sub - memory cell array SMA3. The fourth sub - word - line driver SWD4 can be connected to the word line WL12 included in the first sub - memory cell array SMA1 and can be simultaneously connected to the word line WL22 included in the second sub - memory cell array SMA2. The third sub - word - line driver SWD3 can be connected to the word line WL12 and can be simultaneously connected to the word line WL32 included in the third sub - memory cell array SMA3.

[0029] The first sub - word - line driver SWD1 and the second sub - word - line driver SWD2 drive opposite ends of the word line WL11 simultaneously. The first sub - word - line driver SWD1 can also drive the word line WL31, and the second sub - word - line driver SWD2 can also drive the word line WL21. The third sub - word - line driver SWD3 and the fourth sub - word - line driver SWD4 can drive the word line WL12 at opposite positions simultaneously; in this case, the third sub - word - line driver SWD3 can also drive the word line WL32, and the fourth sub - word - line driver SWD4 can also drive the word line WL22.

[0030] The first sub - word - line driver block SDB1 and the second sub - word - line driver block SDB2 can drive the odd - numbered word lines WL11, WL13, WL15, and WL17 included in the first sub - memory cell array SMA1. Additionally, the first sub - word - line driver block SDB1 can also drive the odd - numbered word lines WL31, WL33, WL35, and WL37 included in the third sub - memory cell array SMA3, and the second sub - word - line driver block SDB2 can also drive the odd - numbered word lines WL21, WL23, WL25, and WL27 included in the second sub - memory cell array SMA2.

[0031] The third sub - word - line driver block SDB3 and the fourth sub - word - line driver block SDB4 can drive the even - numbered word lines WL12, WL14, WL16, and WL18 included in the first sub - memory cell array SMA1. Additionally, the third sub - word - line driver block SDB3 can also drive the even - numbered word lines WL32, WL34, WL36, and WL38 included in the third sub - memory cell array SMA3, and the fourth sub - word - line driver block SDB4 can also drive the even - numbered word lines WL22, WL24, WL26, and WL28 included in the second sub - memory cell array SMA2.

[0032] Word lines that are included in different sub - memory cell arrays and connect the sub - memory cell arrays can be driven simultaneously by the first sub - word - line driver block SDB1 to the fourth sub - word - line driver block SDB4. For example, the word lines WL11, WL21, and WL31 can be included in different sub - memory cell arrays, and the word lines WL11, WL21, and WL31 can connect the sub - memory cell arrays SMA1, SMA2, and SAM3. Thus, the word lines WL11, WL21, and WL31 can be driven simultaneously. Similarly, the word lines WL12, WL22, and WL32 can be driven simultaneously.

[0033] According to an embodiment, one or more sub-word line driver blocks may be disposed on a side of the third sub memory cell array SMA3 facing away from the first sub-word line driver block SDB1 and the third sub-word line driver block SDB3. The sub-word line driver blocks disposed on the side facing away from the first sub-word line driver block SDB1 and the third sub-word line driver block SDB3 may drive multiple word lines WL3 of the third sub memory cell array SMA3 simultaneously with the first sub-word line driver block SDB1 and the third sub-word line driver block SDB3.

[0034] According to an embodiment of the present disclosure, since the word lines included in the sub memory cell array and connecting adjacent sub memory cell arrays may be supplied with a driving voltage from opposite ends of the word lines, the slope of the driving voltage on the word lines may be increased, and the operating performance of the semiconductor memory device 100 may be improved.

[0035] Figure 3 FIG. is a diagram showing multiple word lines and sub-word line drivers included in a sub memory cell array according to an embodiment of the present disclosure. Refer to Figure 3 , the first sub-word line driver SWD1 may supply a word line driving voltage to the word line WL11 in the first direction D1, and the second sub-word line driver SWD2 may supply a word line driving voltage to the word line WL11 in a second direction D2 facing the first direction D1.

[0036] The peripheral circuit region PA12 may be disposed between the first sub memory cell array SMA1 and the second sub memory cell array SMA2, and the peripheral circuit region PA13 may be disposed between the first sub memory cell array SMA1 and the third sub memory cell array SMA3. Multiple sub-word line drivers SWD2, SWD4, SWD6, and SWD8 may be disposed in the peripheral circuit region PA12. Multiple sub-word line drivers SWD1, SWD3, SWD5, and SWD7 may be disposed in the peripheral circuit region PA13.

[0037] The first sub-word line driver SWD1 and the second sub-word line driver SWD2 may control the word line WL11 based on the word line control signal PXI1. The third sub-word line driver SWD3 and the fourth sub-word line driver SWD4 may control the word line WL12 based on the word line control signal PXI2. The fifth sub-word line driver SWD5 and the sixth sub-word line driver SWD6 may control the word line WL13 based on the word line control signal PXI3, and the seventh sub-word line driver SWD7 and the eighth sub-word line driver SWD8 may control the word line WL14 based on the word line control signal PXI4.

[0038] The first sub-word line driver SWD1 may also control the word line WL31 based on the word line control signal PXI1, and the second sub-word line driver SWD2 may also control the word line WL21 based on the word line control signal PXI1. The third sub-word line driver SWD3 may also control the word line WL32 based on the word line control signal PXI2, and the fourth sub-word line driver SWD4 may also control the word line WL22 based on the word line control signal PXI2.

[0039] Figure 3 The word line control signal PXI1 and the word line control signal PXI3 may be included in Figure 2 the odd word line control signal PXI_odd of Figure 3 The word line control signal PXI2 and the word line control signal PXI4 may be included in Figure 2 the even word line control signal PXI_even of

[0040] In an embodiment, when the word line WL11 is selected, each of the first sub-word line driver SWD1 and the second sub-word line driver SWD2 may apply a voltage having a first logic level (e.g., high logic level) "H" generated by a voltage generator to the word line WL11 based on the word line control signal PXI generated by Figure 1 the row decoder 120 of

[0041] Figure 4 is a circuit diagram showing a word line and a sub-word line driver according to an embodiment of the present disclosure. Refer to Figure 4, the first sub - word - line driver SWD1 configured to drive the word - line WL11 may include a first transistor 210_1, a second transistor 220_1, and a third transistor 230_1. The first transistor 210_1 may be a PMOS transistor and may operate as a pull - up transistor. The word - line enable signal NWEIB may be applied to the gate terminal of the first transistor 210_1, the word - line drive signal PXID1 may be applied to the source terminal of the first transistor 210_1, and the drain terminal of the first transistor 210_1 may be connected to the word - line WL11. The first transistor 210_1 may drive the word - line WL11 corresponding to the word - line drive signal PXID1 based on the word - line enable signal NWEIB.

[0042] The second transistor 220_1 may be an NMOS transistor and may operate as a pull - down transistor. The word - line enable signal NWEIB may be applied to the gate terminal of the second transistor 220_1, and the drain terminal and the source terminal of the second transistor 220_1 may be connected to the drain terminal of the first transistor 210_1 and the ground terminal, respectively.

[0043] The third transistor 230_1 may be an NMOS transistor and may operate as a holding transistor for keeping the corresponding word - line at the ground level when the corresponding word - line is not selected. The inverted word - line drive signal PXIB1 may be applied to the gate terminal of the third transistor 230_1, and the drain terminal and the source terminal of the third transistor 230_1 may be connected to the word - line WL11 and the ground terminal, respectively.

[0044] The second sub - word - line driver SWD2 configured to drive the word - line WL11 on a side opposite to the first sub - word - line driver SWD1 may include a first transistor 210_2, a second transistor 220_2, and a third transistor 230_2. The first transistor 210_2, the second transistor 220_2, and the third transistor 230_2 of the second sub - word - line driver SWD2 may correspond to the first transistor 210_1, the second transistor 220_1, and the third transistor 230_1 of the first sub - word - line driver SWD1, respectively. The word - line enable signal NWEIB may be applied to the gate terminal of the first transistor 210_2 of the second sub - word - line driver SWD2, and the word - line drive signal PXID1 may be applied to the source terminal of the first transistor 210_2.

[0045] The third sub - word - line driver SWD3 may include a first transistor 210_3 corresponding to a pull - up transistor, a second transistor 220_3 corresponding to a pull - down transistor, and a third transistor 230_3 corresponding to a holding transistor. The fourth sub - word - line transistor SDW4 may include a first transistor 210_4 corresponding to a pull - up transistor, a second transistor 220_4 corresponding to a pull - down transistor, and a third transistor 230_4 corresponding to a holding transistor. The word - line driving signal PXID2 may be applied to the source terminals of each of the first transistors 210_3 and 210_4, and the inverted word - line driving signal PXIB2 may be applied to the gate terminals of each of the third transistors 230_3 and 230_4.

[0046] The first sub - word - line driver SWD1, the second sub - word - line driver SWD2, the third sub - word - line driver SWD3, and the fourth sub - word - line driver SWD4 may be started (e.g., activated) by a word - line enable signal NWEIB. The first transistors 210_1 of the first sub - word - line driver SWD1 and 210_2 of the second sub - word - line driver SWD2 may be turned on based on the word - line enable signal NWEIB applied to the gate terminals of the first sub - word - line driver SWD1 and the second sub - word - line driver SWD2, and may apply the word - line driving signal PXID1 having a high logic level “H” input to the source terminals of the first sub - word - line driver SWD1 and the second sub - word - line driver SWD2 to the selected word - line WL11. In this case, the word - line driving signal PXID1 having a high logic level “H” may be applied by the first sub - word - line driver SWD1 and the second sub - word - line driver SWD2 to the opposite ends of the word - line WL11.

[0047] The third transistors 230_3 of the third sub - word - line driver SWD3 and 230_4 of the fourth sub - word - line driver SWD4 may be activated by the inverted word - line driving signal PXIB2, and may keep the unselected word - line WL12 at the ground level.

[0048] As Figure 4 shown, the first transistors 210_1, 210_2, 210_3, and 210_4 may be implemented with PMOS transistors, but may be implemented with NMOS transistors depending on the type of the sub - word - line driver. When adjacent word - lines are selected, the third transistors 230_1, 230_2, 230_3, and 230_4 may perform the function of keeping the unselected word - lines at the ground level. When the third transistors 230_1, 230_2, 230_3, and 230_4 are removed, the second transistors 220_1, 220_2, 220_3, and 220_4 may assume the function of keeping the unselected word - lines at the ground level.

[0049] AlthoughFigure 4 The illustrated example includes a CMOS type sub - word line driver, but the embodiments are not limited thereto. For example, the sub - word line driver may include various types of sub - word line drivers having an NMOS type sub - word line driver.

[0050] Figure 5 is a perspective view showing a sub - memory cell array of a semiconductor memory device according to an embodiment of the present disclosure. Refer to Figure 5 , the semiconductor memory device 100 may include a first semiconductor structure SEMS1 and a second semiconductor structure SEMS2 disposed below (or on the lower side) of the first semiconductor structure SEMS1 (e.g., the first semiconductor structure SEMS1 may be in a first direction D1 with respect to the second semiconductor structure SEMS2).

[0051] The first semiconductor structure SEMS1 may include a plurality of sub - memory cell arrays in which a plurality of word lines, a plurality of bit lines, and a plurality of memory cells are disposed. For example, the first semiconductor structure SEMS1 may include a first sub - memory cell array SMA1. The first semiconductor structure SEMS1 may include a plurality of upper metal pads that can be electrically connected to the plurality of word lines and the plurality of bit lines respectively. The second semiconductor structure SEMS2 may include a peripheral circuit. For example, the second semiconductor structure SEMS2 may include a first bit - line sense amplifier circuit BLSA1, a second bit - line sense amplifier circuit BLSA2, an odd sub - word line driver block OSDB, and an even sub - word line driver block ESDB. The second semiconductor structure SEMS2 may also include a plurality of lower metal pads that can be electrically connected to the first bit - line sense amplifier circuit BLSA1, the second bit - line sense amplifier circuit BLSA2, the odd sub - word line driver block OSDB, and the even sub - word line driver block ESDB.

[0052] The first sub - memory cell array SMA1 may include a plurality of word lines and a plurality of bit lines. Some of the word lines included in the first sub - memory cell array SMA1 may be referred to as "odd word lines", and the other word lines included in the first sub - memory cell array SMA1 may be referred to as "even word lines". The odd word lines and the even word lines may be alternately arranged.

[0053] The first bit line sense amplifier circuit BLSA1 and the second bit line sense amplifier circuit BLSA2 can be electrically connected to the bit lines included in the first sub memory cell array SMA1. The first bit line sense amplifier circuit BLSA1 can be connected to some of the bit lines included in the first sub memory cell array SMA1 to amplify the voltage difference between the selected bit line and the reference bit line. The second bit line sense amplifier circuit BLSA2 can be connected to the other bit lines included in the first sub memory cell array SMA1 to amplify the voltage difference between the selected bit line and the reference bit line. The first bit line sense amplifier circuit BLSA1 can be disposed in a first region which is disposed at the periphery among the regions under the first sub memory cell array SMA1, and the second bit line sense amplifier circuit BLSA2 can be disposed in a second region which is disposed at the periphery and away from the first bit line sense amplifier circuit BLSA1 among the regions under the first sub memory cell array SMA1.

[0054] The odd sub word line driver block OSDB and the even sub word line driver block ESDB can be disposed between the first region and the second region. For example, the odd sub word line driver block OSDB and the even sub word line driver block ESDB can be disposed between the first bit line sense amplifier circuit BLSA1 and the second bit line sense amplifier circuit BLSA2. Each of the odd sub word line driver block OSDB and the even sub word line driver block ESDB can include a plurality of sub word line drivers. Each sub word line driver included in the odd sub word line driver block OSDB can be electrically connected to a corresponding odd numbered word line among the odd numbered word lines included in the first sub memory cell array SMA1, and can drive the corresponding odd numbered word line. Each sub word line driver included in the even sub word line driver block ESDB can be electrically connected to a corresponding even numbered word line among the even numbered word lines included in the first sub memory cell array SMA1, and can drive the corresponding even numbered word line.

[0055] Figure 6 is a vertical cross-sectional view of a semiconductor memory device according to an embodiment of the present disclosure. Refer to Figure 6 , the first semiconductor structure SEM1 can include a plurality of upper metal pads UMP which can be electrically connected to the plurality of word lines and the plurality of bit lines of the first sub memory cell array SMA1. The second semiconductor structure SEM2 can include a plurality of lower metal pads LMP which can be electrically connected to the peripheral circuits PCs respectively.

[0056] The first semiconductor structure SEMS1 may include a first substrate 310 and a memory cell array structure MAS formed on the first substrate 310. The memory cell array structure MAS may include a memory cell array MCA and a plurality of first metal lines ML1 configured to route signals of a plurality of word lines and a plurality of bit lines included in the memory cell array MCA. The memory cell array structure MAS may include Figure 1 a memory cell array 110. The memory cell array 110 may include a plurality of sub-memory cell arrays. Each first metal line ML1 may be connected to one of the bit lines and word lines of each sub-memory cell array to route signals on the bit lines or word lines to the outside of the memory cell array structure MAS.

[0057] The second semiconductor structure SEMS2 may include a second substrate 320 disposed on the lower side of the first substrate 310 and a core peripheral circuit structure CPS formed on the second substrate 320. The core peripheral circuit structure CPS may include peripheral circuits PCs formed on the second substrate 320 and a plurality of second metal lines ML2 configured to route signals of the peripheral circuits PCs to the outside of the core peripheral circuit structure CPS. As an example, the peripheral circuits PCs may include a plurality of sub-word line driver blocks and a plurality of bit line sense amplifier circuits. As another example, the peripheral circuits PCs may include Figure 1 a row decoder 120, a column decoder 130, a sense amplifier and a write driver 140, an input / output circuit 150, and a control logic circuit 160.

[0058] An upper metal pad UMP may be disposed at the lower end of the memory cell array structure MAS. The upper metal pad UMP may be electrically connected to the memory cell array MCA through the first metal line ML1. A lower metal pad LMP may be disposed at the upper end of the core peripheral circuit structure CPS. The lower metal pad LMP may be electrically connected to the peripheral circuits PCs through the second metal line ML2.

[0059] The lower metal pad LMP and the upper metal pad UMP may have the same size and the same layout. The lower metal pad LMP and the upper metal pad UMP may include, for example, copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), tin (Sn), or an alloy thereof.

[0060] According to an embodiment of the present disclosure, the semiconductor memory device 100 may have a bonding structure in which a first semiconductor structure SEMS1 and a second semiconductor structure SEMS2 are connected to each other through metal pads. An upper metal pad UMP of the first semiconductor structure SEMS1 and a lower metal pad LMP of the second semiconductor structure SEMS2 may be electrically and physically connected to each other through bonding. For example, the lower metal pad LMP and the upper metal pad UMP may be in direct contact with each other. The lower metal pad LMP and the upper metal pad UMP may be physically and electrically connected to each other through a plurality of metal pad junctions MPJ.

[0061] Figure 7 is a plan view showing the layout of metal pad junctions in a sub - memory cell array according to an embodiment of the present disclosure. Refer to Figure 7 , in the sub - memory cell array, the metal pad junctions MPJ may be classified into a first region to a fourth region (for example, a first region Z1, a second region Z2, a third region Z3, and a fourth region Z4).

[0062] The first region Z1 may correspond to a peripheral region of one sub - memory cell array. The fourth region Z4 may correspond to a peripheral region of the sub - memory cell array that is away from the first region Z1. The second region Z2 and the third region Z3 may correspond to the region between the first region Z1 and the fourth region Z4. For example, the second region Z2 may correspond to the first half of the region between the first region Z1 and the fourth region Z4, and the third region Z3 may correspond to the second half of the region between the first region Z1 and the fourth region Z4 that faces the first half of the region.

[0063] The first region Z1 may include a first bit - line sense amplifier circuit metal pad junction BLSA1_MPJ. The first bit - line sense amplifier circuit metal pad junction BLSA1_MPJ may electrically connect some bit - lines provided in the sub - memory cell array to the first bit - line sense amplifier circuit.

[0064] The second region Z2 may include an odd - sub - word - line driver metal pad junction OSWD_MPJ. The odd - sub - word - line driver metal pad junction OSWD_MPJ may electrically connect odd - numbered word - lines among the word - lines provided in the sub - memory cell array and a sub - word - line driver configured to drive the odd - numbered word - lines.

[0065] The third region Z3 may include an even - sub - word - line driver metal pad junction ESWD_MPJ. The even - sub - word - line driver metal pad junction ESWD_MPJ may electrically connect even - numbered word - lines among the word - lines provided in the sub - memory cell array and a sub - word - line driver configured to drive the even - numbered word - lines.

[0066] The fourth region Z4 may include a second bit line sense amplifier circuit metal pad junction BLSA2_MPJ. The second bit line sense amplifier circuit metal pad junction BLSA2_MPJ may electrically connect other bit lines provided in the sub memory cell array to the second bit line sense amplifier circuit.

[0067] Refer together to Figure 5 and Figure 7 , Figure 5 The first bit line sense amplifier circuit BLSA1 of Figure 7 may be electrically connected to some of the bit lines provided in the first sub memory cell array SMA1 through the first bit line sense amplifier circuit metal pad junction BLSA1_MPJ of Figure 5 The second bit line sense amplifier circuit BLSA2 of Figure 7 may be electrically connected to other bit lines provided in the first sub memory cell array SMA1 through the second bit line sense amplifier circuit metal pad junction BLSA2_MPJ of Figure 5 The sub word line drivers included in the odd sub word line driver block OSDB of Figure 7 may be respectively electrically connected to the odd numbered word lines among the word lines provided in the first sub memory cell array SMA1 through the odd sub word line driver metal pad junction OSWD_MPJ of Figure 5 The sub word line drivers included in the even sub word line driver block ESDB of Figure 7 may be respectively electrically connected to the even numbered word lines among the word lines provided in the first sub memory cell array SMA1 through the even sub word line driver metal pad junction ESWD_MPJ of

[0068] According to an embodiment, the word line drive voltage applied through the odd sub word line driver metal pad junction OSWD_MPJ and the even sub word line driver metal pad junction ESWD_MPJ may also be transferred to another sub memory cell array adjacent to the first sub memory cell array SMA1 of Figure 7

[0069] Figure 8 is a diagram showing a vertical layout of a plurality of sub memory cell arrays and a plurality of sub word line drivers according to an embodiment of the present disclosure when observed in a cross-sectional view. Refer to Figure 8 , the first sub word line driver block SDB1, the second sub word line driver block SDB2, the third sub word line driver block SDB3, and the fourth sub word line driver block SDB4 may drive the word lines included in the first sub memory cell array SMA1.

[0070] The memory cell array structure MAS may include a plurality of sub - memory cell arrays SMA. The first sub - memory cell array SMA1 may include a first odd - numbered word line WL1_odd and a first even - numbered word line WL1_even. The second sub - memory cell array SMA2 may include a second odd - numbered word line WL2_odd and a second even - numbered word line WL2_even, and the third sub - memory cell array SMA3 may include a third odd - numbered word line WL3_odd and a third even - numbered word line WL3_even.

[0071] The core - peripheral circuit structure CPS may include a plurality of sub - word - line driver blocks SDB. The sub - word - line driver included in the first sub - word - line driver block SDB1 can drive the first odd - numbered word line WL1_odd included in the first sub - memory cell array SMA1. The sub - word - line driver included in the first sub - word - line driver block SDB1 can further drive the third odd - numbered word line WL3_odd included in the third sub - memory cell array SMA3. The sub - word - line driver included in the second sub - word - line driver block SDB2 can drive the first odd - numbered word line WL1_odd included in the first sub - memory cell array SMA1. The sub - word - line driver included in the second sub - word - line driver block SDB2 can further drive the second odd - numbered word line WL2_odd included in the second sub - memory cell array SMA2. The sub - word - line driver included in the third sub - word - line driver block SDB3 can drive the first even - numbered word line WL1_even included in the first sub - memory cell array SMA1. The sub - word - line driver included in the third sub - word - line driver block SDB3 can further drive the third even - numbered word line WL3_even included in the third sub - memory cell array SMA3. The sub - word - line driver included in the fourth sub - word - line driver block SDB4 can drive the first even - numbered word line WL1_even included in the first sub - memory cell array SMA1. The sub - word - line driver included in the fourth sub - word - line driver block SDB4 can further drive the second even - numbered word line WL2_even included in the second sub - memory cell array SMA2.

[0072] The first odd word line WL1_odd included in the first sub memory cell array SMA1 can be driven by sub word line drivers included in the first sub word line driver block SDB1 and the second sub word line driver block SDB2. In this case, when the first odd word line WL1_odd is driven, word line drive voltages can be applied from opposite ends of the first odd word line WL1_odd, respectively. In this case, when the first odd word line WL1_odd is driven, the sub word line driver included in the first sub word line driver block SDB1 can apply the word line drive voltage in a first direction (e.g., the right direction), and when the first odd word line WL1_odd is driven, the sub word line driver included in the second sub word line driver block SDB2 can apply the word line drive voltage in a second direction opposite to the first direction (e.g., the left direction).

[0073] The first even word line WL1_even included in the first sub memory cell array SMA1 can be driven by sub word line drivers included in the third sub word line driver block SDB3 and the fourth sub word line driver block SDB4. In this case, when the first even word line WL1_even is driven, word line drive voltages are applied from opposite ends of the first even word line WL1_even, respectively. In this case, when the first even word line WL1_even is driven, the sub word line driver included in the third sub word line driver block SDB3 can apply the word line drive voltage in the first direction, and when the first even word line WL1_even is driven, the sub word line driver included in the fourth sub word line driver block SDB4 can apply the word line drive voltage in a second direction facing the first direction.

[0074] Since each of the first odd word line WL1_odd and the first even word line WL1_even included in the first sub memory cell array SMA1 can be supplied with the word line drive voltage from opposite ends, the slope of the voltage applied to each word line can be improved. Accordingly, the timing of driving each word line can be improved. This can mean an improvement in the performance of the semiconductor memory device 100.

[0075] According to an embodiment, the sub - word line drivers included in the first sub - word line driver block SDB1 may be disposed on one side of the region under the first sub - memory cell array SMA1. The sub - word line drivers included in the second sub - word line driver block SDB2 may be disposed in the region under the second sub - memory cell array SMA2 adjacent to the first sub - memory cell array SMA1. The sub - word line drivers included in the third sub - word line driver block SDB3 may be disposed in the region under the third sub - memory cell array SMA3 adjacent to the first sub - memory cell array SMA1 and facing away from the second sub - memory cell array SMA2. The sub - word line drivers included in the fourth sub - word line driver block SDB4 may be disposed in the region under the first sub - memory cell array SMA1. In this case, the sub - word line drivers included in the fourth sub - word line driver block SDB4 may be disposed on the opposite side of the first sub - word line driver block SDB1.

[0076] The first sub - word line driver block SDB1 and the second sub - word line driver block SDB2 may correspond to Figure 5 the odd - numbered sub - word line driver blocks OSDB, and the third sub - word line driver block SDB3 and the fourth sub - word line driver block SDB4 may correspond to the even - numbered sub - word line driver blocks ESDB.

[0077] Since multiple sub - word line driver blocks SDB can be disposed under multiple sub - memory cell arrays SMA, the planar size of the memory cell array can be reduced. Additionally, since the driving voltage can be supplied separately from the opposite ends of each word line, the operating performance of the semiconductor memory device 100 can be improved.

[0078] In Figure 8 the example shown, the first odd - numbered word lines WL1_odd, the second odd - numbered word lines WL2_odd, and the third odd - numbered word lines WL3_odd, and the first even - numbered word lines WL1_even, the second even - numbered word lines WL2_even, and the third even - numbered word lines WL3_even are shown as separate, but the embodiments are not limited thereto. For example, in some embodiments, the corresponding word lines included in the first odd - numbered word lines WL1_odd, the second odd - numbered word lines WL2_odd, and the third odd - numbered word lines WL3_odd, and the corresponding word lines included in the first even - numbered word lines WL1_even, the second even - numbered word lines WL2_even, and the third even - numbered word lines WL3_even may be alternately disposed in the plane.

[0079] Figure 9 is a diagram showing a part of a memory cell array structure according to an embodiment of the present disclosure. Referring to Figure 9 , the memory cell array structure MAS may include a data storage structure DSS and a signal routing structure SRS.

[0080] The data storage structure DSS may include a plurality of storage cells for storing data and bit lines for accessing the plurality of storage cells. However, as described above, for ease of description, the storage cells and bit lines may be omitted. The data storage structure DSS may include a plurality of sub-storage cell arrays SMA. Each of the plurality of sub-storage cell arrays SMA may include a plurality of word lines. The first sub-storage cell array SMA1 may include a first plurality of word lines WL1, the second sub-storage cell array SMA2 may include a second plurality of word lines WL2, and the third sub-storage cell array SMA3 may include a third plurality of word lines WL3. The second sub-storage cell array SMA2 may be disposed adjacent to one side of the first sub-storage cell array SMA1, and the third sub-storage cell array SMA3 may be disposed adjacent to the opposite side of the first sub-storage cell array SMA1 that faces away from the second sub-storage cell array SMA2.

[0081] The first plurality of word lines WL1, the second plurality of word lines WL2, and the third plurality of word lines WL3 included in the data storage structure DSS may be connected to at least one of the plurality of metal contacts MC11, MC12,..., MC64. For example, one end of the word line WL11 may be connected to the metal contact MC11, and the opposite end of the word line WL11 may be connected to the metal contact MC41. The word line WL12 may be connected to the metal contact MC31 and the metal contact MC21. The word line WL21 may be connected to the metal contact MC41. The word line WL22 may be connected to the metal contact MC21 and the metal contact MC61. The word line WL31 may be connected to the metal contact MC51 and the metal contact MC11. The word line WL32 may be connected to the metal contact MC31.

[0082] The plurality of metal contacts MC11 to MC64 may be formed in connection regions CNA1, CNA2, etc. For example, the metal contacts MC11, MC31, MC12, MC32, MC13, MC33, MC14, and MC34 may be formed in the first connection region CNA1 between the first sub-storage cell array SMA1 and the third sub-storage cell array SMA3. The metal contacts MC41, MC21, MC42, MC22, MC43, MC23, MC44, and MC24 may be formed in the second connection region CNA2 between the first sub-storage cell array SMA1 and the second sub-storage cell array SMA2. The metal contacts MC51, MC52, MC53, and MC54 may be formed in the third connection region CNA3. The metal contacts MC61, MC62, MC63, and MC64 may be formed in the fourth connection region CNA4.

[0083] The signal routing structure SRS may include an odd sub - word line driver metal pad OSWD_MP, an even sub - word line driver metal pad ESWD_MP, and multiple routing metal lines RML. The odd sub - word line driver metal pad OSWD_MP may correspond to Figure 6 some upper metal pads UMP. The odd sub - word line driver metal pad OSWD_MP may be electrically connected to Figure 5 the sub - word line drivers included in the odd sub - word line driver block OSDB. The odd sub - word line driver metal pad OSWD_MP may correspond to Figure 7 the odd sub - word line driver metal pad junction OSWD_MPJ. The even sub - word line driver metal pad ESWD_MP may correspond to Figure 6 the other upper metal pads UMP. The even sub - word line driver metal pad ESWD_MP may be electrically connected to Figure 5 the sub - word line drivers included in the even sub - word line driver block ESDB. The even sub - word line driver metal pad ESWD_MP may correspond to Figure 7 the even sub - word line driver metal pad junction ESWD_MPJ.

[0084] Each routing metal line RML may be electrically connected to a corresponding metal pad and a corresponding metal contact. For example, one routing metal line RML may connect an odd sub - word line driver metal pad OSWD_MP and a metal contact MC11. Another routing metal line RML may connect another odd sub - word line driver metal pad OSWD_MP and a metal contact MC12. Yet another routing metal line RML may connect an even sub - word line driver metal pad ESWD_MP and a metal contact MC21. And, yet another routing metal line RML may connect another even sub - word line driver metal pad ESWD_MP and a metal contact MC22.

[0085] For example, the sub - word line drivers included in the odd sub - word line driver block disposed below the first sub - memory cell array SMA1 can be electrically connected to the metal contacts MC11, MC12, MC13, and MC14 through the routing metal line RML. The sub - word line drivers included in the even sub - word line driver block disposed below the first sub - memory cell array SMA1 can be electrically connected to the metal contacts MC21, MC22, MC23, and MC24 through the routing metal line RML. The sub - word line drivers included in the odd sub - word line driver block disposed below the second sub - memory cell array SMA2 can be electrically connected to the metal contacts MC41, MC42, MC43, and MC44 through the routing metal line RML. The sub - word line drivers included in the even sub - word line driver block disposed below the second sub - memory cell array SMA2 can be electrically connected to the metal contacts MC61, MC62, MC63, and MC64 through the routing metal line RML. The sub - word line drivers included in the even sub - word line driver block disposed below the third sub - memory cell array SMA3 can be electrically connected to the metal contacts MC51, MC52, MC53, and MC54 through the routing metal line RML. The sub - word line drivers included in the even sub - word line driver block disposed below the third sub - memory cell array SMA3 can be electrically connected to the metal contacts MC31, MC32, MC33, and MC34 through the routing metal line RML. According to an embodiment, the routing metal line RML can be formed in one or more metal layers included in the memory cell array structure MAS. The routing metal line RML can correspond to Figure 6 the first metal line ML1.

[0086] When the sub - word line driver corresponding to the word line WL11 among the sub - word line drivers disposed below the first sub - memory cell array SMA1 applies a word line driving voltage, the word line driving voltage can be applied to the word line WL11 through the metal contact MC11. Additionally, the sub - word line driver corresponding to the word line WL11 among the sub - word line drivers disposed below the second sub - memory cell array SMA2 can apply the word line driving voltage simultaneously. In this case, the driving voltage can be applied to the word line WL11 through the metal contact MC41. Therefore, the word line WL11 can be supplied with the word line driving voltage from its opposite ends. Thus, the slope of the driving voltage can be improved, and the operating performance of the semiconductor memory device 100 can be improved.

[0087] Since multiple sub - word line drivers can be disposed not between the multiple sub - memory cell arrays SMA, but instead below the multiple sub - memory cell arrays SMA, the planar size of the memory cell array can be reduced.

[0088] Figure 10 is a diagram showing a word line and a sub - word line driver according to an embodiment of the present disclosure. Refer to Figure 10, the first sub-word line driver SWD1 can supply a word line driving voltage to the word line WL11 in a first direction, and the second sub-word line driver SWD2 can supply a word line driving voltage to the word line WL11 in a second direction facing the first direction.

[0089] A gap region G12 can be provided between the first sub-memory cell array SMA1 and the second sub-memory cell array SMA2, and a gap region G13 can be provided between the first sub-memory cell array SMA1 and the third sub-memory cell array SMA3. Metal contacts MC41 and MC21 can be formed in the gap region G12, and metal contacts MC11 and MC31 can be formed in the gap region G13. Each of the gap regions G12 and G13 in which the metal contacts MC11, MC21, MC31, and MC41 are formed can correspond to the above-described connection region.

[0090] The metal contact MC11 can contact the first end of the word line WL11 and the first end of the word line WL31. The metal contact MC21 can contact the first end of the word line WL12 and the first end of the word line WL22. The metal contact MC31 can contact the second end of the word line WL12 and the first end of the word line WL32. The metal contact MC41 can contact the second end of the word line WL11 and the first end of the word line WL21.

[0091] The first sub-word line driver SWD1 and the second sub-word line driver SWD2 can control the word line WL11 based on the word line control signal PXI1. The third sub-word line driver SWD3 and the fourth sub-word line driver SWD4 can control the word line WL12 based on the word line control signal PXI2.

[0092] The first sub-word line driver SWD1 can output a word line driving voltage having a first logic level (e.g., high logic level “H”) based on the word line control signal PXI1. The word line driving voltage output through the first sub-word line driver SWD1 can be transferred to the lower metal pad LMP1. The output word line driving voltage can be transferred to the upper metal pad UMP1 through the metal pad junction. The word line driving voltage can be transferred to the metal contact MC11 through the routing metal line RML1 formed in one or more metal layers. The output word line driving voltage can be applied to the word line WL11 from the metal contact MC11. Additionally, the output word line driving voltage can also be applied to the word line WL31 from the metal contact MC11.

[0093] The second sub-word line driver SWD2 may output a word line driving voltage having a high logic level "H" to the word line WL11 based on the word line control signal PXI1 being the same control signal as the first sub-word line driver SWD1. The word line driving voltage output through the second sub-word line driver SWD2 may be applied to the word line WL11 through the lower metal pad LMP2, the metal pad junction, the upper metal pad UMP2, the routing metal line RML2, and the metal contact MC41. Additionally, the output word line driving voltage may also be applied to the word line WL21.

[0094] The output voltage of the third sub-word line driver SWD3 may be applied to the word line WL12 and the word line WL32 through the lower metal pad LMP3, the metal pad junction, the upper metal pad UMP3, the routing metal line RML3, and the metal contact MC31. The output voltage of the fourth sub-word line driver SWD4 may be applied to the word line WL12 and the word line WL22 through the lower metal pad LMP4, the metal pad junction, the upper metal pad UMP4, the routing metal line RML4, and the metal contact MC21.

[0095] In the semiconductor memory device 100 according to an embodiment of the present disclosure, since the word line driving voltage may be applied to opposite ends of the word line WL11 through the metal contact MC11 and the metal contact MC41, the slope of the word line driving voltage may be improved compared to the case where the word line driving voltage is applied to only one end of the word line WL11.

[0096] According to an embodiment, a plurality of sub-word line drivers SWD may be disposed in the core peripheral circuit structure CPS below (or on the lower side of) the sub-memory cell arrays SMA1, SMA2, etc., rather than between the sub-memory cell arrays SMA1, SMA2, etc. Therefore, compared to a comparative example in which a plurality of sub-word line drivers SWD may be disposed on the same plane as the sub-memory cell arrays SMA1, SMA2, etc., the horizontal size of the semiconductor memory device 100 according to an embodiment of the present disclosure may be smaller.

[0097] Figure 11 is a circuit diagram showing the configuration of a sub-word line driver according to an embodiment of the present disclosure. Refer to Figure 11, a first sub - word - line driver SWD1 configured to drive word - line WL11 and word - line WL31 may include a first transistor 510_1, a second transistor 520_1, and a third transistor 530_1. The first transistor 510_1 may be a PMOS transistor and may operate as a pull - up transistor. A word - line enable signal NWEIB may be applied to the gate terminal of the first transistor 510_1, a word - line drive signal PXID1 may be applied to the source terminal of the first transistor 510_1, and the drain terminal of the first transistor 510_1 is connected to a lower metal pad LMP1. The first transistor 510_1 may output the word - line drive signal PXID1 to the lower metal pad LMP1 based on the word - line enable signal NWEIB.

[0098] The second transistor 520_1 may be an NMOS transistor and may operate as a pull - down transistor. The word - line enable signal NWEIB may be applied to the gate terminal of the second transistor 520_1, and the drain terminal and the source terminal of the second transistor 520_1 may be connected to the drain terminal of the first transistor 510_1 (or the lower metal pad LMP1) and the ground terminal, respectively.

[0099] The third transistor 530_1 may be an NMOS transistor and may operate as a holding transistor for keeping the corresponding word - lines WL11 and WL31 at the ground level when the corresponding word - lines WL11 and WL31 are not selected. An inverted word - line drive signal PXIB1 may be applied to the gate terminal of the third transistor 530_1, and the drain terminal and the source terminal of the third transistor 530_1 may be connected to the drain terminal of the first transistor 510_1 (or the lower metal pad LMP1) and the ground terminal, respectively.

[0100] The first transistor 510_1, the second transistor 520_1, and the third transistor 530_1 of the first sub - word - line driver SWD1 may be formed in a core - peripheral circuit structure CPS. For example, the first transistor 510_1, the second transistor 520_1, and the third transistor 530_1 may be formed in the transistor layer of the core - peripheral circuit structure CPS. The first transistor 510_1, the second transistor 520_1, and the third transistor 530_1 may be formed below (or on the lower side of) the first sub - memory cell array SMA1.

[0101] The second sub-word line driver SWD2 configured to drive word lines WL11 and WL21 may include a first transistor 510_2, a second transistor 520_2, and a third transistor 530_2. The first transistor 510_2 may be a PMOS transistor and may operate as a pull-up transistor. The first transistor 510_2 may output a word line drive signal PXID1 to a lower metal pad LMP2 based on a word line enable signal NWEIB. The second transistor 520_2 may be an NMOS transistor and may operate as a pull-down transistor. The third transistor 530_2 may be an NMOS transistor and may operate as a holding transistor for keeping the corresponding word lines WL11 and WL21 at a ground level when the corresponding word lines WL11 and WL21 are not selected.

[0102] The first transistor 510_2, the second transistor 520_2, and the third transistor 530_2 of the second sub-word line driver SWD2 may be formed in a core peripheral circuit structure CPS. For example, the first transistor 510_2, the second transistor 520_2, and the third transistor 530_2 may be formed in a transistor layer of the core peripheral circuit structure CPS. The first transistor 510_2, the second transistor 520_2, and the third transistor 530_2 may be formed below (or on the lower side of) a second sub-memory cell array SMA2.

[0103] The third sub-word line driver SWD3 may include a first transistor 510_3, a second transistor 520_3, and a third transistor 530_3. The fourth sub-word line driver SWD4 may include a first transistor 510_4, a second transistor 520_4, and a third transistor 530_4. Each of the first transistor 510_3 and the first transistor 510_4 may output a word line drive signal PXID2 to each of a lower metal pad LMP3 and a lower metal pad LMP4 based on a word line enable signal NWEIB. Each of the second transistor 520_3 and the second transistor 520_4 may be an NMOS transistor and may operate as a pull-down transistor. Each of the third transistor 530_3 and the third transistor 530_4 may be an NMOS transistor and may operate as a holding transistor for keeping the corresponding word lines WL12 and WL22 or the corresponding word lines WL12 and WL32 at a ground level when the corresponding word lines WL12 and WL22 or the corresponding word lines WL12 and WL32 are not selected.

[0104] The first transistor 510_3, the second transistor 520_3, and the third transistor 530_3 of the third sub-word line driver SWD3 may be formed in the core peripheral circuit structure CPS. For example, the first transistor 510_3, the second transistor 520_3, and the third transistor 530_3 may be formed in the transistor layer of the core peripheral circuit structure CPS. The first transistor 510_3, the second transistor 520_3, and the third transistor 530_3 may be formed below (or on the lower side of) the third sub-memory cell array SMA3.

[0105] The first transistor 510_4, the second transistor 520_4, and the third transistor 530_4 of the fourth sub-word line driver SWD4 may be formed in the core peripheral circuit structure CPS. For example, the first transistor 510_4, the second transistor 520_4, and the third transistor 530_4 may be formed in the transistor layer of the core peripheral circuit structure CPS. The first transistor 510_4, the second transistor 520_4, and the third transistor 530_4 may be formed below (or on the lower side of) the first sub-memory cell array SMA1.

[0106] When the word line WL11 is driven, the word line driving signal PXID1 having a high logic level "H" input through the first transistor 510_1 of the first sub-word line driver SWD1 may be applied to the word line WL11 through the lower metal pad LMP1, the upper metal pad UMP1, the routing metal line RML1, and the metal contact MC11. The word line driving signal PXID1 having a high logic level "H" input through the first transistor 510_2 of the second sub-word line driver SWD2 may be applied to the word line WL11 through the lower metal pad LMP2, the upper metal pad UMP2, the routing metal line RML2, and the metal contact MC41. For example, since the word line driving signal PXID1 having a high logic level "H" can be applied to the word line WL11 from the metal contact MC11 and the metal contact MC41, the slope of the word line driving voltage can be improved, and the performance of the semiconductor memory device 100 can be improved. In addition, the plurality of transistors 510_1, 520_1, …, 530_4 included in the plurality of sub-word line drivers SWD1, SWD2, SWD3, and SWD4 may be disposed in the transistor layer of the core peripheral circuit structure CPS below the memory cell array structure MAS. Therefore, the horizontal area of the semiconductor memory device 100 can be reduced.

[0107] Figure 12 is a diagram showing another example of a memory cell array structure according to an embodiment of the present disclosure. Refer to Figure 12 , the memory cell array structure MAS may include a data storage structure DSS and a signal routing structure SRS. The data storage structure DSS may include a fourth sub-memory cell array SMA4 and a fifth sub-memory cell array SMA5.

[0108] The fourth sub - memory cell array SMA4 may include a plurality of word lines WL4 (e.g., word lines WL41 to WL48), and the fifth sub - memory cell array SMA5 may include a plurality of word lines WL5 (e.g., word lines WL51 to WL58).

[0109] The fifth sub - memory cell array SMA5 corresponds to the outermost - set sub - memory cell array among the plurality of sub - memory cell arrays included in the data storage structure DSS. The area of the fifth sub - memory cell array SMA5 may be half of the area of the fourth sub - memory cell array SMA4. The number of memory cells provided at one word line of the fifth sub - memory cell array SMA5 may correspond to half of the number of memory cells provided at one word line of the fourth sub - memory cell array SMA4. The number of bit lines provided in the fifth sub - memory cell array SMA5 may be half of the number of bit lines provided in the fourth sub - memory cell array SMA4.

[0110] Each of the opposite ends of each of the word lines WL41 to WL48 included in the fourth sub - memory cell array SMA4 may be connected to each of the metal contacts MC71, MC72, …, MC78 and each of the metal contacts MC81, MC82, …, MC88.

[0111] The opposite ends of the word line WL51 included in the fifth sub - memory cell array SMA5 may be respectively connected to the metal contact MC81 and the metal contact MC91. The opposite ends of the word line WL53 may be respectively connected to the metal contact MC83 and the metal contact MC93. The opposite ends of the word line WL55 may be respectively connected to the metal contact MC85 and the metal contact MC95, and the opposite ends of the word line WL57 may be respectively connected to the metal contact MC87 and the metal contact MC97.

[0112] The even - numbered sub - word - line driver block and the odd - numbered sub - word - line driver block may be provided below the fourth sub - memory cell array SMA4.

[0113] The even - numbered sub - word - line driver block and the odd - numbered sub - word - line driver block may be provided below the fifth sub - memory cell array SMA5. The word - line drive voltage output from the sub - word - line driver included in the odd - numbered sub - word - line driver block may be transferred to the memory cell array structure MAS through the odd - numbered sub - word - line driver metal pad OSWD_MP. The odd - numbered sub - word - line driver block may apply the word - line drive voltage to the opposite ends of the word line WL51 through the metal contact MC81 and the metal contact MC91.

[0114] Figure 12 An example of one outermost side of the memory cell array is shown, and the other outermost side away from this one outermost side may be similar to Figure 12The example shown. However, the even sub - word line driver block can be disposed below another outermost sub - memory cell array. The even sub - word line driver block can apply a word line driving voltage to opposite ends of each even - numbered word line among the word lines included in another outermost sub - memory cell array.

[0115] Figure 13 FIG. is a diagram showing another example of a word line and a sub - word line driver according to an embodiment of the present disclosure. Refer to Figure 13 , the seventh sub - word line driver SWD7 can apply a word line driving voltage to opposite ends of the word line WL51.

[0116] The fifth sub - memory cell array SMA5 can correspond to the outermost - disposed sub - memory cell array among a plurality of sub - memory cell arrays.

[0117] The seventh sub - word line driver SWD7 can be disposed below the fifth sub - memory cell array SMA5. The seventh sub - word line driver SWD7 can output a word line driving voltage based on a word line control signal PXI3. The output word line driving voltage can be transmitted to the metal contact MC81 and the metal contact MC91 through the lower metal pad LMP7, the upper metal pad UMP7, the routing metal line RML7_1, and the routing metal line RML7_2, respectively. The output word line driving voltage can be applied to opposite ends of the word line WL51 through the metal contact MC81 and the metal contact MC91, respectively.

[0118] Figure 14 FIG. is a diagram showing the slope of the driving voltage at each position according to an embodiment of the present disclosure. As Figure 14 shown, the slope of the word line driving voltage can be improved.

[0119] Case 1 indicates a case where a word line driving voltage having a high logic level “H” is applied only to one end of a word line in a semiconductor memory device. For example, the first end of the word line WL1 can be connected to the metal contact MC1, and its second end can be floating. In the structure corresponding to Case 1, when a voltage having a high logic level “H” is applied to the metal contact MC1 when driving the word line WL1, the voltage VL1 at the position L1 of the word line WL1 close to the metal contact MC1 can have a relatively good slope. In this case, the voltage VL2 at the position L2 corresponding to the floating opposite end will have the worst slope. Since the semiconductor memory device operates based on the worst timing to ensure data integrity, the performance of the semiconductor memory device will be relatively low.

[0120] Case 2 indicates a case where a word line driving voltage having a high logic level “H” can be applied to opposite ends of a word line WL2 in a semiconductor memory device 100 according to an embodiment of the present disclosure. For example, a first end of the word line WL2 can be connected to a metal contact MC2, and its opposite end is connected to a metal contact MC3. In the structure corresponding to Case 2, voltages VL3 and VL5 at positions L3 and L5 close to the metal contact MC2 and the metal contact MC3 can have a relatively good slope, and a voltage VL4 at a central position L4 of the word line WL2 can correspond to a position having the worst slope among positions on the word line WL2. The worst slope of the voltage VL4 in Case 2 can be improved more than the slope of the voltage VL2 at the floating second end in Case 1. In addition, the worst slope of the voltage VL4 in Case 2 can be improved more than the slope of the central portion of the word line WL1 in Case 1. Therefore, since the timing associated with word line driving can be improved, the operating performance of the semiconductor memory device 100 in Case 2 can be improved more than the operating performance of the semiconductor memory device having the structure of Case 1.

[0121] Figure 15A is a diagram showing the layout of a sub memory cell array of a semiconductor memory device according to an embodiment of the present disclosure, and Figure 15B is a diagram showing Figure 15A the layout of a core peripheral circuit corresponding to the sub memory cell array of Figure 15A , the memory cell array MCA can include sub memory cell arrays SMAa, SMAb, …, SMAj. Each of the sub memory cell arrays SMAa, SMAb, …, SMAj can include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells.

[0122] The sub - memory cell arrays SMAa to SMAe can be arranged in the first row, and the sub - memory cell arrays SMAf to SMAj can be arranged in the second row. The sub - memory cell array SMAa can be the sub - memory cell array disposed at the first side end of the first row, and the sub - memory cell array SAMe can be the sub - memory cell array disposed at the second side end of the first row. The sub - memory cell array SMAf can be the sub - memory cell array disposed at the first side end of the second row, and the sub - memory cell array SMAj can be the sub - memory cell array disposed at the second side end of the second row. The word - line connection region WLB or the bit - line connection region BLB can be arranged in the gap region or the outer region of the sub - memory cell arrays SMAa, SMAb, …, SMAj. The word - line connection region WLB can be arranged in the gap between the sub - memory cell arrays in the same row, or can be arranged outside the sub - memory cell arrays in the same row. The bit - line connection region BLB can be arranged in the gap between the sub - memory cell arrays in the same column, or can be arranged outside the sub - memory cell arrays in the same column. Metal contacts for transmitting signals to the word lines included in the sub - memory cell arrays can be formed in the word - line connection region WLB. Metal contacts for transmitting signals to the bit lines included in the sub - memory cell arrays can be formed in the bit - line connection region BLB.

[0123] Reference Figure 15B , the core peripheral circuit CPC can include a plurality of peripheral circuits corresponding to the sub - memory cell arrays SMAa, SMAb, …, SMAj respectively. For example, the core peripheral circuit CPC can include a first bit - line sense amplifier circuit BLSA1a, a second bit - line sense amplifier circuit BLSA2a, and an odd - numbered sub - word - line driver block OSDBa corresponding to the sub - memory cell array SMAa. The first bit - line sense amplifier circuit BLSA1a can be connected to some of the bit lines included in the sub - memory cell array SMAa, and the second bit - line sense amplifier circuit BLSA2a can be connected to the other bit lines included in the sub - memory cell array SMAa. The first bit - line sense amplifier circuit BLSA1a and the second bit - line sense amplifier circuit BLSA2a can control the bit lines of the sub - memory cell array SMAa, and can read and amplify the voltage levels of the bit lines. The odd - numbered sub - word - line driver block OSDBa can include a plurality of sub - word - line drivers. The sub - word - line drivers included in the odd - numbered sub - word - line driver block OSDBa can drive the odd - numbered word lines of the sub - memory cell array SMAa and the sub - memory cell array SMAb.

[0124] In addition, the core peripheral circuit CPC may further include a first bit line sense amplifier circuit BLSA1b, a second bit line sense amplifier circuit BLSA2b, an odd sub-word line driver block OSDBb, and an even sub-word line driver block ESDBb corresponding to the sub memory cell array SMAb. The first bit line sense amplifier circuit BLSA1b and the second bit line sense amplifier circuit BLSA2b may control the bit lines of the sub memory cell array SMAb, and may read and amplify the voltage levels of the bit lines. The even sub-word line driver block ESDBb may include a plurality of sub-word line drivers. The sub-word line drivers included in the even sub-word line driver block ESDBb may drive the even bit lines of the sub memory cell array SMAa and the sub memory cell array SMAb. The odd sub-word line driver block OSDBb may include a plurality of sub-word line drivers. The sub-word line drivers included in the odd sub-word line driver block OSDBb may drive the odd bit lines of the sub memory cell array SMAb and the sub memory cell array SMAc.

[0125] Similarly, the core peripheral circuit CPC may further include first bit line sense amplifier circuits BLSA1c to BLSA1j, second bit line sense amplifier circuits BLSA2c to BLSA2j, odd sub-word line driver blocks OSDBc to OSDBi, and even sub-word line driver blocks ESDBc to ESDBj.

[0126] Figure 15A and Figure 15B The sub memory cell arrays SMAa to SMAj and the peripheral circuits may be in the shape of a matrix having two rows and five columns, but this is only an example, and the embodiments are not limited thereto. The number of rows of the sub memory cell arrays included in the memory cell array MCA may be increased or decreased. Additionally, the number of columns of the sub memory cell arrays may be increased or decreased.

[0127] Figure 16 is a diagram depicting an integrated circuit device. Referring to Figure 16 , the integrated circuit device may include a memory cell array structure MAS and a core peripheral circuit structure CPS.

[0128] The memory cell array structure MAS may be formed on a first substrate 310. The memory cell array structure MAS may include a data storage structure DSS and a signal routing structure SRS. The data storage structure DSS may include a plurality of memory cells each having a storage capacitor C and a select transistor TR, a plurality of bit lines, and a plurality of word lines. The signal routing structure SRS may include a plurality of upper metal pads UMP and a plurality of metal lines ML. The plurality of metal lines ML may provide electrical connections between the plurality of upper metal pads UMP and components of the data storage structure DSS. For example, the plurality of metal lines ML may provide electrical connections between some of the plurality of upper metal pads UMP and the bit lines or between some of the plurality of upper metal pads UMP and the word lines.

[0129] The core-periphery circuit structure CPS can be formed on the second substrate 320. The core-periphery circuit structure CPS can include a transistor layer TRL. A plurality of transistors for driving the memory cell array structure MAS can be disposed on the transistor layer TRL. Some of the plurality of transistors disposed in the transistor layer TRL can be included in a bit line sense amplifier. Other transistors of the plurality of transistors disposed in the transistor layer TRL can be included in a sub-word line driver. Still other transistors of the plurality of transistors disposed in the transistor layer TRL can be included in any other peripheral circuit for the operation of the integrated circuit device.

[0130] A plurality of upper metal pads UMP and a plurality of lower metal pads LMP can be disposed at corresponding positions with respect to each other and provide electrical connection between components formed in the first substrate 310 and components formed in the second substrate 320. The plurality of upper metal pads UMP and the plurality of lower metal pads LMP can constitute a pad array PDA.

[0131] Figure 17 is a diagram showing Figure 16 a plan view of the pad array PDA of the integrated circuit device. Referring Figure 17 to, the pad array PDA can include a plurality of bit line pads BL_PAD and a plurality of word line pads WL_PAD. The pad array PDA can correspond to Figure 16 the plurality of upper metal pads UMP shown. The lower metal pad LMP1 can be disposed similarly to the upper metal pad UMP.

[0132] The plurality of bit line pads BL_PAD can be disposed in a first peripheral region of the plane and a second peripheral region of the plane that is opposite to the first peripheral region. The plurality of bit line pads BL_PAD can be electrically connected to a bit line connection region BLB through one or more metal layers. Signals received through the plurality of bit line pads BL_PAD disposed in the first peripheral region can be routed to a bit line connection region BLBa outside the first peripheral region, and signals received through the plurality of bit line pads BL_PAD disposed in the second peripheral region can be routed to a bit line connection region BLBb outside the second peripheral region.

[0133] The plurality of word line pads WL_PAD can be electrically connected to a word line connection region WLB through one or more metal layers. Signals received through the plurality of word line pads WL_PAD can be routed to the word line connection region WLB.

[0134] The bit line connection regions BLBa and BLBb can provide electrical connections between a plurality of bit line pads BL_PAD and the bit lines included in the memory cell array. The word line connection region WLB can provide electrical connections between a plurality of word line pads WL_PAD and the word lines included in the memory cell array.

[0135] Figure 18A is a vertical cross-sectional view of an integrated circuit device taken along line A-A' of Figure 17 . Referring to Figure 18A , a bit line sense amplifier circuit provided in the transistor layer TRL can be electrically connected to the bit line BL.

[0136] Components other than the components that provide the electrical connection between the bit line sense amplifier circuit provided in the transistor layer TRL and the bit line BL (e.g., adjacent metal pads) can be omitted. The bit line sense amplifier circuit provided in the transistor layer TRL can be electrically connected to the lower metal pad LMP0 through metal lines M0, M1, M2, M3, M4, and M5. The lower metal pad LMP0 can physically and electrically contact the upper metal pad UMP0. The upper metal pad UMP0 can be electrically connected to a plurality of metal lines LM3, LM2, LM1, and LM0. The metal line LM0 can be connected to the bit line BL through a metal contact MC0. The metal contact MC0 can be formed in the bit line connection region BLBa of FIG. 15. The potential change caused by the memory capacitor C and the select transistor TR to the bit line BL can be applied (or transmitted) to the transistor layer TRL through a plurality of metal lines LM0 to LM3, the upper metal pad UMP0, the lower metal pad LMP0, and a plurality of metal lines M0 to M5. The bit line sense amplifier provided in the transistor layer TRL can read the data stored in the memory capacitor C by amplifying the potential change of the bit line BL. The data storage structure DSS can include a plurality of capacitors C, a plurality of select transistors TR, and a plurality of bit lines BL. The signal routing structure SRS can include a plurality of metal lines LM0 to LM3 and the upper metal pad UMP0.

[0137] Figure 18B is a vertical cross-sectional view of an integrated circuit device taken along line B-B' of Figure 17 . Referring to Figure 18B , a sub-word line driver provided in the transistor layer TRL can be electrically connected to the word line WL.

[0138] Components other than those that provide an electrical connection between the sub-word line driver provided in the transistor layer TRL and the word line WL (e.g., adjacent metal pads) may be omitted. The sub-word line driver provided in the transistor layer TRL may be electrically connected to the lower metal pad LMP1 through metal lines M0, M1, M2, M3, M4, and M5. The lower metal pad LMP1 may physically and electrically contact the upper metal pad UMP1. The upper metal pad UMP1 may be electrically connected to a plurality of metal lines LM3, LM2, LM1, and LM0. The metal line LM0 may be connected to the word line WL through the metal contact MC0. The metal contact MC0 may be formed in the word line connection region WLB of FIG. 15. The word line drive voltage output by the sub-word line driver may be applied to the word line WL through a plurality of metal lines M0 to M5, the lower metal pad LMP1, the upper metal pad UMP1, a plurality of metal lines LM0 to LM3, and the metal contact MC0. The selection transistor TR may be switched by the word line drive voltage applied to the word line WL, and thus, the bit line BL and the storage capacitor C may be connected. The data storage structure DSS may include a plurality of storage capacitors C, a plurality of selection transistors TR, a plurality of bit lines BL, and a plurality of word lines WL. The signal routing structure SRS may include a plurality of metal lines LM0 to LM3 and the upper metal pad UMP1.

[0139] As described above, a semiconductor memory device according to an embodiment of the present disclosure may have a structure in which opposite ends of a word line may be connected to a sub-word line driver. According to the above structure, an operating voltage may be applied to the opposite ends of the word line. Therefore, the slope of the drive voltage applied to the sub-word line may be improved, and the performance of the semiconductor memory device may be improved.

[0140] A semiconductor memory device according to an embodiment of the present disclosure may have a structure in which opposite ends of a word line may be respectively connected to a sub-word line driver. According to the above structure, an operating voltage may be applied to the opposite ends of the word line. Therefore, the slope of the drive voltage applied to the sub-word line may be improved, and the performance of the semiconductor memory device may be improved.

[0141] Although some embodiments of the present disclosure have been described above, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A first semiconductor structure, the first semiconductor structure including a first sub - memory cell array and a plurality of upper metal pads, the first sub - memory cell array including a first plurality of word lines, a plurality of bit lines, and a plurality of memory cells, the plurality of upper metal pads being electrically connected to the first plurality of word lines and the plurality of bit lines; and A second semiconductor structure, the second semiconductor structure being disposed below the first semiconductor structure and including a plurality of sub - word line drivers and a plurality of lower metal pads electrically connected to the plurality of sub - word line drivers, Wherein, the plurality of sub - word line drivers include: A first sub - word line driver configured to supply a word line driving voltage to a first end of a first word line among the first plurality of word lines, A second sub - word line driver configured to supply the word line driving voltage to a second end of the first word line, A third sub - word line driver configured to supply the word line driving voltage to a first end of a second word line among the first plurality of word lines, and A fourth sub - word line driver configured to supply the word line driving voltage to a second end of the second word line, and Wherein, each of the plurality of upper metal pads is bonded to a corresponding one of the plurality of lower metal pads one - to - one.

2. The semiconductor memory device according to claim 1, wherein, Each of the first sub - word line driver to the fourth sub - word line driver includes a first transistor, a second transistor, and a third transistor, Wherein, a gate terminal of the first transistor is configured to receive a word line enable signal, a source terminal of the first transistor is configured to receive a corresponding word line driving signal, and a drain terminal of the first transistor is electrically connected to a word line among the first plurality of word lines, Wherein, a gate terminal of the second transistor is configured to receive the word line enable signal, a drain terminal of the second transistor is connected to the drain terminal of the first transistor, and a source terminal of the second transistor is connected to ground, and Wherein, a gate terminal of the third transistor is configured to receive a corresponding inverted word line driving signal, a drain terminal of the third transistor is connected to the drain terminal of the first transistor, and a source terminal of the third transistor is connected to the ground.

3. The semiconductor memory device according to claim 1, wherein, The first sub - word line driver and the fourth sub - word line driver are located in a region below the first sub - memory cell array.

4. The semiconductor memory device according to claim 3, wherein, The first semiconductor structure further includes: A second sub - memory cell array adjacent to a first side of the first sub - memory cell array; and A third sub - memory cell array adjacent to a second side of the first sub - memory cell array opposite to the second sub - memory cell array, Wherein, the second sub - word line driver is located in a region below the second sub - memory cell array, and Wherein, the third sub - word line driver is located in a region below the third sub - memory cell array.

5. The semiconductor memory device according to claim 4, wherein, The third sub-word line driver is configured to supply the word line driving voltage to a first end of a first word line among a third plurality of word lines provided in the third sub memory cell array, and wherein the fourth sub-word line driver is configured to supply the word line driving voltage to a first end of a second word line among a second plurality of word lines provided in the second sub memory cell array.

6. The semiconductor memory device according to claim 3, wherein, The second semiconductor structure further includes: a first bit line sense amplifier circuit connected to some of the plurality of bit lines; and a second bit line sense amplifier circuit connected to other ones of the plurality of bit lines.

7. The semiconductor memory device according to claim 6, wherein, The first bit line sense amplifier circuit is located in a first outermost region included in the region under the first sub memory cell array, wherein the second bit line sense amplifier circuit is located in a second outermost region included in the region under the first sub memory cell array, and wherein the second outermost region faces away from the first outermost region.

8. The semiconductor memory device according to claim 7, wherein, The first sub-word line driver and the fourth sub-word line driver are located in a region between the first outermost region and the second outermost region and included in the region under the first sub memory cell array.

9. The semiconductor memory device according to claim 1, wherein, The first word line is an odd-numbered word line among the first plurality of word lines, and the second word line is an even-numbered word line among the first plurality of word lines.

10. A semiconductor memory device, the semiconductor memory device including: a memory cell array structure located on a first substrate and including a plurality of sub memory cell arrays, the plurality of sub memory cell arrays including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells; a core peripheral circuit structure located on a second substrate under the first substrate, wherein the core peripheral circuit structure includes a first sub-word line driver block, a second sub-word line driver block, a third sub-word line driver block, and a fourth sub-word line driver block, the first sub-word line driver block being configured to supply a word line driving voltage to a first end of a first odd-numbered word line among a first plurality of word lines in a first sub memory cell array among the plurality of sub memory cell arrays, the second sub-word line driver block being configured to supply the word line driving voltage to a second end of the first odd-numbered word line, the third sub-word line driver block being configured to supply the word line driving voltage to a first end of a first even-numbered word line among the first plurality of word lines, and the fourth sub-word line driver block being configured to supply the word line driving voltage to a second end of the first even-numbered word line; and a plurality of metal pad junctions electrically connecting the memory cell array structure and the core peripheral circuit structure.

11. The semiconductor memory device according to claim 10, wherein, The first sub-word line driver block and the fourth sub-word line driver block are located in a region under the first sub memory cell array.

12. The semiconductor memory device according to claim 11, wherein, The second sub - word - line driver block is located in a region below a second sub - memory cell array among the plurality of sub - memory cell arrays. The second sub - memory cell array is adjacent to the first sub - memory cell array in a direction towards the first plurality of word lines, and wherein, the third sub - word - line driver block is located in a region below a third sub - memory cell array among the plurality of sub - memory cell arrays. The third sub - memory cell array faces away from the second sub - memory cell array and is adjacent to the first sub - memory cell array.

13. The semiconductor memory device according to claim 12, wherein, The first sub - word - line driver block is further configured to supply the word - line driving voltage to a first end of a third odd - numbered word line among a third plurality of word lines in the third sub - memory cell array, wherein, the second sub - word - line driver block is further configured to supply the word - line driving voltage to a first end of a second odd - numbered word line among a second plurality of word lines in the second sub - memory cell array, wherein, the third sub - word - line driver block is further configured to supply the word - line driving voltage to a first end of a third even - numbered word line among the third plurality of word lines, and wherein, the fourth sub - word - line driver block is further configured to supply the word - line driving voltage to a first end of a second even - numbered word line among the second plurality of word lines.

14. The semiconductor memory device according to claim 10, wherein, The first odd - numbered word lines and the first even - numbered word lines are arranged alternately.

15. The semiconductor memory device according to claim 11, wherein, The core - peripheral circuit structure further includes: A first bit - line sense amplifier circuit electrically connected to a first bit line among a plurality of bit lines in the first sub - memory cell array; and A second bit - line sense amplifier circuit electrically connected to a second bit line among the plurality of bit lines in the first sub - memory cell array, wherein, the first bit - line sense amplifier circuit is located in a first outermost region included in the region below the first sub - memory cell array, wherein, the second bit - line sense amplifier circuit is located in a second outermost region included in the region below the first sub - memory cell array, and wherein, the second outermost region faces away from the first outermost region.

16. The semiconductor memory device according to claim 15, wherein, The first sub - word - line driver block and the second sub - word - line driver block are located between the first outermost region and the second outermost region.

17. A semiconductor memory device, the semiconductor memory device includes: A first substrate; A first sub - memory cell array located on the first substrate and including a first plurality of word lines; A plurality of upper metal pads arranged in a matrix array shape on the first sub - memory cell array; One or more first metal layers electrically connecting the plurality of upper metal pads to opposite ends of each word line among the first plurality of word lines; A second substrate located on the lower side of the first substrate; A transistor layer located on the second substrate and including a plurality of sub - word - line drivers; A plurality of lower metal pads, the plurality of lower metal pads being in the matrix array shape on the upper side of the transistor layer, wherein each lower metal pad among the plurality of lower metal pads is bonded to a corresponding upper metal pad among the plurality of upper metal pads; and One or more second metal layers, the one or more second metal layers electrically connecting the plurality of lower metal pads to the transistor layer, Wherein each first sub-word line driver among the plurality of first sub-word line drivers included in the plurality of sub-word line drivers is electrically connected to a first metal contact formed at a first end of a corresponding odd-numbered word line among the plurality of odd-numbered word lines included in the first plurality of word lines, Wherein each second sub-word line driver among the plurality of second sub-word line drivers included in the plurality of sub-word line drivers is electrically connected to a second metal contact formed at a second end of the corresponding odd-numbered word line, Wherein each third sub-word line driver among the plurality of third sub-word line drivers included in the plurality of sub-word line drivers is electrically connected to a third metal contact formed at a first end of a corresponding even-numbered word line among the plurality of even-numbered word lines included in the first plurality of word lines, and Wherein each fourth sub-word line driver among the plurality of fourth sub-word line drivers included in the plurality of sub-word line drivers is electrically connected to a fourth metal contact formed at a second end of the corresponding even-numbered word line.

18. The semiconductor memory device according to claim 17, the semiconductor memory device further comprising: A second sub-memory cell array, the second sub-memory cell array being adjacent to a first side of the first sub-memory cell array; And A third sub-memory cell array, the third sub-memory cell array being adjacent to a second side of the first sub-memory cell array opposite to the second sub-memory cell array, Wherein the plurality of first sub-word line drivers and the plurality of fourth sub-word line drivers are located in a region below the first sub-memory cell array, Wherein the plurality of second sub-word line drivers are located in a region below the second sub-memory cell array, and Wherein the plurality of third sub-word line drivers are located in a region below the third sub-memory cell array.

19. The semiconductor memory device according to claim 18, wherein, A second odd-numbered word line among the second plurality of word lines included in the second sub-memory cell array is electrically connected to the plurality of second sub-word line drivers through the second metal contact, Wherein a second even-numbered word line among the second plurality of word lines is electrically connected to the plurality of fourth sub-word line drivers through the fourth metal contact, Wherein a third odd-numbered word line among the third plurality of word lines included in the third sub-memory cell array is electrically connected to the plurality of first sub-word line drivers through the first metal contact, and Wherein a third even-numbered word line among the third plurality of word lines is electrically connected to the plurality of third sub-word line drivers through the third metal contact.

20. The semiconductor memory device according to claim 19, wherein, The first metal contact and the third metal contact are located in a first connection region between the first sub-memory cell array and the third sub-memory cell array, and Wherein, the second metal contact and the fourth metal contact are located in a second connection region between the first sub-storage cell array and the second sub-storage cell array.

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