Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and is applied to the technical field of semiconductors. According to the semiconductor device, the dielectric layer serving as the side wall in the second region is arranged in the first region in an extending manner, so that a new structure of the semiconductor device is provided, and the purpose of improving the efficiency and the reliability of the semiconductor device is achieved at the same time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor structure device and a manufacturing method thereof. Background Art

[0002] With the trend of miniaturization of various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For a dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length within the same semiconductor substrate to reduce the leakage of the capacitive structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is formed by aggregating a large number of memory cells to form an array region for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the memory cell density in the array region must be continuously increased, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technologies or structures need to be further improved to effectively improve the performance and reliability of related memory devices. Summary of the Invention

[0003] The purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof to reduce the probability of bit line collapse or tilt and improve the reliability and performance of the semiconductor device.

[0004] To solve the above technical problems, an embodiment of the present invention provides a semiconductor device, including: a substrate;

[0005] A plurality of bit lines extending along a second direction and disposed on the substrate separately from each other in a first direction perpendicular to the second direction;

[0006] A first dielectric layer located outside the bit lines;

[0007] A second dielectric layer located outside the first dielectric layer;

[0008] A spacer structure, including:

[0009] A third dielectric layer located between adjacent bit lines and in direct contact with the bit lines;

[0010] A fourth dielectric layer extending along the second direction through the first dielectric layer and overlapping with the second dielectric layer within the second dielectric layer.

[0011] Optionally, the plurality of bit lines may include a plurality of first bit lines and at least one second bit line, and the at least one second bit line is disposed outside all of the first bit lines.

[0012] Optionally, the bit line includes a semiconductor layer and a metal layer stacked in sequence from bottom to top, the metal layer contacts the fourth dielectric layer and has a width in the first direction smaller than that when it contacts the third dielectric layer in the first direction;

[0013] Wherein, in the first direction, the width of the first portion is smaller than the width of the second portion.

[0014] Optionally, the third dielectric layer may be located on both sidewalls of the first bit line and at least one sidewall of the second bit line.

[0015] Optionally, the first dielectric layer and the second dielectric layer may further extend to cover one sidewall of the second bit line.

[0016] Optionally, the semiconductor device may further include:

[0017] A fifth dielectric layer, located outside the second dielectric layer.

[0018] Optionally, the ends of the fourth dielectric layer between adjacent bit lines may be connected.

[0019] Optionally, the fourth dielectric layer with connected ends may include a U shape or an ellipse extending in the second direction.

[0020] Optionally, the semiconductor device may further include:

[0021] A filling layer, located in the fourth dielectric layer with connected ends.

[0022] Optionally, the filling layer may further extend along the second direction and fill into partial gaps between adjacent third dielectric layers.

[0023] Optionally, the semiconductor device may further include:

[0024] A plurality of word line structures, extending in the first direction and disposed in the substrate separately from each other in the second direction.

[0025] Optionally, the semiconductor device may further include:

[0026] A plurality of insulating structures, disposed separately in gaps defined by the third dielectric layer on sidewalls of adjacent bit lines and aligned with the word line structures.

[0027] Optionally, the semiconductor device may further include:

[0028] A plurality of conductive plugs are disposed between adjacent ones of the insulating structures.

[0029] To solve the above technical problems, embodiments of the present invention provide a method for manufacturing a semiconductor device, including:

[0030] Providing a substrate;

[0031] Forming a plurality of bit lines extending in a second direction and disposed on the substrate separated from each other in a first direction perpendicular to the second direction;

[0032] Forming a first dielectric layer outside the bit lines;

[0033] Forming a second dielectric layer outside the first dielectric layer;

[0034] Forming a spacer structure, including:

[0035] A third dielectric layer located between adjacent ones of the bit lines and in direct contact with the bit lines;

[0036] A fourth dielectric layer extending in the second direction through the first dielectric layer and overlapping with the second dielectric layer within the second dielectric layer.

[0037] Optionally, ends of the fourth dielectric layer between adjacent ones of the bit lines are connected.

[0038] Optionally, the fourth dielectric layer with connected ends includes a U shape or an ellipse extending in the second direction.

[0039] As described above, a semiconductor device and a method for manufacturing the same provided by the present invention may specifically include a first dielectric layer outside the bit lines, a second dielectric layer outside the first dielectric layer, and a spacer structure composed of a third dielectric layer and a fourth dielectric layer. Moreover, the third dielectric layer and the fourth dielectric layer in the spacer structure may be located at different positions of the bit lines. For example, the third dielectric layer is located on the sidewalls of the bit lines along the second direction, while the fourth dielectric layer extends through the first dielectric layer along the second direction and overlaps with the second dielectric layer within the second dielectric layer. By extending the dielectric layers (the first dielectric layer, the second dielectric layer, and the fifth dielectric layer) serving as sidewalls in the second region to the outside of the bit lines in the first region, a new structure of the semiconductor device is proposed. And by providing a filling layer between adjacent bit lines, adjacent bit lines are isolated and the portions of adjacent bit lines extending in the second region are squeezed and supported, thereby reducing the probability of bit line collapse or tilt, that is, ultimately achieving the purpose of improving the performance and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are used to provide a further understanding of the present application and form a part of the specification. Together with the following detailed description, they are used to explain the present application, but do not constitute a limitation to the present application. In the accompanying drawings:

[0041] Figures 1 to 9 are schematic structural diagrams during the preparation process of the manufacturing method of the semiconductor device provided in the first and second embodiments of the present invention; wherein,

[0042] Figure 6 is a top view of the semiconductor device in the first embodiment of the present invention;

[0043] Figure 8 is a top view of the semiconductor device in the second embodiment of the present invention;

[0044] Figures 10 to 18 are schematic structural diagrams during the preparation process of the manufacturing method of the semiconductor device provided in the third and fourth embodiments of the present invention; wherein,

[0045] Figure 15 is a top view of the semiconductor device in the third embodiment of the present invention;

[0046] Figure 18 is a top view of the semiconductor device in the fourth embodiment of the present invention.

[0047] Among them, the reference numerals are:

[0048] 100 - substrate, 100A - first region, 100B - second region, AR - active region, D1 - first direction, D2 - second direction, D3 - third direction, 101 - trench isolation structure, 110 - insulating layer, 120 - word line structure, 130 - bit line, 131 - first bit line, 131a - first part of the first bit line, 131b - second part of the first bit line, 132 - second bit line, d1 - width of the first bit line on the first region in the first direction, d2 - width of the first bit line on the second region in the first direction, 1301 - semiconductor layer, 1302 - barrier layer, 1303 - metal layer, 1304 - capping layer, 140 - spacer structure, 141 - third dielectric layer, 142 - fourth dielectric layer, 151 - first dielectric layer, 152 - second dielectric layer, 153 - fifth dielectric layer, 160 - filling material layer, 160' / 160'' - filling layer, 170 - insulating structure, 180 - conductive plug.

[0049] In the accompanying drawings, the same components are denoted by the same reference numerals, and the drawings are not drawn to actual scale. Detailed Description

[0050] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further elaborated in detail below in conjunction with the drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present invention and to be able to fully convey the scope of the present invention to those skilled in the art.

[0051] The present invention will be described more specifically by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present invention will be clearer according to the following description and the claims. It should be noted that the drawings are all in a very simplified form and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It can be understood that the meanings of "on...", "above...", and "overhead...", etc. in the present invention should be interpreted in the broadest way, so that "on..." not only means "on" something "without any intermediate features or layers (i.e., directly on something)", but also includes the meaning of having intermediate features or layers "on" something. In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0052] For the convenience of understanding, the first direction, the second direction, and the third direction are defined below, where the first direction and the second direction are directions parallel to the surface of the substrate, corresponding to D1 and D2 in the drawings respectively, and the two are perpendicular to each other. The third direction is perpendicular to the plane where the first direction and the second direction are located and is a direction perpendicular to the surface of the substrate, corresponding to D3 in the drawings, hereinafter simply referred to as the first direction D1, the second direction D2, and the third direction D3.

[0053] Please refer to Figure 6 and Figure 7 , Figure 6 is a top view of the semiconductor device in the first embodiment of the present invention, Figure 7 is Figure 6 a partial structural cross-sectional view of the semiconductor device shown along the AA' tangent. The semiconductor device of the present invention can be used to manufacture a dynamic random access memory (DRAM). Without departing from the spirit of the present invention, the present invention can also be applied to other types of memories.

[0054] As Figure 6 and Figure 7As shown, the semiconductor device in the first embodiment of the present invention includes a substrate 100, a plurality of bit lines 130, a first dielectric layer 151, a second dielectric layer 152, and a plurality of spacer structures 140. Among them, the substrate 100 may include a first region 100A and a second region 100B; exemplarily, the first region 100A is, for example, a storage area (cell region) including semiconductor devices with a relatively high component integration density, and the second region 100B is, for example, a periphery region (periphery region) including semiconductor devices with a relatively low component integration density, and the first region 100A and the second region 100B are, for example, arranged adjacent to each other. In the embodiments of the present invention Figures 1 to 18 Most of the drawings only show cross-sectional views of the corresponding structures in the first region 100A, while some drawings show top views of the corresponding structures on the first region 100A and a small part of the second region 100B. And due to the setting of the AA' tangent position, the word line structure 120 cannot be reflected in the cross-sectional view.

[0055] Specifically, a plurality of trench isolation structures 101 (shallow trench isolation, STI) are provided in the substrate 100 to define a plurality of active regions AR (active area, AA) in the substrate 100, and an insulating layer 110 is further formed on the surface of the substrate 100. Among them, the distance between adjacent shallow trench isolation structures 101 and the width of some shallow trench isolation structures 101 in the first direction D1 and / or the second direction D2 may be the same or different, and the specific setting may be changed based on the relative positional relationship between subsequent formed components and / or parts, such as contact structures, bit lines, etc. In one embodiment, the substrate 100 is any suitable substrate material known in the art, for example, it may be a silicon substrate, a silicon-containing substrate (such as SiC, SiGe), or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but not limited thereto. The shallow trench isolation structure 101 may include a single layer or multiple layers of dielectric materials, and applicable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), nitrogen-doped silicon carbide (NDC), low dielectric constant (low-k) dielectric materials such as fluorinated silicaglass (FSG), silicon carbon oxide (SiCOH), spin-on glass, porous low dielectric constant dielectric materials (porous low-k dielectric material), organic polymer dielectric materials, or a combination of the above materials, but not limited thereto. The material of the insulating layer 110 may be an insulating material, such as an oxide (silicon dioxide) or a nitride (silicon nitride), but not limited thereto.

[0056] The plurality of bit lines 130 may be disposed on the substrate 100 along the first direction D1 and may extend along the second direction D2 to the first region 100A and the second region 100B to intersect with the plurality of active regions AR at the same time. In one embodiment, the plurality of bit lines 130 may include a plurality of first bit lines 131 and at least one second bit line 132, and the at least one second bit line 132 may be disposed outside all the first bit lines 131, for example Figure 6 At least one second bit line 132 shown may be arranged outside the plurality of first bit lines 131 along the first direction D1; illustratively, the width of the first bit line 131 in the first direction D1 may be smaller than the width of the second bit line 132 in the first direction D1, but the present invention is not limited thereto. Specifically, a bit line plug extending into the substrate 100 is further arranged below some of the bit lines 130, such as the first bit line 131, and the first bit line 131 and the second bit line 132 may include the same bit line material layer, for example, both include a semiconductor layer 1301, a barrier layer 1302, a metal layer 1303 and a cap layer 1304 stacked from bottom to top in the third direction D3, but the present invention is not limited thereto. The material of the semiconductor layer 1301 may include single crystal silicon (crystalline silicon), polycrystalline silicon (poly silicon), amorphous silicon (amorphous silicon), doped silicon (doped silicon), silicon germanium (SiGe), or other suitable semiconductor materials, but the present invention is not limited thereto. The material of the barrier layer 1302 may include metal, metal silicide or metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but not limited thereto. The material of the metal layer 1303 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but not limited thereto. The cap layer 1304 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but not limited thereto. Exemplarily, the material of the semiconductor layer 1301 is polysilicon, the material of the barrier layer 1302 is titanium nitride (TiN), the material of the metal layer 1303 is tungsten (W), and the material of the cap layer 1304 is silicon nitride (SiN).

[0057] A plurality of spacer structures 140 are respectively disposed on both side walls of the first bit line 131 and at least one side wall of the second bit line 132, and ends of the spacer structures 140 located between adjacent bit lines 130 are connected to each other (hereinafter referred to as connected). Figure 6The right-side end portions of the adjacent spacer wall structures 140 shown are connected so that the spacer wall structures 140 after the connection of multiple end portions form a U-shaped top view structure extending along the second direction D2. In one embodiment, the details of the spacer wall structure 140 may include a third dielectric layer 141 and a fourth dielectric layer 142. The third dielectric layer 141 is disposed on the two sidewalls of the first bit line 131 and on the sidewall of the second bit line 132 close to the first bit line 131. The fourth dielectric layer 142 is disposed at the end portions of the third dielectric layer 141 (located between adjacent second bit lines 132 and first bit lines 131, and between adjacent first bit lines 131), for example Figure 6 the right-side end portion of the third dielectric layer 141 shown, extends along the second direction D2, passes through the first dielectric layer 151 located outside the plurality of bit lines 130, and overlaps with the second dielectric layer 152 located outside the first dielectric layer 151 within the second dielectric layer 152. That is, the spacer wall structure 140 having a U-shaped top view structure includes two linear third dielectric layers 141 disposed on the sidewalls of adjacent bit lines 130 and extending along the second direction D2, and a fourth dielectric layer 142 having a U-shape along the second direction D2. The U-shaped fourth dielectric layer 142 specifically passes through the first dielectric layer 151 and a part of the second dielectric layer 152. That is, the U-shaped end portions of the U-shaped fourth dielectric layer 142 are all wrapped by the second dielectric layer 152, or it can be understood that the U-shaped end portions of the U-shaped fourth dielectric layer 142 do not penetrate through the second dielectric layer 152, but this is not limited thereto.

[0058] It should be understood that the end portions on the left and right sides of the spacer wall structure 140 extending along the second direction D2 located between adjacent bit lines 130 should be respectively connected, so that the spacer wall structure 140 after the connection of the end portions on the left and right sides forms an elliptical top view structure (not shown) extending along the second direction D2, and Figure 6 only a partial top view structure of the spacer wall structure 140 after the connection of the right-side end portion is shown.

[0059] In one embodiment, the first dielectric layer 151 may include a first portion and a second portion. The first portion of the first dielectric layer 151 may surround the outside of the first bit line 131 and the second bit line 132 along the first direction D1, while the second portion of the first dielectric layer 151 may extend and cover the sidewall of the second bit line 132 on the side away from the first bit line 131 along the second direction D2. The second dielectric layer 152 may be disposed outside the first dielectric layer 151 and, similarly, may also include a first portion and a second portion. The first portion of the second dielectric layer 152 is disposed outside the first portion of the first dielectric layer 151, and the second portion of the second dielectric layer 152 is disposed outside the second portion of the first dielectric layer 151. After passing through a part of the spacer structure 140 on the sidewall of the adjacent bit line 130 in the second direction D2 and wrapping the end of the spacer structure 140, it forms an inverted L-shaped top view structure. Moreover, the semiconductor device in this embodiment further includes a fifth dielectric layer 153 disposed outside the second dielectric layer 152, and the top view structure of the fifth dielectric layer 153 is also an inverted L-shaped top view structure. Thus, the first dielectric layer 151, the second dielectric layer 152, and the fifth dielectric layer 153, which are the sidewall structures (simply referred to as sidewalls) of the gate structure (not shown) on the second region 100B, extend to the outside of the multiple bit lines 130 in the first region 100A. Exemplarily, both the third dielectric layer 141 and the fourth dielectric layer 142 in the spacer structure 140 can be single-layer structures, such as silicon dioxide, or can be multi-layer composite structures, such as an ONO structure stacked with silicon dioxide, silicon nitride, and silicon dioxide. The first dielectric layer 151, the second dielectric layer 152, and the fifth dielectric layer 153 can be dielectric materials with different materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or a combination of the above materials. For example, the material of the first dielectric layer 151 is silicon dioxide, the material of the second dielectric layer 152 is silicon nitride, and the material of the fifth dielectric layer 153 is silicon dioxide. That is, the third dielectric layer 141 and the fourth dielectric layer 142 in the spacer structure 140 can be the same as the stacked materials of the first dielectric layer 151, the second dielectric layer 152, and the fifth dielectric layer 153, but this is not limited thereto.

[0060] Further, the semiconductor device in this embodiment further includes: a plurality of word line structures 120, a filling layer 160', a plurality of insulating structures 170, and a plurality of conductive plugs 180. Among them, each word line structure 120 extends along the first direction D1, and the plurality of word line structures 120 are disposed in the active region AR and / or the shallow trench isolation structure 101 of the substrate 100 separately from each other in the second direction D2. Those skilled in the art should easily understand that the extending directions of the active region AR, the word line structure 120, and the bit line 130 are all different. The extending direction of the word line 120 (the first direction D1) should be perpendicular to the extending direction of the bit line 130 (the second direction D2), and at the same time, it intersects with the plurality of active regions AR and the bit line 130; moreover, each word line structure 120 is insulated from the plurality of bit lines 130 by the insulating layer 110 disposed on the substrate 100. And, the filling layer 160' conformally covers the fourth dielectric layer 142 with an end portion having a U-shaped top view structure, so as to be used for extruding and supporting the portion of the adjacent bit line 130 extending on the second region 100B, thereby reducing the probability of the bit line 130 collapsing or tilting; a plurality of insulating structures 170 are separately disposed in the gaps defined by the third dielectric layer 141 on the sidewalls of the adjacent bit lines 130, and some of the insulating structures 170 are respectively aligned with the corresponding word line structures 120; and the plurality of conductive plugs 180 are interposed between the adjacent insulating structures 170. In one embodiment, the word line structure 120 may include a gate dielectric layer, a work function layer, a conductive layer, and a capping layer, but not limited thereto. The filling layer 160' and the insulating structure 170 may be insulating materials with different materials, such as oxides (silicon dioxide) or nitrides (silicon nitride), and the material of the conductive plug 180 may be a conductive material, such as tungsten, but not limited thereto.

[0061] It should be understood that the "conformal" in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the similarity and relevance in the morphology between two or more shapes.

[0062] Those of ordinary skill in the technical field to which the present invention pertains should easily understand that, in order to meet the requirements of actual products, the semiconductor device of the present invention may also have other forms and is not limited to the foregoing. The following will further describe other embodiments or variations of the semiconductor device of the present invention. And for the sake of simplicity of description, the same components in the embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the embodiments.

[0063] Please refer to Figure 9 and in combination with Figure 7 Figure 9 The top view of the semiconductor device in the second embodiment of the present invention is shown, Figure 7 which is Figure 9 a partial structural cross-sectional view of the semiconductor device shown along the tangent line AA'. As Figure 9As shown, the structure of the semiconductor device in the second embodiment of the present invention is substantially the same as that of the semiconductor device in the foregoing first embodiment. For example, the semiconductor device also includes multiple bit lines 130 (including multiple first bit lines 131 and at least one second bit line 132), a first dielectric layer 151, a second dielectric layer 152, multiple spacer structures 140, multiple insulating structures 170, and multiple conductive plugs 180. Among them, multiple spacer structures 140 are also respectively disposed on both sidewalls of the first bit line 131 and on one sidewall of the second bit line 132, and the ends of the spacer structures 140 located between adjacent bit lines 130 are connected to each other. In detail, it may include a third dielectric layer 141 and a fourth dielectric layer 142. The third dielectric layer 141 is disposed on both sidewalls of the first bit line 131 and on the sidewall of the second bit line 132 close to the first bit line 131, and the fourth dielectric layer 142 is disposed at the ends of the third dielectric layer 141 (located between adjacent second bit lines 132 and first bit lines 131, and between adjacent first bit lines 131). For example Figure 9 as shown at the right end of the third dielectric layer 141. The first dielectric layer 151, the second dielectric layer 152, and the fifth dielectric layer 153 also sequentially surround the outside of the first bit line 131 and the second bit line 132, and the first dielectric layer 151 is in direct contact with the multiple bit lines 130, etc. The same parts will not be described in detail here.

[0064] The main difference between the semiconductor device of the second embodiment of the present invention and the foregoing first embodiment lies in the setting of the filling layer. For the sake of distinction, the filling layer in this embodiment is denoted by the reference numeral "160". Specifically, the filling layer 160" in the second embodiment of the present invention not only conformally covers (or fills) the fourth dielectric layer 142 with an end-to-end connection having a U-shaped or oval-shaped top view structure, but also laterally extends along the second direction D2 into a part of the gap between the third dielectric layers 141 on the sidewalls of adjacent bit lines 130. For example Figure 9 as shown, a part of the gap defined between adjacent third dielectric layers 141 that laterally extends from the second region 100B of the substrate 100 to the first region 100A of the substrate 100 along the second direction D2. Thus, it can also be used to isolate adjacent bit lines 130 while squeezing and supporting the part of the adjacent bit lines 130 extending on the second region 100B, thereby reducing the probability of the bit lines 130 collapsing or tilting.

[0065] It should be understood that since the AA' tangent in the embodiment of the present invention is located in the first region 100A of the substrate 100, that is, it does not cover the filling layer, the cross-sectional structures of the semiconductor devices at the AA' tangent corresponding to the first embodiment and the second embodiment of the present invention are the same, that is, they both correspond to Figure 7 the cross-sectional structure shown.

[0066] Those of ordinary skill in the art to which the present invention pertains should easily understand that, in order to meet the requirements of actual products, the semiconductor devices of the present invention may also have other forms and are not limited to the foregoing. Further embodiments or variations of the semiconductor devices of the present invention will be described below. And for the sake of simplicity, the same components in each embodiment of the present invention are labeled with the same reference numerals to facilitate comparison between the embodiments.

[0067] Please refer to Figure 15 and Figure 16 , Figure 15 , which is a top view of the semiconductor device in the third embodiment of the present invention. Figure 16 is Figure 15 a partial structural cross-sectional view of the semiconductor device shown along the tangent line AA'. As Figure 15 shown, the structure of the semiconductor device in the third embodiment of the present invention is substantially the same as that of the semiconductor device in the foregoing first embodiment. For example, the semiconductor device also includes a plurality of bit lines 130 (including a plurality of first bit lines 131 and at least one second bit line 132), a first dielectric layer 151, a second dielectric layer 152, a plurality of spacer structures 140 (including a third dielectric layer 141 and a fourth dielectric layer 142), a filling layer 160', a plurality of insulating structures 170, and a plurality of conductive plugs 180. Among them, the plurality of spacer structures 140 are also respectively disposed on the two sidewalls of the first bit line 131 and on one sidewall of the second bit line 132, and the ends of the spacer structures 140 located between adjacent bit lines 130 are connected to each other. The third dielectric layer 141 is disposed on the two sidewalls of the first bit line 131 and on the sidewall of the second bit line 132 close to the first bit line 131, and the fourth dielectric layer 142 is disposed at the ends of the third dielectric layer 141 (located between adjacent second bit lines 132 and first bit lines 131, and between adjacent first bit lines 131). For example, Figure 15 the right end of the third dielectric layer 141 shown. The first dielectric layer 151, the second dielectric layer 152, and the fifth dielectric layer 153 also sequentially surround the outside of the first bit line 131 and the second bit line 132, and the first dielectric layer 151 is in direct contact with the plurality of bit lines 130. The filling layer 160' is also conformally filled in the fourth dielectric layer 142 but does not extend laterally into some of the gaps defined by adjacent third dielectric layers 141. The same parts will not be described again here.

[0068] The main difference between the semiconductor device of the third embodiment of the present invention and the foregoing first embodiment is that: the width of the metal layer 1303 in the bit line material layer of the bit line 130 from left to right in the extending direction of the second direction D2 is different in the first direction D1. Specifically, the width of the metal layer 1303 in each bit line 130 of the third embodiment of the present invention in contact with the fourth dielectric layer 142 and in the first direction D1 is smaller than the width of the metal layer 1303 in the bit line 130 in contact with the third dielectric layer 141 and in the first direction D1; combined Figure 10 As shown, the width d2 of the portion of the spacer structure 140 with its ends connected and extending along the second direction D2 in contact with the fourth dielectric layer 142 in the first direction D1 is smaller than the width d1 of the portion of the spacer structure 140 in contact with the third dielectric layer 141 in the first direction D1, that is, d1 > d2; it should be understood that the bit line 130 at this time includes a first bit line 131 and a second bit line 132.

[0069] It should be noted in particular that in the third embodiment of the present invention Figure 15 the bit line 130 shown in only includes a semiconductor layer 1301, a barrier layer 1302, and a metal layer 1303 stacked in sequence from bottom to top along the third direction D3, that is Figure 15 the multiple bit lines 130 in do not include a capping layer 1304 to better show the different widths of the bit line 130 in the second part of the first region 100A of the substrate 100 and in the first part on the second region 100B, but in order to completely show the structure of the bit line 130, when showing Figure 15 the corresponding cross-sectional view Figure 16 the capping layer 1304 of the bit line 130 is drawn accordingly.

[0070] Those of ordinary skill in the art to which the present invention pertains should easily understand that, on the premise of meeting the requirements of actual products, the semiconductor device of the present invention may also have other forms and is not limited to the foregoing. The following will further describe other embodiments or variations of the semiconductor device of the present invention. And for simplicity of description, the same components in the embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the embodiments.

[0071] Please refer to Figure 18 , Figure 18 which is a top view of the semiconductor device in the fourth embodiment of the present invention. As Figure 18As shown, the structure of the semiconductor device in the fourth embodiment of the present invention is substantially the same as that of the semiconductor device in the aforementioned third embodiment. For example, the semiconductor device also includes multiple bit lines 130 (including multiple first bit lines 131 and at least one second bit line 132), a first dielectric layer 151, a second dielectric layer 152, multiple spacer structures 140 (including a third dielectric layer 141 and a fourth dielectric layer 142), multiple insulating structures 170, and multiple conductive plugs 180. Among them, the widths of the metal layers 1303 in the bit line material layers of the respective bit lines 130 in the first direction D1 are different from left to right in the extending direction of the second direction D2. Specifically, the width of the metal layer 1303 in each bit line 130 in the first direction D1 in contact with the fourth dielectric layer 142 is smaller than the width of the metal layer 1303 in the same bit line 130 in the first direction D1 in contact with the third dielectric layer 141. The same parts will not be elaborated here.

[0072] The main difference between the semiconductor device of the fourth embodiment of the present invention and the aforementioned third embodiment lies in the setting of the filling layer. For the convenience of distinction, the filling layer in this embodiment is denoted by the reference numeral 160”. Specifically, the filling layer 160” in the fourth embodiment of the present invention not only conformally covers (or fills) the fourth dielectric layer 142 with an end connected in a U-shape retracted along the first direction D1 in a top view structure, but also horizontally extends along the second direction D2 and fills a part of the gap between the third dielectric layers 141 on the sidewalls of adjacent bit lines 130. For example Figure 18 as shown, a part of the gap defined between adjacent third dielectric layers 141 extending from the second region 100B of the substrate 100 to the first region 100A of the substrate 100 along the second direction D2. Thus, it can also be used to isolate adjacent bit lines 130 while squeezing and supporting the part of the adjacent bit lines 130 extending on the second region 100B, thereby reducing the probability of the bit lines 130 collapsing or tilting.

[0073] In order to enable those of ordinary skill in the art to which the present invention pertains to easily understand the semiconductor devices in the first to fourth embodiments of the present invention, the present invention also provides a method for manufacturing a semiconductor device. The following will further explain the method for manufacturing the semiconductor device proposed by the present invention in combination with the structural schematic diagrams in the preparation process of the method for manufacturing a semiconductor device.

[0074] Among them, Figures 1 to 9 are the structural schematic diagrams in the preparation process of the method for manufacturing the semiconductor devices provided in the first and second embodiments of the present invention.

[0075] Please refer to Figure 1 and Figure 2, first, a substrate 100 (the material is, for example, a silicon substrate) is provided. The substrate 100 includes a first region 100A and a second region 100B. Then, a plurality of trenches (not shown) are formed in both the first region 100A and the second region 100B of the substrate 100 by an etching method. Then, an insulating material (the material is, for example, silicon oxide or silicon oxynitride, etc.) is filled in the trenches to form a plurality of trench isolation structures 101 and a plurality of active regions AR defined by the trench isolation structures 101 within the substrate 100. Exemplarily, the trench isolation structure 101 may be in a long strip shape extending in the vertical direction. Then, by using etching and deposition processes, a plurality of word line structures 120 are formed within the active regions AR and / or the trench isolation structures 101. Then, an insulating layer 110 is formed on the surface of the substrate 100 by using a deposition process such as at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. Then, a plurality of bit line plug holes (not shown) are formed within the insulating layer 110 and the substrate 100. The bit line plug holes are the corresponding positions within the substrate 100 where bit line plugs are formed subsequently. Then, a material layer (the material is, for example, polysilicon) of the bit line plug can be formed within the bit line plug holes by using the above deposition process. Then, a semiconductor layer 1301 (the material is, for example, polysilicon), a barrier layer 1302 (the material is, for example, titanium nitride), a metal layer 1303 (the material is, for example, tungsten metal), and a capping layer 1304 (the material is, for example, silicon nitride) are sequentially stacked from bottom to top on most of the region of the substrate 100 and the material layer of the bit line plug to form a bit line material layer 130. Then, a part of the bit line material layer 130 is vertically etched away along the third direction D3 to form a plurality of first bit lines 131 and at least one second bit line 132 (a plurality of bit lines 130) that are arranged on the substrate 100 and separated from each other along the first direction D1 and extend to the first region 100A and the second region 100B along the second direction D2. At least one second bit line 132 can be arranged outside all the first bit lines 131. Then, a spacer structure 140 (the material is, for example, an ONO stacked structure composed of silicon dioxide, silicon nitride, and silicon dioxide) is formed on both sidewalls of the first bit lines 131 and one sidewall of the second bit line 132. And a first dielectric layer 151 (the material is, for example, silicon dioxide), a second dielectric layer 152 (the material is, for example, silicon nitride), and a fifth dielectric layer 153 (the material is, for example, silicon dioxide) are sequentially formed on the sidewall of the second bit line 132 away from the first bit lines 131. And the first dielectric layer 151, the second dielectric layer 152, and the fifth dielectric layer 153 also extend along the first direction D1 to cover the ends of the plurality of bit lines 130.In one embodiment, the detailed structure of the spacer wall 140 may include a third dielectric layer 141 and a fourth dielectric layer 142. The third dielectric layer 141 is disposed on the sidewalls of the first bit line 131 and on the sidewall of the second bit line 132 adjacent to the first bit line 131. The fourth dielectric layer 142 is disposed at the end of the third dielectric layer 141, and the right ends of adjacent spacer wall structures 140 are connected to each other, so that the spacer wall structures 140 after the connection of multiple ends form a U-shaped top view structure extending along the second direction D2. That is, the spacer wall structure 140 in the U-shaped top view structure includes two linear third dielectric layers 141 disposed on the sidewalls of adjacent bit lines 130 and extending along the second direction D2, and a fourth dielectric layer 142 in a U-shape along the second direction D2. The U-shaped fourth dielectric layer 142 specifically passes through the first dielectric layer 151 and part of the second dielectric layer 152. That is, the U-shaped ends of the U-shaped fourth dielectric layer 142 are all wrapped by the second dielectric layer 152, or it can be understood that the U-shaped ends of the U-shaped fourth dielectric layer 142 do not penetrate through the second dielectric layer 152, but this is not limited thereto.

[0076] Please refer to Figure 3 and Figure 4 , and then, by using a deposition process such as chemical vapor deposition, a filling material layer 160 (the material is, for example, an oxide or silicon nitride) is formed in the spacer wall structure 140 extending along the second direction D2 and having a U-shaped or elliptical top view structure, so as to isolate adjacent bit lines 130 by using the filling material layer 160 and reduce the probability of the bit lines 130 collapsing or tilting.

[0077] Please refer to Figure 5 or Figure 8 , for Figure 6 the semiconductor device structure (the first embodiment) shown, after the filling material layer 160 is formed in the spacer wall structure 140 extending along the second direction D2 and having a U-shaped top view structure, the filling material layer 160 extending along the second direction D2 outside the sidewall of the first dielectric layer 151 adjacent to the word line structure 120 can be removed by using an etching process such as a dry etching process, so as to form a filling layer 160' only filled in the U-shaped fourth dielectric layer 142; if for Figure 9 the semiconductor device structure (the second embodiment) shown, after the filling material layer 160 is formed in the spacer wall structure 140 extending along the second direction D2 and having a U-shaped or elliptical top view structure, the filling material layer 160 on the right side of the word line structure 120 on the rightmost side along the second direction D2 can be retained by using an etching process such as a dry etching process, while the filling material layers 160 on its left side are all removed, so as to form a filling layer 160'' that is not only conformally filled in the fourth dielectric layer 142 with the U-shaped or elliptical ends connected in the top view structure, but also laterally extends along the second direction D2 and fills a part of the gap between the third dielectric layers 141 on the sidewalls of adjacent bit lines 130.

[0078] Please refer to Figure 6 or Figure 9 and in combination with Figure 7 , further, a conductive material (such as tungsten metal) of the conductive plug 180 can be formed in the spacer structure 140 extending along the second direction D2 and having a U-shaped or elliptical top view structure by using a deposition process such as chemical vapor deposition process. Corresponding grooves (not shown) are formed in the regions corresponding to the respective word line structures 120, and then an insulating material (such as silicon nitride) of the insulating structure 170 is filled in the formed plurality of grooves, that is, the insulating structure 170 and the conductive plugs 180 on both sides thereof that are respectively aligned with the corresponding word line structures 120 are defined in the gaps defined by the third dielectric layer 141 on the sidewalls of the adjacent bit lines 130.

[0079] Wherein, Figures 10 to 18 FIG. is a schematic structural diagram during the preparation process of the manufacturing method of the semiconductor device provided in the third and fourth embodiments of the present invention. Since the semiconductor devices of the third to fourth embodiments of the present invention are substantially the same as the foregoing first to second embodiments, the preparation methods of their corresponding components and / or devices are also the same. The parts of the preparation methods of the third to fourth embodiments of the present invention that are the same as the foregoing first to second embodiments will not be described in detail below, and only the different preparation processes of the two will be explained.

[0080] Specifically, as Figure 10 shown, when forming the semiconductor device in the third and fourth embodiments of the present invention, when vertically etching away a part of the bit line material layer 130 (semiconductor layer 1301, barrier layer 1302, metal layer 1303, and capping layer 1304) along the third direction D3 to form a plurality of first bit lines 131 and at least one second bit line 132 (a plurality of bit lines 130) that are separated from each other along the first direction D1 and extend along the second direction D2 on the substrate 100 to the first region 100A and the second region 100B, the part of the metal layer 1303 in the bit line material layer removed in the first direction D1 from left to right in the extending direction of the second direction D2 can be set differently. For example, the width of the metal layer 1303 in the bit line material layer that will be in contact with the fourth dielectric layer 142 and in the first direction D1 can be removed a little more, and the width of the metal layer 1303 in the bit line material layer that will be in contact with the third dielectric layer 141 and in the first direction D1 can be removed less, so that the width of the metal layer 1303 in each of the finally formed bit lines 130 in contact with the fourth dielectric layer 142 and in the first direction D1 is smaller than the width of the metal layer 1303 in the bit line 130 in contact with the third dielectric layer 141 and in the first direction D1.

[0081] In summary, a semiconductor device and a manufacturing method thereof provided by the present invention may specifically include a first dielectric layer located outside the bit line, a second dielectric layer located outside the first dielectric layer, and a spacer structure composed of a third dielectric layer and a fourth dielectric layer. Moreover, the third dielectric layer and the fourth dielectric layer in the spacer structure may be located at different positions of the bit line. For example, the third dielectric layer is located on the sidewall of the bit line along the second direction, while the fourth dielectric layer extends through the first dielectric layer along the second direction and overlaps with the second dielectric layer within the second dielectric layer. By extending the dielectric layers (the first dielectric layer, the second dielectric layer, and the fifth dielectric layer) serving as the sidewalls in the second region to the outside of the bit line in the first region, a new structure of the semiconductor device is proposed. And by providing a filling layer between adjacent bit lines, adjacent bit lines are isolated and the portions of the adjacent bit lines extending in the second region are squeezed and supported, thereby reducing the probability of bit line collapse or tilt, that is, ultimately achieving the purpose of improving the performance and reliability of the semiconductor device.

[0082] The foregoing is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention are all included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: Substrate; Multiple bit lines, extending in a second direction and disposed on the substrate separately from each other in a first direction perpendicular to the second direction; A first dielectric layer, located outside the bit lines; A second dielectric layer, located outside the first dielectric layer; A spacer wall structure, comprising: A third dielectric layer, located between adjacent ones of the bit lines and in direct contact with the bit lines; A fourth dielectric layer, extending in the second direction through the first dielectric layer and overlapping with the second dielectric layer within the second dielectric layer.

2. The semiconductor device according to claim 1, wherein, The multiple bit lines include multiple first bit lines and at least one second bit line, and the at least one second bit line is disposed outside all of the first bit lines.

3. The semiconductor device according to claim 2, wherein, The bit lines include a semiconductor layer and a metal layer stacked in sequence from bottom to top, and the width of the metal layer in the first direction in contact with the fourth dielectric layer is smaller than the width of the metal layer in the first direction in contact with the third dielectric layer.

4. The semiconductor device according to claim 2, characterized in that, The third dielectric layer is located on both sidewalls of the first bit lines and at least one sidewall of the second bit line.

5. The semiconductor device according to claim 2, wherein The first dielectric layer and the second dielectric layer further extend to cover one sidewall of the second bit line.

6. The semiconductor device according to claim 5, wherein, Further comprising: A fifth dielectric layer, located outside the second dielectric layer.

7. The semiconductor device according to claim 2 or 3, characterized in that, The ends of the fourth dielectric layer between adjacent bit lines are connected.

8. The semiconductor device according to claim 7, wherein, The fourth dielectric layer with connected ends includes a U shape or an ellipse extending in the second direction.

9. The semiconductor device according to claim 7, wherein, Further comprising: A filling layer, located in the fourth dielectric layer with connected ends.

10. The semiconductor device according to claim 9, wherein, The filling layer further extends in the second direction and fills a part of the gap between adjacent third dielectric layers.

11. The semiconductor device according to claim 1, wherein, Further comprising: Multiple word line structures, extending in the first direction and disposed separately from each other in the second direction within the substrate.

12. The semiconductor device according to claim 11, wherein, Further comprising: Multiple insulating structures, disposed separately in the gaps defined by the third dielectric layer on the sidewalls of adjacent bit lines and aligned with the word line structures.

13. The semiconductor device according to claim 12, wherein, Further comprising: Multiple conductive plugs, disposed between adjacent insulating structures.

14. A manufacturing method of a semiconductor device, characterized in that, Comprising: Providing a substrate; Forming multiple bit lines, extending in a second direction and disposed on the substrate separately from each other in a first direction perpendicular to the second direction; Forming a first dielectric layer, located outside the bit lines; Forming a second dielectric layer, located outside the first dielectric layer; Forming a spacer wall structure, comprising: A third dielectric layer, located between adjacent ones of the bit lines and in direct contact with the bit lines; A fourth dielectric layer, extending in the second direction through the first dielectric layer and overlapping with the second dielectric layer within the second dielectric layer.

15. The manufacturing method of the semiconductor device according to claim 14, wherein, The ends of the fourth dielectric layer between adjacent bit lines are connected.

16. The manufacturing method of the semiconductor device according to claim 15, wherein, The fourth dielectric layer with connected ends includes a U shape or an ellipse extending in the second direction.

Images