Semiconductor device

Abstract

There is provided a semiconductor device including: a substrate; a plurality of lower electrodes disposed over the substrate, the plurality of lower electrodes including a plurality of first lower electrodes and a plurality of second lower electrodes, the plurality of first lower electrodes and the plurality of second lower electrodes being respectively arranged in a first direction and alternately arranged in a second direction perpendicular to the first direction, each of the plurality of second lower electrodes is offset from each of the plurality of first lower electrodes with respect to a second direction; a support structure contacting the plurality of lower electrodes; a plurality of support holes disposed in the support structure and arranged in the first direction and in the second direction; a dielectric layer disposed on the plurality of lower electrodes; and an upper electrode disposed on the dielectric layer, in which one of the plurality of support holes exposes two of the plurality of first lower electrodes and exposes two of the plurality of second lower electrodes among the plurality of lower electrodes.

Description

[0001] This application is a divisional application of a patent application for invention, with the application date of October 18, 2019, the application number of "201910993307.9", and the invention title of "Method for manufacturing a semiconductor device having a support pattern". Technical Field

[0002] Devices consistent with some example embodiments relate to a semiconductor device having a support pattern. Background Art

[0003] Due to the need for highly integrated and miniaturized semiconductor devices such as dynamic random access memories (DRAMs), the size of capacitors in semiconductor devices has also been miniaturized. A lower electrode having a high aspect ratio is used to obtain a specific / pre-determined capacitance of a capacitor disposed in a fine pattern. A support pattern for supporting the lower electrode is used to prevent or reduce the possibility of the lower electrode collapsing during the process. Summary of the Invention

[0004] Some example embodiments of the inventive concept are directed to providing a method for manufacturing a semiconductor device in which the contact area between the support pattern and the lower electrode is uniform or significantly uniform.

[0005] According to some example embodiments, there is provided a method for manufacturing a semiconductor device, the method including: sequentially stacking a molding layer and a support layer on a substrate; forming a plurality of capacitor holes that pass through the molding layer and the support layer; forming a plurality of lower electrodes that fill the plurality of capacitor holes, the plurality of lower electrodes being arranged in a first direction and a second direction intersecting the first direction; forming a support mask pattern on the support layer and the lower electrodes, the support mask pattern including a plurality of mask holes; and forming a plurality of support holes by patterning the support layer using the support mask pattern. Each of the plurality of lower electrodes has a column shape, each mask hole is located between four adjacent lower electrodes, and each mask hole has a circular shape.

[0006] According to some example embodiments, there is provided a method for manufacturing a semiconductor device, the method including: sequentially stacking a molding layer and a support layer on a substrate; forming a plurality of capacitor holes that pass through the molding layer and the support layer; forming a plurality of lower electrodes that fill the capacitor holes, the plurality of lower electrodes being arranged in a first direction and a second direction intersecting the first direction; forming a support mask pattern on the support layer and the lower electrodes, the support mask pattern including a plurality of mask holes; and forming a plurality of first support holes and a plurality of second support holes arranged in a direction different from the direction of the first support holes by patterning the support layer using the support mask pattern. Each of the plurality of lower electrodes has a column shape, each mask hole is located between four adjacent lower electrodes, and each mask hole has a circular shape.

[0007] According to some example embodiments, a method of manufacturing a semiconductor device is provided, the method including: sequentially stacking a molding layer and a support layer on a substrate; forming a plurality of capacitor holes through the molding layer and the support layer; forming a plurality of lower electrodes filling the capacitor holes, arranging the plurality of lower electrodes in a first direction and a second direction intersecting the first direction, and arranging the plurality of lower electrodes in a honeycomb structure in which the plurality of lower electrodes are located at the centers and vertices of hexagons; forming a support mask pattern on the support layer and the lower electrodes, the support mask pattern including a plurality of mask holes; and forming a plurality of support holes by patterning the support layer using the support mask pattern. Each of the plurality of lower electrodes has a column shape, and each of the plurality of lower electrodes is exposed through at least one of the plurality of support holes. Each mask hole is located between four adjacent lower electrodes, each mask hole has a circular shape, each support hole is located between the four adjacent lower electrodes, and each support hole has an elliptical shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects, features and advantages of the inventive concept will become more apparent to those of ordinary skill in the art by describing example embodiments of the inventive concept in detail with reference to the accompanying drawings, in which: Figure 1 is a plan view of a semiconductor device showing some example embodiments according to the inventive concept.

[0009] Figure 2 is a vertical cross-sectional view of the semiconductor device taken along the line I-I' of Figure 1 the semiconductor device.

[0010] Figures 3 to 7 , Figure 9 , Figure 11 and Figure 12 are cross-sectional views for describing a method of manufacturing a semiconductor device according to process sequences in some example embodiments according to the inventive concept.

[0011] Figure 8 is a plan view of a support mask pattern showing some example embodiments according to the inventive concept.

[0012] Figure 10 is a plan view of an upper support pattern showing some example embodiments according to the inventive concept.

[0013] Figure 13 is an enlarged view of a part of the upper support pattern showing some example embodiments according to the inventive concept.

[0014] Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18Ais a plan view showing a support mask pattern according to some example embodiments of the inventive concept.

[0015] Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B is a plan view showing an upper support pattern according to some example embodiments of the inventive concept.

[0016] Figure 19 is a cross-sectional view showing a semiconductor device according to some example embodiments of the inventive concept.

[0017] Figure 20 is an enlarged view showing a part of an upper support pattern according to some example embodiments of the inventive concept.

[0018] Figure 21 shows a vertical cross-sectional view of the semiconductor device taken along line II-II' and III-III' of Figure 20 .

[0019] Figure 22A is a plan view showing a support mask pattern according to some example embodiments of the inventive concept.

[0020] Figure 22B is a plan view showing a support pattern according to some example embodiments of the inventive concept. DETAILED DESCRIPTION

[0021] Figure 1 is a plan view showing a semiconductor device according to some example embodiments of the inventive concept. Figure 2 is a vertical cross-sectional view of the semiconductor device taken along line I-I of Figure 1 . Referring to

[0022] and Figure 1 and Figure 2 , the semiconductor device 100 may include a substrate 102, a contact plug 104, a lower insulating layer 106, an etch stop film 110, a lower support pattern 130, an upper support pattern 135, a lower electrode 150, a capacitor dielectric layer 160, and an upper electrode 170.

[0023] The substrate 102 may include a semiconductor material. For example, the substrate 102 may be or may include a silicon substrate, a germanium substrate, a silicon-germanium substrate, or a silicon-on-insulator (SOI) substrate. Although not shown, a plurality of switching elements such as transistors may be provided on the substrate 102. The plurality of switching elements may include a plurality of word lines and a plurality of bit lines intersecting the plurality of word lines.

[0024] The contact plug 104 and the lower insulating layer 106 may be disposed on the substrate 102. A plurality of contact plugs 104 may be disposed to be buried in the lower insulating layer 106. The upper surface of each contact plug 104 may be positioned at the same level as the upper surface of the lower insulating layer 106. However, the plurality of contact plugs 104 is not limited thereto, and in some exemplary embodiments, the upper surface of the contact plug 104 may be positioned at a level lower than the upper surface of the lower insulating layer 106. The width of the contact plug 104 may be the same as the width of the lower surface of each lower electrode 150. The contact plug 104 may be electrically connected to the lower electrode 150. The lower insulating layer 106 may insulate the contact plugs 104 to prevent or reduce the possibility of the plurality of contact plugs 104 being electrically connected to each other.

[0025] The contact plug 104 may include a conductive material. For example, the contact plug 104 may include a semiconductor material such as polysilicon (e.g., doped polysilicon), a metal-semiconductor compound such as WSi2, a metal nitride such as TiN and TaN, and / or a metal such as Ti, W, and Ta. The lower insulating layer 106 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0026] The etch stop film 110 may be disposed on the lower insulating layer 106. In some exemplary embodiments, the etch stop film 110 may include silicon nitride, silicon oxynitride, or a combination thereof. In addition, the etch stop film 110 may prevent or reduce the possibility of the etchant leaking under the lower electrode 150 during a wet etching process, thereby preventing or reducing the possibility of the lower insulating layer 106 being etched.

[0027] A plurality of lower electrodes 150 may be disposed on the contact plug 104. The lower electrode 150 may be electrically connected to the contact plug 104 and may include a metal such as Ti, W, Ni, and Co, or a metal nitride such as TiN, TiSiN, TiAlN, TaN, TaSiN, and / or WN. In some exemplary embodiments, the lower electrode 150 may include TiN. The upper surface of the lower electrode 150 may be positioned at the same level as the upper surface of the upper support pattern 135. Each of the plurality of lower electrodes 150 may have a column shape.

[0028] Refer to Figure 1, the lower electrodes 150 may be set to be separated from each other by a certain distance (e.g., a predetermined distance) in a plan view seen from above. In some example embodiments, the lower electrodes 150 may have a honeycomb structure (e.g., a regular hexagon HX having the same side length and the same angle between the sides), in which the lower electrodes 150 are disposed at the centers and vertices of the hexagons. For example, let F refer to the minimum lithography feature size, the distance W1 between the centers of the lower electrodes 150 separated in the first direction D1 may be 3.0F. The distance W2 between the centers of the lower electrodes 150 separated in the second direction D2 may be about 2.6F (e.g., about 1.5 times the square root of 3F). For example, the distance W2 may be related to the distance W1 by the formula for the sides of a 30-60-90 degree triangle.

[0029] The lower support pattern 130 and the upper support pattern 135 may be disposed between the lower electrodes 150. The lower support pattern 130 and the upper support pattern 135 may be connected and support the lower electrodes 150.

[0030] As Figure 1 shown, the lower support pattern 130 and the upper support pattern 135 may have a grid shape, in which openings having a constant pattern are formed on the plate. The lower support pattern 130 and the upper support pattern 135 may include an insulating material such as silicon nitride, silicon oxynitride, or a combination thereof.

[0031] The thickness of the upper support pattern 135 may be greater than the thickness of the lower support pattern 130. When observed in a plan view (e.g., from above), the lower support pattern 130 and the upper support pattern 135 may have the same shape. In some example embodiments, the side surface of the lower support pattern 130 in contact with the lower electrode 150 may be coplanar with the side surface of the upper support pattern 135 in contact with the lower electrode 150.

[0032] The upper support pattern 135 may include a plurality of support holes H2. Each support hole H2 may be disposed between four adjacent lower electrodes 150. The support hole H2 may have an elliptical shape with a short axis along the first direction D1 and a long axis along the second direction D2. The plurality of support holes H2 may be set to be separated from each other by about 6.0F in the first direction D1. In some example embodiments, the plurality of support holes H2 may have a honeycomb structure, in which the support holes H2 are disposed at the center points and vertices of the hexagons. Since the support holes H2 are set to have the above honeycomb structure, all the lower electrodes 150 may be substantially open. For example, the lower electrodes 150 may be exposed through at least one of the plurality of support holes H2.

[0033] The capacitor dielectric layer 160 may be disposed between the lower electrode 150 and the upper electrode 170. For example, the capacitor dielectric layer 160 may be conformally disposed on the surfaces of the etch stop film 110, the lower electrode 150, the lower support pattern 130, and the upper support pattern 135. The capacitor dielectric layer 160 may include metal oxides such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2, dielectric materials such as SrTiO3 (strontium titanate (STO)), BaTiO3, lead zirconate titanate (PZT), and lanthanum lead zirconate titanate (PLZT) having a perovskite structure, or a combination thereof.

[0034] The upper electrode 170 may be disposed on the capacitor dielectric layer 160. The upper electrode 170 may include metals such as Ti, W, Ni, and Co, or metal nitrides such as TiN, TiSiN, TiAlN, TaN, TaSiN, and WN. In some example embodiments, the upper electrode 170 may include TiN.

[0035] Figures 3 to 7 , Figure 9 , Figure 11 and Figure 12 are cross-sectional views for describing a method of manufacturing a semiconductor device according to process sequences in some example embodiments of the inventive concept.

[0036] Referring to Figure 3 , a lower insulating layer 106 in which a contact plug 104 is buried may be disposed on a substrate 102. The etch stop film 110, the lower forming layer 120, the lower support layer 130a, the upper forming layer 125, the upper support layer 135a, and the capacitor mask pattern 140 may be sequentially stacked on the contact plug 104 and the lower insulating layer 106.

[0037] The etch stop film 110 may be disposed on the lower insulating layer 106. The etch stop film 110 may include a material having an etch selectivity with respect to the lower forming layer 120 and the upper forming layer 125. In some example embodiments, the etch stop film 110 may include silicon nitride.

[0038] Each of the lower forming layer 120 and the upper forming layer 125 may include a material having an etch selectivity with respect to the lower support layer 130a and the upper support layer 135a. For example, each of the lower forming layer 120 and the upper forming layer 125 may include silicon oxide, and each of the lower support layer 130a and the upper support layer 135a may include silicon nitride. At least one or both of the lower forming layer 120 and the upper forming layer 125 may be formed by a chemical vapor deposition (CVD) process such as a plasma enhanced CVD (PECVD) process and / or a low pressure CVD (LPCVD) furnace process; however, the inventive concept is not limited thereto.

[0039] The capacitor mask pattern 140 may expose some of the upper support layer 135a. The capacitor mask pattern 140 may define an area in which the lower electrode 150 is disposed. The capacitor mask pattern 140 may include amorphous carbon or polysilicon. The capacitor mask pattern 140 may be formed by a photolithography process.

[0040] Referring Figure 4 , a plurality of capacitor holes CH may be formed according to the capacitor mask pattern 140. Each capacitor hole CH may be formed to pass through the etch stop film 110, the lower molding layer 120, the lower support layer 130a, the upper molding layer 125, and the upper support layer 135a. The capacitor hole CH may have a width (e.g., a predetermined width), and in some exemplary embodiments, the capacitor hole CH may be formed such that its width decreases in the downward direction.

[0041] The capacitor hole CH may be formed by a dry etching process such as a reactive ion etching (RIE) process. For example, after sequentially and anisotropically etching the upper support layer 135a, the upper molding layer 125, the lower support layer 130a, and the lower molding layer 120, some of the etch stop film 110 may be removed to expose the contact plug 104.

[0042] Referring Figure 5 , the lower electrode 150 may be formed in the capacitor hole CH. The lower electrode 150 may be formed by a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a plasma enhanced atomic layer deposition (PEALD) process, or the like. The lower electrode 150 may include a metal such as Ti, W, Ni, and Co, or a metal nitride such as TiN, TiSiN, TiAlN, TaN, TaSiN, and WN. After forming the lower electrode 150, a planarization process may be performed. Some of the lower electrode 150 and the capacitor mask pattern 140 may be removed by the planarization process. The planarization process may be or may include an etch-back process and / or a chemical mechanical planarization (CMP) process; however, the inventive concept is not limited thereto.

[0043] Referring Figure 6 , the support mask layer 145a may be formed on the structure shown in Figure 5 . For example, the support mask layer 145a may be disposed on the upper support layer 135a and the lower electrode 150. In some exemplary embodiments, the support mask layer 145a may be or may include a hard mask and include amorphous carbon and / or polysilicon.

[0044] Figure 8 is a plan view showing a support mask pattern 145 according to some exemplary embodiments of the inventive concept. Figure 7 may correspond to a vertical cross-sectional view taken along line I-I' of Figure 8 .

[0045] First, referring to Figure 7 , some of the support mask layer 145a may be etched to form a support mask pattern 145. In some example embodiments, the support mask layer 145a may be patterned by an exposure process using a photomask. The support mask pattern 145 may include a plurality of mask holes H1. The mask holes H1 may expose some of the upper support layer 135a. For example, the top surface of the upper support layer 135a may be opened. In addition, each mask hole H1 may expose a part of the lower electrode 150. For example, the top surface of the lower electrode 150 may be opened. However, the inventive concept is not limited thereto. For example, in some example embodiments, the lower electrode 150 may not be exposed through the mask holes H1.

[0046] Referring to Figure 8 , each mask hole H1 may have a circular shape and may open / expose two lower electrodes 150. The mask holes H1 may be arranged in a pattern (e.g., a predetermined pattern). For example, each mask hole H1 may be arranged between four adjacent lower electrodes 150. Each mask hole H1 may be located between two adjacent lower electrodes 150 spaced apart from each other in a first direction D1. The distance between two adjacent mask holes H1 may be twice the distance between the lower electrodes 150. For example, the distance between adjacent mask holes H1 may be 6.0F. The plurality of mask holes H1 may have a honeycomb structure in which the plurality of mask holes H1 are arranged at the centers and vertices of hexagons.

[0047] Figure 10 is a plan view showing an upper support pattern according to some example embodiments of the inventive concept. Figure 9 , Figure 11 and Figure 12 may correspond to a manufacturing process according to a vertical cross-section taken along line I-I' of Figure 10 .

[0048] First, referring to Figure 9 , some of the upper support layer 135a may be etched using the support mask pattern 145 to form an upper support pattern 135. The upper support pattern 135 may be formed by a dry etching process. When performing the patterning process, the lower electrode 150 having an etching selectivity with respect to the upper support pattern 135 may not be etched. However, the lower electrode 150 is not limited thereto, and in some example embodiments, some of the lower electrodes 150 may also be etched. Some of the upper molding layer 125 may be exposed through the upper support pattern 135.

[0049] Referring to Figure 10, the support pattern may include a plurality of support holes H2. The support holes H2 may be formed at the positions of the corresponding mask holes H1, and the width of the support holes H2 may be greater than the width of the mask holes H1. Each support hole H2 has an elliptical shape and may extend across four adjacent lower electrodes 150. For example, the support hole H2 may have an elliptical shape with a minor axis along the first direction D1 and a major axis along the second direction D2. The distance between the centers of the support holes H2 may be 6.0F. The plurality of support holes H2 may have a honeycomb structure in which the plurality of support holes H2 are provided at the centers and vertices of a hexagon.

[0050] Referring Figure 10 and Figure 11 , the upper molding layer 125 may be removed. The upper molding layer 125 may be removed by a wet etching process. For example, when the upper molding layer 125 includes silicon oxide, a solution including HF, NH4F, etc. may be used to perform the etching process. When performing the etching process, the lower support pattern 130 and the upper support pattern 135 having etching selectivity with respect to the upper molding layer 125 may not be removed.

[0051] Next, some of the lower support layer 130a may be etched using the support mask pattern 145. The lower support layer 130a may be patterned to form the lower support pattern 130. The lower support pattern 130 includes a plurality of support holes H3 and may have substantially the same shape as the upper support pattern 135. In some example embodiments, the support holes H3 may be smaller than the support holes H2.

[0052] Referring Figure 12 , the lower molding layer 120 may be removed. For example, the lower molding layer 120 may be removed by a wet etching process. The etching stop film 110, the lower support pattern 130, and the upper support pattern 135 having etching selectivity with respect to the lower molding layer 120 may not be removed. Removing the lower molding layer 120 enables a cavity C to be formed between the lower electrodes 150 and between the lower support pattern 130 and the upper support pattern 135. The lower support pattern 130 and the upper support pattern 135 may support and connect the plurality of lower electrodes 150.

[0053] Referring again Figure 2 , a capacitor dielectric layer 160 and an upper electrode 170 may be formed on the synthesized structure shown in Figure 12 . For example, the capacitor dielectric layer 160 may be formed conformally along the surfaces of the etching stop film 110, the lower support pattern 130, the upper support pattern 135, and the lower electrodes 150.

[0054] The capacitor dielectric layer 160 may include metal oxides such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and / or TiO2, dielectric materials such as SrTiO3 (STO), BaTiO3, PZT, and PLZT having a perovskite structure, and / or combinations thereof. The capacitor dielectric layer 160 may be formed by a CVD process and / or an ALD process, etc.

[0055] The upper electrode 170 may be formed to cover the capacitor dielectric layer 160. The upper electrode 170 may fill all the spaces between the lower electrodes 150, between the lower support pattern 130 and the upper support pattern 135, etc. The lower electrode 150, the capacitor dielectric layer 160, and the upper electrode 170 may be used as a capacitor.

[0056] The upper electrode 170 may include the same material as the lower electrode 150. For example, the upper electrode 170 may include TiN. The upper electrode 170 may be formed by a CVD process, an ALD process, etc.

[0057] As Figures 7 to 10 shown, the mask hole H1 may be provided between four adjacent lower electrodes 150. Each support hole H2 formed according to the pattern of the mask hole H1 may be provided between the four adjacent lower electrodes 150 to substantially expose all the lower electrodes 150. Since all the lower electrodes 150 are exposed, subsequent processes may be performed uniformly or more uniformly. In addition, since the support holes H2 are formed along the pattern of the circular mask hole H1, the possibility that adjacent support holes H2 are connected to each other may be prevented or reduced. Accordingly, the possibility of the problem that the lower electrode 150 collapses during the process may be prevented or reduced.

[0058] Figure 13 is an enlarged view showing a part of the upper support pattern according to some embodiments of the inventive concept.

[0059] Referring to Figure 8 and Figure 13, a mask hole H1 may be formed across two adjacent lower electrodes 150. The upper support layer 135a may be patterned using the mask hole H1 to form a support hole H2 that opens four lower electrodes 150. Since the upper support layer 135a is etched from the portion exposed by the mask hole H1, the two exposed lower electrodes 150 may be more open than the two remaining lower electrodes 150. In some example embodiments, before forming the support hole H2, the first lower electrode 150a and the second lower electrode 150b may be exposed by the mask hole H1. The support hole H2 formed by the patterning process may open the first lower electrode 150a, the second lower electrode 150b, the third lower electrode 150c, and the fourth lower electrode 150d. The first lower electrode 150a and the second lower electrode 150b may be more open than the third lower electrode 150c and the fourth lower electrode 150d. For example, the first open area S1 opened by the first lower electrode 150a or the second lower electrode 150b may be larger than the second open area S2 opened by the third lower electrode 150c or the fourth lower electrode 150d. That is, the first open area S1 of the first lower electrode 150a and the second lower electrode 150b near the center of the support hole H2 may be larger than the second open area S2 of the third lower electrode 150c and the fourth lower electrode 150d.

[0060] Figure 14A , Figure 15A , Figure 16A , Figure 17A and Figure 18A is a plan view illustrating a support mask pattern according to some example embodiments of the inventive concepts. Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B is a plan view illustrating an upper supporting pattern according to some example embodiments of the inventive concepts. Figure 14B , Figure 15B , Figure 16B , Figure 17B and Figure 18B Each upper support pattern 135 shown in FIG. 1 includes a plurality of support holes H2 having an elliptical shape, and the plurality of support holes H2 may substantially open all of the lower electrodes 150. For example, the support holes H2 may be provided so that all of the lower electrodes 150 are opened in the remaining region except for the edge region of the upper support pattern 135.

[0061] Reference Figure 14A , the support mask pattern 145 may include a plurality of mask holes H1. Figure 14B , you can use Figure 14A The support mask pattern 145 shown in FIG. 1 forms the upper support pattern 135 .

[0062] A plurality of support holes H2 can be arranged to be spaced apart from each other by a certain distance (e.g., a predetermined distance) in the second direction D2 to form columns. For example, the distance between the plurality of support holes H2 forming the columns can be about 5.2F (e.g., about 3 times the square root of 3F). In this specification, the distance between the support holes H2 can be defined as the distance between the centers of the support holes H2. The columns can be arranged to be spaced apart from each other in the first direction D1. For example, the columns can be arranged to be spaced apart from each other by 4.5F in the first direction D1. In addition, adjacent columns can be arranged to be misaligned with each other. For example, they can be arranged in a lattice shape that is offset from each other by about 2.6F in the second direction D2.

[0063] Referring to Figure 15A , the support mask pattern 145 can include a plurality of mask holes H1. Referring to Figure 15B , the upper support pattern 135 can be formed using the support mask pattern 145 shown in Figure 15A .

[0064] A plurality of support holes H2 can be arranged to be spaced apart from each other by a certain distance (e.g., a predetermined distance) to form a lattice structure. For example, the centers of the support holes H2 can be arranged to be spaced apart from each other by 6.0F in the first direction D1 and the second direction D2. The support holes H2 can have an elliptical shape with a short axis along the third direction D3 and a long axis along the fourth direction D4. Here, the third direction D3 can be defined as the direction inclined 30° counterclockwise from the second direction D2. The fourth direction D4 can be defined as the direction inclined 30° counterclockwise from the axis of the first direction D1. The third direction D3 can be orthogonal or perpendicular to the fourth direction D4.

[0065] Referring to Figure 16A , the support mask pattern 145 can include a plurality of mask holes H1. Referring to Figure 16B , the upper support pattern 135 can be formed using the support mask pattern 145 shown in Figure 16A .

[0066] A plurality of support holes H2 can be arranged to be spaced apart from each other by a certain distance (e.g., a predetermined distance) to form a lattice structure. For example, the centers of the support holes H2 can be arranged to be spaced apart from each other by 6.0F in the first direction D1 and the second direction D2. The support holes H2 can have an elliptical shape with a long axis along the fifth direction D5 and a short axis along the sixth direction D6. Here, the fifth direction D5 can be defined as the direction inclined 30° clockwise from the axis of the first direction D1. The sixth direction D6 can be the direction inclined 30° clockwise from the axis of the second direction D2. The fifth direction D5 can be orthogonal or perpendicular to the sixth direction D6.

[0067] Referring to Figure 17A, the support mask pattern 145 may include a plurality of first mask holes H1a and a plurality of second mask holes H1b. Referring to 17B, the upper support pattern 135 may be formed using the support mask pattern 145 shown in Figure 17A .

[0068] The upper support pattern 135 may include a plurality of first support holes H2a and a plurality of second support holes H2b, and the plurality of first support holes H2a and the plurality of second support holes H2b are arranged to be misaligned. The plurality of first support holes H2a and the plurality of second support holes H2b may be respectively disposed at positions of the plurality of first mask holes H1a and the plurality of second mask holes H1b. The plurality of first support holes H2a or the second support holes H2b may form columns spaced apart from each other in the second direction D2. For example, the plurality of first support holes H2a may form a first column spaced apart from each other in the second direction D2 by about 5.2F (e.g., about 3 times the square root of 3F). In addition, the plurality of second support holes H2b may form a second column spaced apart from each other in the second direction D2 by about 5.2F. The first column and the second column may be alternately arranged in the first direction D1. For example, the columns may be arranged to be spaced apart from each other in the first direction D1 by 6.0F. In addition, adjacent columns may be arranged to be misaligned with each other. For example, they may be arranged in a lattice shape staggered from each other by about 2.6F in the second direction D2. The first support hole H2a may have an elliptical shape having a major axis along the fifth direction D5 and a minor axis along the sixth direction D6. The second support hole H2b may have an elliptical shape having a minor axis along the third direction D3 and a major axis along the fourth direction D4.

[0069] Referring to Figure 18A , the support mask pattern 145 may include a plurality of first mask holes H1a, a plurality of second mask holes H1b, and a plurality of third mask holes H1c. Referring to Figure 18B , the upper support pattern 135 may be formed using the support mask pattern 145 shown in Figure 18A .

[0070] The upper support pattern 135 may include a plurality of first support holes H2a, a plurality of second support holes H2b, and a plurality of third support holes H2c. The plurality of first support holes H2a, the plurality of second support holes H2b, and the plurality of third support holes H2c may be respectively disposed at positions of the plurality of first mask holes H1a, the plurality of second mask holes H1b, and the plurality of third mask holes H1c. The first support hole H2a may have an elliptical shape having a major axis along the fifth direction D5 and a minor axis along the sixth direction D6. The second support hole H2b may have an elliptical shape having a minor axis along the third direction D3 and a major axis along the fourth direction D4. The third support hole H2c may have an elliptical shape having a minor axis along the first direction D1 and a major axis along the second direction D2.

[0071] A plurality of first support holes H2a and a plurality of second support holes H2b may form a first column arranged to be spaced apart from each other by a certain distance (e.g., a predetermined distance) in a second direction D2. For example, the first column may have a structure in which the first support holes H2a and the second support holes H2b are alternately arranged. The adjacent first support hole H2a and second support hole H2b may be arranged to be spaced apart from each other by 1.5F in a first direction D1 and by 5.2F in the second direction D2. A plurality of third support holes H2c may form a second column arranged to be spaced apart from each other by 10.2F in the second direction D2. The distance between the centers of the plurality of third support holes H2c may be 10.2F. The first column and the second column may be alternately arranged in the first direction D1.

[0072] Figure 19 is a cross-sectional view showing a semiconductor device according to some example embodiments of the inventive concept.

[0073] Referring to Figure 19 , the semiconductor device may include memory cells. The memory cells may include word lines, bit lines BL, and capacitors. The capacitors may include Figure 2 the lower electrode 150, the capacitor dielectric layer 160, and the upper electrode 170 shown in

[0074] The substrate 102 may include an active region 14 and an element isolation layer 16. The active region 14 and the element isolation layer 16 may be disposed on the substrate 102. The element isolation layer 16 may have a shallow trench isolation (STI) structure and include an insulating material. For example, the element isolation layer 16 may include silicon oxide. The impurity region 18 may be disposed in the active region 14. The impurity region 18 may have n-type conductivity. The impurity region 18 may be doped with at least one of phosphorus and arsenic.

[0075] The gate insulating layer 20 and the gate electrode 22 may be disposed in the substrate 102. The gate electrode 22 may be or may include a word line. The upper surface of the gate electrode 22 may be positioned at a level lower than the upper surface of the substrate 102. The gate electrode 22 includes a conductive material, for example, may include doped polysilicon, a metal material, and / or a metal silicide material. The gate insulating layer 20 may be disposed to surround the side surface and the lower surface of the gate electrode 22. The gate insulating layer 20 may include an insulating material such as silicon oxide and / or a high-k dielectric material. The gate capping layer 24 may be disposed on the gate electrode 22. The gate capping layer 24 may include silicon nitride, silicon oxynitride, or a combination thereof.

[0076] The first insulating pattern 30 may be disposed on the upper surface of the substrate 102. The first insulating pattern 30 may cover the upper surface of the gate capping layer 24. The first insulating pattern 30 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and may be formed as a single layer or multiple layers.

[0077] The bit line contact plug DC can pass through the first insulating pattern 30 and can be disposed on the impurity region 18. The upper surface of the substrate 102 can be recessed such that the lower surface of the bit line contact plug DC is positioned at a level lower than the upper surface of the substrate 102. The horizontal width of the bit line contact plug DC can be greater than the horizontal width of the impurity region 18, and the bit line contact plug DC can be electrically connected to the impurity region 18. The bit line contact plug DC can include a conductive material such as doped polysilicon, metal, and / or metal silicide.

[0078] The bit line structure BLS can include a bit line BL and a second insulating pattern 44 sequentially stacked on the bit line contact plug DC. The bit line BL can include a first conductive pattern 40 and a second conductive pattern 42 disposed on the first conductive pattern 40. The first conductive pattern 40 can include doped polysilicon, and the second conductive pattern 42 can include at least one of tungsten (W), aluminum (Al), copper (Cu), nickel (Ni), and cobalt (Co). The second insulating pattern 44 can be disposed on the second conductive pattern 42 and can include silicon nitride and / or silicon oxynitride.

[0079] The bit line spacer 46 is formed on the side surfaces of the bit line contact plug DC and the bit line structure BLS, and the bit line spacer 46 can have a pair of structures facing each other with the bit line contact plug DC and the bit line structure BLS therebetween. The bit line spacer 46 can include silicon oxide, silicon nitride, or silicon oxynitride, and can also include air gaps therein.

[0080] The storage node contact BC is disposed between the bit lines BL and can be disposed on the edges on both sides of the active region 14. The storage node contact BC is formed to pass through the first insulating pattern 30 and can be electrically connected to the impurity region 18. The upper surface of the storage node contact BC can be positioned at a level higher than the upper surface of the first insulating pattern 30. The storage node contact BC can include doped polysilicon and / or metal.

[0081] The third insulating pattern 48 can be disposed on the first insulating pattern 30 between the storage node contacts BC. The third insulating pattern 48 can electrically insulate the storage node contacts BC from each other. The upper surface of the third insulating pattern 48 can be positioned at a level higher than the upper surface of the storage node contact BC. The third insulating pattern 48 can include silicon nitride.

[0082] The blocking pattern 50 may be disposed on the storage node contact BC and the third insulating pattern 48, and a landing pad LP may be disposed on the blocking pattern 50. The landing pad LP may be a contact plug and may be electrically connected to the lower electrode 150. The blocking pattern 50 may protect the landing pad LP and the storage node contact BC. The blocking pattern 50 may include TiN, Ti / TiN, TiSiN, TaN, and / or WN. The landing pad LP may include tungsten.

[0083] The fourth insulating pattern 52 may be disposed between the landing pads LP. The lower end of the fourth insulating pattern 52 may pass through the blocking pattern 50 and may be connected to the third insulating pattern 48. The fourth insulating pattern 52 may be the lower insulating layer 106. The upper surface of the fourth insulating pattern 52 may be positioned at the same level as the upper surface of the landing pad LP. The fourth insulating pattern 52 may electrically insulate the landing pads LP from each other. The fourth insulating pattern 52 may include silicon oxide, silicon nitride, and / or silicon oxynitride.

[0084] Figure 20 is an enlarged view showing a part of the upper support pattern according to some example embodiments of the inventive concept. Figure 21 shows along Figure 20 a vertical cross-sectional view of the semiconductor device taken along lines II-II' and III-III'.

[0085] Referring to Figure 20 and Figure 21 , the semiconductor device may include a first lower electrode 150a, a second lower electrode 150b, a third lower electrode 150c, and a fourth lower electrode 150d. The first lower electrode 150a may have substantially the same cross-sectional area as the second lower electrode 150b. The third lower electrode 150c may have substantially the same cross-sectional area as the fourth lower electrode 150d.

[0086] Referring to Figure 9 and Figure 11 , the support hole H2, the first lower electrode 150a exposed through the mask hole H1 when forming the support hole H2, and the second lower electrode 150b may be etched first. When performing the etching process, some of the upper ends of the first lower electrode 150a and the second lower electrode 150b may be removed. Referring again to Figure 21 , the cross-sectional area of the first lower electrode 150a may be different from the cross-sectional areas of the third lower electrode 150c and the fourth lower electrode 150d. For example, the cross-sectional area of the upper surface of the first lower electrode 150a may be smaller than the cross-sectional area of the upper surface of the third lower electrode 150c.

[0087] Figure 22A is a plan view showing a support mask pattern according to some example embodiments of the inventive concept. Figure 22BIt is a plan view showing a support pattern according to some example embodiments of the inventive concept.

[0088] Referring to Figure 22A and Figure 22B , the support mask pattern 145 may include a plurality of mask holes H1. The mask holes H1 may have a circular shape and may be disposed between four adjacent lower electrodes 150. The upper support pattern 135 may include a plurality of support holes H2. The support holes H2 may be formed across four adjacent lower electrodes 150. Each support hole H2 may have an elliptical shape. Each support hole H2 may expose four lower electrodes 150, but there may be lower electrodes 150 among the plurality of lower electrodes 150 that are not exposed.

[0089] According to some example embodiments, the contact area between the support pattern and the lower electrode may be uniformly controlled.

[0090] Although some example embodiments of the inventive concept have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that the inventive concept may be implemented in other specific forms without changing the technical scope or essential features. The above embodiments should be considered only in a descriptive sense and not for purposes of limitation.

Claims

1. A semiconductor device, comprising: a substrate; a plurality of lower electrodes disposed above the substrate, the plurality of lower electrodes including a plurality of first lower electrodes and a plurality of second lower electrodes, the plurality of first lower electrodes and the plurality of second lower electrodes being respectively arranged in a first direction and alternately arranged in a second direction perpendicular to the first direction, each of the plurality of second lower electrodes being offset from each of the plurality of first lower electrodes with respect to the second direction; a support structure contacting the plurality of lower electrodes; a plurality of support holes disposed in the support structure and arranged in the first direction and in the second direction; a dielectric layer disposed on the plurality of lower electrodes; and an upper electrode disposed on the dielectric layer, wherein one of the plurality of support holes exposes two of the plurality of first lower electrodes and exposes two of the plurality of second lower electrodes among the plurality of lower electrodes, and the area of the side surface of at least one of the two first lower electrodes exposed by the one of the plurality of support holes among the plurality of first lower electrodes is larger than the area of the side surface of at least one of the two second lower electrodes exposed by the one of the plurality of support holes among the plurality of second lower electrodes.

2. The semiconductor device according to claim 1, wherein, The width of the one of the plurality of support holes in the first direction is smaller than the width of the one of the plurality of support holes in the second direction.

3. The semiconductor device according to claim 1, wherein, The plurality of support holes are offset from each other with respect to the first direction and with respect to the second direction.

4. The semiconductor device according to claim 1, wherein, Each of the plurality of lower electrodes is columnar in shape.

5. The semiconductor device according to claim 1, wherein, Each of the plurality of lower electrodes is cylindrical in shape with a recessed portion.

6. The semiconductor device according to claim 1, wherein, The support structure includes a lower support structure having a plurality of lower support holes and an upper support structure having a plurality of upper support holes, the lower support structure being at a lower level than the upper support structure with respect to the main surface of the substrate, and the plurality of lower support holes and the plurality of upper support holes being stacked on top of each other in a direction perpendicular to the main surface of the substrate.

7. The semiconductor device according to claim 1, wherein, Each of the plurality of lower electrodes and the upper electrode includes titanium nitride.

8. The semiconductor device according to claim 1, wherein, The dielectric layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide.

9. The semiconductor device according to claim 1, wherein, The plurality of lower electrodes are arranged in a honeycomb structure in which the plurality of lower electrodes are located at the center and vertices of a hexagon.

10. The semiconductor device according to claim 1, wherein, The plurality of first lower electrodes are arranged side by side with the plurality of support holes in the first direction, and the plurality of second lower electrodes are arranged side by side with the plurality of support holes in the second direction, and the plurality of support holes expose all of the plurality of first lower electrodes and the plurality of second lower electrodes.

11. The semiconductor device according to claim 1, wherein, The minimum distance from the central portion of the cross section of the plurality of first lower electrodes to the plurality of support holes is smaller than the minimum distance from the central portion of the cross section of the plurality of second lower electrodes to the plurality of support holes.

12. The semiconductor device according to claim 1, wherein, When viewed from the inside of the plurality of support holes, the plurality of support holes protrude in the first direction.

13. A semiconductor device, comprising: a substrate; A plurality of lower electrodes are disposed above a substrate. The plurality of lower electrodes include a plurality of first lower electrodes and a plurality of second lower electrodes. The plurality of first lower electrodes and the plurality of second lower electrodes are respectively arranged in a first direction and alternately arranged in a second direction perpendicular to the first direction. Each of the plurality of lower electrodes is a cylindrical shape having a recessed portion; A support structure contacts the plurality of lower electrodes; A plurality of support holes are provided in the support structure and are arranged in the first direction and in the second direction; A dielectric layer is provided on a side surface of each of the plurality of lower electrodes and on the recessed portion; And An upper electrode is provided on the dielectric layer and fills the recessed portion of each of the plurality of lower electrodes, wherein each of the plurality of second lower electrodes is offset from each of the plurality of first lower electrodes with respect to the second direction, wherein one of the plurality of support holes exposes two of the plurality of first lower electrodes and exposes two of the plurality of second lower electrodes among the plurality of lower electrodes, a width of the one of the plurality of support holes in the first direction is smaller than a width of the one of the plurality of support holes in the second direction, the plurality of support holes are offset from each other with respect to the first direction and with respect to the second direction, and a side surface area of at least one of the two first lower electrodes exposed by the one of the plurality of support holes among the plurality of first lower electrodes is larger than a side surface area of at least one of the two second lower electrodes exposed by the one of the plurality of support holes among the plurality of second lower electrodes.

14. The semiconductor device according to claim 13, wherein, The dielectric layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide, and each of the plurality of lower electrodes and the upper electrode includes titanium nitride.

15. The semiconductor device according to claim 13, wherein, A minimum distance from a central portion of a cross section of the plurality of first lower electrodes to the plurality of support holes is smaller than a minimum distance from a central portion of a cross section of the plurality of second lower electrodes to the plurality of support holes.

16. The semiconductor device according to claim 13, wherein, When viewed from the inside of the plurality of support holes, the plurality of support holes protrude in the first direction.

17. A semiconductor device, comprising: A substrate; A plurality of lower electrodes are disposed above the substrate. The plurality of lower electrodes include a plurality of first lower electrodes and a plurality of second lower electrodes. The plurality of first lower electrodes and the plurality of second lower electrodes are respectively arranged in a first direction and alternately arranged in a second direction perpendicular to the first direction. Each of the plurality of lower electrodes is a columnar shape; A support structure contacts the plurality of lower electrodes; A plurality of support holes are provided in the support structure and are arranged in the first direction and in the second direction; A dielectric layer is provided on a side surface and a top surface of each of the plurality of lower electrodes; And An upper electrode is provided on the dielectric layer, wherein each of the plurality of second lower electrodes is offset from each of the plurality of first lower electrodes with respect to the second direction, Among them, one of the plurality of support holes exposes two of the plurality of first lower electrodes and two of the plurality of second lower electrodes among the plurality of lower electrodes. The width of the one support hole among the plurality of support holes in the first direction is smaller than the width of the one support hole among the plurality of support holes in the second direction. The plurality of support holes are offset from each other with respect to the first direction and with respect to the second direction, and The area of the side surface of at least one of the two first lower electrodes exposed by the one support hole among the plurality of support holes is larger than the area of the side surface of at least one of the two second lower electrodes exposed by the one support hole among the plurality of support holes.

18. The semiconductor device according to claim 17, wherein, The dielectric layer includes at least one of hafnium oxide, zirconium oxide, aluminum oxide, and titanium oxide, and Each of the plurality of lower electrodes and the upper electrode includes titanium nitride.

19. The semiconductor device according to claim 17, wherein, When viewed from the inside of the plurality of support holes, the plurality of support holes protrude in the first direction.

20. The semiconductor device according to claim 17, wherein The minimum distance from the central portion of the cross-section of the plurality of first lower electrodes to the plurality of support holes is smaller than the minimum distance from the central portion of the cross-section of the plurality of second lower electrodes to the plurality of support holes.

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