Flash memory and forming method thereof

Abstract

A method of forming a flash memory includes forming an isolation layer to surround a plurality of active regions, forming a plurality of gate stacks across the active regions and the isolation layer, implanting a dopant into an upper portion of the isolation layer to form a doped isolation layer, partially denting the doped isolation layer, and forming a plurality of gate stacks across the active regions and the isolation layer. And forming a dielectric material over the gate stack, the active region and the doped isolation layer.

Description

Technical Field

[0001] The present invention relates to flash memories, and more particularly to flash memories having air gaps. Background Art

[0002] To increase the device density of flash memory devices and improve their overall performance, existing techniques for manufacturing flash memory devices must focus on continuously reducing the device size. However, new challenges have emerged during the process of miniaturizing the minimum size of some components, such as contact plugs. Therefore, there is a need in the industry to improve the methods for manufacturing flash memory devices to overcome the problems caused by the reduction of device size. Summary of the Invention

[0003] In some embodiments of the present invention, a flash memory is provided. The flash memory includes a plurality of active regions on a substrate, a plurality of lower first isolation layers surrounding the active regions, a plurality of gate stacks spanning across the active regions, and a plurality of upper second isolation layers surrounding the active regions. An air gap is located in the second isolation layer, and the air gap includes a first portion between a first gate stack and a second gate stack, and a second portion between a first active region and a second active region.

[0004] In some embodiments of the present invention, a method for forming a flash memory is provided. The method includes forming an isolation layer to surround a plurality of active regions, forming a plurality of gate stacks spanning across the active regions and the isolation layer, implanting dopants into an upper portion of the isolation layer to form a doped isolation layer, partially etching the doped isolation layer, and forming a dielectric material on the gate stacks, the active regions, and the doped isolation layer. Brief Description of the Drawings

[0005] To make the features and advantages of the present invention more apparent and understandable, different embodiments are hereinafter specifically described in conjunction with the accompanying drawings as follows:

[0006] Figure 1 is a plan view (layout) showing a flash memory according to some embodiments.

[0007] Figures 2A-1 to 2G-3 is a cross-sectional view showing the flash memory at various intermediate stages of formation according to some embodiments.

[0008] Figure 3 is according to some embodiments, showing Figure 2G-2 a variation of the flash memory of

[0009] 100 Flash memory;

[0010] 102 Substrate;

[0011] 104 Active region;

[0012] 106 Tunnel oxide;

[0013] 108 First semiconductor layer;

[0014] 110, 132 Substrate layer;

[0015] 110' Doped substrate layer;

[0016] 112, 134 Isolation layer;

[0017] 112' Doped isolation layer;

[0018] 114 Gate stack;

[0019] 116 Gate dielectric layer;

[0020] 118 Second semiconductor layer;

[0021] 120 Conductive layer;

[0022] 122, 124 Mask layer;

[0023] 126 Depression;

[0024] 128 Protective layer;

[0025] 130 Trench;

[0026] 136 Air gap;

[0027] 136A First part;

[0028] 136B Second part;

[0029] 1000 Implantation process;

[0030] 1050 Annealing process;

[0031] D1 First direction;

[0032] D2 Second direction;

[0033] IS Isolation structure;

[0034] H, R1, R2 Depth;

[0035] T1, T2, T3 Thickness. Detailed implementation

[0036] The present invention will be fully described below with reference to the drawings of the embodiments of the present invention. However, the present invention can be implemented in various different embodiments and should not be limited to the embodiments described herein. The thicknesses of the layers and regions in the drawings are enlarged for clarity, and the same or similar reference numerals in each drawing denote the same or similar elements.

[0037] Figure 1A plan view (layout) of the flash memory 100 is shown. According to some embodiments of the present invention, as Figure 1 shown, the flash memory 100 includes a plurality of active regions 104 and an isolation structure IS surrounding the active regions 104. In some embodiments, the active regions 104 are semiconductor strips, and the isolation structure IS may include multiple layers of dielectric materials.

[0038] The flash memory 100 further includes a plurality of gate stacks 114 spanning the active regions 104 and the isolation structure IS. In some embodiments, the flash memory 100 can be used to form a NAND-type flash memory device. Each gate stack 114 includes a plurality of conductive layers, which can be configured as a floating gate, a control gate, and / or a word line of the flash memory device.

[0039] For simplicity and clarity, the plan view only shows some components of the flash memory 100. Some other components of the flash memory 100 can be shown in Figures 2A-1 to 2G-3 For ease of illustration, Figure 1 a reference direction is shown. The first direction D1 and the second direction D2 are horizontal directions. The first direction D1 is parallel to the long axis of the gate stack 114, and the second direction D2 is parallel to the long axis of the active region 104. In some embodiments, the first direction D1 and the second direction D2 are substantially perpendicular.

[0040] To improve the electrical properties of the flash memory device, such as data retention and / or cross-talk between memory cells (e.g., during programming, erasing, etc.), an air gap 136 can be formed in the isolation structure IS. The air gap 136 may include a first portion 136A and a second portion 136B. The first portion 136A extends along the first direction D1 between adjacent gate stacks 114, and the second portion 136B is formed between an adjacent active region 104 and an adjacent gate stack 114. The air gap 136 is configured to reduce the parasitic capacitance between adjacent gate stacks 114. For illustration, only one first portion 136A of the air gap 136 and a column of the second portion 136B are shown in Figure 1 However, the first portion 136A can be formed between any two adjacent gate stacks 114, and a column of the second portion 136B can be formed between any two adjacent active regions 104.

[0041] Figure 1 A reference cross-section is shown. The cross-section A-A is a plane parallel to the second direction D2 and passing through an active region 104. The cross-section B-B is a plane parallel to the second direction D2 and passing through the isolation structure IS. The cross-section C-C is a plane parallel to the first direction D1 and passing between the gate stacks 114.

[0042] Figures 2A-1 to 2G-3 are cross-sectional schematic views showing the formation of the flash memory 100 at various intermediate stages according to some embodiments. Figures 2A-1 to 2G-1 、 Figures 2A-2 to 2G-2 and Figures 2A-3 to 2G-3 correspond to Figure 1 the cross-sections A-A, B-B, and C-C in

[0043] Figure 2A-1 、 Figure 2A-2 and Figure 2A-3 show the flash memory after the formation of the active region 104 and the isolation layer 112. In some embodiments, a substrate 102 is provided. The substrate 102 can be an elemental semiconductor substrate, such as a silicon or germanium substrate, or a compound semiconductor substrate, such as a silicon carbide or gallium arsenide substrate. In some embodiments, the substrate 102 can be a semiconductor-on-insulator (SOI) substrate.

[0044] A tunneling oxide 106 and a first semiconductor layer 108 are sequentially formed on the substrate 102. The tunneling oxide 106 can be made of silicon oxide. The first semiconductor layer 108 can comprise doped polysilicon material. A patterned mask layer (not shown) can be formed on the first semiconductor layer 108, and the first semiconductor layer 108, the tunneling oxide 106, and the underlying substrate 102 are etched using the patterned mask layer to form trenches. The portions of the substrate 102 that protrude between the trenches form the active region 104.

[0045] A substrate layer 110 is formed along the first semiconductor layer 108, the tunneling oxide 106, the active region 104, and the substrate 102 to partially fill the trenches. The substrate layer 110 can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination of the foregoing. An isolation layer 112 is formed on the substrate layer 110 to overfill the trenches. The isolation layer 112 can be made of a silicon oxide-based material, such as spin-on glass (SOG) deposited using a spin coating process and then annealed or cured. In some embodiments, the isolation layer 112 is undoped. For example, the concentration of dopants (e.g., phosphorus) is less than 10 14 cm -3 .

[0046] A planarization process, such as chemical mechanical polishing (CMP) or back etching, is performed on the isolation layer 112 and the substrate layer 110 until the patterned mask layer (not shown) is exposed. Then a back etching process is performed to expose the sidewalls of the first semiconductor layer 108. In some embodiments, the thickness T1 of the isolation layer 112 and the underlying substrate layer 110 ranges from about 150 nanometers to about 200 nanometers.

[0047] Figure 2B-1 、 Figure 2B-2 andFigure 2B-3 The flash memory is shown after forming gate stacks 114. The gate stacks 114 are formed over the active region 104 and the isolation layer 112. Each gate stack 114 includes a tunnel oxide 106, a first semiconductor layer 108, an inter-gate dielectric layer 116, a second semiconductor layer 118, a conductive layer 120, a first mask layer 122, and a second mask layer 124. The first semiconductor layer 108 can be configured as a floating gate of the resulting flash memory device, and the second semiconductor layer 118 can be configured as a control gate of the resulting flash memory device. The conductive layer 120 can be configured as a word line of the resulting flash memory device.

[0048] The second semiconductor layer 118 may include a doped polysilicon material. The inter-gate dielectric layer 116 may be a three-layer structure including oxide-nitride-oxide (ONO). The conductive layer 120 may include tungsten (W), titanium (Ti), tantalum (Ta), tungsten nitride (WN), titanium nitride (TiN), tantalum nitride (TaN), cobalt silicide (CoSi), nickel silicide (NiSi) or tungsten silicide (WSi). The first and second mask layers 122 and 124 may be made of a dielectric material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO), other suitable materials and / or combinations thereof.

[0049] Using photolithography and etching processes, the mask layers 124 and 122, the conductive layer 120, the second semiconductor layer 118, the inter-gate dielectric layer 116, the first semiconductor layer 108, and the tunnel oxide 106 are patterned to form the gate stack 114. During the etching process, the tunnel oxide 106 not covered by the gate stack 114 remains on the top surface of the active region 104.

[0050] In the etching process for forming the gate stack 114, portions of the substrate layer 110 and the isolation layer 112 that are not covered by the gate stack 114 are etched back to form a recess 126. In some embodiments, the depth R1 of the recess 126 is in the range of about 30 nanometers to about 80 nanometers. In some embodiments, the ratio of the depth R1 to the thickness T1 is in the range of about 0.15 to about 0.53. If the ratio is too small, the size (or volume) of the air gap formed thereafter will be too small. If the ratio is too large, the variation in the depth R1 of the recess 126 between different locations will be too large, resulting in poor uniformity in the size of the air gap formed thereafter. This will cause the resulting flash memory device to have significant differences in electrical properties between different locations.

[0051] Figure 2C-1 , Figure 2C-2 and Figure 2C-3A flash memory after the implantation process 1000 is shown. The implantation process 1000 is performed on the flash memory 100 to introduce dopants into the isolation layer 112. The upper portion of the isolation layer 112 is doped to form a doped isolation layer 112'. The doped isolation layer 112' may have a faster etching rate than the undoped isolation layer 112 in subsequent etching processes, which can improve the etching rate variation of the doped isolation layer 112' between different positions in subsequent etching processes.

[0052] The implantation process 1000 can be performed using a high-current ion implanter or a similar device. Multiple ion beams are used to implant species or dopants in the implantation process 1000, which can be achieved by using multiple ion species that are ionized and accelerated to implant into the flash memory 100. In some embodiments, the implanted species (or dopants) may include phosphorus (P), boron (B), other suitable implanted species, combinations of the foregoing, or the like.

[0053] The tunneling oxide 106 can protect the active region 104. Therefore, in the implantation process 1000, the active region 104 is substantially undoped or slightly doped with dopants. The tunneling oxide 106 that is not covered by the gate stack 114 is also doped with dopants. In addition, the upper portion of the substrate layer 110 is doped to form a doped substrate layer 110'. As Figure 2C-3 shown, the doped isolation layer 112' extends to a deeper position than the doped substrate layer 110'.

[0054] Figure 2D-1 、 Figure 2D-2 and Figure 2D-3 A flash memory after the annealing process 1050 is shown. The annealing process 1050 is performed on the flash memory 100 to drive the dopants to a deeper position, thereby expanding the thickness of the doped isolation layer 112'. After the annealing process 1050, the thickness T2 of the doped isolation layer 112' is in the range of about 50 nanometers to about 100 nanometers. In some embodiments, the ratio of the thickness T2 to the thickness T1 is in the range of about 0.25 to about 0.67. If the ratio is too small, the etching rate variation of the doped isolation layer 112' between different positions may not be sufficiently improved. If the ratio is too large, this may have a negative impact on the gate stack 114 because driving the dopants to a deeper position requires a higher temperature and / or a longer time for the annealing process 1050.

[0055] In some embodiments, the annealing process 1050 can be a rapid thermal annealing (RTA) process. The annealing process 1050 is performed at a temperature of about 900°C to 1000°C for a duration of less than 1 second and in an environment of N2, Ar, or a combination of the foregoing.

[0056] Figure 2E-1 、Figure 2E-2 and Figure 2E-3 shows the flash memory after forming the protective layer 128. The protective layer 128 is formed on the flash memory 100 to partially fill the recess 126 and the space between the gate stacks 114. The protective layer 128 can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination of the foregoing. The protective layer 128 is configured to avoid damaging the active region 104 in a subsequent etching process.

[0057] Figure 2F-1 、 Figure 2F-2 and Figure 2F-3 shows the flash memory after the etching process. An etching process is performed on the flash memory 100 to etch the recessed doped isolation layer 112', the doped substrate layer 110', and the substrate layer 110. In some embodiments, the etching process can be isotropic etching, such as wet etching using diluted hydrofluoric acid. In the etching process, the protective layer 128 is removed. The recess 126 is enlarged in the vertical direction to a depth R2, where the depth R2 is measured downward from the upper surface of the tunneling oxide 106, and the recess 126 is enlarged laterally and connected to each other to form a trench 130.

[0058] Compared with the case of directly etching the undoped isolation layer 112, the variation of the depth R2 between different positions of the trench 130 becomes better because the doped isolation layer 112' has a faster etching rate in the etching process. The thickness T3 of the remaining doped isolation layer 112' is less than about 10 nanometers. In some embodiments, the doped isolation layer 112' can be completely removed (i.e., the thickness T3 is zero) in the etching process to expose the isolation layer 112.

[0059] Figure 2G-1 、 Figure 2G-2 and Figure 2G-3 shows the flash memory after forming the substrate layer 132, the isolation layer 134, and the air gap 136. The substrate layer 132 is conformally formed along the flash memory 100 to partially fill the trench 130. The substrate layer 132 can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination of the foregoing. The isolation layer 134 is formed on the substrate layer 132 to fill the space between the trench 130 and the gate stacks 114. The isolation layer 134 can be made of a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination of the foregoing. In some embodiments, the isolation layer 134 is undoped. For example, the concentration of dopants (such as phosphorus) is less than 10 14 cm -3 。

[0060] The isolation layer 134, the doped isolation layer 112', and the isolation layer 112 can jointly serve as Figure 1The isolation structure IS shown. The isolation layer 112 surrounds the lower part of the active region 104, the doped isolation layer 112' surrounds the middle part of the active region 104, and the isolation layer 134 surrounds the upper part of the active region 104.

[0061] The space between the trench 130 and the gate stack 114 is sealed by the isolation layer 134, thereby forming a plurality of air gaps 136. The air gap 136 includes a first portion 136A and a second portion 136B. The first portion 136A extends in a first direction D1 between adjacent gate stacks 114, and the second portion 136B is formed between an adjacent active region 104 and an adjacent gate stack 114. As Figure 2G-2 shown, in a second direction D2, the second portions 136B in a column are separated from each other by the isolation layer 134. As Figure 2G-3 shown, each first portion 136A is connected to a row (column) of second portions 136B in the first direction D1. In some embodiments, the second portion 136B may extend to a position directly below the gate stack 114. The top of the first portion 136A may be higher than the top surface of the gate stack 114.

[0062] Since the depth R2 of the trench 130 varies less between different positions, the depth H of the air gap 136 (measured downward from the upper surface of the active region 104) also has a small variation between different positions, as Figure 2G-3 shown. Therefore, the differences in electrical properties (e.g., data retention, and crosstalk between memory cells during operations such as programming, erasing, etc.) between different positions of the resulting flash memory device can be improved.

[0063] Figure 3 is a variation of a flash memory shown according to some embodiments Figure 2G-2 of. Figure 3 The embodiment of Figures 2A-1 to 2G-3 is similar to the embodiment of

[0064] except that the second portions 136B of the air gaps 136 in a column are connected to each other, thereby continuously extending below the gate stack 114 in the second direction D2.

[0065] Although the present invention has been disclosed above with the foregoing embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains, without departing from the spirit and scope of the present invention, may make some modifications and refinements. Therefore, the protection scope of the present invention shall be defined by the scope of the claims.

Claims

1. A flash memory, characterized in that, Comprising: Multiple active regions, on a substrate; A first isolation layer, surrounding multiple lower portions of the active regions; Multiple gate stacks, spanning across the active regions; And A second isolation layer, surrounding multiple upper portions of the active regions, wherein an air gap is located in the second isolation layer, and the air gap includes a first portion between a first gate stack and a second gate stack in the gate stacks, and a second portion between a first active region and a second active region in the active regions.

2. The flash memory according to claim 1, wherein Further comprising: A third isolation layer, surrounding multiple middle portions between the upper and lower portions of the active regions, wherein a doping concentration of the third isolation layer is higher than a doping concentration of the first isolation layer.

3. The flash memory according to claim 2, wherein The second isolation layer is doped with phosphorus, boron, or a combination of the foregoing.

4. The flash memory according to claim 1, wherein The second portion of the air gap extends directly below the first gate stack and the second gate stack.

5. The flash memory according to claim 1, characterized in that, A top end of the first portion of the air gap is higher than multiple top surfaces of the gate stacks.

6. The flash memory according to claim 1, wherein The second portion of the air gap continuously extends below the gate stacks.

7. The flash memory according to claim 1, characterized in that, The second isolation layer includes a portion extending below the gate stacks.

8. The flash memory according to claim 1, characterized in that, The air gap includes a third portion between a third active region and the second active region, and the first portion of the air gap connects the second portion and the third portion of the air gap.

9. The flash memory according to claim 1, wherein Each of the gate stacks includes a floating gate and a control gate located above the floating gate.

10. A method for forming a flash memory, characterized in that, Comprising: Forming an isolation layer to surround multiple active regions; Forming multiple gate stacks spanning across the active regions and the isolation layer; Injecting a dopant into an upper portion of the isolation layer to form a doped isolation layer; Partially etching the doped isolation layer; And Forming a dielectric material above the gate stacks, the active regions, and the doped isolation layer.

11. The method for forming a flash memory according to claim 10, wherein Further comprising: Performing an annealing process on the doped isolation layer after injecting the dopant into the upper portion of the isolation layer and before partially etching the doped isolation layer.

12. The method for forming a flash memory according to claim 10, wherein The step of forming the gate stacks spanning across the active regions and the isolation layer includes: Sequentially depositing a gate dielectric layer, a semiconductor layer, and a conductive layer; and Etching the gate dielectric layer, the semiconductor layer, the conductive layer, and etching the isolation layer.

13. The method for forming a flash memory according to claim 10, wherein, The isolation layer has multiple depressions between the gate stacks, and the step of partially etching the doped isolation layer includes: expanding the depressions such that the depressions are connected to each other to form a trench.

14. The method for forming a flash memory according to claim 13, wherein, The dielectric material seals the trench to form multiple air gaps.

15. The method for forming a flash memory according to claim 10, wherein The dopant includes phosphorus, boron, or a combination of the foregoing.

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