Resistive memory cell, resistive memory array including same, and method of manufacturing resistive memory cell

Abstract

The invention relates to a resistive memory cell, a resistive memory array including the resistive memory cell, and a method of manufacturing the resistive memory cell. A resistive memory cell may include a lower electrode, an upper electrode, a variable resistance layer, and a charge bypass layer. The upper electrode may be substantially perpendicular to the lower electrode. The variable resistance layer may be interposed between the lower electrode and the upper electrode. The variable resistance layer may have a resistance that varies by the conductive filament based on an electric field between the lower electrode and the upper electrode, and the conductive filament may include reversibly generated oxygen vacancies. When a voltage, which may be higher than a programming voltage applied to the upper electrode, may be applied to the lower electrode, the charge bypass layer may include a plurality of discontinuous vertical grain boundaries and a plurality of horizontal grain boundaries connected between the discontinuous vertical grain boundaries.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0000929, filed with the Korean Intellectual Property Office on January 3, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments generally relate to semiconductor integrated circuit technology, and more particularly, to resistive memory cells, resistive memory arrays including the resistive memory cells, and methods of manufacturing the resistive memory cells. Background Art

[0004] Recently, with the increasing demand for portable digital application devices such as digital cameras, tablet computers, and smartphones, the market for non - volatile memory devices has greatly expanded.

[0005] NAND flash memory devices are typical programmable non - volatile memory devices with improved storage capacity and multi - level and / or three - dimensional cell structures. However, the basic limitations of NAND flash memory devices have been exposed, from manufacturing difficulties to long drive times due to the block access architecture.

[0006] As an alternative to NAND flash memory devices, resistive memory devices can use variable resistors having a resistance that can be changed or reversed.

[0007] Resistive memory devices can include a variable resistance layer. Resistive memory devices can switch between a high - resistance state reflecting a data state and a reversible low - resistance state. Thus, resistive memory devices can switch quickly at a speed of no more than about 10 ns (nanoseconds). Resistive memory devices can be driven by low power of about 1 pJ (picojoule) / operation. In addition, resistive memory devices can include simple cells to facilitate effective scaling. Summary of the Invention

[0008] Example embodiments provide a resistive memory cell having improved switching characteristics.

[0009] Example embodiments also provide a resistive memory array including the above - mentioned resistive memory cells.

[0010] Example embodiments further provide a method of manufacturing the above - mentioned resistive memory cells.

[0011] According to an example embodiment, a resistive memory cell can be provided. The resistive memory cell can include a lower electrode, an upper electrode, a variable resistance layer, and a charge bypass layer. The upper electrode can be substantially perpendicular to the lower electrode. The variable resistance layer can be interposed between the lower electrode and the upper electrode. The variable resistance layer can have a resistance that changes through conductive filaments, which can include reversibly generated oxygen vacancies, based on an electric field between the lower electrode and the upper electrode. When a voltage that can be higher than a programming voltage applied to the upper electrode can be applied to the lower electrode, the charge bypass layer can include a plurality of discontinuous vertical grain boundaries and a plurality of horizontal grain boundaries connecting adjacent discontinuous vertical grain boundaries.

[0012] In an example embodiment, the charge bypass layer can include at least one conductive two-dimensional (2D) layer.

[0013] According to an example embodiment, a resistive memory array can be provided. The resistive memory array can include a plurality of bit lines, a plurality of word lines intersecting the bit lines, and a plurality of resistive memory cells located between the bit lines and the word lines. The resistive memory cell can include a programming electrode, a ground electrode, a variable resistance layer, and a charge bypass layer. The programming electrode can be electrically connected to the bit line to receive a programming voltage. The ground electrode can be electrically connected to the word line to generate a vertical electric field together with the programming electrode. The variable resistance layer can be interposed between the programming electrode and the ground electrode. The variable resistance layer can have a resistance that changes through conductive filaments, which can include oxygen vacancies selectively formed based on the vertical electric field. The charge bypass layer can be disposed between the ground electrode and the variable resistance layer. When the programming voltage can be lower than the voltage of the ground electrode, the charge bypass layer can bypass oxygen vacancies generated from the ground electrode to horizontal grain boundaries that can be substantially perpendicular to the vertical electric field to inhibit oxygen vacancies in the horizontal grain boundaries of the charge bypass layer.

[0014] According to an example embodiment, a method of manufacturing a resistive memory cell can be provided. In the method of manufacturing a resistive memory cell, a lower electrode can be formed. A seed layer can be formed on the lower electrode. The charge bypass layer including a conductive 2D material layer can be formed using the seed layer. The variable resistance layer can be formed on the charge bypass layer. An oxygen vacancy storage layer can be formed on the variable resistance layer. The upper electrode can be formed on the oxygen vacancy storage layer.

[0015] In an example embodiment, the seed layer can include graphene.

[0016] According to an exemplary embodiment, in order to prevent reset errors of memory cells in a resistive memory device, a charge bypass layer including at least one conductive 2D material layer may be interposed between an electrode (e.g., a lower electrode) having a relatively high voltage and a variable resistance layer. Unwanted charges generated in the variable resistance layer and the lower electrode adjacent to each other in the vertical direction may be bypassed horizontally by the charge bypass layer. Accordingly, charge exchange between the variable resistance layer and the lower electrode may be blocked, so that unwanted abnormal filaments are not generated. As a result, in a reset operation, the variable resistance layer may be maintained in a high resistance state. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features, and advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a block diagram showing a resistive memory device according to an embodiment of the present disclosure;

[0019] Figure 2 is a perspective view showing a part of a resistive memory array according to an embodiment of the present disclosure;

[0020] Figure 3 is a cross-sectional view showing a resistive memory cell according to an embodiment of the present disclosure;

[0021] Figure 4 is a view showing grains of a charge bypass layer according to an embodiment of the present disclosure;

[0022] Figures 5A to 5C is a cross-sectional view showing a charge bypass layer according to an embodiment of the present disclosure;

[0023] Figure 6 is a cross-sectional view showing a resistive memory cell for explaining a set programming operation according to an embodiment of the present disclosure;

[0024] Figure 7 is a cross-sectional view showing a resistive memory cell for explaining a reset programming operation according to an embodiment of the present disclosure;

[0025] Figure 8 is a cross-sectional view showing a resistive memory cell for explaining a read operation according to an embodiment of the present disclosure;

[0026] Figure 9 is a flowchart showing a method of manufacturing a resistive memory cell of a resistive memory device according to an embodiment of the present disclosure;

[0027] Figure 10 is a view showing Figure 9 the steps for forming a charge bypass layer; and

[0028] Figures 11 to 14 is a cross-sectional view showing a method of manufacturing a resistive memory cell according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Various embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The accompanying drawings are schematic illustrations of various embodiments (and intermediate structures). Accordingly, variations in the illustrated configurations and shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Thus, the described embodiments should not be construed as limited to the specific configurations and shapes shown herein, but may include deviations in configurations and shapes that do not depart from the spirit and scope of the present invention as defined by the appended claims.

[0030] The present invention is described herein with reference to cross-sectional views and / or plan views of idealized embodiments of the invention. However, embodiments of the present invention should not be construed as limiting the inventive concept. Although some embodiments of the present invention will be shown and described, those of ordinary skill in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the present invention.

[0031] As used herein, the term "configured" means that the dimensions, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one device are in a predetermined manner to facilitate the operation of one or more of the structure and the device.

[0032] As used herein, the terms "vertical," "longitudinal," "horizontal," and "lateral" refer to the principal plane of a structure and are not necessarily defined by the earth's gravitational field. A "horizontal" or "lateral" direction is a direction substantially parallel to the principal plane of the structure, while a "vertical" or "longitudinal" direction is a direction substantially perpendicular to the principal plane of the structure. The principal plane of a structure is defined by the surface of the structure having a relatively large area compared to the other surfaces of the structure. Referring to the accompanying drawings, a "horizontal" or "lateral" direction can be perpendicular to the indicated "Z" axis and can be parallel to the indicated "X" axis and / or parallel to the indicated "Y" axis; a "vertical" or "longitudinal" direction can be parallel to the indicated "Z" axis, can be perpendicular to the indicated "X" axis, and can be perpendicular to the indicated "Y" axis.

[0033] As used herein, for ease of description, spatial relative terms (such as "below", "beneath", "bottom", "above", "upper", "top", "front", "rear", "left", "right", etc.) may be used to describe the relationship of one element or feature to another element or feature, as shown in the figures. Unless otherwise stated, spatial relative terms are intended to cover different orientations of the material in addition to the orientations depicted in the figures. For example, if the material in the figures is inverted, an element described as "below" or "beneath" or "under" or "on the bottom" of another element or feature will be oriented "above" or "on the top" of the other element or feature. Thus, depending on the context in which the term is used, the term "below" can cover both the above and below orientations, which will be apparent to those of ordinary skill in the art. The material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped) and the spatial relative descriptors used herein are to be interpreted accordingly.

[0034] As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms.

[0035] As used herein, the phrases "coupled to" and "connected to" refer to structures that are operably connected to each other, such as being electrically connected by a direct ohmic connection or by an indirect connection (e.g., through another structure).

[0036] The resistive memory device of an example embodiment can be applied to a neural network system. The resistive memory device can include a resistive memory array and a circuit block configured to control the resistive memory array. The resistive memory array can include a plurality of resistive memory cells having a charge bypass layer. The charge bypass layer can be interposed between a variable resistance layer and an electrode having a relatively high voltage to block the exchange of charges (such as oxygen vacancies and oxygen ions) between the electrode and the variable resistance layer. The charge bypass layer can include at least one two-dimensional (2D) conductive layer or semiconductor layer. The 2D conductive layer or semiconductor layer can include a plurality of discontinuous vertical grain boundaries and a plurality of horizontal grain boundaries connecting between the discontinuous vertical grain boundaries, and can be arranged such that the diffusion path of the charge bypass layer can include the horizontal grain boundaries located between adjacent discontinuous vertical grain boundaries and the plurality of discontinuous vertical grain boundaries. Thus, oxygen vacancies and oxygen ions located between the electrode and the vertically adjacent variable resistance layer can diffuse along the horizontal grain boundaries.

[0037] Figure 1 is a block diagram showing a resistive memory device according to an embodiment of the present disclosure.

[0038] Refer to Figure 1, the resistive memory device 10 may include a resistive memory array 100, a row decoding block 110, a column decoding block 120, a sense amplifier block 130, a memory controller 140, and an input / output circuit block 150.

[0039] The resistive memory array 100 may include a plurality of resistive memory cells MC. The resistive memory cells MC may be programmable to different logic states. In an embodiment, each resistive memory cell MC may be programmed to two states: a low resistance and a high resistance, represented by logic 0 (e.g., logic low) and logic 1 (e.g., logic high). The resistive memory cells MC may be reversibly switched between the low resistance state and the high resistance state.

[0040] In an embodiment, the resistive memory cells MC may be arranged in a neural memory unit for mimicking neural network functions such as learning functions, e.g., in a cross-point array shape.

[0041] In an embodiment, the resistive memory cell MC may include a variable resistance layer. The variable resistance layer may be changed to a low resistance state (hereinafter, referred to as a set state) or a high resistance state (hereinafter, referred to as a reset state) according to the applied voltage and the shape of the applied voltage.

[0042] A voltage change that changes the characteristics of the variable resistance layer may be applied, i.e., a change in the threshold voltage may indicate a synaptic weight in a neuromorphic system. A change in the synaptic weight may represent learning or be explained by learning, and may be similar to a change in a biological synaptic function.

[0043] The resistive memory array 100 may include a plurality of word lines WL0 to WL2 and a plurality of bit lines BL0 to BL2. In an embodiment, the word lines WL0 to WL2 and the bit lines BL0 to BL2 may cross each other. The resistive memory cell MC may be connected to the cross-section between the word lines WL0 to WL2 and the bit lines BL0 to BL2. The cross-section may correspond to the address of the resistive memory cell MC.

[0044] In an embodiment, when selecting, programming, or reading a resistive memory cell MC, all the word lines and bit lines connected to the resistive memory cell MC may be activated. The resistive memory cell MC will be described in detail below.

[0045] The row decoding block 110 and the column decoding block 120 may select the resistive memory cell MC. For example, the row decoding block 110 may receive a row address from the memory controller 140. The row decoding block 110 may activate the word line WL based on the row address. The column decoding block 120 may receive a column address from the memory controller 140. The column decoding block 120 may activate the bit line BL based on the column address. Thus, the resistive memory cell MC that can be connected to the activated word line WL and the activated bit line BL may be accessed to perform a memory operation.

[0046] The sense amplifier block 130 can determine the programming state of the resistive memory cell MC, such as the resistance state. The sense amplifier block 130 can detect the current flowing through the resistive memory cell MC to sense the information in the selected resistive memory cell MC. The sense amplifier block 130 can use the current flowing through the resistive memory cell MC to sense the resistance state as a logic low (low resistance state) or a logic high (high resistance state).

[0047] The memory controller 140 can control the operations (such as read operations, write operations, etc.) of the resistive memory cell MC through various components such as the row decoding block 110, the column decoding block 120, and the sense amplifier block 130. For example, the memory controller 140 can receive various commands from an external device to generate a row address and a column address for selecting the resistive memory cell MC. In addition, the memory controller 140 can generate and control various voltages or currents for the operation of the resistive memory array 100.

[0048] The input / output circuit block 150 can be arranged to facilitate signal exchange between the row decoding block 110 and the memory controller 140, between the column decoding block 120 and the memory controller 140, and between the sense amplifier block 130 and the memory controller 140.

[0049] The resistive memory cells MC in the resistive memory array 100 can be grouped into memory cells, such as neural memory cells for storing analog data. Therefore, the memory controller 140 can be connected to the neural memory cells. Therefore, the memory controller 140 can be a neural memory cell controller. The neural memory cells can be configured and arranged to mimic a neural network architecture.

[0050] Figure 2 is a perspective view showing a part of a resistive memory array according to an embodiment of the present disclosure.

[0051] Referring to Figure 2 , the word lines WL0 and WL1 of the resistive memory array 100 can be arranged in parallel along the first direction D1. The bit lines BL0 and BL1 of the resistive memory array 100 can be located in a plane different from the plane in which the word lines WL0 and WL1 are located. The bit lines BL0 and BL1 can be arranged parallel to each other. The bit lines BL0 and BL1 can extend along a direction (e.g., the second direction D2) intersecting the first direction D1.

[0052] As described above, the resistive memory cell MC can be located at the intersection between the bit lines BL0 and BL1 and the word lines WL0 and WL1. Each resistive memory cell MC can include a bottom electrode BE, a charge bypass layer CD, a variable resistance layer RL, and a top electrode TE.

[0053] The lower electrode BE can be electrically connected to the word lines WL0 and WL1. The upper electrode TE can be electrically connected to the bit lines BL0 and BL1. Alternatively, the lower electrode BE can be electrically connected to the bit lines BL0 and BL1, and the upper electrode TE can be electrically connected to the word lines WL0 and WL1.

[0054] The variable resistance layer RL can include a material having a resistance that can be changed by a voltage difference between the upper electrode TE and the lower electrode BE (i.e., a vertical electric field between the upper electrode TE and the lower electrode BE).

[0055] The upper electrode TE can include an oxygen vacancy storage layer for generating charges such as oxygen vacancies.

[0056] The charge bypass layer CD can prevent the exchange of oxygen vacancies or oxygen ions between the lower electrode BE and the variable resistance layer RL. The charge bypass layer CD will be described in more detail below.

[0057] Figure 3 is a cross-sectional view showing a resistive memory cell according to an embodiment of the present disclosure, and Figure 4 is a view showing grains of a charge bypass layer according to an embodiment of the present disclosure.

[0058] Referring to Figure 3 , the resistive memory cell 200 can include a lower electrode 210, a charge bypass layer 220, a variable resistance layer 230, an oxygen vacancy storage layer 240, and an upper electrode 250.

[0059] The lower electrode 210 can include at least one of W, Au, Pt, Pd, Rh, Ir, Ru, Ti, Ta, Mo, Cr, and V, a nitride containing one or more of the above metals, a silicon compound containing one or more of the above metals, an oxide containing one or more of the above metals, etc.

[0060] The charge bypass layer 220 can be located between the lower electrode 210 and the variable resistance layer 230. The charge bypass layer 220 can prevent the exchange of unwanted oxygen vacancies and oxygen ions between the lower electrode 210 and the variable resistance layer 230.

[0061] In an embodiment, the charge bypass layer 220 can bypass oxygen vacancies generated from the lower electrode 210 in the horizontal directions D1 and D2, rather than bypassing in the vertical direction D3 in the direction of the variable resistance layer 230. In addition, the charge bypass layer 220 can prevent oxygen ions in the variable resistance layer 230 from diffusing in the vertical direction D3 in the direction of the lower electrode 210.

[0062] The charge bypass layer 220 can include at least one 2D material layer having conductivity. As Figure 4As shown, the charge bypass layer 220 may include a plurality of grain boundaries B configured to define a plurality of grains G. In an exemplary embodiment, the grain boundaries B of the charge bypass layer 220 may be diffusion paths for oxygen vacancies and oxygen ions (hereinafter referred to as charges).

[0063] In an embodiment, the grain boundaries B of the charge bypass layer 220 may include vertical grain boundaries VB and horizontal grain boundaries LB. The vertical grain boundaries VB may include boundaries extending diagonally, through which charges may be transferred from the upper surface S1 of the lower electrode 210 to the lower surface S2 of the variable resistance layer 230 or from the lower surface S2 of the variable resistance layer 230 to the upper surface S1 of the lower electrode 210, and in a third direction D3 substantially perpendicular to the upper surface S1 of the lower electrode 210. The horizontal grain boundaries LB may include boundaries extending in a direction substantially parallel to the surface of the lower electrode 210.

[0064] In an embodiment, the vertical grain boundaries VB of the charge bypass layer 220 may include a plurality of vertical grain boundaries VB1, VB2, VB3, and VB4. A plurality of horizontal grain boundaries LB1, LB2, and LB3 may be inserted into the space between vertically adjacent vertical grain boundaries (e.g., VB1, VB2, VB3, and VB4).

[0065] For example, Figure 4 the reference numeral SC in the figure may represent the shortest diffusion path of charges through the charge bypass layer 220. The shortest diffusion path SC may be longer than the sum of the lengths of the discontinuous vertical grain boundaries VB1, VB2, VB3, and VB4. That is, the shortest diffusion path SC may be the sum of the sum of the lengths of the discontinuous vertical grain boundaries VB1, VB2, VB3, and VB4 and the sum of the lengths of the discontinuous horizontal grain boundaries LB1, LB2, and LB3.

[0066] Alternatively, the length da of at least one of the horizontal grain boundaries LB1, LB2, and LB3 disposed between the discontinuous vertical grain boundaries VB1, VB2, VB3, and VB4 may be substantially equal to or greater than the length db of each of the discontinuous vertical grain boundaries VB1, VB2, VB3, and VB4. This results in the diffusion path of charges being longer than the vertical thickness of the charge bypass layer 220 and generally becoming even longer.

[0067] In addition, the lengths of the horizontal grain boundaries LB between adjacent vertical grain boundaries may be different from each other. The diffusion of charges may be delayed more or less proportionally to the lengths of the horizontal grain boundaries LB between adjacent vertical grain boundaries VB.

[0068] That is, although charges may enter the charge bypass layer 220, the charges may be restricted by the vertical grain boundaries VB and the horizontal grain boundaries LB. Therefore, it may not be easy for charges to be transferred between the variable resistance layer 230 and the lower electrode 210.

[0069] InFigure 4 In [description], the crystal grain G may have a quadrilateral shape, but the embodiments are not limited thereto. Alternatively, the crystal grain G may have various shapes, sizes, and characteristics according to the manufacturing process used to form the charge bypass layer 220.

[0070] Figures 5A to 5C is a cross-sectional view showing a charge bypass layer according to an embodiment of the present disclosure.

[0071] Referring to Figure 5A , the charge bypass layer 220a may include at least one first 2D material layer 222 and at least one second 2D material layer 224. The 2D material layer may have a lattice on a 2D plane. In addition, a set of lattices grown from one crystal nucleus may be referred to as a crystal grain.

[0072] For example, the first 2D material layer 222 may be formed on the lower electrode 210. The first 2D material layer 222 may have semiconductor characteristics. The semiconductor characteristics may allow the characteristics of the first 2D material layer 222 to vary between an insulator and a conductor according to the applied voltage.

[0073] In an embodiment, the first 2D material layer 222 may include a transition metal dichalcogenide (TMD). The transition metal in the TMD may include Mo, W, Pd, Pt, Ti, Zr, Hf, V, Nb, Ta, W, Tc, Re, Co, Rh, Ir, Ni, Zn, Sn, etc. The chalcogenide in the TMD may include S, Se, Te, etc. For example, the chalcogenide may include at least one of MoS2, MoSe2, WS2, WSe2, WTe2, MoTe2, ZrS2, ZrSe2, GaSe, GaTe2, HfS2, HfSe2, SnSe, PtSe2, PdSe2, PdTe2, ReSe2, VS2, VSe2, NbSe2, FeSe2, and FeTe2. The first 2D material layer 222 may have a bandgap of about 0.3 eV to about 2.0 eV, regardless of the above materials.

[0074] The second 2D material layer 224 having conductivity may include a MXene material. The structural formula of the MXene material may be MaXb (where a and b are natural numbers). M in the MXene may represent at least one transition metal. X in the MXene may include C or N.

[0075] For example, M may include at least one of Sc, Y, Lu, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, and W. In some embodiments, the MXene may include at least one of Ti2CdC, Sc2InC, Ti2AlC, Ti2GaC, Ti2InC, Ti2TIC, V2AlC, V2GaC, Cr2GaC, Ti2AlN, Ti2GaN, Ti2InN, V2GaN, Cr2GaN, Ti2GeC, Ti2SnC, Ti2PbC, V2GeC, Cr2AlC, Cr2GeC, V2PC, V2AsC, Ti2SC, Zr2InC, Zr2TlC, NLBAlC, NLBGaC, NLBInC, Mo2GaC, Zr2InN, Zr2TlN, Zr2SnC, Zr2PbC, NLBSnC, NLBPC, NLBAsC, Zr2SC, NLBSC, Hf2InC, Hf2TlC, Ta2AlC, Ta2GaC, Hf2SnC, Hf2PbC, Hf2SnN, Hf2SC; Ti3AlC2, V3AlC2, Ti3SiC2, Ti3GeC2, Ti3SnC2, Ta3AlC2; Ti4AlN3, V4AlC3, Ti4GaC3, Ti4SiC3, Ti4GeC3, Nb4AlC3, and Ta4AlC3.

[0076] The second 2D material layer 224 may include an MXene material having a single-type 2D lamination or a stacked-type 2D lamination.

[0077] Since the first 2D material layer 222 and the second 2D material layer 224 may have different properties, such as Figure 5A shown, the size of the crystal grains G1 in the first 2D material layer 222 may be different from the size of the crystal grains G2 in the second 2D material layer 224.

[0078] For example, the vertical grain boundary VB10 of the first 2D material layer 222 and the vertical grain boundary VB20 of the second 2D material layer may be discontinuous. The horizontal grain boundary LB may be connected between the vertical grain boundaries VB10 and VB20 to extend the charge transfer path.

[0079] In Figure 5A the first 2D material layer 222 may be formed above the lower electrode 210. The second 2D material layer 224 may be formed below the variable resistance layer 230. Alternatively, the second 2D material layer 224 may be formed above the lower electrode 210, while the first 2D material layer 222 may be formed below the variable resistance layer 230.

[0080] Reference Figure 5B, the charge bypass layer 220b of some embodiments may include a first 2D material layer 222 and a second 2D material layer 224 stacked alternately at least twice.

[0081] Reference Figure 5C , the charge bypass layer 220c of some embodiments may include a first 2D lower layer 222a, a second 2D material layer 224, and a first 2D upper layer 222b stacked in sequence.

[0082] The variable resistance layer 230 may be formed between the lower electrode 210 and the upper electrode 250. Specifically, the variable resistance layer 230 may be located between the charge bypass layer 220 and the oxygen vacancy storage layer 240. The variable resistance layer 230 may include a transition metal oxide. For example, the transition metal in the transition metal oxide may include at least one of Ta, Sc, Y, Ti, Zr, V, Cr, Nb, Os, Mn, Fe, Ni, Cu, Ag, Zn, Hf, and W. Alternatively, the transition metal in the variable resistance layer 230 may include a material substantially the same as the material of the lower electrode 210, but the embodiments are not limited thereto. For example, the variable resistance layer 230 may include a perovskite oxide, and the switching characteristic of the resistance value may be represented by an electric pulse. Alternatively, the variable resistance layer 230 may include either a unipolar material that exhibits a switching characteristic independent of the polarity of the applied voltage or a bipolar material that exhibits opposite switching characteristics under different polarities, but the embodiments are not limited thereto.

[0083] The variable resistance layer 230 may have a stoichiometric composition or an oxygen vacancy composition. The variable resistance layer 230 may include a metal oxide having an oxidation potential higher than that of the oxygen vacancy storage layer 240. For example, when the oxygen vacancy storage layer 240 includes Ta, the variable resistance layer 230 may include hafnium oxide having an oxidation potential higher than that of tantalum oxide.

[0084] The oxygen vacancy storage layer 240 may be located between the variable resistance layer 230 and the upper electrode 250. The oxygen vacancy storage layer 240 may include a conductive material. For example, the oxygen vacancy storage layer 240 may have an optimal oxidation potential such that a metal or a metal oxide can be easily reversed in oxidation / reduction according to the direction of the electric field. The oxygen vacancy storage layer 240 may include at least one of Ta, Ti, Zr, V, W, and Ru. In addition, oxygen may be dissolved in the oxygen vacancy storage layer 240.

[0085] The resistive memory cell 200 may perform a memory operation through the exchange of oxygen ions and oxygen vacancies between the oxygen vacancy storage layer 240 and the variable resistance layer 230.

[0086] The upper electrode 250 may face the lower electrode 210. The upper electrode 250 may be electrically connected to the oxygen vacancy storage layer 240. The upper electrode 250 may include at least one of the following: W, Au, Pt, Pd, Rh, Ir, Ru, Ti, Ta, Mo, Cr, and V; nitrides including the above metals; silicon compounds including the above metals; oxides including the above metals, etc.

[0087] The upper electrode 250 may include a conductive material that is more reactive with respect to oxygen ions than the lower electrode 210. Therefore, when a set / reset voltage may be applied to the upper electrode 250, ionization in the upper electrode 250 may be generated faster than ionization in the lower electrode 210.

[0088] Figure 6 is a cross-sectional view of a resistive memory cell for explaining a set programming operation according to an embodiment of the present disclosure, Figure 7 is a cross-sectional view of a resistive memory cell for explaining a reset programming operation according to an embodiment of the present disclosure, and Figure 8 is a cross-sectional view of a resistive memory cell for explaining a read operation according to an embodiment of the present disclosure. Figure 6 and Figure 7 The resistive memory cell 200 in

[0089] Reference Figure 6 , a positive programming voltage +Vpgm such as a set voltage Vset may be applied to the upper electrode 250. A ground voltage may be applied to the lower electrode 210. Therefore, the upper electrode 250 may be a programming electrode. The lower electrode 210 may be a ground electrode. When the voltage difference between the set voltage Vset and the ground voltage is not less than the threshold voltage, an electrochemical reaction may be induced in the oxygen vacancy storage layer 240 to generate oxygen vacancies Vo.

[0090] Oxygen ions O in the variable resistance layer 230 2- and the oxygen vacancies Vo in the oxygen vacancy storage layer 240 may be exchanged with each other under the electric field between the upper electrode 250 and the lower electrode 210. Therefore, a conductive filament CF containing oxygen vacancies Vo may be generated in the variable resistance layer 230, and the conductive filament CF may be formed to pass through the variable resistance layer 230 such that the conductive filament CF may serve as a current path. Accordingly, the resistance of the variable resistance layer 230 may be reduced, so that the resistive memory cell 200 may be switched to a low resistance state, i.e., a set state.

[0091] See Figure 7, a negative programming voltage -Vpgm such as, for example, a reset voltage Vreset can be applied to the upper electrode 250. A ground voltage can be applied to the lower electrode 210. When the voltage difference between the reset voltage Vreset and the ground voltage is not less than the threshold voltage, oxygen vacancies Vo in the variable resistance layer 230 can be transferred to the oxygen vacancy storage layer 240 presenting a relatively negative potential, and the conductive filament CF can be disconnected. Therefore, the conductive filament CF serving as a current path can be cut off to increase the resistance of the variable resistance layer 230. As a result, the resistive memory cell 200 can be switched to a high-resistance state, i.e., a reset state.

[0092] However, since the upper electrode 250 can receive a voltage with a negative potential level when resetting the resistive memory cell 200, the lower electrode 210 can present a relatively high potential level. Therefore, oxygen ions O 2- (including oxygen ions O in the metal oxide and the insulating intermediate layer 2- ) can be transferred to the surface of the lower electrode 210. Similarly, since the lower electrode 210 can include a metal, an electro-ion reaction can be generated for bonding oxygen ions O 2- to generate the required oxygen vacancies.

[0093] When the lower electrode 210 can directly contact the variable resistance layer 230 without the charge bypass layer 220, oxygen vacancies Vo and oxygen ions O 2- can be exchanged between the lower electrode 210 and the variable resistance layer 230. The undesired exchange of oxygen vacancies Vo and oxygen ions O 2- may cause the re-establishment of the broken conductive filament. Therefore, although the variable resistance layer 230 can present a high-resistance state through the reset voltage Vreset, in this case, a negative set for maintaining the low-resistance state may be generated through an abnormal conductive filament.

[0094] On the contrary, when the charge bypass layer 220 is interposed between the lower electrode 210 and the variable resistance layer 230, the diffusion of the remaining oxygen ions O 2- in the variable resistance layer 230 to the lower electrode 210 can be blocked. In addition, the diffusion of oxygen vacancies Vo in the lower electrode 210 to the variable resistance layer 230 can also be blocked. That is, although oxygen vacancies Vo and oxygen ions O 2- may diffuse into the charge bypass layer 220, oxygen vacancies Vo and oxygen ions O 2- may be restricted by the vertical and horizontal grain boundaries in the charge bypass layer 220 to prevent the diffusion of oxygen vacancies Vo and oxygen ions O 2- to the variable resistance layer 230 and the lower electrode 210.

[0095] In addition, since the reactivity of the lower electrode 210 may be lower than that of the upper electrode 250, the timing of oxygen vacancy generation can be delayed. That is, the diffusion of oxygen vacancies Vo and oxygen ions O 2- can be blocked, and at the same time, the timing of oxygen vacancy generation can be delayed, so that abnormal filaments will not be generated in the variable resistance layer 230.

[0096] In addition, since the charge bypass layer 220 can have conductivity, there will be no loss of set voltage and reset voltage caused by the charge bypass layer 220.

[0097] After the set programming operation and / or the reset programming operation, as Figure 8 shown, a read voltage Vread can be applied to the upper electrode 250. A ground voltage can be applied to the lower electrode 210. The read voltage Vread can function to induce current flow between the upper electrode 250 and the lower electrode 210 while the resistance of the variable resistance layer 230 remains unchanged. The current flowing from the lower electrode 210 to the upper electrode 250 measured by a sensor electrically connected to the upper electrode 250 can be used to read the resistance state of the resistive memory cell 200.

[0098] Figure 9 is a flowchart showing a method of manufacturing a resistive memory cell of a resistive memory device according to an embodiment of the present disclosure, Figure 10 is a flowchart showing Figure 9 the steps for forming the charge bypass layer, and Figures 11 to 14 is a cross-sectional view showing a method of manufacturing a resistive memory cell according to an embodiment of the present disclosure.

[0099] Referring to Figure 9 and Figure 11 , in Figure 9 step S10, the lower electrode 210 can be formed. The lower electrode 210 can include: W, Au, Pt, Pd, Rh, Ir, Ru, Ti, Ta, Mo, Cr, V; nitrides of the above metals; silicides of the above metals; oxides of the above metals; combinations thereof, etc. The lower electrode 210 can be formed by a chemical vapor deposition (CVD) process, a metalorganic CVD (MOCVD) process, an atomic layer deposition (ALD) process, etc. The lower electrode 210 can include a junction region having conductive impurities.

[0100] Referring to Figure 9 , Figure 10 , Figure 12 and Figure 13 , in Figure 9 step S20, the charge bypass layer 220 can be formed on the lower electrode 210. Specifically, in Figure 10In step S21, a seed layer 215 can be formed on the lower electrode 210. For example, the seed layer 215 can include a graphene layer. The graphene layer can be a nanocrystalline 2D material layer with a uniform hexagonal honeycomb lattice. The graphene layer can be formed by a CVD process, an MOCVD process, an ALD process, etc.

[0101] In Figure 10 step S22, the graphene layer can be used as the seed layer 215 to form the first 2D material layer 222. The first 2D material layer 222 can have semiconductor characteristics. For example, the first 2D material layer 222 can include a transition metal chalcogenide. Since the first 2D material layer 222 can be formed using the graphene layer with a uniform nanolattice as the seed layer 215, the first 2D material layer 222 can have uniform grain boundaries.

[0102] In Figure 10 step S23, a second 2D material layer 224 can be formed on the first 2D material layer 222. The second 2D material layer 224 can be formed by a CVD process, an MOCVD process, an ALD process, etc. Since the properties of the second 2D material layer 224 can be different from those of the first 2D material layer 222, the second 2D material layer 224 can have a different grain arrangement and grain boundary arrangement from the first 2D material layer 222. However, since the second 2D material layer 224 can be formed based on the first 2D material layer 222 with uniform grains, the second 2D material layer 224 can also have a uniform grain arrangement.

[0103] Referring to Figure 9 and Figure 14 In Figure 9 step S30, a variable resistance layer 230 can be formed on the second 2D material layer 224. As described above, the variable resistance layer 230 can include a transition metal oxide. For example, the variable resistance layer 230 can be formed by a CVD process, an MOCVD process, an ALD process, etc.

[0104] In Figure 9 step S40, an oxygen vacancy storage layer 240 can be formed on the variable resistance layer 230. As described above, the oxygen vacancy storage layer 240 can include a metal or a metal compound with an oxidation potential lower than that of the variable resistance layer 230. Therefore, since the oxygen vacancy storage layer 240 can have a relatively low oxidation potential, an electrochemical reaction can be generated quickly by applying a voltage or a current. For example, the oxygen vacancy storage layer 240 can be formed by a CVD process, an MOCVD process, an ALD process, etc.

[0105] In Figure 9In step S50, the upper electrode 250 may be formed on the oxygen vacancy storage layer 240. The upper electrode 250 may include a metal-containing material having a reactivity higher than that of the lower electrode 210.

[0106] According to an exemplary embodiment, in order to prevent reset errors of memory cells in a resistive memory device, a charge bypass layer may be interposed between an electrode having a relatively high voltage (e.g., the lower electrode) and the variable resistance layer, and the charge bypass layer may include at least one conductive 2D material layer. Unwanted charges in the variable resistance layer and the lower electrode that are adjacent to each other in the vertical direction may be bypassed by the charge bypass layer in the horizontal direction. Accordingly, charge exchange between the variable resistance layer and the lower electrode may be blocked so that unwanted abnormal filaments are not generated. Thus, in the reset operation, the variable resistance layer may be maintained in a high-resistance state.

[0107] In an exemplary embodiment, the resistive memory array may be applied to an analog memory such as a neural network system, but is not limited thereto. For example, the resistive memory array of the exemplary embodiment may be applied to a memory device of various semiconductor systems.

[0108] In addition, the charge bypass layer may be interposed between the lower electrode and the variable resistance layer, but is not limited thereto. For example, the lower electrode in contact with the charge bypass layer may be an electrode having a relatively high potential.

[0109] The above embodiments of the present invention are intended to illustrate rather than limit the present invention. Various alternatives and equivalents are possible. The present invention is not limited to the embodiments described herein. The present invention is also not limited to any specific type of semiconductor device. Other additions, subtractions, or modifications will be apparent in view of the present disclosure and are intended to fall within the scope of the appended claims.

Claims

1. A resistive memory cell, comprising: A lower electrode; An upper electrode, which is arranged to be substantially perpendicular to the lower electrode; A variable resistance layer, which is interposed between the lower electrode and the upper electrode, and the variable resistance layer has a resistance that is changed by conductive filaments based on an electric field between the lower electrode and the upper electrode, and the conductive filaments include reversibly generated oxygen vacancies; And A charge bypass layer, which is interposed between the lower electrode and the variable resistance layer, Wherein, the charge bypass layer includes: A plurality of discontinuous vertical grain boundaries; and At least one horizontal grain boundary, which is connected between adjacent discontinuous vertical grain boundaries.

2. The resistive memory cell according to claim 1, wherein, The charge bypass layer bypasses charges in the horizontal direction to prevent charge exchange between the lower electrode and the variable resistance layer, where the charges are generated in the lower electrode and the variable resistance layer by applying a voltage higher than the programming voltage to the lower electrode.

3. The resistive memory cell according to claim 2, wherein, The length of the horizontal grain boundary is greater than the length of each vertical grain boundary.

4. The resistive memory cell according to claim 1, wherein, The charge bypass layer includes at least one conductive 2D layer, where 2D refers to two-dimensional.

5. The resistive memory cell according to claim 4, wherein, The charge bypass layer includes a plurality of stacked 2D material layers, and each of the plurality of stacked 2D material layers includes different grains.

6. The resistive memory cell according to claim 4, wherein, The charge bypass layer includes: At least one 2D semiconductor layer; and At least one conductive 2D material layer.

7. The resistive memory cell according to claim 6, wherein, The at least one conductive 2D material layer comprises at least one of the following: Ti2CdC, Sc2InC, Ti2AlC, Ti2GaC, Ti2InC, Ti2TIC, V2AlC, V2GaC, Cr2GaC, Ti2AlN, Ti2GaN, Ti2InN, V2GaN, Cr2GaN, Ti2GeC, Ti2SnC, Ti2PbC, V2GeC, Cr2AlC, Cr2GeC, V 2P C, V2AsC, Ti2SC, Zr2InC, Zr2TlC, NLBAlC, NLBGaC, NLBInC, Mo2GaC, Zr2InN, Zr2TlN, Zr2SnC, Zr2PbC, NLBSnC, NLBPC, NLBAsC, Zr2SC, NLBSC, Hf2InC, Hf2TlC, Ta2AlC, Ta2GaC, Hf2SnC, Hf2PbC, Hf2SnN, Hf2SC; Ti3AlC2, V3AlC2, Ti3SiC2, Ti3GeC2, Ti3SnC2, Ta3AlC2; Ti4AlN3, V4AlC3, Ti4GaC3, Ti4SiC3, Ti4GeC3, Nb4AlC3 and Ta4AlC3.

8. The resistive memory cell according to claim 6, wherein, The at least one 2D semiconductor layer includes a transition metal chalcogenide, and the transition metal chalcogenide includes at least one of MoS2, MoSe2, WS2, WSe2, WTe2, MoTe2, ZrS2, ZrSe2, GaSe, GaTe2, HfS2, HfSe2, SnSe, PtSe2, PdSe2, PdTe2, ReSe2, VS2, VSe2, NbSe2, FeSe2, and FeTe2.

9. The resistive memory cell according to claim 1, further comprising an oxygen vacancy storage layer interposed between the variable resistance layer and the upper electrode to selectively generate oxygen vacancies based on the programming voltage.

10. The resistive memory cell according to claim 1, wherein, At least one of the lower electrode and the upper electrode includes at least one of the following: a metal, a nitride including the metal, a silicon compound including the metal, and an oxide including the metal, and the metal includes at least one of W, Au, Pt, Pd, Rh, Ir, Ru, Ti, Ta, Mo, Cr, and V.

11. The resistive memory cell according to claim 10, wherein, The upper electrode includes a material that is more reactive to oxygen ions than the lower electrode.

12. A resistive memory array, comprising: A plurality of bit lines; A plurality of word lines, which cross the bit lines; And A plurality of resistive memory cells, located between the bit lines and the word lines, Wherein, each of the resistive memory cells includes: A programming electrode, which is electrically connected to the bit line to receive a programming voltage; A ground electrode, which is electrically connected to the word line to generate a vertical electric field together with the programming electrode; A variable resistance layer, which is interposed between the programming electrode and the ground electrode, and the variable resistance layer has a resistance that is changed by conductive filaments based on the vertical electric field, and the conductive filaments include reversibly generated oxygen vacancies; and A charge bypass layer, which is interposed between the ground electrode and the variable resistance layer, bypasses oxygen vacancies generated from the ground electrode when the programming voltage is lower than the voltage of the programming electrode to horizontal grain boundaries substantially perpendicular to the vertical electric field, so as to inhibit the oxygen vacancies in the horizontal grain boundaries of the charge bypass layer.

13. The resistive memory array according to claim 12, wherein, The charge bypass layer includes a plurality of stacked 2D material layers, and at least one of the plurality of stacked 2D material layers includes conductive MXene, where 2D refers to two-dimensional.

14. The resistive memory array according to claim 13, wherein, The charge bypass layer includes: A first 2D material layer formed on the ground electrode; and A second 2D material layer formed on the first 2D material layer, where the second 2D material layer includes crystal grains different from those of the first 2D material layer.

15. The resistive memory array according to claim 12, further comprising an oxygen vacancy storage layer interposed between the variable resistance layer and the programming electrode to selectively generate the oxygen vacancies based on the programming voltage.

16. A method of manufacturing a resistive memory cell, the method comprising: Forming a lower electrode; Forming a seed layer on the lower electrode; Using the seed layer to form a charge bypass layer, the charge bypass layer including a conductive 2D material layer, where 2D refers to two-dimensional; Forming a variable resistance layer on the charge bypass layer; Forming an oxygen vacancy storage layer on the variable resistance layer; And Forming an upper electrode on the oxygen vacancy storage layer.

17. The method according to claim 16, wherein, The seed layer includes a graphene layer.

18. The method according to claim 17, wherein Forming the charge bypass layer includes: Forming a first 2D material layer based on the seed layer; and Forming a second 2D material layer based on the first 2D material layer, where the second 2D material layer includes a material different from that of the first 2D material layer.

19. The method according to claim 18, wherein Either the first 2D material layer or the second 2D material layer has conductivity, while the remaining one of the first 2D material layer and the second 2D material layer has semiconductor characteristics.

20. The method according to claim 16, wherein At least one of the lower electrode, the seed layer, the charge bypass layer, the variable resistance layer, the oxygen vacancy storage layer, and the upper electrode is formed by a chemical vapor deposition (CVD) process, a metal-organic chemical vapor deposition (MOCVD) process, or an atomic layer deposition (ALD) process.

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