Electronic device

Abstract

The embodiment of the invention relates to electronic equipment. The memory circuit includes a semiconductor substrate having selection transistors arranged therein, the semiconductor substrate including a first region and a second region, the first region forming a first row extending in a first direction, and the second region forming a second row extending in the first direction. In one embodiment, a memory circuit includes an interconnect stack including a continuous level including a first insulating layer and a second insulating layer, an interconnect element defined in the interconnect stack. The memory circuitry includes a plurality of memory cells arranged over levels of the stack, each memory cell coupled to the first region by at least one interconnect element, the second regions of the same second row being coupled together by interconnect elements located in at least one level of the stack.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of priority of French Patent Application No. 2400013, entitled "Dispositif électronique", filed on January 2, 2024, which is incorporated herein by reference in its entirety to the extent permitted by law. Technical Field

[0003] The present disclosure generally relates to electronic devices, and more particularly to electronic devices including memory circuits, particularly phase change memory circuits. Background Art

[0004] A phase change material is a material capable of changing its crystalline state under the action of heat and more particularly of switching between a crystalline state and an amorphous state, the amorphous state having a higher resistance than the crystalline state. This phenomenon is used to define two memory states distinguished by the resistance measured by means of the phase change material, for example 0 and 1.

[0005] There is a need to improve electronic chips including memory circuits having memory cells and their manufacturing methods based on phase change materials. Summary of the Invention

[0006] Embodiments provide an electronic device including a memory circuit, the memory circuit including:

[0007] A semiconductor substrate having a selection transistor disposed therein, the semiconductor substrate including a first doped region of a first conductivity type and a second doped region of a second conductivity type opposite to the first conductivity type, the first region forming a first row extending in a first direction and the second region forming a second row extending in the first direction;

[0008] An interconnect stack disposed on the semiconductor substrate, the interconnect stack including successive levels, each level including a first insulating layer and a second insulating layer having interconnect elements defined therein; and

[0009] A plurality of memory cells disposed above at least one level of the interconnect stack, each memory cell being coupled to the first region by at least one interconnect element, and the second regions of the same second row being coupled together by interconnect elements located in the at least one level of the interconnect stack.

[0010] According to one embodiment, the semiconductor substrate includes, starting from its upper surface:

[0011] A third layer of a first conductivity type;

[0012] A fourth layer of a second conductivity type, the fourth layer being located on top of and in contact with the third layer; and

[0013] A fifth layer, the fifth layer including a first region and a second region, the fifth layer being located on top of and in contact with the fourth layer.

[0014] According to one embodiment, the fourth layer, the third layer, and the first and second regions of the fifth layer form a select transistor.

[0015] According to one embodiment, the device includes a first trench extending in a first direction and a second trench extending in a second direction orthogonal to the first direction, the first trench and the second trench partitioning the substrate into components, each component including a first region and a second region.

[0016] According to one embodiment, the first and second regions of the component are separated by a third trench having a height lower than the heights of the first trench and the second trench.

[0017] According to one embodiment, the second trench has a height lower than the height of the first trench, and the first and second regions of the component are separated by a third semiconductor region.

[0018] According to one embodiment, each memory cell is electrically coupled to the first region via a first conductive via extending through the entire thickness of at least one level of the interconnect stack.

[0019] According to one embodiment, the first conductive via is made of a metal material.

[0020] According to one embodiment, the first conductive via is made of tungsten, cobalt, or copper.

[0021] According to one embodiment, the interconnect element includes a second conductive via and a conductive track that extends laterally over a surface area greater than the surface area of the second conductive via.

[0022] According to one embodiment, the device includes an alternation of a first row and a second row.

[0023] According to one embodiment, the two rows closest to each first row or each second row are the first row and the second row.

[0024] According to one embodiment, each memory cell includes a sixth layer of phase change material, a resistive element in contact with the lower surface of the sixth layer, and a seventh conductive layer in contact with the upper surface of the sixth layer.

[0025] According to one embodiment, a method includes forming a plurality of select transistors. Forming the plurality of select transistors includes forming a plurality of first doped regions of a first conductivity type and a plurality of second doped regions of a second conductivity type, the second conductivity type being opposite to the first conductivity type. The first regions form a first row extending in a first direction. The second regions form a second row extending in the first direction. The method includes forming an interconnect stack disposed on a semiconductor substrate, the interconnect stack including successive tiers. Each tier includes a first insulating layer and a second insulating layer having interconnect elements therein. The method includes forming a plurality of memory cells disposed above at least one tier of the interconnect stack. Each memory cell is coupled to a first region by at least one interconnect element. The second regions of the same second line are connected together by interconnect elements located in at least one tier of the interconnect stack.

[0026] According to one embodiment, a device includes a semiconductor substrate including a first layer of semiconductor material and a second layer of semiconductor material, the second layer of semiconductor material being on the first layer of semiconductor material. The semiconductor substrate includes a plurality of first doped regions of a first conductivity type and a plurality of second doped regions of a second conductivity type, the plurality of first doped regions of the first conductivity type being disposed in a first row in the second layer, and the plurality of second doped regions of the second conductivity type being disposed in a second row in the second layer. The device includes a plurality of first isolation trenches extending from the top of the semiconductor substrate through the second layer and partially into the second layer, and each first isolation trench contacts at least one first doped region and at least one second doped region. The device includes a plurality of second isolation trenches extending from the top of the semiconductor substrate through the entire first layer, and each second isolation trench contacts at least one first doped region and at least one second doped region. The device includes a plurality of pairs of insulating layers stacked on one another, a plurality of memory cells above the pairs of insulating layers, and a plurality of conductive interconnect elements in the pairs of insulating layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above features and advantages and other features and advantages will be described in detail in the remainder of the disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0028] Figure 1A 、 Figure 1B and Figure 1C illustrate embodiments of an electronic device;

[0029] Figure 2 illustrate another embodiment of an electronic device;

[0030] Figure 3A andFigure 3B shows another embodiment of the electronic device; and

[0031] Figure 4 shows a variation of the above embodiment. Detailed Description

[0032] In the respective figures, the same features have been designated by the same reference numerals. Specifically, the structural and / or functional features common between the respective embodiments may have the same reference numerals, and the same structures, dimensions, and material properties may be provided.

[0033] For clarity, only those steps and elements that contribute to an understanding of the described embodiments have been shown and described in detail.

[0034] Unless otherwise stated, when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor, and when referring to two elements coupled together, this means that the two elements may be connected, or they may be coupled via one or more other elements.

[0035] In the following description, in cases where absolute position determiners such as "front", "rear", "top", "bottom", "left", "right", etc., or relative position determiners such as "top", "bottom", "upper", "lower", etc., or orientation determiners such as "horizontal", "vertical", etc. are referred to, unless otherwise specified, the orientation of the drawing is referred to.

[0036] Unless otherwise stated, the expressions "about", "approximate", "substantially", and "approximately" mean plus or minus 10%, preferably plus or minus 5%.

[0037] Figure 1A , Figure 1B and Figure 1C shows an example of the electronic device 11 (as an example, the electronic chip 11). More specifically, Figure 1A is a partial and simplified cross-sectional view along the plane A-A of Figure 1B and Figure 1C . Figure 1B is a partial and simplified cross-sectional view along the plane B-B of Figure 1A and Figure 1C . Figure 1C is a partial and simplified cross-sectional view along the plane C-C of Figure 1A and Figure 1B .

[0038] More specifically, Figures 1A to 1CIllustrated is a part of the memory circuit of chip 11. As an example, chip 11 includes, in a part not shown, a logic circuit adjacent to the memory circuit. The logic circuit and the memory circuit are, for example, simultaneously fabricated inside and on top of the same semiconductor substrate.

[0039] The electronic chip includes a semiconductor substrate 13. As an example, substrate 13 is made of silicon.

[0040] Substrate 13 includes, for example, a doped semiconductor layer 15 of a first conductivity type (as an example, N-type) doped with arsenic or phosphorus atoms. Layer 15 is, for example, located on another semiconductor layer 17 of substrate 13 and, for example, in contact with another semiconductor layer 17 of substrate 13, the other semiconductor layer 17 being doped with a second conductivity type (e.g., doped with boron atoms), the second conductivity type being opposite to the first conductivity type and, for example, being P-type.

[0041] Substrate 13 includes, for example, a semiconductor layer 25. Layer 25 is, for example, located on layer 15. Thus, layer 25 is separated from layer 17 by layer 15. Layer 25 is flush with the upper surface of substrate 13.

[0042] Substrate 13 is divided into a plurality of components 12. Components 12 are preferably arranged in an array. The substrate thus includes rows and columns of components 12. Each component 12 is associated with a memory cell M and is preferably at least partially in front of said memory cell M.

[0043] Memory cells M are, for example, organized in an array of rows and columns in a top view. The rows and columns are respectively referred to as word lines and bit lines, and each memory cell M is located at the intersection of a bit line and a word line. As an example, Figure 1A the memory cells M illustrated in are memory cells M of the same word line (WL), while Figure 1B the memory cells shown in are memory cells of the same bit line (BL). In Figure 1A only 8 bit lines are shown, and in Figure 1B only 3 word lines are shown. However, in practice, the memory circuit may include different numbers of bit lines and word lines, for example, greater than 8 and 3. The array of components 12 thus substantially corresponds to the array of memory cells M.

[0044] Components 12 are separated from each other by insulating trenches 14. Insulating trenches 14 are, for example, shallow trench isolation (STI) trenches. Trenches 14 are, for example, divided into two categories: trenches 14a extending in a first direction, the first direction corresponding to, for example, the bit line direction; and trenches 14b extending in a second direction, the second direction corresponding to, for example, the word line direction. Insulating trenches 14a and 14b are, for example, orthogonal and form a grid.

[0045] The insulating trenches 14 extend, for example, from the upper surface of the substrate, preferably from the upper surface of layer 15. The trenches 14 preferably extend in layer 25, in layer 15, and in a part of layer 17. As an example, each insulating trench 14b extends longitudinally in the word line direction along the entire length of the word line. As an example, each insulating trench 14a extends longitudinally in the bit line direction along the entire length of the bit line. The insulating trenches 14 are filled with a dielectric material such as silicon oxide. The depth of the trenches 14 is, for example, in the range of 250 nm to 400 nm.

[0046] The substrate 13 further includes insulating trenches 16 or insulating trench 16. The trenches 16 are, for example, ultra-shallow trench isolation (SSTI) trenches. As an example, each trench 16 extends longitudinally in the word line direction along the entire length of the word line. As an example, the trenches 16 extend vertically through layer 25 and layer 15. More specifically, the trenches 16 extend through layer 25 and extend in a part of layer 15. The height of the trenches 16 is less than the height of layer 25 and layer 15. In other words, the trenches 16 do not extend all the way to layer 17. The trenches 16 extend, for example, from the upper surface of layer 25. The insulating trenches 16 are filled with a dielectric material, for example, silicon oxide. The depth of the trenches 16 is, for example, in the range of 20 nm to 40 nm.

[0047] Each trench 16 is located between two trenches 14b. Thus, the substrate 13 includes an alternation of trenches 14b and trenches 16 in the bit line direction. Each component 12 thus includes a part of the trench 16. The trenches 16 thus divide the part of layer 25 of each component 12 into two regions 27 and 29. Each component 12 thus includes preferably a single region 27 and preferably a single region 29. The regions 27 and 29 of the same component 12 are separated by the trench 16.

[0048] Each region 27 or 29 preferably extends along the entire height of layer 25. Each region 27 or 29 is thus flush with the upper surface of layer 25. Each region 27 or 29 contacts layer 15, for example, through the lower surface.

[0049] Preferably, the regions 27 of the components 12 in the same row or the same column are aligned. Similarly, the regions 29 of the components 12 in the same row or the same column are also aligned. In Figures 1A to 1C the embodiment, the substrate 13 includes rows of regions 27 extending in the word line direction and rows of regions 29 extending in the word line direction. In Figures 1A to 1C the example, the substrate 13 thus includes a plurality of rows, the plurality of rows including an alternation of regions 27 and regions 29 extending in the bit line direction. Thus, in the bit line direction, the substrate 13 includes an alternation of rows of regions 27 and rows of regions 29.

[0050] Region 27 is doped, for example, with a second conductivity type, for example type P. Region 27 is doped, for example, to a higher degree than layer 17. Each region 27 has, for example, a memory cell M at its top.

[0051] Region 29 is doped, for example, with a first conductivity type, for example type N. Region 29 is doped, for example, to a higher degree than layer 15. Different from region 27, there is no memory cell M at the top of region 29.

[0052] As an example, chip 11 includes a dummy gate pattern 19 disposed on the upper surface of layer 25, and the dummy gate pattern 19 extends longitudinally, for example, in the word line direction. The gate pattern 19 extends, for example, over the trench 16, for example, along the entire length of the trench. Thus, the gate pattern 19 is, for example, common to all components 12 forming the same row in the word line direction. Each gate pattern 19 is made of, for example, a semiconductor material, for example, made of silicon, for example, made of polysilicon.

[0053] Chip 11 includes an insulating layer 18 that covers the upper surface of layer 25 and the upper surface of the gate pattern 19. The insulating layer 18 is in contact with, for example, the upper surface of layer 25 and the upper surface of the gate pattern 19. The insulating layer 18 covers, for example, the entire upper surface of layer 25. The insulating layer 18 has a thickness, for example, in the range of 80 nm to 300 nm, for example, in the range of 120 nm to 200 nm.

[0054] Layer 18 includes conductive vias 20 and 22. Vias 20 and 22 are shown in dashed lines in Figure 1C Vias 20 and 22 are in contact with layer 25. More specifically, via 20 is in contact with region 29 through its lower surface, and via 22 is in contact with region 27 through its lower surface. Vias 20 and 22 extend, for example, along the entire height of layer 18. In other words, vias 20 and 22 extend from the upper surface of layer 18 to the lower surface of layer 18, that is, for example, from the upper surface of layer 18 to the upper surface of layer 25.

[0055] The top of layer 18 has an interconnect stack 35. The interconnect stack 35 is formed, for example, on the upper surface of the insulating layer 18 and covers, for example, the entire surface of the insulating layer 18. The interconnect stack 35 is formed, for example, by successive levels 36, and each level 36 includes an insulating layer 37 and an insulating layer 39. The interconnect stack 35 includes, for example, level 36a, and level 36a includes an insulating layer 39a formed on the top of the insulating layer 18 and in contact with the upper surface of the insulating layer 18. The interconnect stack 35 further includes an insulating layer 37a formed on the insulating layer 39a. For example, the insulating layer 37a is formed over the entire surface of the insulating layer 39a. As an example, the insulating layer 37a is in contact with the upper surface of the insulating layer 39a through its lower surface.

[0056] The interconnect stack 35 may further include additional tiers formed on tier 36a, i.e., additional tiers on top of and in contact with the insulating layer 37a. In Figure 1A , Figure 1B and Figure 1C , the interconnect stack 35 includes, for example, four additional tiers formed by layer 37b and layer 39b, layer 37c and layer 39c, layer 37d and layer 39d, and layer 37e and layer 39e, respectively. In practice, the number of tiers in the interconnect stack 35 may be different from 5, e.g., greater than 5.

[0057] As an example, the interconnect stack 35 has a thickness in the range from 300 nm to 800 nm, e.g., in the range from 400 nm to 700 nm, e.g., a thickness of about 500 nm.

[0058] As an example, the insulating layers 18 and 37 are made of a material having a low dielectric constant, e.g., a material having a dielectric constant less than 5 (corresponding to the dielectric coefficient of the material relative to the dielectric coefficient of vacuum), e.g., a material having a dielectric constant less than 4. The insulating layer 37 is made of, for example, silicon nitride or SiCN. As an example, the insulating layer 39 is made of an oxide having a low dielectric constant (referred to as "low-k" or "ultra-low-k").

[0059] Each tier 36 includes a via 69 and a rail 71, and the rail 71 extends, for example, in the layer 39 from the upper surface of the layer 39 and is thus flush with the upper surface of the layer 39. Preferably, the rail 71 of the tier 36 extends only in the layer 39 of the tier 36. The vias 69 of the tiers of the stack 35 extend through the layer 39 and the layer 37. More specifically, the vias 69 of the tiers of the stack 35 extend from the lower surface of the rail 71 of the same tier to the lower surface of the layer 37. Preferably, each via 69 of the tiers of the stack 35 contacts the lower surface of the rail 71 of the same tier 36 through the upper surface and contacts the upper surface of the rail 71 of the lower tier or the upper surface of the via 20 or 22 extending through the layer 18 through the lower surface.

[0060] The vias and the conductive rails 71 and 69 are made of a metal material, e.g., made of copper. As an example, the conductive rail 71 extends laterally over a surface area in the range from 20 nm × 20 nm to 60 nm × 60 nm (e.g., about 30 nm × 30 nm). As an example, the conductive rail 71 extends laterally over a surface area larger than the surface area of the via 69.

[0061] In this embodiment, the memory cells M are formed in level 36d of stack 35. Level 36d includes layer 37d and layer 39d. More generally, the memory cells are located in any level of stack 35. Preferably, all the memory cells are located in the same level. As an example, the memory cells are located in a level above the bottom level of the stack. In other words, the level of stack 35 containing the memory cells M is preferably separated from layer 18 by at least one level of stack 35.

[0062] As an example, the memory cell M is a phase change memory cell and each memory cell includes layer 47, which is made of a phase change material, such as a chalcogenide material, such as an alloy of germanium, antimony and tellurium (GeSbTe) known as GST. Layer 47 has a thickness, for example, in the range of 30 nm to 100 nm, such as a thickness of about 50 nm. Layer 47 is preferably located in layer 39d, preferably entirely within layer 39d. Memory cells M of the same bit line, for example, include a common layer 47. Thus, chip 11 includes as many layer 47s as there are bit lines. Each layer 47 thus extends in layer 39d in the bit line direction.

[0063] In each memory cell M, the phase change material is controlled, for example, by a metal resistive heating element 49 located below the phase change material. Element 49 contacts the lower surface of layer 47 through its upper level. The lower surface of each element 49 is, for example, coplanar with the lower surface of layer 37 (i.e., Figures 1A to 1C layer 37d in the example) of the level of stack 35 having the memory cell M located therein. As an example, the heating element 49 has a thickness, for example, in the range from 30 nm to 100 nm, such as a thickness of about 60 nm.

[0064] For example, layer 47 has layer 53 on its top. Layer 53 is made of a conductive material, such as a metal, for example. More specifically, the upper surface of each layer 47 is at least partially covered, for example, completely covered, by layer 53. Each layer 53 preferably extends along the entire length of layer 47 in the bit line direction. In Figures 1A to 1C the example, each layer 53 is thus common to all the memory cells of the same bit line. Layer 53 is located in layer 36d, preferably in layer 39d, for example, entirely within layer 39d. As an example, the upper surface of layer 53 is flush with the upper surface of layer 39d.

[0065] As an example, in each memory cell M, the metal element 49 and layer 53 respectively form the lower electrode and the upper electrode of the memory cell, and more specifically, the lower electrode and the upper electrode of the variable resistance element formed by the phase change material layer 47. As an example, the tops of the memory cells M of the same bit line have the same layer 53. In other words, the upper electrodes 53 of the memory cells M of the same bit line are interconnected.

[0066] Memory cells M of adjacent bit lines are insulated from each other, for example, by an insulating layer 39d and possibly a layer 37d.

[0067] In Figures 1A to 1C In the example of, for each memory cell M, a component 12 including a region 27 vertically aligned with the memory cell M, a portion of layer 15 located in the component 12, a region 29, and a portion of layer 17 located in the component 12 define a bipolar transistor, here a PNP-type bipolar transistor, and the bipolar transistor is used to select the memory cell M. Each memory cell M is associated, for example, with a bipolar transistor in the component 12 located in front of the memory cell. In this example, the region 27 forms the emitter region of the transistor, the regions 15 and 29 form the base region of the transistor, and the layer 17 forms the collector region of the transistor. As an example, the collector is common to all transistors in the array and is connected, for example, to ground.

[0068] Each memory cell M is electrically connected to a selection transistor. Each memory cell M is associated with the selection transistor via a conductive via 63 that extends through all levels of the interconnect stack 35 between the level including the memory cell and layer 18. As an example, the via 63 extends through all insulating layers 37 and 39 of the interconnect stack 35 between layer 37d and layer 18.

[0069] As an example, the via 63 associated with each memory cell M contacts the lower surface of the resistive heating element 49 of the memory cell M through its upper surface. The via 63 contacts, for example, the conductive via 22 through its lower surface, and the conductive via 22 itself contacts the upper surface of the region 27 of the component 12 associated with the memory cell M. In other words, for each memory cell M, the corresponding via 63 electrically couples the heating element 49 of the memory cell to the underlying region 27.

[0070] The conductive via 63 is made of a metal material, for example. The conductive via 63 is made of tungsten, for example. As a variant, the conductive via is made of cobalt or copper. The conductive via 63 has a width, for example, that is intercepted in the plane of Figure 1A and Figure 1B and is in the range from 20 nm to 80 nm, for example, about 40 nm.

[0071] Regions 29 of layer 25 of the same word line are coupled together, for example, by conductive vias 69 and conductive rails 71 that are located in a level of the interconnect stack 35 below the level where the memory cells are located. Thus, the conductive vias 69 and conductive rails 71 that couple regions 29 of layer 25 of the same word line are located between the level including the memory cells and layer 18. In Figures 1A to 1CIn the example, regions 29 are coupled to each other through vias 69 and rails 71, which are located in levels 36a, 36b, and 36c, that is, in the three levels closest to layer 18 of stack 35.

[0072] Thus, in the bit line direction, chip 11 and more specifically the memory circuit includes an alternation of a first line and a second line. Each first line includes region 29 and the lines of rails 71 and vias 69 that couple said region 29. Each second line includes region 27, via 63 in contact with said region 27, and the line of memory cell 27 associated with said region 27. Thus, each via 63 associated with memory cell M is separated from the vias 63 of adjacent word lines by vias 69 and rails 71 that couple the region 29 of the lines of region 29.

[0073] Figure 2 Another embodiment of electronic device 100 is shown. More specifically, Figure 2 A simplified and partial cross-sectional view of device 100 in a plane similar to the plane of Figure 1B is shown.

[0074] Device 100 includes the elements of device 11, which will not be described in detail here.

[0075] Device 100 is different from Figures 1A to 1C device 11 in that device 100 includes an alternation of components 12 in the bit line (BL) direction, with regions 27 and regions 29 being inverted from one component to the next. In other words, in the bit line direction, each region 27 or 29 is located between region 27 and region 29. Thus, each region 27 or 29 includes adjacent region 27 and adjacent region 29 in the bit line direction. Device 100 includes a first row of regions 27 and a second row of regions 29, with the first row and the second row extending in the word line direction. The first row and the second row are each located between the first row and the second row. Thus, the two rows closest to the first row or the second row are the first row and the second row. Thus, each trench 14b preferably directly separates two regions 27 or two regions 29. Each region 27 is separated from region 29 by trench 16 and from region 27 by trench 14b. Each region 29 is separated from region 29 by trench 14b and from region 27 by trench 16.

[0076] As in the previous embodiment described, the top of each region 27 has vias 22 and 63 and memory cell M. The top of each region 29 has via 20, and an alternation of vias 69 and rails 71 that couple the regions 29 of the same row of region 29 together. Thus, each via 63 is located between the alternation of vias 63 and vias 69 and rails 71.

[0077] Figure 2 The structure includes adjacent regions 27 and adjacent region 29. The adjacent regions 27 and 29 can be advantageously doped simultaneously, which enables the formation of wider mask openings. In addition, such placement allows for a reduction in the size of the memory cells. In fact, regions 27 and 29 can now have dimensions smaller than the minimum dimension of the semiconductor region manufacturing method.

[0078] Figure 3A and Figure 3B shows another embodiment of the electronic device 102. More specifically, Figure 3A shows a simplified and partial cross-sectional view of the device 102 along Figure 3B plane A-A, and Figure 3B corresponds to a simplified and partial cross-sectional view of the device 102 along Figure 3A plane B-B.

[0079] The device 102 includes the elements of the device 11, which will not be described in detail here.

[0080] The device 102 is different from Figures 1A to 1C the device 11 in that the trench 14a is replaced with an insulating trench 104. The trench 104 is, for example, an ultra-shallow trench isolation (SSTI) trench. As an example, the trench 104 extends vertically in layers 25 and 15. More specifically, the trench 104 extends through layer 25 and extends into a portion of layer 15. Preferably, the height of the trench 104 is less than the height of layers 25 and 15. In other words, the trench 104 preferably does not extend all the way to layer 17. The trench 104, for example, extends from the upper surface of layer 25. The insulating trench 104 is filled with a dielectric material, such as silicon oxide, for example. The depth of the trench 104 is, for example, in the range of 20 nm to 40 nm.

[0081] In addition, the device 102 is different from the device 11 in that the device 102 does not include the trench 16 that separates the regions 27 and 29 of the single component 12. The regions 27 and 29 of the same component 12 are thus separated by the region 106 of layer 25. Each region 106 is thus located in layer 25 at the position of the trench 16. The region 106 is preferably made of the same semiconductor material as layer 15, such as silicon. The region 106 is, for example, doped with the same conduction type as layer 15. For example, the region 106 has the same dopant concentration as layer 15. Preferably, the region 106 has a lower dopant concentration than the dopant concentration of region 29.

[0082] One advantage of the embodiment of FIG. 3 is that it avoids using two depths to implement the manufacturing method for dual shallow trench isolation, which means double etching, double filling, and double planarization steps for the trench. Such a method is time-consuming and costly.

[0083] Figure 4 shows a variant of the above embodiment. More specifically, Figure 4 shows a part of an embodiment according to the variant Figure 1B of.

[0084] In Figure 4 the variant of, the conductivity types of the layers and regions of the substrate 13 are inverted. Thus, layer 17 is N-type doped, layer 15 is P-type doped, region 27 is N-type doped, and region 29 is P-type doped to a higher degree than layer 15. Thus, the select transistor of each memory cell is an NPN bipolar transistor.

[0085] Figures 1A to 1C An advantage of the embodiment of is that the distance between the memory cells is substantially constant, which makes it possible to avoid perturbations from one cell to another.

[0086] Figure 2 An advantage of the embodiment of is that the adjacent regions 27 and the adjacent regions 29 can be doped simultaneously, which makes it possible to form a larger mask opening.

[0087] Figure 4 An advantage of the embodiment of is that NPN bipolar transistors generally have a better β factor Ic / Ib than PNP bipolar transistors. Thus, for the same emitter current, the current in the base may leak less and the current in the collector may leak more. Thus, the voltage on the word line is smaller.

[0088] An advantage of the present embodiment including the via 63 is that the lack of conductive rails in layer 37 reduces the risk of parasitic capacitance, facilitating the formation of layer 37 in materials other than those having a low dielectric constant.

[0089] One advantage of the present embodiment is that it makes it possible to eliminate the metal layer size constraints for PCM cell integration, because the surface area of the via 63 can be smaller than the surface area of the rail 71 at the surface of the interconnect stack 35. This embodiment advantageously does not include the via 69 and the rail 71.

[0090] Another advantage of the present embodiment including the via 63 is that forming the memory cell above the interconnect level 36 makes it possible to eliminate the risk of contamination of the PCM layer of the memory cell generated by the formation of the interconnect stack and the various metal layers 71 and 69.

[0091] Yet another advantage of the present embodiment is that it is compatible with known methods and logic parts, and the logic parts are not affected.

[0092] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these different embodiments and variations can be combined, and other variations will occur to those skilled in the art. Specifically, although each region 27 is coupled to a memory cell through via 22 and a single via 63, and the single via 63 extends through the levels of the stack 35 that separate the memory cell from layer 18, in all the described embodiments, via 63 can be replaced by continuous rails 71 and vias 69, which are located in the levels of the stack 35 that separate the memory cell from layer 18.

[0093] Finally, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art based on the above functional indications.

[0094] In one embodiment, an electronic device (11, 100, 102) includes a memory circuit that includes: a semiconductor substrate (13) having a selection transistor disposed therein, the semiconductor substrate (13) including a first doped region (27) of a first conductivity type (P, N) and a second doped region (29) of a second conductivity type (N, P), the second conductivity type (N, P) being opposite to the first conductivity type, the first region forming a first row extending in a first direction (WL), and the second region forming a second row extending in the first direction (WL); an interconnect stack (35) disposed on the semiconductor substrate (13), the interconnect stack (35) including successive levels, each level including a first insulating layer (37) and a second insulating layer (39), the first insulating layer (37) and the second insulating layer (39) having interconnect elements (63, 71, 69) defined therein; and a plurality of memory cells (M) disposed above at least one level of the interconnect stack (35), each memory cell being coupled to the first region (27) through at least one interconnect element (63, 69, 71), and the second regions (29) of the same second line being connected together through interconnect elements (69, 71) located in the at least one level of the interconnect stack (35).

[0095] In one embodiment, the semiconductor substrate (13) includes, starting from the upper surface: a third layer (17) of a first conductivity type; a fourth layer (15) of a second conductivity type, the fourth layer being on top of and in contact with the third layer (17); and a fifth layer (25) including the first region (27) and the second region (29), the fifth layer being on top of and in contact with the fourth layer (15).

[0096] In one embodiment, the fourth layer (15), the third layer (17), and the first and second regions (27, 29) of the fifth layer (25) may form a select transistor.

[0097] In one embodiment, the device includes first trenches (14, 14b) extending in a first direction (WL) and second trenches (14, 14a, 104) extending in a second direction (BL) orthogonal to the first direction, and the first and second trenches divide the substrate into components (12), each component (12) including a first region (27) and a second region (29).

[0098] In one embodiment, the first and second regions (27, 29) of the component (12) are separated by a third trench (16) having a height smaller than the height of the first trenches (14, 14b) and the height of the second trenches (14, 14a).

[0099] In one embodiment, the second trench (104) has a height smaller than the height of the first trenches (14, 14b), and the first and second regions (27, 29) of the component (12) are separated by a third semiconductor region (106).

[0100] In one embodiment, each memory cell (M) is electrically coupled to the first region (27) via a first conductive via (63) that extends through the entire thickness of at least one level of the interconnect stack (35).

[0101] In one embodiment, the first conductive via (63) is made of a metal material.

[0102] In one embodiment, the first conductive via (63) is made of tungsten, cobalt, or copper.

[0103] In one embodiment, the interconnect element includes a second conductive via (69) and a conductive rail (71) that extends laterally over a surface area larger than the surface area of the second conductive via (63).

[0104] In one embodiment, the device includes an alternation of a first row and a second row.

[0105] In one embodiment, the two rows closest to each first row or each second row are the first row and the second row.

[0106] In one embodiment, each memory cell (M) includes a sixth layer (47) made of a phase change material, a resistance element (49) in contact with the lower surface of the sixth layer, and a seventh conductive layer (53) in contact with the upper surface of the sixth layer.

[0107] These and other changes may be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed so as to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments and the full scope of equivalents to such claims. Accordingly, the claims are not limited by the disclosure.

Claims

1. An electronic device, the electronic device comprising a memory circuit, the memory circuit comprising: A semiconductor substrate having a selection transistor disposed therein, the semiconductor substrate including a first doped region of a first conductivity type and a second doped region of a second conductivity type, the second conductivity type being opposite to the first conductivity type, the first region forming a first row extending in a first direction, and the second region forming a second row extending in the first direction; An interconnect stack disposed on the semiconductor substrate, the interconnect stack including successive levels, each level including a first insulating layer and a second insulating layer having interconnect elements therein; And A plurality of memory cells disposed above at least one level of the interconnect stack, each memory cell being coupled to the first region by at least one interconnect element, and the second regions of the same second line being connected together by interconnect elements located in the at least one level of the interconnect stack.

2. The device according to claim 1, wherein the semiconductor substrate includes, starting from an upper surface: A third layer of the first conductivity type; A fourth layer of the second conductivity type, the fourth layer being on top of and in contact with the third layer; And A fifth layer including the first region and the second region, the fifth layer being on top of and in contact with the fourth layer.

3. The device according to claim 2, wherein the fourth layer, the third layer, and the first and second regions of the fifth layer form the selection transistor.

4. The device according to claim 1, including a first trench and a second trench, the first trench extending in the first direction and the second trench extending in a second direction orthogonal to the first direction, the first trench and the second trench dividing the substrate into components, each component including a first region and a second region.

5. The device according to claim 4, wherein the first and second regions of the component are separated by a third trench having a height smaller than the height of the first trench and the height of the second trench.

6. The device according to claim 4, wherein the second trench has a height smaller than the height of the first trench, and the first and second regions of the component are separated by a third semiconductor region.

7. The device according to claim 1, wherein each memory cell is electrically coupled to the first region via a first conductive via extending through the entire thickness of at least one level of the interconnect stack.

8. The device according to claim 7, wherein the first conductive via is made of a metal material.

9. The device according to claim 7, wherein the first conductive via is made of tungsten, cobalt, or copper.

10. The device according to claim 1, wherein the interconnect element comprises a second conductive via and a conductive rail, and the conductive rail extends laterally over a surface area that is larger than the surface area of the second conductive via.

11. The device according to claim 1, comprising an alternation of a first row and a second row.

12. The device according to claim 1, wherein the two rows closest to each first row or each second row are the first row and the second row.

13. The device according to claim 1, wherein each memory cell comprises a sixth layer of phase change material, a resistive element, and a seventh conductive layer, the resistive element being in contact with the lower surface of the sixth layer, and the seventh conductive layer being in contact with the upper surface of the sixth layer.

14. A method, comprising: forming a plurality of select transistors, wherein forming the plurality of select transistors comprises: forming a plurality of first doped regions of a first conductivity type and a plurality of second doped regions of a second conductivity type, the second conductivity type being opposite to the first conductivity type, the first regions forming a first row extending in a first direction, and the second regions forming a second row extending in the first direction; forming an interconnect stack disposed on the semiconductor substrate, the interconnect stack comprising successive levels, each level comprising a first insulating layer and a second insulating layer, and the first insulating layer and the second insulating layer having interconnect elements therein; and forming a plurality of memory cells disposed on at least one level of the interconnect stack, each memory cell being coupled to a first region by at least one interconnect element, and the second regions of the same second line being connected together by an interconnect element located in the at least one level of the interconnect stack.

15. The method according to claim 14, wherein the semiconductor substrate comprises, starting from the upper surface: a third layer of a first conductivity type; a fourth layer of a second conductivity type, the fourth layer being on top of and in contact with the third layer; and a fifth layer comprising the first regions and the second regions, the fifth layer being on top of and in contact with the fourth layer.

16. The method according to claim 15, wherein the fourth layer, the third layer, and the first regions and the second regions of the fifth layer form the select transistors.

17. The method according to claim 14, wherein each memory cell is electrically coupled to a first region via a first conductive via that extends through the entire thickness of at least one level of the interconnect stack.

18. A device, comprising: a semiconductor substrate, the semiconductor substrate comprising: a first layer of semiconductor material; a second layer of semiconductor material, the second layer being on the first layer of semiconductor material; a plurality of first doped regions of a first conductivity type, the plurality of first doped regions being arranged in a first row in the second layer; and a plurality of second doped regions of a second conductivity type, the plurality of second doped regions being arranged in a second row in the second layer; A plurality of first isolation trenches extending from a top of the semiconductor substrate through the second layer and partially into the second layer, and each first isolation trench contacting at least one first doped region and at least one second doped region; A plurality of second isolation trenches extending from the top of the semiconductor substrate through the entire first layer, and each second isolation trench contacting at least one first doped region and at least one second doped region; A plurality of pairs of insulating layers stacked on one another; A plurality of memory cells over the pairs of insulating layers; and A plurality of conductive interconnect elements in the pairs of insulating layers.

19. The apparatus of claim 18, wherein the conductive interconnect elements electrically couple each memory cell to a first region.

20. The apparatus of claim 19, wherein the conductive interconnect elements electrically couple each second doped region in the second doped regions of the same line.

Images