Self-aligned silicon germanium heterojunction bipolar transistor (HBT) structure with low base region connection resistance and manufacturing method of self-aligned silicon germanium HBT structure
By forming non-planar grooves at the base zone window and epitaxial SiGe layer, the problem of difficulty in reducing the base zone connection resistance in silicon-germanium HBT devices is solved, and the characteristic frequency and highest oscillation frequency are improved, and it is compatible with the CMOS process.
Patent Information
- Application Number
- CN202510378719.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-04
AI Technical Summary
In the prior art, when silicon germanium HBT devices optimize the characteristic frequency and the highest oscillation frequency, the base region connection resistance is difficult to effectively reduce, resulting in an increase in process complexity.
A non-selective epitaxial is used to form a non-planar groove at the base area window to form an inner base area and an outer base area, and a self-aligned silicon germanium HBT structure with low base area connection resistance is formed through self-alignment injection, including forming a SiGe layer in the middle of the non-planar groove to reduce the connection resistance of the inner base area and the outer base area.
It effectively reduces the base region connection resistance and base region-transmitting area capacitance, improves the characteristic frequency and highest oscillation frequency of SiGe HBT, and is compatible with the standard CMOS process, has fewer process steps, and has good scalability.
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Figure CN120264784A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor integrated circuits, and particularly relates to a self-aligned SiGe HBT structure with low base connection resistance and a manufacturing method thereof. Background Art
[0002] Compared with standard Si BJT and CMOS devices, modern SiGe BiCMOS technology has the advantages of significantly better radio frequency performance and low noise characteristics at the same process node, and its process performance indicators can meet the requirements of various communication markets, so it is widely used in the field of wireless communication.
[0003] SiGe HBT (i.e., SiGe HBT) devices utilize SiGe / Si energy band engineering to improve the carrier transit speed and can achieve very high characteristic frequencies. However, in most existing technologies, there is a conflict between optimizing the characteristic frequency and the maximum oscillation frequency because it is difficult to effectively reduce the base connection resistance; raising the base is one way, but this method greatly increases the process complexity. Summary of the Invention
[0004] Aiming at the deficiencies of the above-mentioned prior art, the technical problem to be solved by the present invention is: to provide a self-aligned SiGe HBT structure with low base connection resistance and a manufacturing method thereof.
[0005] To solve the above technical problem, the present invention provides the following technical solutions:
[0006] A manufacturing method of a self-aligned SiGe HBT structure with low base connection resistance includes the following steps:
[0007] S100. Complete the process steps before fabricating the base region and open the base region window;
[0008] S200. Etch a non-planar groove at the base region window;
[0009] S300. Epitaxially grow a SiGe layer in a non-selective manner. The SiGe layer forms an inner base region on the single-crystal silicon surface in the middle of the non-planar groove and forms an outer base region on the oxide surface outside the inner base region;
[0010] S400. Fabricate the emitter region;
[0011] S500. Complete the subsequent manufacturing process.
[0012] Further, in the step S300, the thickness of the non-selectively epitaxially grown SiGe layer is 400 Å - 700 Å, and the SiGe layer is a composite layer, including a Si buffer layer, a SiGe doped layer, and a Si capping layer.
[0013] Further, the step S100 includes the following sub-steps:
[0014] S110. Lithographically etch a plurality of shallow trenches on a silicon substrate, and deposit silicon oxide to fill each shallow trench with silicon oxide to form a plurality of shallow trench isolation regions. Meanwhile, form a first silicon oxide layer on the silicon substrate; the plurality of shallow trench isolation regions divide a part of the silicon substrate into a CMOS region and an HBT region, and divide the CMOS region into a CMOS active region and a substrate contact region, and divide the HBT region into a collector active region and a collector contact region;
[0015] S120. Form a polysilicon gate above the CMOS active region, form gate silicon oxide by oxidation on the surface of the polysilicon gate, and form source / drain extension regions by implantation on the CMOS active regions on both sides of the polysilicon gate;
[0016] S130. Form a selective ion implantation region by implantation in the middle of the collector active region;
[0017] S140. Deposit an oxide on the silicon substrate to form a second silicon oxide layer, and then deposit a nitride on the second silicon oxide layer to form a first silicon nitride layer;
[0018] S150. Open a base region window in the HBT region by lithographically etching the first silicon nitride layer; the width of the base region window is greater than the width of the collector active region.
[0019] Further, in the step S200, remove the second silicon oxide layer in the base region window area by wet etching to form a non-planar groove, and the etching depth is 200 Å to 1200 Å; the non-planar groove forms an annular concave area at the connection of the collector active region and the shallow trench, and a side etching structure is formed at the part of the edge of the non-planar groove below the silicon nitride.
[0020] Further, in the step S300, the SiGe layer formed on the surface of the single-crystalline silicon inside the concave area is a single-crystalline SiGe region, and the single-crystalline SiGe region forms an inner base region, and the SiGe layer formed on the surface of the oxide inside and outside the concave area is a polycrystalline SiGe region, and the polycrystalline SiGe region forms an outer base region.
[0021] Further, in the step S130, when forming the selective ion implantation region by implantation, the implantation energy is 10 keV to 100 keV, the implantation dose is 1E13 cm -3 ~2E14 cm -3 , and the implanted impurity is arsenic or antimony.
[0022] Further, the step S400 includes the following sub-steps:
[0023] S410. Deposit a third silicon oxide layer and a polysilicon sacrificial layer on the silicon substrate in sequence, and etch the polysilicon sacrificial layer to form a sacrificial emitter region above the selective ion implantation region; the width of the sacrificial emitter region is 1 / 2 to 1 / 5 of the width of the collector active region;
[0024] S420. Deposit a high-quality oxide layer on the silicon substrate, and dry-etch the high-quality oxide layer to retain the high-quality oxide layer outside the sacrificial emitter region to form a silicon oxide sidewall;
[0025] S430. Inject P-type impurities in the outer base region to reduce the resistance of the connection region between the inner base region and the outer base region, and form an inner and outer base region connection extension region around the selective ion implantation region;
[0026] S440. Etch and remove the sacrificial emitter region and the third silicon oxide layer below the sacrificial emitter region, open the emitter region window to expose the surface of the SiGe layer;
[0027] S450. Deposit or non-selectively epitaxially grow a silicon layer, and pattern-etch the silicon layer to form an emitter region.
[0028] Further, in the step S430, the implantation energy is 10 KeV to 60 KeV, the implantation dose is 5E14 cm -3 ~1E16 cm -3 , and the implanted impurity is boron or BF2+.
[0029] Further, in the step S450, the growth mode of the silicon layer is deposition or non-selective epitaxy, the in-situ impurity is arsenic or phosphorus, and the doping concentration is 5e19 cm -3 ~2e20 cm -3 .
[0030] A self-aligned SiGe HBT structure with a low base region connection resistance is made by using the manufacturing method of the self-aligned SiGe HBT structure with a low base region connection resistance as described in any one of the above.
[0031] The present invention provides a self-aligned SiGe HBT structure with a low base region connection resistance and its manufacturing method, which can be well compatible with the existing process conditions, can reduce the base region connection resistance and the base-emitter capacitance at the same time, so as to improve the characteristic frequency and the maximum oscillation frequency of the SiGe HBT. Compared with the self-aligned HBT manufacturing methods of other existing technical routes, in the present invention, the shallow trench isolation oxide layer near the base region active region is wet-etched to form a non-planar groove in the base region as the epitaxial region, and the thickness of the connection region formed after subsequent self-aligned implantation is greater than the epitaxial thickness of the base region, effectively reducing the connection resistance between the inner base region and the outer base region. This process is compatible with the standard CMOS process, has fewer process steps, and has good scalability. Description of the Drawings
[0032] The accompanying drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation of the present application. In the drawings:
[0033] Figure 1 It is a flowchart of an embodiment of the manufacturing method of the self-aligned SiGe HBT structure with a low base region connection resistance according to the present invention.
[0034] Figure 2 It is a schematic structural diagram after forming a shallow trench isolation region and a first silicon oxide layer on a silicon substrate.
[0035] Figure 3 It is a schematic structural diagram after forming a polysilicon gate, a gate oxide, and a source / drain extension region.
[0036] Figure 4 It is a schematic structural diagram after implanting to form a selective ion implantation region.
[0037] Figure 5 It is a schematic structural diagram after depositing a second silicon oxide layer and a first silicon nitride layer and opening a base region window.
[0038] Figure 6 It is a schematic structural diagram after forming a non-planar groove at the base region window.
[0039] Figure 7 It is a schematic structural diagram after epitaxially forming a SiGe layer.
[0040] Figure 8 It is a schematic structural diagram after forming a second silicon oxide layer and a polysilicon sacrificial layer.
[0041] Figure 9 It is a schematic structural diagram after forming a silicon oxide sidewall.
[0042] Figure 10 It is a schematic structural diagram after forming an inner and outer base region connection extension region.
[0043] Figure 11 It is a schematic structural diagram after forming an emitter window.
[0044] Figure 12 It is a schematic structural diagram after forming a silicon emitter.
[0045] Figure 13 It is a schematic structural diagram after forming a silicon nitride sidewall in the CMOS region.
[0046] The reference numerals in the specification are as follows:
[0047] Silicon substrate - 101; Shallow trench isolation region - 102; First silicon oxide layer - 110; Second silicon oxide layer - 120; First silicon nitride layer - 130; SiGe layer - 140; Third silicon oxide layer - 150; Polysilicon sacrificial layer - 160;
[0048] Polysilicon gate - 201; Gate silicon oxide - 202; Source / drain extension region - 203; Silicon nitride sidewall - 204; CMOS active region - 210; Substrate contact region - 220;
[0049] Selective ion implantation region - 301; Base region window - 302; Inner base region - 303; Outer base region - 304; Silicon oxide sidewall - 305; Inner / outer base region connection extension region - 306; Emitter region window - 307; Silicon emitter region - 308; Collector active region - 310; Collector contact region - 320; Non - planar groove - 330; Concave region - 331; Side - cut structure - 332. Detailed implementation manners
[0050] The following illustrates the implementation manners of the present invention through specific examples. The diagrams provided in the following examples only schematically show the basic concept of the present invention. Without conflict, the features in the following examples and the examples can be combined with each other.
[0051] Please refer to Figure 1 , Figure 1 , which is a flowchart of an embodiment of the method for fabricating a self - aligned SiGe HBT structure with low base region connection resistance according to the present invention. The method for fabricating a self - aligned SiGe HBT structure with low base region connection resistance in this embodiment includes the following steps:
[0052] S100. Complete the process steps before fabricating the base region and open the base region window 302. This step may include the following sub - steps:
[0053] S110. Please refer to Figure 2 , and through photolithography and etching, a plurality of shallow trenches are formed on the silicon substrate 101, and each shallow trench is filled with silicon oxide by deposition to form a plurality of shallow trench isolation regions 102. At the same time, a first silicon oxide layer 110 is formed on the silicon substrate 101. The plurality of shallow trench isolation regions 102 divide the upper part of the silicon substrate 101 into a CMOS region and an HBT region, and divide the CMOS region into a CMOS active region 210 and a substrate contact region 220, and divide the HBT region into a collector active region 310 and a collector contact region 320. In this embodiment, the width of the collector active region 310 is 0.2 μm - 2 μm, the width of the collector contact region 320 is 0.1 μm - 2 μm, the width of the shallow trench isolation region 102 is generally 0.2 μm - 1 μm, and the depth is generally 0.2 μm - 0.8 μm.
[0054] S120. Please refer toFigure 3 , a polysilicon gate 201 is formed above the CMOS active region 210, and gate oxide 202 is formed by oxidation on the surface of the polysilicon gate 201; lightly doped source / drain extension regions 203 are formed by implantation in the CMOS active regions 210 on both sides of the polysilicon gate 201.
[0055] S130, please refer to Figure 4 , an N+-type selective ion implantation region 301 is formed by implanting N-type impurities with medium energy and high dose in the middle of the collector active region 310. In this step, the implantation energy is generally 10 KeV to 100 KeV, and the implantation dose is generally 1E13 cm -3 ~2E14 cm -3 , and the implanted impurities can be arsenic or antimony.
[0056] S140, please refer to Figure 5 , an oxide is deposited on the silicon substrate 101 to jointly form a second oxide layer 120 with the previous first oxide layer 110, and the thickness of the second oxide layer 120 is 100 Å to 300 Å. Then, a nitride is deposited on the second oxide layer 120 to form a first silicon nitride layer 130, and the thickness of the first silicon nitride layer 130 is 100 Å to 500 Å.
[0057] S150, please continue to refer to Figure 5 , the first silicon nitride layer 130 is etched through photolithography to open a base window 302 in the HBT region, and the first silicon nitride layer 130 can be etched by dry etching. The width of the base window 302 is greater than the width of the collector active region 310, so that the base window 302 extends outward from the collector active region 310 to the shallow trench isolation regions 102 on both sides.
[0058] S200, please refer to Figure 6 , a non-planar groove 330 is etched at the base window 302. In this embodiment, the second oxide layer 120 in the region of the base window 302 is removed by wet etching to form a non-planar groove 330, and the etching depth is 200 Å to 1200 Å. The non-planar groove 330 is a groove with a non-planar bottom structure, and an annular concave region 331 is formed at the connection of the non-planar groove 330 with the collector active region 310 and the shallow trench. The cross-sectional shape of the concave region 331 is wider at the top and narrower at the bottom. For example, the cross-sectional shape of the concave region 331 can be triangular or trapezoidal. A side etching structure 332 is formed at the edge of the non-planar groove 330 below the silicon nitride.
[0059] S300, please refer to Figure 7, the SiGe layer 140 is epitaxially formed in a non-selective manner, and the in-situ doped impurity can be boron and form a trapezoidal distribution with a peak concentration of 5e19 cm -3 ~2e20 cm -3 . The SiGe layer 140 forms an inner base region 303 on the single-crystal silicon surface in the middle of the non-planar groove 330, and forms an outer base region 304 on the oxide surface outside the inner base region 303. Among them, the SiGe layer 140 formed on the single-crystal silicon surface inside the lower concave region 331 (i.e., the collector active region 310) is a single-crystal SiGe region, and the single-crystal SiGe region forms the inner base region 303. The SiGe layer 140 formed on the oxide surface of the lower concave region 331 and its outer side (i.e., the shallow trench isolation region 102) is a polycrystalline SiGe region, and the polycrystalline SiGe region forms the outer base region 304.
[0060] In this embodiment, the thickness of the non-selectively epitaxially grown SiGe layer 140 is 400 Å to 700 Å, and the SiGe layer 140 is a composite SiGe layer 140, including a Si buffer SiGe layer 140, a SiGe doped SiGe layer 140, and a Si capping SiGe layer 140. In this step, since the lower concave region 331 is formed at the edge of the collector active region 310 in the non-planar groove 330, after the SiGe layer 140 is epitaxially formed, the SiGe layer 140 in the lower concave region 331 will be thicker than other regions, so that the inner base region 303 and the outer base region 304 can be formed by only one epitaxy, and there is no need to perform secondary epitaxial thickening on the outer base region 304.
[0061] S400. Fabricate the emitter region. This step may include the following sub-steps:
[0062] S410. Please refer to Figure 8 , deposit a third silicon oxide layer 150 and a polysilicon sacrificial layer on the silicon substrate 101 in sequence, and etch the polysilicon sacrificial layer to form a sacrificial emitter region 160 above the selective ion implantation region 301. The thickness of the third silicon oxide layer 150 is generally 100 Å to 300 Å, and the thickness of the sacrificial emitter region 160 (i.e., the polysilicon sacrificial layer) is generally 1000 Å to 3000 Å; the width of the sacrificial emitter region 160 is 1 / 2 to 1 / 5 of the width of the collector active region 310.
[0063] S420. Please refer to Figure 9 , deposit a high-quality oxidized SiGe layer 140 on the silicon substrate 101, and dry-etch the high-quality oxidized SiGe layer 140 to retain the high-quality oxidized SiGe layer 140 outside the sacrificial emitter region 160 to form a silicon oxide sidewall 305. The thickness of the high-quality oxidized SiGe layer 140 is 500 Å to 3000 Å.
[0064] S430. Please refer toFigure 10 , P-type impurities are implanted into the outer base region 304 to reduce the resistance of the connection region between the inner base region 303 and the outer base region 304, and a connection extension region 306 of the inner and outer base regions is formed around the selective ion implantation region 301 by self-aligned ion implantation. In this step, the implantation energy is generally 10 KeV to 60 KeV, and the implantation dose is generally 5E14 cm -3 ~1E16 cm -3 , and the implanted impurity can be boron or BF2+.
[0065] S440. Please refer to Figure 11 , etch away the sacrificial emitter region 160 and the third silicon oxide layer 150 below the sacrificial emitter region 160 (of course, at this time, a part of the silicon oxide sidewall 305 will also be etched), open the emitter window 307, and expose the surface of the SiGe layer 140.
[0066] S450. Please refer to Figure 12 , deposit or non-selectively epitaxially grow an N+-type doped silicon layer 140, and pattern etch the silicon layer 140 to form an emitter region. In this step, the growth method of the silicon layer 140 can be deposition or non-selective epitaxy, so as to form a polysilicon or single-crystal emitter region. The in-situ impurity of the silicon layer 140 can be arsenic or phosphorus, and the doping concentration is generally 5e19 cm -3 ~2e20 cm -3 .
[0067] S500. Please refer to Figure 13 , complete the subsequent SiGe BiCMOS manufacturing process. This step includes etching the first silicon nitride layer 130, the SiGe layer 140, and the third silicon oxide layer 150 in the CMOS region to form a silicon nitride sidewall 204 outside the polysilicon gate 201; and processes such as source-drain region implantation and rapid thermal annealing, which are all conventional processes in the HBT device manufacturing process and have nothing to do with the improvement of this embodiment, so they will not be elaborated here.
[0068] In this embodiment, a wet etching method is used to form a non-planar groove in the base region. The inner base region 303 and the outer base region 304 can be formed through one-time epitaxy and self-aligned implantation, which can simultaneously reduce the base connection resistance and the base-emitter capacitance, thereby improving the characteristic frequency and the maximum oscillation frequency of the SiGe HBT. Compared with the self-aligned HBT manufacturing methods of other existing technical routes, in this embodiment, the shallow trench isolation oxide SiGe layer 140 near the CMOS active region 210 in the base region is wet-etched to form a non-planar groove as the epitaxial region of the base region. The thickness of the connection region formed after subsequent self-aligned implantation is greater than the epitaxial thickness of the base region, effectively reducing the connection resistance between the inner base region 303 and the outer base region 304. This process is compatible with the standard CMOS process, has fewer process steps, and has good scalability.
[0069] The present invention also discloses a self - aligned SiGe HBT structure with a low base - connection resistance. The self - aligned SiGe HBT structure with a low base - connection resistance of the present invention can be fabricated by using the fabrication method of the self - aligned SiGe HBT structure with a low base - connection resistance in any of the above - mentioned embodiments. The self - aligned SiGe HBT structure fabricated by the above - mentioned method can reduce both the base - connection resistance and the base - emitter capacitance, thereby improving the characteristic frequency and the maximum oscillation frequency of the SiGe HBT.
[0070] The above - mentioned embodiments only express the preferred embodiments of the present invention, and the description thereof is relatively specific and detailed. However, it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.
Claims
1. A manufacturing method of a self-aligned SiGe HBT structure with a low base region connection resistance, characterized in that, It includes the following steps: S100. Complete the process steps before fabricating the base region and open the base region window; S200. Etch to form a non-planar groove at the base region window; S300. Epitaxially grow a SiGe layer in a non-selective manner. The SiGe layer forms an inner base region on the single-crystalline silicon surface in the middle of the non-planar groove and forms an outer base region on the oxide surface outside the inner base region; S400. Fabricate the emitter region; S500. Complete the subsequent fabrication process.
2. The manufacturing method of the self-aligned SiGe HBT structure with a low base region connection resistance according to claim 1, characterized in that , In the step S300, the thickness of the non-selectively epitaxially grown SiGe layer is 400 Å to 700 Å. The SiGe layer is a composite layer, including a Si buffer layer, a SiGe doped layer, and a Si capping layer.
3. The manufacturing method of the self-aligned SiGe HBT structure with a low base region connection resistance as described in claim 1, characterized in that , The step S100 includes the following sub-steps: S110. Use photolithography and etching to form a plurality of shallow trenches on the silicon substrate, and fill each shallow trench with silicon oxide by deposition to form a plurality of shallow trench isolation regions. At the same time, form a first silicon oxide layer on the silicon substrate. The plurality of shallow trench isolation regions divide the upper part of the silicon substrate into a CMOS region and an HBT region, divide the CMOS region into a CMOS active region and a substrate contact region, and divide the HBT region into a collector active region and a collector contact region; S120. Form a polysilicon gate above the CMOS active region, form gate oxide silicon on the surface of the polysilicon gate by oxidation, and form source / drain extension regions by implantation on the CMOS active regions on both sides of the polysilicon gate; S130. Form a selective ion implantation region by implantation in the middle of the collector active region; S140. Deposit an oxide on the silicon substrate to form a second silicon oxide layer, and then deposit a nitride on the second silicon oxide layer to form a first silicon nitride layer; S150. Open the base region window in the HBT region by photolithographically etching the first silicon nitride layer. The width of the base region window is greater than the width of the collector active region.
4. The method for fabricating a self-aligned SiGe HBT structure with a low base region connection resistance according to claim 3, wherein , In the step S200, remove the second silicon oxide layer in the base region window area by wet etching to form a non-planar groove, and the etching depth is 200 Å to 1200 Å. The non-planar groove forms an annular concave area at the connection between the collector active region and the shallow trench, and a side etching structure is formed at the part of the edge of the non-planar groove below the silicon nitride.
5. The method for fabricating a self-aligned SiGe HBT structure with a low base region connection resistance as claimed in claim 4, wherein , In the step S300, the SiGe layer formed on the single-crystalline silicon surface inside the concave area is a single-crystalline SiGe region, and the single-crystalline SiGe region forms the inner base region. The SiGe layer formed on the oxide surface inside and outside the concave area is a polycrystalline SiGe region, and the polycrystalline SiGe region forms the outer base region.
6. The manufacturing method of the self-aligned SiGe HBT structure with low base region connection resistance as claimed in claim 3, characterized in that ,In the step S130, when forming a selective ion implantation region by implantation, the implantation energy is 10 keV to 100 keV, and the implantation dose is 1E13 cm -3 ~2E14 cm -3 , and the implanted impurity is arsenic or antimony.
7. The manufacturing method of the self-aligned SiGe HBT structure with a low base region connection resistance according to any one of claims 1 to 6, characterized in that, The step S400 includes the following sub-steps: S410. Deposit a third silicon oxide layer and a polysilicon sacrificial layer on the silicon substrate in sequence, and etch the polysilicon sacrificial layer to form a sacrificial emitter region above the selective ion implantation region. The width of the sacrificial emitter region is 1 / 2 to 1 / 5 of the width of the collector active region; S420. Deposit a high-quality oxide layer on the silicon substrate, and dry-etch the high-quality oxide layer to retain the high-quality oxide layer outside the sacrificial emitter region to form a silicon oxide sidewall; S430. Inject P-type impurities into the outer base region to reduce the resistance of the connection region between the inner base region and the outer base region, and form an inner and outer base connection extension region around the selective ion implantation region; S440. Etch away the sacrificial emitter region and the third silicon oxide layer below the sacrificial emitter region, open the emitter window, and expose the surface of the SiGe layer; S450. Deposit or non-selectively epitaxially grow a silicon layer, and perform patterned etching on the silicon layer to form an emitter region.
8. The manufacturing method of the self-aligned SiGe HBT structure with low base region connection resistance as described in claim 7, characterized in that, In the step S430, the implantation energy is 10 keV to 60 keV, the implantation dose is 5E14 cm -3 ~1E16 cm -3 , and the implanted impurity is boron or BF2+.
9. The manufacturing method of the self-aligned SiGe HBT structure with low base region connection resistance as described in claim 7, characterized in that, In the step S450, the silicon layer is grown by deposition or non-selective epitaxy, the in-situ impurity is arsenic or phosphorus, and the doping concentration is 5e19 cm -3 ~2e20 cm -3 .
10. A self-aligned SiGe HBT structure with a low base connection resistance, characterized in that: It is made by using the manufacturing method of the self-aligned SiGe HBT structure with a low base region connection resistance as described in any one of claims 1 to 9.