HEMT (High Electron Mobility Transistor) device with adjustable threshold voltage and preparation method thereof

Abstract

The invention discloses an HEMT device capable of regulating and controlling threshold voltage and a preparation method of the HEMT device. The HEMT device comprises a substrate, a nucleating layer, a buffer layer, a channel layer and a barrier layer which are arranged from bottom to top. A source electrode and a drain electrode are arranged at the two ends of the barrier layer respectively, and metal interconnection layers are arranged on the source electrode and the drain electrode; a SiN passivation layer is arranged on the barrier layer; a concave gate structure is arranged in the SiN passivation layer, and gate dielectric layers are arranged on the inner wall of the concave gate structure and the surface of the SiN passivation layer; a gate electrode is arranged on the gate dielectric layer; a SiNx protection layer is arranged above the gate electrode and on the surface of the gate dielectric layer, the gate dielectric layer comprises a dielectric insertion layer and a ferroelectric layer, the dielectric insertion layer is made of an AlN or Al2O3 material, and the ferroelectric layer is made of a material which has a wurtzite structure and contains a third nitride compound of transition metal. According to the invention, the nitride containing the transition metal and having the wurtzite structure as an epitaxial material is introduced as the ferroelectric layer, so that the performance and reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a HEMT device with adjustable threshold voltage and a preparation method thereof. Background Art

[0002] Due to the different energy band structures between the AlGaN and GaN layers, a potential well exists at the interface of the GaN-based high electron mobility transistor device (HEMT), resulting in a large amount of two-dimensional electron gas (2DEG) with high electron mobility near the AlGaN / GaN heterojunction interface. The existence of this 2DEG enables the HEMT to achieve fast switching and high-frequency operation capabilities, so it has broad application prospects in high-frequency and high-power switching devices. Usually, the 2DEG always exists and is in the conductive working state without gate regulation, that is, the HEMT is in the on state (normally open structure). This increases potential safety hazards in practical applications (even in the case of gate voltage failure, the component is always in the on state). In addition, it becomes more difficult to fabricate integrated logic gates using the normally open structure.

[0003] With the increasingly wide application of GaN-based HEMTs, especially in power electronic circuits, a normally off structure is required, that is, the 2DEG needs to be turned off without applying a gate voltage, or only conduct a very small cut-off current. So far, such normally off devices have been realized through various alternative methods, such as through Schottky gate structures, recessed gate structures, or implanting fluoride ions under the gate, etc. However, the HEMT devices prepared by these methods have only very low threshold voltages (Vth), usually in the range of less than or close to 1V. To obtain a higher threshold voltage, it can be achieved through a p-doped AlGaN gate. However, the performance of such a device depends on the metallization effect of the gate contact as a Schottky contact or an ohmic contact, which may generate high gate leakage current. If a Schottky contact is formed, the depletion region of p-GaN reduces the direct control of the gate potential on the 2DEG.

[0004] In addition, normally-off GaN-based HEMTs can also be realized by using ferroelectric (FE) materials, similar to the concept of FE field-effect transistors (FE-FETs). For example, in memory applications, a variable bias voltage is integrated into the gate stack through movable charges in the ferroelectric material, so that the threshold voltage is higher than 0V, enabling the HEMT to be in the off state even without an applied gate voltage. So far, this method has been implemented in established oxide-based ferroelectrics, such as oxides like LiNbO3, Pb(Zr,Ti)O3, BaTiO3, HfO2, etc. For example, patent application number CN107369704A describes an FE-HEMT with a gate stack structure, having a gate dielectric layer of AlN or Al2O3, and using a hafnium zirconium oxide-based composite ferroelectric material such as HfZrO to regulate the threshold voltage. Additionally, patent application number CN102299576B uses LiNbO3 or LiTaO3 as an FE alternative material. However, these oxide materials have low compatibility with the epitaxial process, resulting in a relatively high defect density at the interface between the ferroelectric layer and the epitaxial layer, which is not conducive to improving device performance. Moreover, the Curie temperature of traditional oxide ferroelectric materials is relatively low, usually around 350 °C, which means that in a high-temperature environment, the polarization state of these materials may be unstable, affecting the performance and reliability of the device. Summary of the Invention

[0005] In view of the above problems, the present invention aims to provide a HEMT device capable of regulating the threshold voltage and its manufacturing method. By introducing a nitride containing transition metals with a wurtzite structure similar to the epitaxial material as the ferroelectric layer, the defect density between the ferroelectric layer and the barrier layer is improved, and the performance and reliability of the device are enhanced.

[0006] The technical solution of the present invention is as follows:

[0007] On the one hand, the present invention provides a HEMT device capable of regulating the threshold voltage, including a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer arranged from bottom to top; source electrodes and drain electrodes are respectively arranged at both ends on the barrier layer, and a metal interconnection layer is arranged on the source electrodes and the drain electrodes; a SiN passivation layer with an edge extending downward to the buffer layer is arranged on the barrier layer; a recessed gate structure is arranged in the SiN passivation layer, and a concave gate dielectric layer is arranged on the inner wall of the recessed gate structure and the surface of the SiN passivation layer; a gate electrode is arranged on the gate dielectric layer; a SiN x protection layer is arranged above the gate electrode and on the surface of the gate dielectric layer. The gate dielectric layer is a stacked gate structure, and the gate dielectric layer includes a dielectric insertion layer and a ferroelectric layer arranged from bottom to top. The dielectric insertion layer is made of AlN or Al2O3 material, and the ferroelectric layer is made of a material of a third nitride compound with a wurtzite structure and containing transition metals.

[0008] Preferably, the thickness of the buffer layer is 0.6 - 3 μm, the thickness of the channel layer is 200 - 250 nm, and the thickness of the barrier layer is 15 - 25 nm; the main surface of the channel layer is disposed opposite to the main surface of the buffer layer, and the main surface of the barrier layer is disposed opposite to the main surface of the channel layer.

[0009] Preferably, the thickness of the dielectric insertion layer is 5 - 20 nm.

[0010] Preferably, the ferroelectric layer is an AlScN ferroelectric material; the thickness of the ferroelectric layer is 5 - 1000 nm.

[0011] On the other hand, the present invention also provides a method for manufacturing a HEMT device with adjustable threshold voltage, including the following steps: S1: Use MOCVD epitaxial growth method on a substrate to sequentially grow a nucleation layer, a buffer layer, a channel layer, and a barrier layer to obtain an epitaxial substrate; S2: Photolithograph a device isolation region on the barrier layer of the epitaxial substrate, and use ICP inductively coupled plasma etching process or ion implantation process to fabricate the device isolation region; S3: Photolithograph a source electrode region and a drain electrode region on the barrier layer of the epitaxial substrate, and prepare the source electrode and the drain electrode through electron beam evaporation process and metal lift-off process; S4: Use PECVD plasma enhanced chemical vapor deposition method to deposit a SiN passivation layer on the epitaxial substrate; S5: Photolithograph a gate trench region on the SiN passivation layer, and use RIE reactive ion etching process to etch the SiN passivation layer in the gate trench region to the barrier layer; S6: Use MOCVD metal organic chemical vapor deposition epitaxial growth method on the SiN passivation layer and the gate trench region of the epitaxial substrate to sequentially prepare a dielectric insertion layer and a ferroelectric layer, and the dielectric insertion layer and the ferroelectric layer constitute a gate dielectric layer; S7: Photolithograph a gate electrode region on the gate dielectric layer, and prepare the gate electrode through electron beam evaporation process and metal lift-off process; S8: Use PECVD plasma enhanced chemical vapor deposition method to deposit SiN x protective layer; S9: Photolithograph an opening region of the metal interconnection layer on the SiN x protective layer, and use RIE reactive ion etching process to etch the opening region to the source electrode, the drain electrode, and the gate electrode; S10: Fabricate a metal interconnection layer on the SiN x protective layer and the opening region, and prepare the metal interconnection layer through electron beam evaporation process and metal lift-off process to complete the fabrication of the HEMT device with adjustable threshold voltage.

[0012] Preferably, the lithography of the device isolation region on the barrier layer of the epitaxial substrate in step S2 includes the following steps: ultrasonically clean the epitaxial substrate successively with acetone, isopropyl alcohol, and pure water for 10 min and then dry it; bake it at 145 °C for 10 min and then clean it with oxygen plasma for 2 min; spin-coat photoresist on the cleaned epitaxial substrate to a thickness of 1 - 1.5 μm and bake it at 95 °C for 1.5 min; expose and develop the epitaxial substrate after spin-coating and baking with a lithography machine, rinse with pure water, and dry with nitrogen to leave an etching pattern; fabricate the device isolation region using ICP inductively coupled plasma etching process, using boron trichloride with a volume flow rate of 30 - 50 sccm as the reaction gas, and setting the RF power of the upper electrode and the lower electrode of the inductively coupled plasma etching system to 150 - 300 W and 15 - 30 W respectively, and the reaction chamber pressure to 6 - 10 mTorr; after forming the isolation region pattern through lithography exposure and development, using boron trichloride with a flow rate of 30 - 50 sccm as the reaction gas, under the process conditions of setting the RF power of the upper electrode to 150 - 300 W, the RF power of the lower electrode to 15 - 30 W, and the chamber pressure to 6 - 10 mTorr in the inductively coupled plasma etching system, etch the barrier layer, the channel layer, and part of the buffer layer to a depth of 300 - 350 nm successively, and after the etching is completed, ultrasonically clean with acetone, isopropyl alcohol, and pure water to remove the photoresist and dry it.

[0013] Preferably, the deposition of the SiN passivation layer on the epitaxial substrate by PECVD plasma enhanced chemical vapor deposition method in step S4 includes the following steps: ultrasonically clean the epitaxial substrate on which device isolation and source electrode and drain electrode fabrication have been completed successively with acetone, isopropyl alcohol, and pure water, dry it with nitrogen, bake it at 145 °C for 10 minutes, and clean the surface with oxygen plasma; then, in the plasma enhanced chemical vapor deposition system, using ammonia with a flow rate of 15 - 45 sccm and silane with a flow rate of 30 - 60 sccm as reaction gases, deposit a 100 - nm - thick SiN passivation layer on the surfaces of the source electrode, drain electrode, and barrier layer under the conditions of a substrate temperature of 250 - 280 °C, a chamber pressure of 180 - 220 Pa, and an RF power of 25 - 50 W.

[0014] Preferably, the step of photolithographing the gate trench region on the SiN passivation layer in step S5 includes the following steps: successively ultrasonically cleaning and drying the epitaxial substrate deposited with the SiN passivation layer with acetone, isopropyl alcohol, and pure water, performing oxygen plasma cleaning after baking at 145 °C for 10 minutes; spin-coating a photoresist with a thickness of 1-1.5 μm and pre-baking at 95 °C for 2 minutes, removing the photoresist in the gate trench region through photolithographic exposure and development; etching the SiN passivation layer in the gate trench region by using an ICP etching process, with the etching reaction gases being BCl3 and AR2, the reaction chamber pressure being 8 mTorr, the RF powers of the upper electrode and the lower electrode being 300 W and 30 W respectively, etching and removing 100 nm of the SiN passivation layer in the gate trench region until the barrier layer is exposed, and removing the photoresist and drying after the etching is completed.

[0015] Preferably, the step of fabricating a gate dielectric layer including a dielectric insertion layer and a ferroelectric layer on the SiN passivation layer and the gate trench region in step S6 includes the following steps: successively ultrasonically cleaning and drying the epitaxial substrate after etching the gate trench with acetone, isopropyl alcohol, and pure water and nitrogen drying, performing oxygen plasma treatment after baking at 145 °C, and then using a metal-organic chemical vapor deposition process, with trimethylaluminum and ammonia as precursors, the flow rate of trimethylaluminum being 15-25 sccm and the flow rate of ammonia being 200-350 sccm, depositing the dielectric insertion layer under the conditions of a substrate temperature of 850-900 °C and an RF power of 25-50 W; subsequently, through a plasma-enhanced chemical vapor deposition process, with trimethylaluminum, trimethylscandium, and ammonia as precursors, the flow rate of trimethylaluminum being 10-20 sccm, the flow rate of trimethylscandium being 5-15 sccm, and the flow rate of ammonia being 100-200 sccm, depositing the ferroelectric layer under the same temperature and RF power conditions.

[0016] Preferably, in step S10, on the SiN x fabricating a metal interconnection layer on the passivation layer and the opening region includes the following steps: successively ultrasonically cleaning and drying the epitaxial substrate with a SiN x passivation layer and an opening structure with acetone, isopropyl alcohol, and pure water and nitrogen drying, performing oxygen plasma cleaning after baking at 145 °C, spin-coating a photoresist with a thickness of 0.7-1 μm and pre-baking at 110 °C for 2 minutes, forming a metal interconnection pattern through photolithographic exposure and development; removing the bottom film by plasma cleaning, evacuating to 7×10 -6 Torr in an electron beam evaporator, successively evaporating a Ni layer with a thickness of 100 nm and an Au layer with a thickness of 200 nm to form a metal interconnection stack structure, and then ultrasonically cleaning with a stripping solution, isopropyl alcohol, and pure water to remove the photoresist and excess metal, finally forming a metal interconnection layer in the opening region and completing the device fabrication.

[0017] The beneficial effects of the present invention are:

[0018] 1. The present invention uses a ferroelectric material with adjustable polarization state, which is placed between the gate and the dielectric layer to achieve the regulation of the HEMT threshold voltage. By applying a voltage to the gate, the polarization state of the ferroelectric material changes, and the mobile charges in the ferroelectric material integrate a variable bias voltage into the gate stack, making the threshold voltage higher than 0V. Thus, the HEMT can be in a non-conductive state even without applying a gate voltage, that is, a normally-off structure, improving the safety of the actual application of the device.

[0019] 2. The material used for the ferroelectric layer in the present invention is a third nitride compound with a wurtzite crystal structure and containing one or more group III elements. Since group III nitrides are usually semiconductor materials with a large bandgap and group III nitride compounds can have a high degree of polarization, the HEMT can have particularly low losses. In particular, ferroelectric materials made of nitride compounds or zinc-containing oxide compounds can have a particularly high polarization, which may cause a large shift in the threshold voltage of the HEMT due to the high polarization. Therefore, the HEMT has a larger threshold voltage, and thus a larger operating region can be achieved.

[0020] 3. The present invention uses a third nitride compound material with a wurtzite structure and containing transition metals as the ferroelectric layer. This material has a similar material structure to the epitaxial layer and is compatible with the epitaxial layer preparation process, thus significantly reducing the interface defect density and improving the device performance. Materials with a wurtzite structure (such as III-N semiconductors or ZnO) can be epitaxially deposited, making the layer sequence preparation process of the first layer, the second layer, and the ferroelectric third layer compatible, with a very low defect structure density. A boundary layer with a particularly low defect density can be obtained between the second layer and the third layer, thus obtaining particularly good material properties in the ferroelectric part of the gate structure.

[0021] 4. The ferroelectric nitride compound or oxide compound material used in the present invention has a high Curie temperature, and the maximum operating temperature can exceed 1000°C, which is much higher than that of iron oxide ferroelectrics (up to 350°C). Therefore, even at high operating temperatures, the polarization state of the ferroelectric material can remain stable, thus improving the stability and reliability of the device in a high-temperature environment. Therefore, the HEMT of the present invention is particularly suitable for power electronic components, such as current converters. The high-temperature stability also allows for a high degree of flexibility in selecting the production process of the HEMT, such as using a gate leading process, etc. Brief Description of the Drawings

[0022] Figure 1 is a cross-sectional schematic diagram of the HEMT device with adjustable threshold voltage in the embodiment of the present invention;

[0023] Figure 2It is a flowchart for fabricating a HEMT device with adjustable threshold voltage in an embodiment of the present invention.

[0024] Reference numerals: 1, substrate; 2, nucleation layer; 3, buffer layer; 4, channel layer; 5, barrier layer; 6, source electrode; 7, drain electrode; 8, SiN passivation layer; 9, gate dielectric layer; 91, dielectric insertion layer; 92, ferroelectric layer; 10, gate electrode; 11, SiN x protective layer; 12, metal interconnection layer. Detailed implementation manners

[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments, but it does not limit the scope of the present invention and is only for illustrative purposes. It should be noted that, without conflict, the embodiments and technical features in the embodiments of the present application can be combined with each other. Unless otherwise specified, all technical and scientific terms used in the present application have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The experimental methods used in the following embodiments are all conventional methods unless otherwise specified. The materials, reagents, etc. used in the following embodiments can be obtained from commercial channels unless otherwise specified.

[0026] Embodiment 1

[0027] Please refer to Figure 1 , which shows a HEMT device with adjustable threshold voltage of the present invention. From bottom to top, it includes a substrate 1, an AlN nucleation layer 2, a GaN buffer layer 3, a GaN channel layer 4, and an AlGaN barrier layer 5; source electrodes 6 and drain electrodes 7 are respectively provided at both ends on the barrier layer 5, and a metal interconnection layer 12 is provided on the source electrodes 6 and drain electrodes 7; a SiN passivation layer 8 with an edge extending downward to the GaN buffer layer 3 is provided on the AlGaN barrier layer 5; a recessed gate structure is provided in the SiN passivation layer 8, and a concave gate dielectric layer 9 is provided on the inner wall of the recessed gate structure and the surface of the SiN passivation layer 8;

[0028] The gate dielectric layer 9 is a stacked gate structure. The gate dielectric layer 9 includes an AlN dielectric insertion layer 91 and an AlScN ferroelectric layer 92 arranged from bottom to top. The thickness of the AlN dielectric insertion layer 91 is 5 - 20 nm, and the thickness of the AlScN ferroelectric layer 92 is 5 - 1000 nm: a gate electrode 10 is provided on the gate dielectric layer 9. A SiN x protective layer 11 is provided above the gate electrode 10 and on the surface of the gate dielectric layer 9. SiN x There are openings provided in the SiN

[0029] Specifically, the substrate 1 includes but is not limited to a silicon substrate 1, a sapphire substrate 1, a silicon carbide substrate 1, and a GaN substrate 1, with a thickness of 0.5 - 1 mm; the thickness of the AlN nucleation layer 2 is 150 nm; the thickness of the GaN buffer layer 3 is 600 nm; the thickness of the GaN channel layer 4 is 200 nm; the thickness of the AlGaN barrier layer 5 is 20 nm, and the Al component is 25%; the thickness of the AlN dielectric insertion layer 91 is 5 nm; the thickness of the AlScN ferroelectric layer 92 is 5 - 1000 nm; the thickness of the SiN passivation layer 8 is 100 nm; the thickness of the SiN passivation layer 8 is 250 nm.

[0030] Please refer to Figure 2 , which shows the manufacturing flow chart of a HEMT device with adjustable threshold voltage according to the present invention.

[0031] This embodiment also provides a method for manufacturing a stacked-gate GaN-based HEMT device whose gate dielectric includes a 5-nm AlN dielectric insertion layer 91 and a 5-nm ferroelectric layer 92:

[0032] Step 1: Use MOCVD to sequentially grow a 150-nm AlN nucleation layer 2, a 600-nm GaN buffer layer 3, a 200-nm GaN channel layer 4, and a 20-nm AlGaN barrier layer 5 on the sapphire substrate 1.

[0033] Step 2: Etch the device isolation region on the epitaxial substrate to the AlGaN barrier layer 5.

[0034] 2a) Photolithograph the device isolation region on the AlGaN barrier layer 5:

[0035] First, ultrasonically clean the epitaxial substrate in acetone, isopropyl alcohol, and pure water for 10 min in sequence, and blow dry the surface moisture with a nitrogen gun.

[0036] Then, place the epitaxial substrate on a hot plate and bake it at 145 °C for 10 min, and then clean it with oxygen plasma for 2 min.

[0037] Next, spin coat photoresist on the epitaxial substrate with a clean surface, with a spin coating thickness of 1 μm, and place the epitaxial substrate on a hot plate and bake it at 95 °C for 1.5 min.

[0038] Finally, place the epitaxial substrate with spin coating completed in a photolithography machine to expose the surface of the spin-coated epitaxial substrate, place the exposed epitaxial substrate in a developer for development, then rinse the epitaxial substrate with pure water and blow dry it with nitrogen, and finally leave the pattern to be etched.

[0039] 2b) Etch the device isolation region on the AlGaN barrier layer 5:

[0040] First, place the epitaxial substrate that has completed spin coating and development in an inductively coupled plasma etcher for etching. Sequentially etch away the AlGaN barrier layer 5, GaN channel layer 4, and part of the GaN buffer layer 3, with an etching depth of 300 nm. The process conditions for inductively coupled plasma etching are as follows: Boron trichloride is used as the reaction gas, with a flow rate of 50 sccm. The RF powers of the upper and lower electrodes are 300 W and 30 W respectively, and the reaction chamber pressure is 8 mTorr.

[0041] Then, ultrasonically clean the etched epitaxial substrate in acetone, isopropyl alcohol, and pure water for 10 min respectively, and finally dry the surface moisture with a nitrogen gun.

[0042] Step 3, fabricate the source electrode 6 and drain electrode 7 on the AlGaN barrier layer 5 of the epitaxial substrate.

[0043] 3a) Photolithograph the source electrode region and drain electrode region on the AlGaN barrier layer 5:

[0044] First, ultrasonically clean the epitaxial substrate that has completed device isolation in acetone, isopropyl alcohol, and pure water for 10 min respectively, and dry the surface moisture with a nitrogen gun.

[0045] Then, place the epitaxial substrate on a hot plate and bake it at 145 °C for 10 min, and then clean it with oxygen plasma for 2 min.

[0046] Next, spin coat photoresist on the epitaxial substrate with a clean surface. The spin coating rate is 4000 rpm, and the spin coating thickness is 0.7 μm. Place the epitaxial substrate in an oven at 110 °C and bake for 2 min.

[0047] Finally, place the epitaxial substrate with completed spin coating in a photolithography machine to expose the surface of the spin-coated epitaxial substrate. Place the exposed epitaxial substrate in a developer for development, then rinse the epitaxial substrate with pure water and dry it with nitrogen, finally leaving the required pattern.

[0048] 3b) Evaporate the source electrode 6 and drain electrode 7 on the AlGaN barrier layer 5:

[0049] First, place the developed epitaxial substrate in a plasma cleaner and clean it for 2 min to remove the bottom film.

[0050] Then, place the sample in an electron beam evaporator. After the vacuum degree of the reaction chamber reaches 7×10 -6 Torr, evaporate ohmic metal on the surface of the epitaxial substrate to form the source electrode 6 and drain electrode 7. The ohmic metal is a metal stack structure composed of four metals, Ti, Al, Ni, and Au from bottom to top in sequence, with thicknesses of 20 nm, 130 nm, 50 nm, and 100 nm respectively.

[0051] Next, the epitaxial substrate after ohmic metal evaporation is peeled off, and ultrasonically cleaned in stripping solution, isopropyl alcohol, and pure water for 10 min respectively to remove the metal attached to the photoresist, leaving only the metal on the AlGaN barrier layer 5 in the developed area. After the sample is cleaned with pure water and dried with nitrogen, the source electrode 6 and drain electrode 7 are finally formed;

[0052] 3c) The epitaxial substrate with the metal peeled off is placed in a rapid thermal annealing furnace for annealing. Annealing is carried out at 870 °C for 30 s in an N2 atmosphere, so that the metal of the source electrode 6 and drain electrode 7 diffuses into the GaN channel layer 4, and the ohmic metal makes ohmic contact with the 2DEG.

[0053] Step 4, deposit a SiN passivation layer 8 on the epitaxial substrate by PECVD.

[0054] 4a) Surface cleaning of the epitaxial substrate that has completed device isolation and the preparation of ohmic metal for the source electrode 6 and drain electrode 7:

[0055] First, the epitaxial substrate is successively ultrasonically cleaned in acetone, isopropyl alcohol, and pure water for 10 min, and the surface moisture is blown dry with a nitrogen gun;

[0056] Then, the epitaxial substrate is placed on a hot plate and baked at 145 °C for 10 min, and then cleaned with oxygen plasma for 2 min;

[0057] 4b) Deposit a SiN passivation layer 8 on the source electrode 6, drain electrode 7, and the AlGaN barrier layer 5 in the active region by PECVD. The deposition thickness is 100 nm. The PECVD process conditions are as follows: ammonia and silane are used as reaction gases, the volume flow rate of ammonia is 45 sccm, the volume flow rate of silane is 45 sccm, the temperature of substrate 1 is 260 °C, the pressure in the reaction chamber is 200 Pa, and the radio frequency power is 50 W.

[0058] Step 5, etch the gate trench area on the SiN passivation layer 8 of the epitaxial substrate.

[0059] 5a) Photolithography of the gate trench area on the SiN passivation layer 8 of the epitaxial substrate:

[0060] First, the epitaxial substrate with the SiN passivation layer 8 deposited is successively ultrasonically cleaned in acetone, isopropyl alcohol, and pure water for 10 min, and the surface moisture is blown dry with a nitrogen gun;

[0061] Then, the epitaxial substrate is placed on a hot plate and baked at 145 °C for 10 min, and then cleaned with oxygen plasma for 2 min;

[0062] Next, spin-coat photoresist on the epitaxial substrate with a clean surface. The spin-coating thickness is 1 μm, and the epitaxial substrate is placed on a hot plate and baked at 95 °C for 2 min;

[0063] Finally, place the epitaxial substrate after spin coating in a lithography machine to expose the surface of the spin-coated epitaxial substrate. Place the exposed epitaxial substrate in a developer to develop it to remove the photoresist in the gate trench area, rinse it with pure water and dry it with nitrogen gas;

[0064] 5b) Use ICP etching process to etch the SiN passivation layer 8 in the gate trench area. The etching reaction gases are BCl3 and AR2, the reaction chamber pressure is 8 mTorr, the RF powers of the upper electrode and the lower electrode are 300 W and 30 W respectively, the etching depth is 100 nm, etch until the AlGaN barrier layer 5, and remove the photoresist and dry it after etching.

[0065] Step 6, use MOCVD to prepare an AlN / AlScN stacked gate dielectric layer 9 on the SiN passivation layer 8 and the gate trench area of the epitaxial substrate.

[0066] 6a) Perform surface cleaning on the epitaxial substrate after etching the gate trench area:

[0067] First, place the epitaxial substrate in acetone, isopropyl alcohol, and pure water in sequence for ultrasonic cleaning for 10 min, and blow dry the surface moisture with a nitrogen gun;

[0068] Then, place the epitaxial substrate on a hot plate and bake it at 145 °C for 10 min, and then clean it with oxygen plasma for 2 min;

[0069] 6b) Use MOCVD process to deposit an AlN dielectric insertion layer 91 with a thickness of 5 nm; the reaction precursor sources used in the deposition process are trimethylaluminum (TMA), the reaction gas is NH3, and their flow rates are 20 sccm and 350 sccm respectively, the temperature of substrate 1 is 900 °C, and the RF power is 50 W.

[0070] 6c) Use PECVD process to deposit an AlScN ferroelectric layer 92 with a thickness of 5 nm; the reaction precursor sources used in the deposition process are TMA and trimethylscandium (TMS), the reaction gas is NH3, and their volume flow rates are 10 sccm, 5 sccm, and 200 sccm respectively, the temperature of substrate 1 required for the process is 900 °C, and the RF power is 50 W.

[0071] Step 7, fabricate a gate electrode 10 on the gate dielectric layer 9 where the gate electrode 10 area is located.

[0072] 7a) Lithograph the gate electrode area on the gate dielectric layer 9:

[0073] First, place the epitaxial substrate after gate dielectric deposition in acetone, isopropyl alcohol, and pure water in sequence for ultrasonic cleaning for 10 min, and blow dry the surface moisture with a nitrogen gun;

[0074] Then, place the epitaxial substrate on a heating plate and bake it at 145 °C for 10 min, and then clean it with oxygen plasma for 2 min;

[0075] Next, spin coat photoresist on the epitaxial substrate with a clean surface. The spin coating rate is 4000 rpm, and the spin coating thickness is 0.7 μm. Place the epitaxial substrate on a heating plate and bake it at 110 °C for 2 min;

[0076] Finally, place the epitaxial substrate with spin coating completed in a lithography machine to expose the surface of the spin-coated epitaxial substrate. Place the exposed epitaxial substrate in a developer for development. Then, rinse the epitaxial substrate with pure water and dry it with nitrogen gas, finally leaving the required pattern;

[0077] 7b) Evaporate the gate on the gate dielectric layer 9:

[0078] First, place the developed epitaxial substrate in a plasma cleaner and clean it for 2 min to remove the bottom film;

[0079] Then, put the sample into an electron beam evaporator and start pumping vacuum until the vacuum degree of the reaction chamber reaches 7×10 - 6 Torr. Then, evaporate the gate metal on the surface of the epitaxial substrate to form a gate. The gate metal is a metal stack structure composed of two metals, Ni and Au, from bottom to top in sequence, and their thicknesses are 50 and 100 nm respectively;

[0080] Next, strip the epitaxial substrate with the gate metal evaporated. Ultrasonically clean it in the stripping solution, isopropyl alcohol, and pure water for 10 min respectively to remove the metal attached to the photoresist, only leaving the metal on the gate electrode area;

[0081] Finally, rinse the epitaxial substrate with the metal stripped with pure water and dry it with nitrogen gas. The gate forms a Schottky contact with the underlying gate dielectric layer 9;

[0082] Step 8, deposit a SiN passivation layer 8 on the epitaxial substrate by PECVD.

[0083] 8a) Clean the surface of the epitaxial substrate after the Schottky gate metal preparation is completed:

[0084] First, place the epitaxial substrate in acetone, isopropyl alcohol, and pure water in sequence and ultrasonically clean it for 10 min, and blow dry the surface moisture with a nitrogen gun;

[0085] Then, place the epitaxial substrate on a heating plate and bake it at 145 °C for 10 min, and then clean it with oxygen plasma for 2 min;

[0086] 8b) On the gate and the gate dielectric layer 9, deposit a SiN passivation layer 8 using the PECVD process, with a growth thickness of 250 nm. The PECVD process conditions are as follows: ammonia and silane are used as reaction gases, the volume flow rate of ammonia is 45 sccm, the volume flow rate of silane is 45 sccm, the temperature of substrate 1 is 260 °C, the pressure in the reaction chamber is 200 Pa, and the RF power is 50 W.

[0087] Step 9, open source electrode 6, drain electrode 7, and the gate region on the SiN passivation layer 8 of the epitaxial substrate.

[0088] 9a) Lithographically open the area on the SiN passivation layer 8 of the epitaxial substrate:

[0089] First, sequentially place the epitaxial substrate with the deposited SiN passivation layer 8 into acetone, isopropyl alcohol, and pure water for ultrasonic cleaning for 10 min, and blow dry the surface moisture with a nitrogen gun.

[0090] Then, place the epitaxial substrate on a hot plate and bake it at 145 °C for 10 min, and then perform oxygen plasma cleaning for 2 min.

[0091] Next, spin coat photoresist on the epitaxial substrate with a clean surface, with a spin coating thickness of 1 μm, and place the epitaxial substrate on a hot plate and bake it at 95 °C for 2 min.

[0092] Finally, place the epitaxial substrate with the spin coating completed into a lithography machine to expose the surface of the spin-coated epitaxial substrate, place the exposed epitaxial substrate into a developer for development, rinse it with pure water, and blow dry it with nitrogen, finally leaving the etched pattern.

[0093] 9b) Use the RIE etching process to etch the SiN passivation layer 8 in the corresponding regions of source electrode 6, drain electrode 7, and the gate. The etching reaction gases are CF4 and O2, with both flow rates being 25 sccm, the electrode RF power being 120 W, the etching depth being 250 nm, and etching until the electrode metal layer.

[0094] Step 10, fabricate a metal interconnection layer 12 on the SiN x protective layer 11 and the open area.

[0095] 10a) Lithographically open the metal interconnection area on the SiN x protective layer 11 and the open area:

[0096] First, sequentially place the epitaxial substrate that has completed the deposition of the SiN x protective layer 11 and the opening into acetone, isopropyl alcohol, and pure water for ultrasonic cleaning for 10 min, and blow dry the surface moisture with a nitrogen gun.

[0097] Then, place the epitaxial substrate on a hot plate and bake it at 145 °C for 10 min, and then perform oxygen plasma cleaning for 2 min.

[0098] Next, spin coat photoresist on the surface-cleaned epitaxial substrate with a spin coating thickness of 0.7 μm, and bake the epitaxial substrate at 110 °C for 2 min;

[0099] Finally, place the epitaxial substrate after spin coating in a lithography machine to expose the surface of the photoresist-coated epitaxial substrate, place the exposed epitaxial substrate in a developer for development, then rinse the epitaxial substrate with pure water and dry it with nitrogen, finally leaving the required pattern;

[0100] 10b) Evaporate an interconnection metal layer on the SiN x protective layer 11 and the opening area:

[0101] First, place the developed epitaxial substrate in a plasma cleaner for 2 min to remove the bottom film;

[0102] Then, place the sample in an electron beam evaporator, evacuate to a reaction chamber vacuum of 7×10 -6 Torr, and evaporate an interconnection metal on the surface of the epitaxial substrate to form a metal interconnection layer 12. The metal interconnection layer 12 is a metal stack structure composed of two metals, Ni and Au, from bottom to top, with thicknesses of 100 and 200 nm respectively;

[0103] Finally, perform metal lift-off on the epitaxial substrate after evaporating the interconnection metal. Specifically, place the epitaxial substrate in a stripping solution, isopropyl alcohol, and pure water for ultrasonic cleaning for 10 min to remove the metal attached to the photoresist, leaving only the metal on the opening area;

[0104] Finally, rinse the epitaxial substrate after metal lift-off with pure water and dry it with nitrogen, and the HEMT device fabrication is completed.

[0105] Example 2

[0106] A preparation method of a stacked-gate GaN-based HEMT device with a gate dielectric including a 5-nm AlN dielectric insertion layer 91 and a 50-nm ferroelectric layer 92:

[0107] Steps 1 to 5 are the same as those in Example 1, so they are omitted here.

[0108] Step 6, prepare an AlN / AlScN stacked-gate dielectric layer 9 on the SiN passivation layer 8 and the gate trench area of the epitaxial substrate by MOCVD.

[0109] 6a) Clean the surface of the epitaxial substrate after etching the gate trench area:

[0110] First, place the epitaxial substrate in acetone, isopropyl alcohol, and pure water for ultrasonic cleaning for 10 min, and dry the surface moisture with a nitrogen gun;

[0111] Then, place the epitaxial substrate on a heating plate and bake it at 145 °C for 10 min, and then clean it with oxygen plasma for 2 min;

[0112] 6b) Deposit an AlN dielectric insertion layer 91 with a thickness of 5 nm using the MOCVD process. The deposition process uses TMA as the reaction precursor source, the reaction gas is NH3, and their flow rates are 20 sccm and 350 sccm respectively. The temperature of substrate 1 is 900 °C, and the RF power is 50 W;

[0113] 6c) Deposit an AlScN ferroelectric layer 92 with a thickness of 50 nm using the PECVD process. The reaction precursor sources used in the deposition process are TMA and TMS, the reaction gas is NH3, and their flow rates are 10 sccm, 5 sccm, and 200 sccm respectively. The temperature of substrate 1 required for the process is 900 °C, and the RF power is 50 W.

[0114] Steps 7 to 10 are the same as those in Example 1, so they are omitted here.

[0115] After the above steps, a stacked-gate GaN-based HEMT device with a gate dielectric including a 5-nm AlN dielectric insertion layer 91 and a 50-nm ferroelectric layer 92 in Example 2 is fabricated.

[0116] Example 3

[0117] A method for fabricating a stacked-gate GaN-based HEMT device with a gate dielectric including a 5-nm AlN dielectric insertion layer 91 and a 200-nm ferroelectric layer 92:

[0118] Steps 1 to 5 are the same as those in Example 1, so they are omitted here.

[0119] Steps 6a) and 6b) for depositing an AlN dielectric insertion layer 91 with a thickness of 5 nm using the MOCVD process are the same as those in Example 1, so they are omitted here.

[0120] 6c) Deposit an AlScN ferroelectric layer 92 with a thickness of 200 nm using the PECVD process. The reaction precursor sources used in the deposition process are TMA and TMS, the reaction gas is NH3, and their flow rates are 10 sccm, 5 sccm, and 200 sccm respectively. The temperature of substrate 1 required for the process is 900 °C, and the RF power is 50 W.

[0121] Steps 7 to 10 are the same as those in Example 1, so they are omitted here.

[0122] After the above steps, a stacked-gate GaN-based HEMT device with a gate dielectric including a 5-nm AlN dielectric insertion layer 91 and a 200-nm ferroelectric layer 92 in Example 3 is fabricated.

[0123] In summary, the present invention uses ferroelectric materials to regulate the threshold voltage, which causes less damage to the device surface compared to processes such as recessed gate etching, and can avoid disadvantages such as surface non-uniformity and unstable device performance caused by etching. Secondly, the present invention uses a dielectric insertion layer and a ferroelectric layer to form a stacked gate dielectric structure, which can better exert the polarization modulation effect of the ferroelectric layer, thereby shifting the threshold voltage in the positive direction. Finally, the ferroelectric material used in the present invention is a material of a third nitride compound with a wurtzite structure and containing transition metals. Compared with some oxide ferroelectric materials, the structure of this ferroelectric material is similar to the material structure of the epitaxial layer and can be compatible with the epitaxial layer preparation process. Therefore, the interface defect density is very low, and the improvement effect on device performance is significant.

[0124] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the equivalent embodiments by using the technical content disclosed above within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A HEMT device with adjustable threshold voltage, comprising a substrate (1), a nucleation layer (2), a buffer layer (3), a channel layer (4) and a barrier layer (5) arranged from bottom to top; source electrodes (6) and drain electrodes (7) are respectively arranged at both ends on the barrier layer (5), and a metal interconnection layer (12) is arranged on the source electrodes (6) and the drain electrodes (7); a SiN passivation layer (8) with an edge extending downward to the buffer layer (3) is arranged on the barrier layer (5); a recessed gate structure is arranged in the SiN passivation layer (8), and a concave gate dielectric layer (9) is arranged on the inner wall of the recessed gate structure and the surface of the SiN passivation layer (8); a gate electrode (10) is arranged on the gate dielectric layer (9); a SiN x protective layer (11) is arranged above the gate electrode (10) and on the surface of the gate dielectric layer (9), and is characterized in that The gate dielectric layer (9) is a stacked gate structure. The gate dielectric layer (9) includes a dielectric insertion layer (91) and a ferroelectric layer (92) arranged from bottom to top. The dielectric insertion layer (91) is made of AlN or Al2O3 material, and the ferroelectric layer (92) is made of a material of a third nitride compound with a wurtzite structure and containing transition metals.

2. The HEMT device with adjustable threshold voltage according to claim 1, wherein The thickness of the buffer layer (3) is 0.6 - 3 μm, the thickness of the channel layer (4) is 200 - 250 nm, and the thickness of the barrier layer (5) is 15 - 25 nm; the main surface of the channel layer (4) is arranged opposite to the main surface of the buffer layer (3), and the main surface of the barrier layer (5) is arranged opposite to the main surface of the channel layer (4).

3. The HEMT device with adjustable threshold voltage according to claim 1, wherein The thickness of the dielectric insertion layer (91) is 5 - 20 nm.

4. The HEMT device with adjustable threshold voltage according to claim 1, wherein The ferroelectric layer (92) is an AlScN ferroelectric material; the thickness of the ferroelectric layer (92) is 5 - 1000 nm.

5. The manufacturing method of a HEMT device with adjustable threshold voltage according to claim 1, characterized in that, Including the following steps: S1: Use the MOCVD epitaxial growth method to sequentially grow a nucleation layer (2), a buffer layer (3), a channel layer (4), and a barrier layer (5) on the substrate (1) to obtain an epitaxial substrate; S2: Photolithograph the device isolation region on the barrier layer (5) of the epitaxial substrate, and use the ICP inductively coupled plasma etching process or the ion implantation process to fabricate the device isolation region; S3: Photolithograph the source electrode region and the drain electrode region on the barrier layer (5) of the epitaxial substrate, and prepare the source electrode (6) and the drain electrode (7) through the electron beam evaporation process and the metal lift-off process; S4: Use the PECVD plasma enhanced chemical vapor deposition method to deposit a SiN passivation layer (8) on the epitaxial substrate; S5: Photolithograph the gate trench region on the SiN passivation layer (8), and use the RIE reactive ion etching process to etch the SiN passivation layer (8) in the gate trench region to the barrier layer (5); S6: Use the MOCVD metal organic chemical vapor deposition epitaxial growth method to sequentially prepare a dielectric insertion layer (91) and a ferroelectric layer (92) on the SiN passivation layer (8) and the gate trench region of the epitaxial substrate. The dielectric insertion layer (91) and the ferroelectric layer (92) constitute the gate dielectric layer (9); S7: Photolithograph the gate electrode region on the gate dielectric layer (9), and prepare the gate electrode (10) through the electron beam evaporation process and the metal lift-off process; S8: Deposit SiN on the epitaxial substrate by using the PECVD (Plasma Enhanced Chemical Vapor Deposition) method x protective layer (11); S9: On the SiN x Photolithographically define the opening regions of the metal interconnect layer (12) on the protective layer (11), and use the RIE reactive ion etching process to etch the opening regions down to the source electrode (6), drain electrode (7), and gate electrode (10); S10: On SiN x Fabricate a metal interconnection layer (12) on the protective layer (11) and the opening region, and prepare the metal interconnection layer (12) through an electron beam evaporation process and a lift-off process to complete the fabrication of the HEMT device with an adjustable threshold voltage.

6. The preparation method of the HEMT device with adjustable threshold voltage according to claim 5, characterized in that, The step of photolithographing the device isolation region on the barrier layer (5) of the epitaxial substrate in step S2 includes the following steps: The epitaxial substrate is ultrasonically cleaned with acetone, isopropyl alcohol, and pure water in sequence for 10 min and then dried. Then it is baked at 145 °C for 10 min and then cleaned with oxygen plasma for 2 min; the photoresist is spin-coated on the cleaned epitaxial substrate to a thickness of 1 - 1.5 μm and baked at 95 °C for 1.5 min; after spin-coating and baking, the epitaxial substrate is exposed and developed by a mask aligner, rinsed with pure water, and dried with nitrogen to leave the etching pattern; The device isolation region is fabricated by using ICP inductively coupled plasma etching process. Boron trichloride with a volume flow rate of 30 - 50 sccm is used as the reaction gas. The RF powers of the upper electrode and the lower electrode set in the inductively coupled plasma etching system are 150 - 300 W and 15 - 30 W respectively, and the reaction chamber pressure is 6 - 10 mTorr. After forming the isolation region pattern through photolithography exposure and development, using boron trichloride with a flow rate of 30 - 50 sccm as the reaction gas, under the process conditions of setting the RF power of the upper electrode at 150 - 300 W, the RF power of the lower electrode at 15 - 30 W and the chamber pressure at 6 - 10 mTorr in the inductively coupled plasma etching system, the barrier layer (5), the channel layer (4) and part of the buffer layer (3) are etched successively to a depth of 300 - 350 nm. After the etching is completed, the photoresist is removed by ultrasonic cleaning with acetone, isopropyl alcohol and pure water and then dried.

7. The manufacturing method of the HEMT device with adjustable threshold voltage according to claim 5, characterized in that, The step of depositing the SiN passivation layer (8) on the epitaxial substrate by using PECVD plasma enhanced chemical vapor deposition method in the step S4 includes the following steps: The epitaxial substrate on which the device isolation and the source electrode (6) and the drain electrode (7) have been fabricated is successively subjected to ultrasonic cleaning with acetone, isopropyl alcohol and pure water, dried with nitrogen, baked at 145 °C for 10 minutes, and the surface is cleaned by oxygen plasma. Subsequently, in the plasma enhanced chemical vapor deposition system, with ammonia flow rate of 15 - 45 sccm and silane flow rate of 30 - 60 sccm as the reaction gases, at the substrate (1) temperature of 250 - 280 °C, the chamber pressure of 180 - 220 Pa and the RF power of 25 - 50 W, a SiN passivation layer (8) with a thickness of 100 nm is deposited on the surfaces of the source electrode (6), the drain electrode (7) and the barrier layer (5).

8. The manufacturing method of the HEMT device with adjustable threshold voltage according to claim 5, characterized in that, The step of photolithographing the gate trench region on the SiN passivation layer (8) in the step S5 includes the following steps: The epitaxial substrate deposited with the SiN passivation layer (8) is successively subjected to ultrasonic cleaning with acetone, isopropyl alcohol and pure water and then dried, baked at 145 °C for 10 minutes and then cleaned by oxygen plasma; a photoresist with a thickness of 1 - 1.5 μm is spin-coated and pre-baked at 95 °C for 2 minutes, and the photoresist in the gate trench region is removed through photolithography exposure and development; the SiN passivation layer (8) in the gate trench region is etched by using ICP etching process, the etching reaction gases are BCl3 and AR2, the reaction chamber pressure is 8 mTorr, the RF powers of the upper electrode and the lower electrode are 300 W and 30 W respectively, the SiN passivation layer (8) with a thickness of 100 nm in the gate trench region is etched away until the barrier layer (5) is exposed, and after the etching is completed, the photoresist is removed and dried.

9. The preparation method of the HEMT device with adjustable threshold voltage according to claim 5, characterized in that, The step of fabricating the gate dielectric layer (9) including the dielectric insertion layer (91) and the ferroelectric layer (92) on the SiN passivation layer (8) and the gate trench region in the step S6 includes the following steps: The epitaxial substrate after etching the gate trenches is successively ultrasonically cleaned with acetone, isopropyl alcohol and pure water and dried with nitrogen. After baking at 145 °C and oxygen plasma treatment, using the metalorganic chemical vapor deposition process, with trimethylaluminum and ammonia as precursors, the flow rate of trimethylaluminum is 15 - 25 sccm and the flow rate of ammonia is 200 - 350 sccm, the dielectric insertion layer (91) is deposited at the substrate (1) temperature of 850 - 900 °C and the radio frequency power of 25 - 50 W; Subsequently, through the plasma enhanced chemical vapor deposition process, with trimethylaluminum, trimethylscandium and ammonia as precursors, the flow rate of trimethylaluminum is 10 - 20 sccm, the flow rate of trimethylscandium is 5 - 15 sccm, and the flow rate of ammonia is 100 - 200 sccm, the ferroelectric layer (92) is deposited under the same temperature and radio frequency power conditions.

10. The manufacturing method of the HEMT device with adjustable threshold voltage according to claim 5, characterized in that, In the step S10, on the SiN x Fabricating the metal interconnection layer (12) on the protective layer (11) and the opening area includes the following steps: For an epitaxial substrate with a SiN x protective layer (11) and an opening structure, ultrasonic cleaning with acetone, isopropyl alcohol, and pure water is performed in sequence, followed by nitrogen drying. After baking at 145 °C and oxygen plasma cleaning, a photoresist with a thickness of 0.7 - 1 μm is spin-coated and pre-baked at 110 °C for 2 minutes, and a metal interconnect pattern is formed through photolithographic exposure and development; after removing the bottom film by plasma cleaning, the vacuum is pumped to 7×10 -6 Torr in an electron beam evaporation instrument, and a Ni layer with a thickness of 100 nm and an Au layer with a thickness of 200 nm are evaporated in sequence to form a metal interconnect stack structure. Subsequently, the photoresist and excess metal are removed by ultrasonic cleaning with a stripping solution, isopropyl alcohol, and pure water, and finally, a metal interconnect layer (12) is formed in the opening area and the device fabrication is completed.

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