Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

Embodiments of the present invention disclose a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes a semiconductor body, which includes a first surface, a second surface, a well region, and a first region; the first surface is provided with a gate trench and a source trench; a first insulating layer is located on the bottom surface and sidewalls of the gate trench; a trench gate is located on the side of the first insulating layer in the gate trench away from the semiconductor body; a source trench structure includes a filling layer located in the source trench; an interlayer insulating layer covers the trench gate and the source trench structure and is provided with a first through-hole and a second through-hole; the source contacts the first region through the first through-hole and contacts the filling layer through the second through-hole; and the drain is located on the second surface. The embodiments of the present invention can achieve a gap-free sidewall of the source trench structure and ensure that the filling layer and the source are at the same potential, thereby improving the reliability of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) are widely used in power electronics, automobiles, aerospace and other fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] Existing trench-type silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) offer advantages such as high current density and small cell pitch. However, the high electric fields at the trench bottom and corners result in high electric fields on the gate oxide, making it susceptible to gate oxide breakdown. To protect the gate oxide, a dual-trench SiC MOSFET device is designed, with silicon dioxide covering the gate trench, leaving a portion of the SiC and source trench exposed.

[0004] However, when etching silicon dioxide, a certain amount of overetching is required to ensure complete etching, which leads to the loss of the oxide layer and filler in the source trench. During the subsequent metal filling process, gaps appear on the sidewalls of the source trench, reducing the reliability of the semiconductor device. Summary of the Invention

[0005] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to solve the problem that gaps appear on the sidewalls of a source trench and reduce the reliability of the semiconductor device.

[0006] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0007] A semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface, and the well region being configured as a second conductivity type and located on a side of the first region away from the first surface; a gate trench being provided on the first surface, the gate trench extending from the first surface into the semiconductor body; a source trench being provided on the first surface, the source trench extending from the first surface into the semiconductor body; and a first insulating layer being provided on the bottom surface and sidewalls of the gate trench.

[0008] A trench gate is located in the gate trench on a side of the first insulating layer away from the semiconductor body; the first insulating layer is used to insulate the semiconductor body from the trench gate;

[0009] A source trench structure, comprising a filling layer, wherein the filling layer is located in the source trench;

[0010] an interlayer insulating layer, located on the first surface and covering the trench gate and source trench structures; the interlayer insulating layer is provided with a first through hole and a second through hole; the first through hole is used to expose at least a portion of the first region; the second through hole is used to expose a portion of the filling layer;

[0011] a source electrode, located on a side of the interlayer insulating layer away from the first surface, contacting the first region through the first through hole, and contacting the filling layer through the second through hole;

[0012] The drain is located on the second surface.

[0013] Optionally, the semiconductor body further includes a second region; the second region is set to the second conductivity type and is located at the bottom and sidewalls of the source trench.

[0014] Optionally, the source trench structure further includes a second insulating layer, and the second insulating layer is located on the bottom surface and sidewalls of the source trench.

[0015] Optionally, a groove is provided on the side of the filling layer away from the semiconductor body; in the direction from the first surface to the second surface, the depth of the groove is less than the thickness of the filling layer; in the direction perpendicular to the first surface to the second surface, the width of the groove is equal to the width of the second through hole and less than the width of the filling layer.

[0016] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising:

[0017] A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body further including a well region and a first region, the first region being configured as a first conductivity type and located on the first surface, and the well region being configured as a second conductivity type and located on a side of the first region away from the first surface; a gate trench being provided on the first surface, the gate trench extending from the first surface into the semiconductor body; a source trench being provided on the first surface, the source trench extending from the first surface into the semiconductor body; and the semiconductor body further including a first insulating layer, the first insulating layer being located on a bottom surface and sidewalls of the gate trench;

[0018] A trench gate is formed on a side of the first insulating layer away from the semiconductor body in the gate trench; the first insulating layer is used to insulate the semiconductor body and the trench gate;

[0019] forming a source trench structure including a filling layer in the source trench;

[0020] An interlayer insulating layer is formed on the first surface, the interlayer insulating layer covering the trench gate and the source trench structure; the interlayer insulating layer is provided with a first through hole and a second through hole; the first through hole is used to expose at least a portion of the first region; the second through hole is used to expose a portion of the filling layer;

[0021] A source electrode is formed on a side of the interlayer insulating layer away from the first surface; the source electrode contacts the first region through the first through hole and contacts the filling layer through the second through hole;

[0022] A drain electrode is formed on the second surface.

[0023] Optionally, providing a semiconductor body includes:

[0024] Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other;

[0025] A transition well region and a transition area are formed on the first surface; the transition area is set to a first conductivity type and is located on the first surface; the transition well region is set to a second conductivity type and is located on a side of the transition area away from the first surface;

[0026] forming a gate trench on the first surface, the gate trench extending from the first surface into the semiconductor body;

[0027] forming a source trench on the first surface, wherein the source trench extends from the first surface into the semiconductor body;

[0028] A second region is formed on the bottom surface and sidewall of the source trench; the second region is set to a second conductivity type; a transition region retained after forming the gate trench, the source trench, and the second region is used as the first region; and a transition well region retained after forming the gate trench, the source trench, and the second region is used as the well region;

[0029] A first insulating layer is formed on the bottom surface and sidewalls of the gate trench.

[0030] Optionally, forming a source trench structure including a filling layer in the source trench includes:

[0031] forming a second insulating layer on the bottom surface and sidewalls of the source trench;

[0032] A filling layer is formed on a side of the second insulating layer away from the semiconductor body.

[0033] Optionally, forming an interlayer insulating layer on the first surface includes:

[0034] forming a transition insulating layer on the first surface;

[0035] A first through hole and a second through hole are formed in the transition insulating layer; and the transition insulating layer retained after the first through hole and the second through hole are formed serves as an interlayer insulating layer.

[0036] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used to support the semiconductor device.

[0037] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0038] The power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0039] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0040] The technical solution of an embodiment of the present invention provides a dual-trench silicon carbide MOSFET device, in which an interlayer insulating layer is provided to cover the trench gate to achieve insulation isolation between the trench gate and the source; and an interlayer insulating layer is provided to cover the source trench structure. The interlayer insulating layer is provided with a first through-hole and a second through-hole; the first through-hole is used to expose at least a portion of the first region, and the source electrode forms an ohmic contact with the exposed portion of the first region through the first through-hole; the second through-hole is used to expose a portion of the filling layer, and the source electrode contacts the exposed portion of the filling layer through the second through-hole, so that the source electrode and the filling layer are at the same potential and gaps are avoided on the sidewalls of the source trench, thereby improving the reliability of the semiconductor device.

[0041] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0044] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0045] Figure 3-Figure 6is a cross-sectional view corresponding to each step of a method for manufacturing a semiconductor device provided in accordance with an embodiment of the present invention;

[0046] Figure 7 According to an embodiment of the present invention, Figure 2 A schematic diagram of the process included in S110;

[0047] Figures 8-12 According to an embodiment of the present invention, Figure 2 The cross-sectional views corresponding to the steps included in S110;

[0048] Figure 13 According to an embodiment of the present invention, Figure 2 A schematic diagram of the process included in S130;

[0049] Figure 14 According to an embodiment of the present invention, Figure 2 The cross-sectional views corresponding to the steps included in S130;

[0050] Figure 15 According to an embodiment of the present invention, Figure 2 Schematic diagram of the process included in S140. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] In order to improve the reliability of semiconductor devices, the embodiments of the present invention provide the following technical solutions:

[0054] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention, such as Figure 1 As shown, the semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 also includes a well region 103 and a first region 104, the first region 104 is set to a first conductivity type and is located on the first surface 101, and the well region 103 is set to a second conductivity type and is located on a side of the first region 104 away from the first surface 101; the first surface 101 is provided with a gate trench 105, and the gate trench 105 extends from the first surface 101 into the semiconductor body 100; the first surface 101 is also provided with a source trench 106, and the source trench 106 extends from the first surface 101 into the semiconductor body 100; the semiconductor body 100 also includes a first insulating layer 107, and the first insulating layer 107 is located on the bottom surface and sidewalls of the gate trench 105; a trench gate 108 is located in the gate trench 105, a first insulating layer 107 is located on a side away from the semiconductor body 100; the first insulating layer 107 is used to insulate the semiconductor body 100 and the trench gate 108; the source trench structure 200 includes a filling layer 201, and the filling layer 201 is located in the source trench 106; the interlayer insulating layer 300 is located on the first surface 101 and covers the trench gate 108 and the source trench structure 200; the interlayer insulating layer 300 is provided with a first through hole 301 and a second through hole 302; the first through hole 301 is used to expose at least a portion of the first region 104; the second through hole 302 is used to expose a portion of the filling layer 201; the source 400 is located on a side of the interlayer insulating layer 300 away from the first surface 101, contacts the first region 104 through the first through hole 301, and contacts the filling layer 201 through the second through hole 302; the drain 500 is located on the second surface 102.

[0055] In embodiments of the present invention, semiconductor devices include, but are not limited to, N-type MOSFETs or P-type MOSFETs. Semiconductor body 100 may be made of a third-generation wide-bandgap semiconductor material, such as a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. Silicon carbide MOSFET semiconductor devices offer the advantages of high withstand voltage, low on-resistance, and high frequency, further improving semiconductor device performance.

[0056] For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type.

[0057] For example, for an N-type MOSFET, the first region 104 is an N+ doped region, where the N-type dopant ions may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, where the P-type dopant ions may be aluminum (Al) ions or boron (B) ions. The first region 104 can be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion, or vapor deposition.

[0058] like Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through a single epitaxial process, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0059] The first surface 101 of the semiconductor body 100 is provided with a gate trench 105 and a source trench 106. The semiconductor device of the embodiment of the present invention is a dual-trench silicon carbide MOSFET device. The gate trench 105 and the source trench 106 can both be formed by photolithography and etching processes. If the gate trench 105 and the source trench 106 have the same trench depth, they can be formed by a single photolithography and etching process. If the gate trench 105 and the source trench 106 have different trench depths, they require two photolithography and etching steps.

[0060] The semiconductor body 100 also includes a first insulating layer 107. The first insulating layer 107 can be formed by a thermal oxidation process. The first insulating layer 107 can be a gate oxide layer. The first insulating layer 107 is located on the bottom surface and sidewalls of the gate trench 105. The first insulating layer 107 is thicker on the bottom surface of the gate trench 105 and thinner on the sidewalls of the gate trench 105. Polysilicon is deposited on the side of the first insulating layer 107 in the gate trench 105 away from the semiconductor body 100 to form a trench gate 108. The first insulating layer 107 serves to insulate the semiconductor body 100 from the trench gate 108.

[0061] The source trench structure 200 includes a filling layer 201. The filling layer 201 can be formed by depositing doped polysilicon within the source trench 106. The interlayer insulating layer 300 can be made of silicon dioxide. The interlayer insulating layer 300 covers the trench gate 108 and isolates the trench gate 108 from the source 400. The interlayer insulating layer 300 also covers the source trench structure 200, protecting the sidewalls of the source trench 106 and preventing gaps therein, thereby improving the reliability of the semiconductor device.

[0062] The source electrode 400 can be formed by depositing metal on the first surface 101. The source electrode 400 forms an ohmic contact with the exposed portion of the first region 104 through the first through-hole 301. The source electrode 400 contacts the exposed portion of the filling layer 201 through the second through-hole 302, so that the source electrode 400 and the filling layer 201 are at the same potential.

[0063] The technical solution of an embodiment of the present invention provides a dual-trench silicon carbide MOSFET device, in which an interlayer insulating layer 300 is provided to cover the trench gate 108, thereby achieving insulation isolation between the trench gate 108 and the source 400; and an interlayer insulating layer 300 is provided to cover the source trench structure 200. The interlayer insulating layer 300 is provided with a first through-hole 301 and a second through-hole 302; the first through-hole 301 is used to expose at least a portion of the first region 104, and the source 400 forms an ohmic contact with the exposed portion of the first region 104 through the first through-hole 301; the second through-hole 302 is used to expose a portion of the filling layer 201, and the source 400 contacts the exposed portion of the filling layer 201 through the second through-hole 302, so that the source 400 and the filling layer 201 are at the same potential, and gaps are avoided on the sidewalls of the source trench 106, thereby improving the reliability of the semiconductor device.

[0064] In an optional embodiment of the present invention, reference Figure 1 The semiconductor body 100 further includes a second region 109 ; the second region 109 is configured to be of the second conductivity type and is located at the bottom and sidewalls of the source trench 106 .

[0065] In an embodiment of the present invention, for an N-type MOSFET, P+ ion implantation is performed at the bottom and sidewalls of the source trench 106 to form a second region 109. The second region 109 is a P+ doped region with a doping concentration greater than that of the well region 103. The first through hole 301 exposes a portion of the first region 104 and a portion of the second region 109, thereby forming a good ohmic contact with the source 400.

[0066] In an optional embodiment of the present invention, reference Figure 1 The source trench structure 200 further includes a second insulating layer 203 , which is located on the bottom surface and sidewalls of the source trench 106 .

[0067] In an embodiment of the present invention, the second insulating layer 203 can be formed by a thermal oxidation process. The second insulating layer 203 can be an oxide layer. The second insulating layer 203 is located on the bottom surface and sidewalls of the source trench 106. The second insulating layer 203 on the bottom surface of the source trench 106 is thicker, while the second insulating layer 203 on the sidewalls of the source trench 106 is thinner. Doped polysilicon is deposited on the side of the second insulating layer 203 in the source trench 106 away from the semiconductor body 100 to form a filling layer 201. The filling layer 201 and the second insulating layer 203 together constitute the source trench structure 200.

[0068] In an optional embodiment of the present invention, reference Figure 1 A groove 202 is provided on the side of the filling layer 201 away from the semiconductor body 100; in the direction X from the first surface 101 to the second surface 102, the depth of the groove 202 is less than the thickness of the filling layer 201; in the direction Y perpendicular to the first surface 101 and pointing to the second surface 102, the width of the groove 202 is equal to the width of the second through hole 302 and is less than the width of the filling layer 201.

[0069] In an embodiment of the present invention, a groove 202 is provided on a side of the filling layer 201 away from the semiconductor body 100. The groove 202 can be formed by photolithography and etching. The second through hole 302 is connected to the groove 202, so that the retained interlayer insulating layer 300 can cover the source trench structure 200 to protect the side wall of the source trench 106 and avoid the appearance of a gap on the side wall of the source trench 106, and can also ensure that the source 400 and the filling layer 201 are at the same potential.

[0070] The depth of the groove 202 is set to be smaller than the thickness of the filling layer 201, and the second through hole 302 is connected to the groove 202 in the direction Y perpendicular to the first surface 101 and pointing to the second surface 102, and in the direction Y perpendicular to the first surface 101 and pointing to the second surface 102, the width of the groove 202 and the width of the second through hole 302 are both smaller than the width of the filling layer 201, ensuring that the retained interlayer insulating layer 300 covers the source trench structure 200 to protect the side walls of the source trench 106, avoid the appearance of gaps on the side walls of the source trench 106, and ensure that the source 400 and the filling layer 201 are at the same potential, thereby improving the reliability of the semiconductor device.

[0071] refer to Figure 1 , the semiconductor device also includes a passivation layer 600 and a polyimide layer 700. The passivation layer 600 is arranged on the side of the source 400 away from the semiconductor body 100. The material of the passivation layer 600 can be silicon nitride. The passivation layer 600 is used to prevent the semiconductor device from being corroded, oxidized or affected by other external factors, thereby improving the corrosion resistance and stability of the semiconductor device. The polyimide layer 700 covers the passivation layer 600. The polyimide layer 700 can be a thin film or coating made of polyimide material. The polyimide layer 700 has high temperature resistance, radiation resistance, electrical insulation properties and good mechanical properties. Providing a polyimide layer 700 can improve the performance of the semiconductor device.

[0072] Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, the method for manufacturing the semiconductor device includes:

[0073] S110. Provide a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other; the semiconductor body also includes a well region and a first region, the first region is set to a first conductive type and is located on the first surface, and the well region is set to a second conductive type and is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body; a source trench is also provided on the first surface, and the source trench extends from the first surface into the semiconductor body; the semiconductor body also includes a first insulating layer, and the first insulating layer is located on the bottom surface and sidewalls of the gate trench.

[0074] refer to Figure 3 The semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 also includes a well region 103 and a first region 104, the first region 104 is set to the first conductivity type and is located on the first surface 101, and the well region 103 is set to the second conductivity type and is located on the side of the first region 104 away from the first surface 101; the first surface 101 is provided with a gate trench 105, and the gate trench 105 extends from the first surface 101 into the semiconductor body 100; the first surface 101 is also provided with a source trench 106, and the source trench 106 extends from the first surface 101 into the semiconductor body 100; the semiconductor body 100 also includes a first insulating layer 107, and the first insulating layer 107 is located on the bottom surface and sidewall of the gate trench 105.

[0075] A gate trench 105 and a source trench 106 are formed on the first surface 101 through photolithography and etching processes. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. For an N-type MOSFET, the first region 104 is an N+ doped region, where the N-type dopant ions may be phosphorus (P) or nitrogen (N) ions; the well region 103 is a P-well region, where the P-type dopant ions may be aluminum (Al) or boron (B) ions. The first region 104 can be formed on the first surface 101 of the semiconductor body 100 through processes such as ion implantation, ion diffusion, or vapor deposition. The semiconductor body 100 also includes a first insulating layer 107. This first insulating layer 107 can be formed through a thermal oxidation process. The first insulating layer 107 may be a gate oxide layer. The first insulating layer 107 is located on the bottom surface and sidewalls of the gate trench 105 . The first insulating layer 107 on the bottom surface of the gate trench 105 is thicker, and the first insulating layer 107 on the sidewalls of the gate trench 105 is thinner.

[0076] like Figure 3As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through a single epitaxial process, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0077] Optional, reference Figure 3 The semiconductor body 100 further includes a second region 109 ; the second region 109 is configured to be of the second conductivity type and is located at the bottom and sidewalls of the source trench 106 .

[0078] S120, forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench; the first insulating layer is used to insulate the semiconductor body and the trench gate.

[0079] refer to Figure 4 Polysilicon is deposited on the side of the first insulating layer 107 in the gate trench 105 away from the semiconductor body 100 to form a trench gate 108. The first insulating layer 107 is used to insulate the semiconductor body 100 from the trench gate 108.

[0080] S130 , forming a source trench structure including a filling layer in the source trench.

[0081] refer to Figure 5 , a source trench structure 200 including a filling layer 201 is formed in the source trench 106 ; the filling layer 201 can be formed by depositing doped polysilicon in the source trench 106 .

[0082] In an optional embodiment of the present invention, the groove 202 is formed on a side of the filling layer 201 away from the semiconductor body 100 by photolithography and etching.

[0083] Optionally, a second insulating layer 203 is formed on the bottom surface and sidewalls of the source trench 106 by a thermal oxidation process, and doped polysilicon is deposited on the side of the second insulating layer 203 in the source trench 106 away from the semiconductor body 100 to form a filling layer 201. The filling layer 201 and the second insulating layer 203 together constitute the source trench structure 200.

[0084] S140. An interlayer insulating layer is formed on the first surface, the interlayer insulating layer covering the trench gate and source trench structure; the interlayer insulating layer is provided with a first through hole and a second through hole; the first through hole is used to expose at least a portion of the first area; the second through hole is used to expose a portion of the filling layer.

[0085] refer to Figure 6An interlayer insulating layer 300 is formed on the first surface 101. The interlayer insulating layer 300 covers the trench gate 108 and the source trench structure 200. The interlayer insulating layer 300 is provided with a first through hole 301 and a second through hole 302. The first through hole 301 is used to expose at least a portion of the first region 104. The second through hole 302 is used to expose a portion of the filling layer 201. The material of the interlayer insulating layer 300 can be silicon dioxide.

[0086] In an optional embodiment of the present invention, reference Figure 6 The second through hole 302 is connected to the groove 202, which can not only allow the retained interlayer insulating layer 300 to cover the source trench structure 200 to protect the sidewalls of the source trench 106 and avoid gaps on the sidewalls of the source trench 106, but also ensure that the source 400 and the filling layer 201 are at the same potential, thereby improving the reliability of the semiconductor device.

[0087] S150 , forming a source electrode on a side of the interlayer insulating layer away from the first surface; the source electrode contacts the first region through the first through hole, and contacts the filling layer through the second through hole.

[0088] refer to Figure 1 A source electrode 400 is formed by depositing metal on a side of the interlayer insulating layer 300 away from the first surface 101 . The source electrode 400 contacts the first region 104 through the first through hole 301 and contacts the filling layer 201 through the second through hole 302 .

[0089] S160 , forming a drain on the second surface.

[0090] refer to Figure 1 , metal is deposited on one side of the second surface 102 of the semiconductor body 100 to form a drain 500 .

[0091] The technical solution of an embodiment of the present invention provides a method for manufacturing a semiconductor device for forming a dual-trench silicon carbide MOSFET device, wherein an interlayer insulating layer 300 is formed covering the trench gate 108 to achieve insulation isolation between the trench gate 108 and the source 400; and an interlayer insulating layer 300 is formed covering the source trench structure 200. The interlayer insulating layer 300 is provided with a first through-hole 301 and a second through-hole 302. The first through-hole 301 is used to expose at least a portion of the first region 104, and the source 400 forms an ohmic contact with the exposed portion of the first region 104 through the first through-hole 301. The second through-hole 302 is used to expose a portion of the filling layer 201, and the source 400 contacts the exposed portion of the filling layer 201 through the second through-hole 302. This ensures that the source 400 and the filling layer 201 are at the same potential, avoids the formation of gaps on the sidewalls of the source trench 106, and improves the reliability of the formed semiconductor device.

[0092] In an optional embodiment of the present invention, Figure 7 According to an embodiment of the present invention, Figure 2 The flow chart of S110 is shown in FIG. Figure 7 As shown, S110 provides a semiconductor body including:

[0093] S1101 , provide a semiconductor body, wherein the semiconductor body includes a first surface and a second surface arranged opposite to each other.

[0094] refer to Figure 8 The semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other. The semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 through a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0095] S1102, forming a transition well region and a transition region on the first surface; the transition region is set to a first conductivity type and is located on the first surface; the transition well region is set to a second conductivity type and is located on a side of the transition region away from the first surface.

[0096] refer to Figure 9 A transition well region 30 and a transition region 40 are formed on the first surface 101; the transition region 40 is configured as a first conductivity type and is located on the first surface 101; the transition well region 30 is configured as a second conductivity type and is located on a side of the transition region 40 away from the first surface 101. The transition region 40 can be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion, or vapor deposition. The transition well region 30 can be formed on a side of the transition region 40 away from the first surface 101 by processes such as ion implantation, ion diffusion, or vapor deposition. For example, for an N-type MOSFET, the transition well region 30 is a P-well region, and the transition region 40 is an N+ doped region.

[0097] S1103 , forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body.

[0098] refer to Figure 10 Through photolithography and etching processes, a gate trench 105 is formed on the first surface 101 , and the gate trench 105 extends from the first surface 101 into the semiconductor body 100 .

[0099] S1104 , forming a source trench on the first surface, wherein the source trench extends from the first surface into the semiconductor body.

[0100] refer to Figure 10Through photolithography and etching processes, a source trench 106 is formed on the first surface 101 , and the source trench 106 extends from the first surface 101 into the semiconductor body 100 .

[0101] S1105. Form a second region on the bottom surface and sidewall of the source trench; set the second region to a second conductive type; form the gate trench, the source trench, and the transition region retained after the second region is formed as the first region; and form the gate trench, the source trench, and the transition well region retained after the second region is formed as the well region.

[0102] refer to Figure 11 A second region 109 is formed on the bottom surface and sidewall of the source trench 106 by P+ ion implantation; the second region 109 is set to the second conductivity type; the transition region 40 retained after the gate trench 105, the source trench 106 and the second region 109 are formed is used as the first region 104; the transition well region 30 retained after the gate trench 105, the source trench 106 and the second region 109 are formed is used as the well region 103.

[0103] S1106 , forming a first insulating layer on the bottom surface and sidewalls of the gate trench.

[0104] refer to Figure 12 A first insulating layer 107 is formed on the bottom surface and sidewalls of the gate trench 105 by a thermal oxidation process. The first insulating layer 107 may be a gate oxide layer. The first insulating layer 107 on the bottom surface of the gate trench 105 is relatively thick, while the first insulating layer 107 on the sidewalls of the gate trench 105 is relatively thin.

[0105] In an optional embodiment of the present invention, Figure 13 According to an embodiment of the present invention, Figure 2 The flow chart of S130 is shown in FIG. Figure 13 As shown, S130 forming a source trench structure including a filling layer in the source trench includes:

[0106] S1301 , forming a second insulating layer on the bottom surface and sidewalls of the source trench.

[0107] refer to Figure 14 A second insulating layer 203 is formed on the bottom surface and sidewalls of the source trench 106 by a thermal oxidation process. Polysilicon is deposited on the side of the first insulating layer 107 away from the semiconductor body 100 in the gate trench 105 to form a trench gate 108.

[0108] S1302 , forming a filling layer on a side of the second insulating layer away from the semiconductor body.

[0109] refer to Figure 14Doped polysilicon is deposited on the side of the second insulating layer 203 away from the semiconductor body 100 to form a filling layer 201. The second insulating layer 203 and the filling layer 201 together constitute the source trench structure 200. A recess 202 is formed on the side of the filling layer 201 away from the semiconductor body 100 through photolithography and etching processes. It should be noted that the recess 202 can be formed through photolithography and etching processes after forming the filling layer 201, or it can be formed when forming the interlayer insulating layer and etching the through hole.

[0110] In an optional embodiment of the present invention, Figure 15 According to an embodiment of the present invention, Figure 2 The flow chart of S140 is shown in FIG. Figure 15 As shown, S140 forms an interlayer insulating layer on the first surface, including:

[0111] S1401, forming a transition insulating layer on the first surface.

[0112] refer to Figure 14 and Figure 6 After forming the trench gate 108 and the filling layer 201, a transition insulating layer is deposited on the first surface 101. The transition insulating layer can be silicon dioxide. After that, it is necessary to etch away part of the transition insulating layer, and the etching stops at the silicon carbide layer. In order to ensure that the etching is complete, a certain amount of overetching is required, which will cause the loss of the second insulating layer 203 and the filling layer 201 in the source trench 106. When the metal is subsequently filled, a gap will appear on the side wall of the source trench 106. Therefore, a part of the transition insulating layer is retained above the source trench 106, so that there is no gap on the side wall of the source trench 106, thereby improving the reliability of the semiconductor device.

[0113] S1402, forming a first through hole and a second through hole in the transition insulating layer; the transition insulating layer retained after forming the first through hole and the second through hole serves as an interlayer insulating layer.

[0114] refer to Figure 6 The first through hole 301 and the second through hole 302 are formed in the transition insulating layer by photolithography and etching processes; the transition insulating layer remaining after forming the first through hole 301 and the second through hole 302 serves as the interlayer insulating layer 300. The second through hole 302 is connected to the groove 202.

[0115] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not further elaborated herein.

[0116] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0117] Therefore, the power conversion circuit includes the beneficial effects of any semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0118] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0119] Therefore, the beneficial effects of the vehicle including any power conversion circuit package described in any embodiment of the present invention will not be repeated here.

[0120] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0121] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface, and the well region being configured as a second conductivity type and located on a side of the first region away from the first surface; a gate trench being provided on the first surface, the gate trench extending from the first surface into the semiconductor body; a source trench being provided on the first surface, the source trench extending from the first surface into the semiconductor body; the semiconductor body further comprising a first insulating layer, the first insulating layer being located on a bottom surface and sidewalls of the gate trench; a trench gate, located in the gate trench on a side of the first insulating layer away from the semiconductor body; The first insulating layer is used to insulate the semiconductor body and the trench gate; A source trench structure, comprising a filling layer, wherein the filling layer is located in the source trench; an interlayer insulating layer, located on the first surface and covering the trench gate and the source trench structure; The interlayer insulating layer is provided with a first through hole and a second through hole; the first through hole exposes at least a portion of the first area located on the first surface; the second through hole exposes a portion of the filling layer; a source electrode, located on a side of the interlayer insulating layer away from the first surface, contacting the first region through the first through-hole and contacting the filling layer through the second through-hole, such that the source electrode and the filling layer have the same potential; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The semiconductor body further includes a second region; the second region is configured to be of a second conductivity type and is located at the bottom and sidewalls of the source trench.

3. The semiconductor device according to claim 1, wherein The source trench structure further includes a second insulating layer, which is located on the bottom surface and sidewalls of the source trench.

4. The semiconductor device according to claim 1, wherein A groove is provided on the side of the filling layer away from the semiconductor body; in the direction from the first surface to the second surface, the depth of the groove is less than the thickness of the filling layer; in the direction perpendicular to the first surface pointing to the second surface, the width of the groove is equal to the width of the second through hole and less than the width of the filling layer.

5. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface, and the well region being configured as a second conductivity type and located on a side of the first region away from the first surface; a gate trench being provided on the first surface, the gate trench extending from the first surface into the semiconductor body; a source trench being provided on the first surface, the source trench extending from the first surface into the semiconductor body; the semiconductor body further comprising a first insulating layer, the first insulating layer being located on a bottom surface and sidewalls of the gate trench; forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench; The first insulating layer is used to insulate the semiconductor body and the trench gate; forming a source trench structure including a filling layer in the source trench; forming an interlayer insulating layer on the first surface, wherein the interlayer insulating layer covers the trench gate and the source trench structure; The interlayer insulating layer is provided with a first through hole and a second through hole; the first through hole is used to expose at least a portion of the first area located on the first surface; the second through hole is used to expose a portion of the filling layer; forming a source electrode on a side of the interlayer insulating layer away from the first surface; The source electrode contacts the first region through the first through-hole and contacts the filling layer through the second through-hole, so that the source electrode and the filling layer are at the same potential; A drain electrode is formed on the second surface.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The semiconductor body provided includes: Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; A transition well region and a transition area are formed on the first surface; the transition area is set to a first conductivity type and is located on the first surface; the transition well region is set to a second conductivity type and is located on a side of the transition area away from the first surface; forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body; forming a source trench on the first surface, wherein the source trench extends from the first surface into the semiconductor body; A second region is formed on the bottom surface and sidewall of the source trench; the second region is set to a second conductivity type; the transition region retained after forming the gate trench, the source trench, and the second region is used as the first region; the transition well region retained after forming the gate trench, the source trench, and the second region is used as the well region; A first insulating layer is formed on the bottom surface and sidewalls of the gate trench.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: A source trench structure including a filling layer is formed in the source trench, comprising: forming a second insulating layer on the bottom surface and sidewalls of the source trench; A filling layer is formed on a side of the second insulating layer away from the semiconductor body.

8. The method for manufacturing a semiconductor device according to claim 5, wherein: forming an interlayer insulating layer on the first surface, comprising: forming a transition insulating layer on the first surface; A first through hole and a second through hole are formed in the transition insulating layer; and the transition insulating layer remaining after forming the first through hole and the second through hole serves as an interlayer insulating layer.

9. A power module, characterized in that: The invention comprises a substrate and the semiconductor device according to any one of claims 1 to 4, wherein the substrate is used to support the semiconductor device.

10. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is electrically connected to the circuit board.

11. A vehicle, characterized in that: The invention comprises a load and a power conversion circuit as claimed in claim 10, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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