Semiconductor device, storage system and preparation method of semiconductor device
By adjusting the fin structure and gate settings of the fin field effect transistor, the problems of weakened gate control capabilities and serious leakage current are solved, and higher device reliability and electrical performance are achieved.
Patent Information
- Application Number
- CN202311844385.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-27
- Publication Date
- 2025-07-04
AI Technical Summary
As the semiconductor process accuracy reaches below 5nm, the gate width of the fin field effect transistor decreases, resulting in a weakening of the gate's control ability to the channel, serious leakage problems, affecting device reliability and electrical performance.
A semiconductor device is designed, by adjusting the structure of the fin, the side surface of the second sub-part is recessed relative to the side surface of the third sub-part and extending in the length direction of the fin, and combining with the appropriate gate oxide layer thickness design, the channel portion and the conductive portion are formed to optimize the arrangement of the gate electrode.
The gate control capability of the channel is improved, the leakage current is reduced, and the channel current is maintained fully formed, which improves the reliability and electrical performance of the device.
Smart Images
Figure CN120264808A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of semiconductor chips, and in particular, to a semiconductor device, a storage system, and a method for manufacturing a semiconductor device. Background Art
[0002] In advanced process technologies, fin field-effect transistors (FinFETs) are mostly used for transistors in storage circuits. However, as the process precision reaches below 5 nm, various defects have also emerged in fin field-effect transistors. For example, as the device is continuously miniaturized, the width of the gate in the fin field-effect transistor gradually decreases, resulting in a weakened control ability of the gate over the channel and an increasingly serious leakage problem of the device. Summary of the Invention
[0003] The embodiments of the present disclosure adopt the following technical solutions:
[0004] On the one hand, a semiconductor device is provided. The semiconductor device includes a substrate, a fin, a shallow trench isolation layer, and a gate.
[0005] Wherein, the fin is disposed on the surface of the substrate; the fin includes a first sub-part, a second sub-part, and a third sub-part that are sequentially connected in a direction away from the substrate; the side surface of the second sub-part is recessed relative to the side surface of the third sub-part; the side surface is a surface extending in the length direction of the fin. The shallow trench isolation layer is disposed on the surface of the substrate and surrounds the first sub-part. The gate is disposed on the side of the shallow trench isolation layer away from the substrate, and is disposed on the side surface of the second sub-part, the side surface of the third sub-part, and the surface of the third sub-part away from the substrate.
[0006] In some embodiments, the side surface of the second sub-part protrudes relative to the side surface of the first sub-part.
[0007] In some embodiments, the cross-section of the second sub-part perpendicular to the length direction of the fin and the cross-section of the third sub-part perpendicular to the length direction of the fin together form a circular arc, and from the end of the second sub-part close to the third sub-part to the end of the second sub-part close to the first sub-part, the chord length of the circular arc gradually decreases.
[0008] In some embodiments, the side surface of the second sub-part is recessed relative to the side surface of the first sub-part.
[0009] In some embodiments, the side surface of the third sub-part protrudes relative to the side surface of the first sub-part.
[0010] In some embodiments, the maximum dimension of the third sub-part in a second direction is less than or equal to the minimum dimension of the first sub-part in the second direction; the second direction is parallel to the substrate and intersects with the length direction of the fin.
[0011] In some embodiments, the minimum dimension of the second sub - portion in the second direction is 50 nm to 60 nm.
[0012] In some embodiments, the semiconductor device further includes a gate oxide layer disposed between the second sub - portion and the gate, and between the third sub - portion and the gate. The thickness of the portion of the gate oxide layer located on the second sub - portion is less than the thickness of the portion of the gate oxide layer located on the third sub - portion.
[0013] In some embodiments, the fin includes channel portions and conductive portions alternately arranged along the length - extending direction of the fin; both the channel portions and the conductive portions are disposed on the side of the first sub - portion away from the substrate, and the portions of the second sub - portion and the third sub - portion facing the gate serve as channel portions.
[0014] Wherein, the semiconductor device further includes a contact structure disposed at least on the side of the conductive portion away from the substrate.
[0015] On the other hand, a storage system is provided. The storage system includes a controller and a semiconductor device provided in any of the foregoing embodiments. The controller is coupled to the semiconductor device to control the semiconductor device to store data.
[0016] In yet another aspect, a method for manufacturing a semiconductor device is provided, the method including:
[0017] Forming a fin on the surface of the substrate; the fin includes a first sub - portion and a second initial portion connected in sequence along the direction away from the substrate. Forming a shallow trench isolation layer; the shallow trench isolation layer is disposed on the surface of the substrate and surrounds the first sub - portion. Changing the dimension of the second initial portion in the second direction to form a second sub - portion and a third sub - portion connected in sequence along the direction away from the substrate; the side surface of the second sub - portion is recessed relative to the side surface of the third sub - portion; the side surface is a surface extending in the length direction of the fin; the second direction is parallel to the substrate and intersects with the length direction of the fin. Forming a gate; the gate is disposed on the side of the shallow trench isolation layer away from the substrate and is disposed on the side surface of the second sub - portion, the side surface of the third sub - portion, and the surface of the third sub - portion away from the substrate.
[0018] In some embodiments, changing the dimension of the second initial portion in the second direction to form a second sub - portion and a third sub - portion connected in sequence along the direction away from the substrate includes:
[0019] Depositing a semiconductor material on the surface of the second initial portion to form the second sub - portion and the third sub - portion; the side surface of the second sub - portion protrudes relative to the side surface of the first sub - portion.
[0020] In some embodiments, changing the dimension of the second initial portion in the second direction to form a second sub - portion and a third sub - portion connected in sequence along the direction away from the substrate includes:
[0021] Form a gate oxide layer on the surface of the second initial portion; on the side surface of the second initial portion, along the direction away from the substrate, the thickness of the gate oxide layer gradually becomes thicker. Thin the gate oxide layer until the portion of the side surface of the second initial portion close to the first sub-portion is exposed. Etch the exposed side surface of the second initial portion to form a second sub-portion; the third sub-portion is the unexposed portion of the second initial portion; the side surface of the second sub-portion is recessed relative to the side surface of the first sub-portion.
[0022] In some embodiments, after etching the exposed side surface of the second initial portion to form a second sub-portion, it further includes:
[0023] Deposit a semiconductor material on the surface of the third sub-portion such that the side surface of the third sub-portion protrudes relative to the side surface of the first sub-portion. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings required for some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and do not limit the actual dimensions of the products involved in the embodiments of the present disclosure, the actual processes of the methods, etc.
[0025] Figure 1 It is a schematic structural diagram of a storage system according to some embodiments;
[0026] Figure 2 It is a schematic structural diagram of a semiconductor device according to some embodiments;
[0027] Figure 3 It is along Figure 2 The structural cross-sectional view taken along the section line A-A' in;
[0028] Figure 4 It is along Figure 2 A cross-sectional view of a structure taken along the section line B-B' in;
[0029] Figure 5 It is along Figure 2 Another cross-sectional view of the structure taken along the section line B-B' in;
[0030] Figure 6 It is along Figure 2 Another cross-sectional view of the structure taken along the section line B-B' in;
[0031] Figure 7 It is along Figure 2 The side view in the C direction in;
[0032] Figures 8 to 10 It is a flowchart of the preparation of a semiconductor device according to some embodiments;
[0033] Figures 11 to 20 These are cross-sectional views corresponding to the respective preparation steps of the semiconductor device. Specific embodiments
[0034] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.
[0035] In the description of the present disclosure, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present disclosure.
[0036] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to".
[0037] In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.
[0038] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.
[0039] In describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, in describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other. Also, for example, in describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.
[0040] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C" and includes the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.
[0041] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.
[0042] As used herein, "about", "substantially", or "approximately" includes the recited value and an average within an acceptable deviation range of the particular value, where the acceptable deviation range is determined by one of ordinary skill in the art in view of the measurement being discussed and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).
[0043] In the context of the present disclosure, the meanings of "on", "above", and "over" should be construed in the broadest manner such that "on" not only means "directly on something", but also includes "on something" with intervening features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also includes "above" or "over" something with no intervening features or layers therebetween (i.e., directly on something).
[0044] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations resulting from, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.
[0045] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself can be patterned. The materials added on the substrate can be patterned or can remain unpatterned. In addition, the substrate can include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials such as glass, plastic, or sapphire wafers.
[0046] The present disclosure provides an electronic device, which can be, for example, different types of user devices or terminal devices such as a mobile phone, a tablet, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a charging household small appliance (e.g., a soymilk maker, a floor sweeping robot), a drone, a radar, an aerospace device, a vehicle-mounted device, a vehicle, etc.; the electronic device can also be a network device such as a base station. The specific form of the electronic device is not particularly limited in the embodiments of the present application.
[0047] A storage system 1000 is provided in the electronic device (refer to Figure 1 ) to store relevant data in the electronic device.
[0048] Exemplarily, the electronic device may further include at least one of a central processing unit (CPU for short) and a cache.
[0049] Embodiments of the present disclosure also provide a storage system, Figure 1 which is a schematic structural diagram of a storage system 1000 provided in the embodiments of the present disclosure.
[0050] As Figure 1 shown, the storage system 1000 includes a semiconductor device 100 and a controller 200. The controller 200 is coupled to the semiconductor device 100 to control the semiconductor device 100 to store data.
[0051] The storage system 1000 can be applied to the above-mentioned electronic device. For example, it can be integrated or encapsulated in the electronic device. For example, it can be encapsulated in the electronic device through a universal flash storage (UFS for short) package or an embedded multi-media card (eMMC for short) package.
[0052] Alternatively, the storage system 1000 can also be integrated into a card-type memory. The card-type memory can include any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a three-dimensional memory, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, and a UFS.
[0053] Alternatively, the storage system 1000 can also be integrated into a Solid State Drive (SSD).
[0054] Exemplarily, the foregoing controller 200 can be configured to manage data stored in the semiconductor device 100 and communicate with an external device (such as a host).
[0055] Exemplarily, the controller 200 can also be configured to control the operation of the semiconductor device 100, such as controlling the semiconductor device 100 to perform read, erase, and programming operations.
[0056] Exemplarily, the controller 200 can also be configured to manage at least one of various functions regarding data stored in or to be stored in the semiconductor device 100, including bad block management, garbage collection, logical-to-physical address conversion, and wear leveling.
[0057] Exemplarily, the controller 200 can also be configured to process an error correction code for data read from or written to the semiconductor device 100.
[0058] Of course, the controller 200 can also perform any other suitable functions. For example, the controller 200 can format the semiconductor device 100. For example, the controller 200 can also communicate with an external device (such as a host) through at least one of various interface protocols.
[0059] It should be noted that the interface protocol can include at least one of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, and a Firewire protocol.
[0060] Exemplarily, the storage system 1000 can include one semiconductor device 100, or as Figure 1As shown, it includes a plurality of semiconductor devices 100.
[0061] The foregoing semiconductor device 100 may be a 3D memory. Alternatively, the foregoing semiconductor device 100 may be a part of a 3D memory, for example, it may be a Fin FET.
[0062] The "3D memory" may refer to a device formed by a string of memory cell transistors that are arranged in an array on the main surface of a substrate and extend in a direction perpendicular to the substrate.
[0063] In some embodiments, the foregoing semiconductor device 100 may also be applied in other systems. For example, an integrated circuit is provided in an embodiment of the present application, and the integrated circuit includes at least one such semiconductor device 100.
[0064] Among them, the integrated circuit may be a memory circuit, or may also be a logic circuit, an analog circuit, an input / output circuit, etc.
[0065] An embodiment of the present disclosure also provides a semiconductor device 100. Figure 2 It is a schematic structural diagram of the semiconductor device 100 provided by the embodiment of the present disclosure. Figure 3 It is along Figure 2 The cross-sectional view of the sectional line A-A' in Figure 4 It is along Figure 2 A cross-sectional view of the sectional line B-B' in
[0066] The semiconductor device 100 may be applied in the foregoing storage system 1000, or may also be applied as a separate device in other electronic devices. The specific application scenario thereof is not limited in the present disclosure.
[0067] In some embodiments, as shown in Figure 2 and Figure 3 the semiconductor device 100 includes a substrate 10, fins 20, a shallow trench isolation layer 30, and a gate 40.
[0068] Among them, by way of example, the material of the substrate 10 may include a semiconductor material. For example, it may be one of bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), and silicon germanium-on-insulator (SGOI).
[0069] The substrate 10 is used as a carrier for arranging structures such as fins 20, a shallow trench isolation layer 30, and a gate 40. The material of any carrier with a certain supporting force is within the protection scope of the embodiments of the present disclosure, and the material of the substrate 10 is not limited in the embodiments of the present disclosure.
[0070] Refer to Figure 2 、Figure 3 and Figure 4 , fin 20 is disposed on the surface of substrate 10. The fin 20 extends along the first direction X.
[0071] Wherein, the first direction X is parallel to the surface of the substrate 10 away from the fin 20, that is, the lower surface of the substrate 10 in the figure.
[0072] Exemplarily, referring to Figure 2 and Figure 4 , the semiconductor device 100 may include a plurality of fins 20, and the plurality of fins 20 may be arranged along the second direction Y.
[0073] Wherein, the second direction Y is parallel to the surface of the substrate 10 away from the fin 20 and intersects with the first direction X. For example, the second direction Y is perpendicular to the first direction X.
[0074] Exemplarily, one or more transistors T arranged in sequence along the first direction X may be formed on each fin 20. Figure 2 Only one transistor T formed on one fin 20 is taken as an example for illustration, and the number of transistors provided on each fin 20 is not limited.
[0075] Exemplarily, referring to Figure 3 , the fin 20 may include a channel portion 2A and a conductive portion 2B alternately arranged along the first direction X. Referring to Figure 3 , in one transistor T, two conductive portions 2B are respectively disposed on two opposite sides of the channel portion 2A along the first direction X.
[0076] Wherein, the channel portion 2A is the portion of the fin 20 covered by the gate 40, which is used to form a channel under the control of the gate 40, and the conductive portion 2B is used to form the source and drain of the transistor T in the semiconductor device 100.
[0077] For example, referring to Figure 3 , two conductive portions 2B respectively disposed on two sides of the channel portion 2A along the first direction X are respectively used as the source and drain of the transistor T in the semiconductor device 100. After a channel is formed in the channel portion 2A under the control of the gate 40, conduction between the two conductive portions 2B on both sides of the channel portion 2A (i.e., between the source and the drain) can be achieved, thereby turning on the transistor T.
[0078] Exemplarily, the doping type of the conductive portion 2B is different from that of the channel portion 2A.
[0079] Exemplarily, the doping concentration of the conductive portion 2B is greater than that of the channel portion 2A. The conductive portion 2B is highly doped, thereby improving the conductivity of the conductive portion 2B (i.e., the source and the drain).
[0080] Exemplarily, the conductive portion 2B can be integrally provided with the channel portion 2A, or the conductive portion 2B can be independently formed by using an epitaxial growth method and an etching process.
[0081] Exemplarily, by selecting the type of epitaxial material and doped atoms, the conductive portion 2B can be P-type doped or N-type doped.
[0082] Exemplarily, the material of the conductive portion 2B can be, for example, a germanium-silicon mixture.
[0083] Referring to Figure 3 and Figure 4 , the fin 20 includes a first sub-portion 21, a second sub-portion 22, and a third sub-portion 23 that are sequentially connected in a direction away from the substrate 10.
[0084] Exemplarily, referring to Figure 3 , the portions of the second sub-portion 22 and the third sub-portion 23 facing the gate 40 can serve as the aforementioned channel portion 2A. That is, the portion of the second sub-portion 22 covered by the gate 40 and the portion of the third sub-portion 23 covered by the gate 40 can jointly serve as the channel portion 2A.
[0085] Exemplarily, referring to Figure 3 , the portions of the second sub-portion 22 and the third sub-portion 23 not covered by the gate 40 can serve as the aforementioned conductive portion 2B.
[0086] For example, the portions of the second sub-portion 22 and the third sub-portion 23 not covered by the gate 40 can be highly doped to form the conductive portion 2B.
[0087] Exemplarily, the first sub-portion 21 can also be integrally provided with the substrate 10; that is, there may not be a physical interface between the first sub-portion 21 and the substrate 10. For example, by using an etching process to remove a part of the material of the substrate 10 from the upper surface of the substrate 10 to form a fin 20 with a preset shape on the substrate 10, in this case, the first sub-portion 21 of the fin 20 is integrally provided with the substrate 10.
[0088] Exemplarily, referring to Figure 3 , the aforementioned channel portion 2A and conductive portion 2B are provided on a side of the first sub-portion 21 away from the substrate 10.
[0089] Exemplarily, the doping concentration of the first sub-portion 21 can be different from the doping concentration of the conductive portion 2B. For example, the doping concentration of the first sub-portion 21 is less than the doping concentration of the conductive portion 2B.
[0090] Exemplarily, the doping concentration and doping type of the first sub - portion 21 and the channel portion 2A can be the same. In this case, the first sub - portion 21 can be integrally formed with the channel portion 2A, that is, there may not be a physical interface between the first sub - portion 21 and the channel portion 2A. For example, by an etching process, a part of the material of the substrate 10 is removed from the upper surface of the substrate 10 to form a fin 20 with a preset shape on the substrate 10. In this case, the part of the fin 20 surrounded by the shallow trench isolation layer 30 serves as the first sub - portion 21, and the part not surrounded by the shallow trench isolation layer 30 serves as the channel portion 2A, that is, the first sub - portion 21 and the channel portion 2A can be integrally formed in essence.
[0091] Refer to Figure 4 , the side surface of the second sub - portion 22 is recessed with respect to the side surface of the third sub - portion 23. That is, the maximum dimension of the second sub - portion 22 in the second direction Y is less than or equal to the maximum dimension of the third sub - portion 23 in the second direction Y. Or it can be understood that at least the dimension of the end of the second sub - portion 22 connected to the third sub - portion 23 in the second direction Y is less than or equal to the dimension of the end of the third sub - portion 23 connected to the second sub - portion 22 in the second direction Y.
[0092] It can be understood that the aforementioned "side surface" is the surface extending in the length extension direction of the fin 20 (i.e., the first direction X). For example, the "side surface" here refers to the two opposite side surfaces of the fin 20 along the second direction Y.
[0093] It should be noted that the "recess" here does not mean that the two opposite side surfaces of the second sub - portion 22 in the second direction Y can only be recessed towards the approaching direction. For example, refer to Figure 4 , the two opposite side surfaces of the second sub - portion 22 in the second direction Y can also be convex towards the separating direction, as long as it is ensured that the side surface of the second sub - portion 22 is closer to the inside of the fin 20 than the side surface of the third sub - portion 23. For example, refer to Figure 4 , the left - hand side surface of the second sub - portion 22 is closer to the right than the left - hand side surface of the third sub - portion 23. The present disclosure embodiment does not limit the outer shapes of the second sub - portion 22 and the third sub - portion 23.
[0094] Refer to Figure 2 and Figure 4 , the shallow trench isolation layer 30 is disposed on the surface of the substrate 10, and the shallow trench isolation layer 30 surrounds the first sub - portion 21.
[0095] That is, the shallow trench isolation layer 30 surrounds and is disposed at the end of the fin 20 close to the substrate 10 to achieve electrical insulation between adjacent two fins 20.
[0096] Exemplarily, the material of the shallow trench isolation layer 30 is an insulating material. For example, the material of the shallow trench isolation layer 30 may include binary or multi-component compounds composed of elements such as silicon (Si), carbon (C), nitrogen (N), oxygen (O), etc.
[0097] Refer to Figure 2 and Figure 4 , the gate 40 is disposed on a side of the shallow trench isolation layer 30 away from the substrate 10, and is disposed on the side surface of the second sub-part 22, the side surface of the third sub-part 23, and the surface of the third sub-part 23 away from the substrate 10.
[0098] The gate 40 is used to control the formation of a channel in the channel part 2A, so as to control the conduction between two conductive parts 2B located on both sides of the channel part 2A, or to control the non-formation of a channel in the channel part 2A, so that the two conductive parts 2B located on both sides of the channel part 2A are disconnected. That is, the gate 40 is used to control the opening and closing of the transistor T in the semiconductor device 100.
[0099] It can be understood that, refer to Figure 2 , the gate 40 is only disposed on a part of the side surface of the second sub-part 22, a part of the side surface of the third sub-part 23, and a part of the surface of the third sub-part 23 away from the substrate 10. That is, the gate 40 does not completely cover the second sub-part 22 and the third sub-part 23, and the gate 40 only covers the parts of the second sub-part 22 and the third sub-part 23 for forming a channel.
[0100] Exemplarily, the material of the gate 40 may include at least one of materials such as metal materials, polysilicon, and single crystal silicon.
[0101] With the rapid development of semiconductor technology, the integration degree of the semiconductor device 100 is getting higher and higher, resulting in an increasing aspect ratio of the fin 20 (the ratio of the dimension of the fin 20 in the third direction Z to the dimension of the fin 20 in the second direction Y). During the formation of the fin 20, the part of the fin 20 closer to the substrate 10 is more difficult to etch, resulting in the fin 20 having an upper-narrow and lower-wide shape in some embodiments (that is, the dimension of the part of the fin 20 closer to the substrate 10 in the second direction Y is larger). After the gate 40 is disposed on the fin 20, the gate control ability of the gate 40 gradually weakens along the direction closer to the substrate 10, which easily leads to a relatively serious leakage current in the semiconductor device 100 and affects the reliability of the semiconductor device 100.
[0102] By reducing the overall width of the fin 20 (i.e., the dimension in the second direction Y), the gate control ability of the gate 40 can be improved and the generation of leakage current can be reduced. However, after the overall width of the fin 20 is reduced, the cross-sectional area of the channel formed in the fin 20 (the cross-section of the fin 20 parallel to the second direction Y) decreases, resulting in an increase in channel resistance and a decrease in the passing current, seriously affecting the electrical performance of the semiconductor device 100.
[0103] In the semiconductor device 100 provided by the embodiments of the present disclosure, by setting the side surface of the second sub-portion 22 of the fin 20 to be recessed relative to the side surface of the third sub-portion 23 of the fin 20, it can be ensured that at least in the channel portion 2A, the size (e.g., average size) of the portion close to the substrate 10 in the second direction Y is smaller than the size (e.g., average size) of the portion away from the substrate 10 in the second direction Y. Thereby, the gate control ability of the gate 40 at the portion for forming the channel of the second sub-portion 22 is improved, and leakage current between the source and the drain at this position is avoided. At the same time, by keeping the size of the portion of the channel portion 2A away from the substrate 10 larger in the second direction Y, it can be ensured that the overall cross-sectional area (the area of the cross-section parallel to the second direction Y) of the channel portion 2A is not greatly affected, thereby ensuring the full formation of the channel current, taking into account the solution of the leakage current of the semiconductor device 100 and the full formation of the channel current, and improving the reliability of the semiconductor device 100.
[0104] In some embodiments, as Figure 4 shown, the side surface of the second sub-portion 22 protrudes relative to the side surface of the first sub-portion 21.
[0105] That is, the width (the size in the second direction Y) of the portion of the fin 20 provided on the side away from the substrate 10 of the shallow trench isolation layer 30 is increased, so that while the side surface of the second sub-portion 22 is recessed relative to the side surface of the third sub-portion 23, the width of the second sub-portion 22 is also made larger than the width of the first sub-portion 21. Thereby, the overall average width of at least the portion of the fin 20 for forming the channel portion 2A can be made larger than the width of the first sub-portion 21, thus reserving space for reducing the overall width of the fin 20. Even when the overall width of the fin 20 is reduced to improve the gate control ability, it is still ensured that the channel portion 2A (referring to the description above, composed of a portion of the second sub-portion 22 and a portion of the third sub-portion 23) has a larger cross-sectional area (the area of the cross-section parallel to the second direction Y), thereby further improving the reliability of the semiconductor device 100.
[0106] It should be noted that the "protrusion" here can be understood as that the average width (the size in the second direction Y) of the end portion of the second sub-portion 22 connected to the first sub-portion 21 is greater than or equal to the width of the end portion of the first sub-portion 21 connected to the second sub-portion 22. The embodiments of the present disclosure do not limit the shape of the second sub-portion 22.
[0107] Exemplarily, as Figure 4As shown, the cross-section of the second sub-part 22 perpendicular to the length direction of the fin 20 (the length direction refers to the first direction X) and the cross-section of the third sub-part 23 perpendicular to the length direction of the fin 20 can jointly form an arc shape, and from the end of the second sub-part 22 close to the third sub-part 23 to the end of the second sub-part 22 close to the first sub-part 21, the chord length of the arc shape gradually decreases.
[0108] That is, the width of the second sub-part 22 (the dimension in the second direction Y) is set to gradually decrease along the direction close to the substrate 10, so as to ensure that the side surface of the second sub-part 22 is recessed relative to the side surface of the third sub-part 23, so that the average width of at least the part of the channel portion 2A in the fin 20 close to the substrate 10 is smaller than the average width of the part of the channel portion 2A far from the substrate 10, thereby reducing the leakage current of the part of the channel portion 2A close to the substrate 10. At the same time, ensure the channel cross-sectional area of the entire channel portion 2A and optimize the reliability of the semiconductor device 100.
[0109] Exemplarily, as Figure 4 shown, the width of one end of the second sub-part 22 close to the substrate 10 is the same as the width of one end of the first sub-part 21 far from the substrate 10, and the side surface of the second sub-part 22 is arc-shaped, so that the second sub-part 22 can gradually protrude from the first sub-part 21 along the direction away from the substrate 10.
[0110] That is, referring to Figure 4 , the second sub-part 22 and the third sub-part 23 are round-headed, so that the average width of the part of the fin 20 on the side of the shallow trench isolation layer 30 far from the substrate 10 is greater than the width of the first sub-part 21, thereby reserving space for reducing the overall width of the fin 20 and avoiding the problem of reducing the channel cross-sectional area and thus reducing the electrical performance of the semiconductor device 100 after the overall width of the fin 20 is reduced.
[0111] Figure 5 And Figure 6 are other cross-sectional views along the section line B-B' in Figure 2 .
[0112] In some embodiments, as Figure 5 and Figure 6 shown, the side surface of the second sub-part 22 is recessed relative to the side surface of the first sub-part 21.
[0113] That is, referring to Figure 5 and Figure 6, the dimension of the second sub - portion 22 in the second direction Y is smaller than the dimension of the end portion of the first sub - portion 21 connected to the second sub - portion 22 in the second direction Y. Thus, the side surface of the second sub - portion 22 is recessed relative to the side surface of the third sub - portion 23. On the basis of reducing the leakage current at the position where the second sub - portion 22 is located, the dimension of the second sub - portion 22 in the second direction Y is further reduced, thereby further reducing the leakage current at the position where the second sub - portion 22 is located in the channel portion 2A and improving the electrical performance of the semiconductor device 100.
[0114] Exemplarily, refer to Figure 5 , the maximum dimension of the third sub - portion 23 in the second direction Y is less than or equal to the minimum dimension of the first sub - portion 21 in the second direction Y.
[0115] For example, the first sub - portion 21 and the third sub - portion 23 can be fabricated in the same etching process, so that the side surface of the first sub - portion 21 and the side surface of the third sub - portion 23 are substantially in the same plane. And due to the high aspect ratio of the fin 20, the width of the first sub - portion 21 is greater than the width of the third sub - portion 23.
[0116] In this embodiment, the third sub - portion 23 and the first sub - portion 21 are integrally formed, which reduces the manufacturing difficulty of the semiconductor device 100. At the same time, ensuring that the side surface of the second sub - portion 22 is recessed relative to the side surfaces of the first sub - portion 21 and the third sub - portion 23 can ensure that the width of the end of the channel portion 2A relatively close to the substrate 10 (i.e., the position where the second sub - portion 22 is located) is smaller, thereby reducing the leakage current at this position and improving the control ability of the gate 40 at this position, and improving the reliability of the semiconductor device 100.
[0117] Exemplarily, refer to Figure 6 , the side surface of the third sub - portion 23 protrudes relative to the side surface of the first sub - portion 21.
[0118] That is, by increasing the dimension of the third sub - portion 23 in the second direction Y, it is possible to ensure that the channel portion 2A still has a relatively large channel cross - sectional area after reducing the overall width of the fin 20 to improve the gate control ability, thereby ensuring the electrical performance of the semiconductor device 100.
[0119] In addition, in the case where the conductive portion 2B is formed by the portions of the second sub - portion 22 and the third sub - portion 23 not covered by the gate 40, setting the side surface of the third sub - portion 23 to protrude relative to the side surface of the first sub - portion 21 and increasing the dimension of the third sub - portion 23 in the second direction Y can increase the dimension of the portion of the conductive portion 2B far from the substrate 10 (formed by the third sub - portion 23) in the second direction Y, thereby increasing the area of the surface of the conductive portion 2B far from the substrate 10, which is convenient for the contact structure 60 (refer to Figure 7 ) to be deposited on the surface of the conductive portion 2B far from the substrate 10, and improving the stability of the electrical signal input of the conductive portion 2B.
[0120] Figure 7 A side view along the C direction in Figure 2 is shown.
[0121] For example, referring to Figure 7 , the semiconductor device 100 further includes a contact structure 60. The contact structure 60 is disposed at least on a side of the conductive portion 2B away from the substrate 10, so as to facilitate external connection of the conductive portion 2B.
[0122] By setting the third sub-portion 23 to have a larger size in the second direction Y, the contact area between the conductive portion 2B and the contact structure 60 can be increased, thereby improving the electrical connection performance between the conductive portion 2B and the contact structure 60, and further improving the reliability of the semiconductor device 100.
[0123] In some embodiments, referring to Figure 6 , the ratio of the maximum dimension d1 (i.e., the maximum thickness) of the second sub-portion 22 in the direction perpendicular to the substrate 10 to the maximum dimension d2 (i.e., the maximum thickness) of the third sub-portion 23 in the direction perpendicular to the substrate 10 is 0.5 to 2.
[0124] That is, the thickness of the portion of the channel portion 2A close to the substrate 10 occupies approximately one-third to two-thirds of the entire thickness of the channel portion 2A. For example, the ratio of the maximum dimension d1 of the second sub-portion 22 in the direction perpendicular to the substrate 10 to the maximum dimension d2 of the third sub-portion 23 in the direction perpendicular to the substrate 10 can be 0.5, 0.75, 1, 1.238, or 2.
[0125] By controlling the thickness of the second sub-portion 22 to occupy approximately one-third to two-thirds of the entire thickness of the channel portion 2A, the depression position of the fin 20 can be effectively restricted, avoiding the problem that the second sub-portion 22 is too short, resulting in fewer depression positions of the fin 20 and poor gate control ability of the gate 40 over the channel, and still having a leakage current problem. Also, it can avoid the problem that the second sub-portion 22 is too long, resulting in more depression positions and a decrease in the channel cross-sectional area (the cross-sectional area of the channel portion 2A parallel to the second direction Y), which affects the electrical performance of the semiconductor device 100, taking into account both good gate control ability and sufficient channel current of the semiconductor device 100.
[0126] In some embodiments, referring to Figure 6 , the minimum dimension d3 of the second sub-portion 22 in the second direction Y is 50 nm to 60 nm.
[0127] That is, after reducing the width of the second sub-portion 22, the minimum value of the width of the second sub-portion 22 can be 50 nm to 60 nm. For example, it can be 50 nm, 53.7 nm, 57.85 nm, or 60 nm.
[0128] By limiting the minimum width of the second sub - portion 22 within 50 nm to 60 nm, on the one hand, it can ensure that the width of the second sub - portion 22 is reduced to a degree that can improve the gate control ability. On the other hand, it can also avoid the problem that the excessive reduction of the second sub - portion 22 leads to the instability of the entire fin 20 structure, taking into account both the electrical performance and the structural stability of the semiconductor device 100.
[0129] In some embodiments, referring to Figures 2 to 7 , the semiconductor device 100 may further include a gate oxide layer 50.
[0130] Referring to Figures 2 to 7 , the gate oxide layer 50 is disposed between the second sub - portion 22 and the gate 40, and between the third sub - portion 23 and the gate 40, that is, the gate oxide layer 50 is disposed between the channel portion 2A and the gate 40 to achieve electrical insulation between the gate 40 and the channel portion 2A, thereby facilitating the control of the gate 40 over the channel (carriers) in the channel portion 2A.
[0131] Exemplarily, referring to Figure 5 , the thickness of the portion of the gate oxide layer 50 located on the second sub - portion 22 is less than the thickness of the portion of the gate oxide layer 50 located on the third sub - portion 23.
[0132] For example, the gate oxide layer 50 located on the second sub - portion 22 may be one layer, and the gate oxide layer 50 located on the third sub - portion 23 may be two layers.
[0133] This design is beneficial to the fabrication of the semiconductor device 100, which will be described in the subsequent fabrication method embodiments.
[0134] The embodiments of the present disclosure also provide a method for fabricating a semiconductor device 100. Figure 8 , Figure 9 and Figure 10 are some fabrication flowcharts of the semiconductor device 100 provided by the embodiments of the present disclosure, Figures 11 to 20 are the structural schematic diagrams corresponding to the respective fabrication steps of the semiconductor device 100 provided by the embodiments of the present disclosure.
[0135] In some embodiments, as Figure 8 shown, the fabrication method includes:
[0136] S1: Referring to Figure 11 , form a fin 20 on the surface of the substrate 10.
[0137] Referring to Figure 11 , the fin 20 includes a first sub - portion 21 and a second initial portion 22A connected in sequence along the direction away from the substrate 10.
[0138] It can be understood that in this step S1, the first sub - part 21 and the second initial part 22A are integrally arranged, and there is no physical interface between them. The distinction in naming here is only for more clearly explaining the preparation process and does not limit the two to have special designs.
[0139] S2: Refer to Figure 12 , and form a shallow trench isolation layer 30.
[0140] Refer to Figure 12 , the shallow trench isolation layer 30 is disposed on the surface of the substrate 10 and is arranged around the first sub - part 21.
[0141] It can be understood that, referring to Figure 12 , the first sub - part 21 is the part of the fin 20 surrounded by the shallow trench isolation layer 30, and the second initial part 22A is the part of the fin 20 not surrounded by the shallow trench isolation layer 30. The second initial part 22A is exposed above the shallow trench isolation layer 30, facilitating the subsequent formation of the channel part 2A and the conductive part 2B (or facilitating the formation of the second sub - part 22 and the third sub - part 23).
[0142] S3: Refer to Figure 13 、 Figures 15 to 17 、 Figure 19 , change the size of the second initial part 22A in the second direction Y to form a second sub - part 22 and a third sub - part 23 connected in sequence along the direction away from the substrate 10.
[0143] Refer to Figure 13 , in this step S3, the side surface of the second sub - part 22 is recessed relative to the side surface of the third sub - part 23. Here, the side surface is the surface extending in the length direction of the fin 20.
[0144] S4: Refer to Figure 14 、 Figure 18 and Figure 20 , and form a gate 40.
[0145] Refer to Figure 14 , the gate 40 is disposed on the side of the shallow trench isolation layer 30 away from the substrate 10, and is arranged on the side surface of the second sub - part 22, the side surface of the third sub - part 23, and the surface of the third sub - part 23 away from the substrate 10.
[0146] It can be understood that the beneficial effects that can be achieved by the preparation method of the semiconductor device provided in the above - mentioned embodiments of the present disclosure can refer to the beneficial effects brought by the design method of the semiconductor device in the above text, which will not be elaborated here.
[0147] The following will provide multiple embodiments to exemplarily illustrate the preparation method of the foregoing semiconductor device 100.
[0148] Embodiment 1:
[0149] Refer to Figure 9 , the manufacturing method includes:
[0150] S1: Refer to Figure 11 , and form fins 20 on the surface of substrate 10.
[0151] S2: Refer to Figure 12 , and form shallow trench isolation layer 30.
[0152] S31: Refer to Figure 13 , deposit semiconductor material on the surface of the second initial portion 22A to form a second sub-portion 22 and a third sub-portion 23.
[0153] Refer to Figure 13 , the side surface of the second sub-portion 22 protrudes relative to the side surface of the first sub-portion 21.
[0154] S4: Refer to Figure 14 , and form gate 40.
[0155] Exemplarily, refer to Figure 14 , before forming gate 40, it further includes: forming gate oxide layer 50.
[0156] In this embodiment, the change in the size of the second initial portion 22A in the second direction Y (i.e., step S3) is achieved through step S31.
[0157] In the first embodiment, by depositing semiconductor material on the surface of the second initial portion 22A, the widths of the formed second sub-portion 22 and third sub-portion 23 (i.e., the sizes in the second direction Y) are made larger, and the side surface of the second sub-portion 22 is recessed relative to the side surface of the third sub-portion 23.
[0158] It should be noted that "depositing semiconductor material on the surface of the second initial portion 22A" does not limit this step to the deposition process, and other processes that can lay semiconductor material on the surface of the second initial portion 22A to thicken the second initial portion 22A from all directions are within the protection scope of this application.
[0159] For example, the second initial portion 22A can be thickened to form the second sub-portion 22 and the third sub-portion 23 by using an epitaxial growth process.
[0160] For example, during the epitaxial growth process, the morphology of the fins 20 can be adjusted by controlling various parameters of the transported gas (such as gas flow rate, temperature, air pressure, or transport duration, etc.), so as to achieve the purpose that the side surface of the second sub-portion 22 is recessed relative to the side surface of the third sub-portion 23.
[0161] For example, parameters such as the flow rate, temperature, or time of hydrogen transported to the surface of the fins 20 during the epitaxial growth process can be controlled.
[0162] For example, along the direction away from the substrate 10, the flow rate of the gas delivered to the surface of the second initial portion 22A is first small, then gradually increases, and then gradually decreases, so as to change the width of the second initial portion 22A (the dimension in the second direction Y) from small to large and then to small, that is, to obtain Figure 13 the shape of the fin 20 shown in, and achieve the purpose that the side surface of the second sub-portion 22 is recessed relative to the side surface of the third sub-portion 23.
[0163] On the one hand, in this manufacturing process, the overall width of the fin 20 (including the first sub-portion 21) can be reduced, thereby improving the gate control ability of the gate 40. Refer to Figure 14 , the average widths of the second sub-portion 22 and the third sub-portion 23 are greater than the width of the first sub-portion 21. Therefore, even when the overall width of the fin 20 is reduced, a sufficient channel cross-sectional area can still be ensured, taking into account the relatively high gate control ability and sufficient channel current of the semiconductor device 100. On the other hand, the side surface of the second sub-portion 22 formed by depositing semiconductor material is recessed relative to the side surface of the third sub-portion 23, so that the control ability of the gate 40 for the second sub-portion 22 can be made relatively equivalent to that of the third sub-portion 23, reducing the leakage current at the position of the second sub-portion 22. On the other hand, the width of the third sub-portion 23 is relatively large, so that the width of the conductive portion 2B formed by the portion of the third sub-portion 23 not covered by the gate 40 (refer to Figure 3 ) can be relatively large, facilitating the preparation of the contact structure 60 (refer to Figure 7 ) on the conductive portion 2B and realizing the external connection of the conductive portion 2B.
[0164] Example 2:
[0165] Refer to Figure 10 , this manufacturing method includes:
[0166] S1: Refer to Figure 11 , form a fin 20 on the surface of the substrate 10.
[0167] S2: Refer to Figure 12 , form a shallow trench isolation layer 30.
[0168] S32: Refer to Figure 15 , form a gate oxide layer 50 on the surface of the second initial portion 22A.
[0169] Refer to Figure 15 , on the side surface of the second initial portion 22A, along the direction away from the substrate 10, the thickness of the gate oxide layer 50 gradually becomes thicker.
[0170] Exemplarily, the step of forming the gate oxide layer 50 may include: depositing an insulating material on the shallow trench isolation layer 30 and etching the insulating material in the direction towards the substrate 10. During the etching process, the position where the fin 20 is located is covered by a mask plate, so that after etching the insulating material, a gate oxide layer 50 can be retained on the fin 20.
[0171] It can be understood that, referring to Figure 15 , limited by the relatively high aspect ratio of the fin 20, the fin 20 has a shape that is narrower at the top and wider at the bottom. Therefore, after the gate oxide layer 50 is formed, the closer to the substrate 10, the thinner the gate oxide layer 50 is.
[0172] S33: Referring to Figure 16 , the gate oxide layer 50 is thinned until a portion of the side surface of the second initial portion 22A close to the first sub-portion 21 is exposed.
[0173] It can be understood that since the closer to the substrate 10, the thinner the gate oxide layer 50 is, during the process of thinning the gate oxide layer 50, the portion of the gate oxide layer 50 close to the substrate 10 is removed first, so that a portion of the side surface of the second initial portion 22A close to the first sub-portion 21 can be exposed.
[0174] S34: Referring to Figure 17 , the exposed side surface of the second initial portion 22A is etched to form the second sub-portion 22.
[0175] In the second embodiment, referring to Figure 17 , the third sub-portion 23 is the unexposed portion of the second initial portion 22A, that is, the portion of the second initial portion 22A not covered by the gate oxide layer 50.
[0176] Referring to Figure 17 , through step S34, not only can the side surface of the second sub-portion 22 be recessed relative to the side surface of the third sub-portion 23, but also the side surface of the second sub-portion 22 can be retracted relative to the side surface of the first sub-portion 21.
[0177] S4: Referring to Figure 18 , the gate 40 is formed.
[0178] Exemplarily, referring to Figure 18 , before step S4, it may further include: forming another layer of the gate oxide layer 50 again, and the gate oxide layer 50 covers the side surface of the second sub-portion 22 and the surface of the aforementioned gate oxide layer 50, so that the side surface of the second sub-portion 22 has a layer of the gate oxide layer 50, and the surface of the third sub-portion 23 has two layers of the gate oxide layer 50.
[0179] In this embodiment, the change in the size of the second initial portion 22A in the second direction Y (i.e., step S3) is achieved through steps S32 to S34.
[0180] In the second embodiment, the second sub - portion 22 is etched by utilizing the feature that the fin 20 is narrower at the top and wider at the bottom, such that the width of the formed second sub - portion 22 (the dimension in the second direction Y) is smaller than the width of the third sub - portion 23, thereby reducing the leakage current at the position where the second sub - portion 22 is located and improving the electrical performance of the semiconductor device 100.
[0181] The manufacturing process provided in the second embodiment can achieve the reduction of the width of the second sub - portion 22 through simple process design, effectively reducing the leakage current in the semiconductor device 100 and improving the gate control ability of the gate 40.
[0182] Embodiment Three:
[0183] Based on the foregoing second embodiment, this third embodiment adds step S35.
[0184] Refer to Figure 10 , this step S35 is carried out before step S4 and after step S34 of the second embodiment.
[0185] S35: Deposit a semiconductor material on the surface of the third sub - portion 23, such that the side surface of the third sub - portion 23 protrudes relative to the side surface of the first sub - portion 21.
[0186] That is, in this third embodiment, not only is the width of the second sub - portion 22 etched such that the side surface of the second sub - portion 22 is recessed relative to the side surfaces of the first sub - portion 21 and the third sub - portion 23, but also the width of the third sub - portion 23 is increased. Therefore, the generation of leakage current in the semiconductor device 100 is further reduced, and it can also ensure that the surface area of the conductive portion 2B formed by the third sub - portion 23 away from the substrate 10 is larger, which is beneficial to the preparation of the contact structure 60 (refer to Figure 7 ) on the conductive portion 2B and improves the external connection effect of the conductive portion 2B.
[0187] It can be understood that other necessary steps in this third embodiment can refer to the descriptions in the foregoing embodiments and will not be elaborated here.
[0188] The above - mentioned are only the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claimed rights.
Claims
1. A semiconductor device, characterized in that, Comprising: A substrate; Fins disposed on the surface of the substrate; the fins include a first sub - portion, a second sub - portion, and a third sub - portion sequentially connected in a direction away from the substrate; the side surface of the second sub - portion is recessed relative to the side surface of the third sub - portion; the side surface is a surface extending in the length direction of the fin. A shallow trench isolation layer disposed on the surface of the substrate and surrounding the first sub - portion. A gate disposed on the side of the shallow trench isolation layer away from the substrate and disposed on the side surface of the second sub - portion, the side surface of the third sub - portion, and the surface of the third sub - portion away from the substrate.
2. The semiconductor device according to claim 1, wherein The side surface of the second sub - portion protrudes relative to the side surface of the first sub - portion.
3. The semiconductor device according to claim 2, wherein, The cross - section of the second sub - portion perpendicular to the length direction of the fin and the cross - section of the third sub - portion perpendicular to the length direction of the fin together form an arc shape, and from the end of the second sub - portion close to the third sub - portion to the end of the second sub - portion close to the first sub - portion, the chord length of the arc shape gradually decreases.
4. The semiconductor device according to claim 1, characterized in that, The side surface of the second sub - portion is recessed relative to the side surface of the first sub - portion.
5. The semiconductor device according to claim 4, characterized in that, The side surface of the third sub - portion protrudes relative to the side surface of the first sub - portion.
6. The semiconductor device according to claim 4, wherein, The maximum dimension of the third sub - portion in a second direction is less than or equal to the minimum dimension of the first sub - portion in the second direction; the second direction is parallel to the substrate and intersects with the length direction of the fin.
7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The minimum dimension of the second sub - portion in the second direction is 50 nm - 60 nm.
8. The semiconductor device according to any one of claims 4 to 6, characterized in that, Further comprising: A gate oxide layer disposed between the second sub - portion and the gate, and between the third sub - portion and the gate; the thickness of the part of the gate oxide layer on the second sub - portion is less than the thickness of the part of the gate oxide layer on the third sub - portion.
9. The semiconductor device according to any one of claims 1 to 6, characterized in that, The fins include channel portions and conductive portions alternately arranged along the length extension direction of the fins; both the channel portions and the conductive portions are disposed on the side of the first sub - portion away from the substrate, and the portions of the second sub - portion and the third sub - portion facing the gate serve as the channel portions. The semiconductor device further comprises: A contact structure disposed at least on the side of the conductive portion away from the substrate.
10. A storage system, characterized in that, Comprising: The semiconductor device according to any one of claims 1 - 9; A controller coupled to the semiconductor device to control the semiconductor device to store data.
11. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming fins on the surface of a substrate; the fins include a first sub - portion and a second initial portion sequentially connected in a direction away from the substrate. Forming a shallow trench isolation layer. The shallow trench isolation layer is disposed on the surface of the substrate and surrounds the first sub - portion. Changing the dimension of the second initial portion in a second direction to form a second sub - portion and a third sub - portion sequentially connected in a direction away from the substrate; the side surface of the second sub - portion is recessed relative to the side surface of the third sub - portion; the side surface is a surface extending in the length direction of the fin; the second direction is parallel to the substrate and intersects with the length direction of the fin. Form a gate; the gate is disposed on a side of the shallow trench isolation layer away from the substrate, and is disposed on a side surface of the second sub - portion, a side surface of the third sub - portion, and a surface of the third sub - portion away from the substrate.
12. The preparation method according to claim 11, characterized in that, Changing the dimension of the second initial portion in the second direction to form a second sub - portion and a third sub - portion connected in sequence along a direction away from the substrate includes: Depositing a semiconductor material on the surface of the second initial portion to form the second sub - portion and the third sub - portion; a side surface of the second sub - portion protrudes relative to a side surface of the first sub - portion.
13. The preparation method according to claim 11, characterized in that, Changing the dimension of the second initial portion in the second direction to form a second sub - portion and a third sub - portion connected in sequence along a direction away from the substrate includes: Forming a gate oxide layer on the surface of the second initial portion; on a side surface of the second initial portion, along a direction away from the substrate, the thickness of the gate oxide layer gradually becomes thicker. Thinning the gate oxide layer until a portion of the side surface of the second initial portion close to the first sub - portion is exposed. Etching the exposed side surface of the second initial portion to form the second sub - portion; the third sub - portion is the unexposed portion of the second initial portion; a side surface of the second sub - portion is recessed relative to a side surface of the first sub - portion.
14. The preparation method according to claim 13, wherein, After etching the exposed side surface of the second initial portion to form the second sub - portion, it further includes: Depositing a semiconductor material on the surface of the third sub - portion such that a side surface of the third sub - portion protrudes relative to a side surface of the first sub - portion.