Ring gate transistor and manufacturing method thereof

Abstract

The invention discloses a gate-all-around transistor and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for improving the forming quality of a source region and a drain region in the gate-all-around transistor. The gate-all-around transistor comprises a semiconductor substrate, an active structure, a gate stack structure, a gate side wall and a semiconductor liner layer. The active structure is disposed on the semiconductor substrate. The active structure comprises a source region, a drain region and at least one layer of nano structure located between the source region and the drain region. And two ends of each layer of nano structure are electrically connected with the source region and the drain region respectively. The gate stack structure is arranged on the semiconductor substrate and surrounds the periphery of each layer of nano structure. The grid side walls stretch across the at least one layer of nano structure and are located on the two sides of the grid stacking structure in the length direction. The semiconductor liner layer is arranged between the gate stack structure and the source region and between the gate stack structure and the drain region, and is arranged between each layer of nano structure and the source region and between each layer of nano structure and the drain region. The conductivity type of the semiconductor liner layer is the same as the conductivity type of the source region and the drain region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a gate-all-around transistor and a manufacturing method thereof. Background Art

[0002] The gate stack structure included in the gate-all-around transistor is formed not only on the top and side walls of at least one layer of nanostructure, but also on the bottom of at least one layer of nanostructure. Therefore, compared with planar transistors and fin field-effect transistors, the gate-all-around transistor has advantages such as higher gate control ability. Based on this, when the transistors included in a semiconductor device adopt gate-all-around transistors, the working performance of the semiconductor device can be improved. Additionally, during actual application, inner sidewalls can be provided between the gate stack structure and the source region, and between the gate stack structure and the drain region to prevent the etchant for etching the sacrificial layer from damaging the source region and the drain region during the process of releasing at least one layer of nanostructure, which is beneficial for controlling the length of the gate stack structure.

[0003] However, there are many defects in the source region and the drain region of the gate-all-around transistor formed by the existing manufacturing method, which is not conducive to improving the working performance of the gate-all-around transistor. Summary of the Invention

[0004] The purpose of the present invention is to provide a gate-all-around transistor and a manufacturing method thereof, which are used to improve the formation quality of the source region and the drain region in the gate-all-around transistor, reduce the number of defects in the source region and the drain region, facilitate the source region and the drain region to provide effective stress for the nanostructure, and are beneficial for improving the yield and working performance of the gate-all-around transistor.

[0005] To achieve the above purpose, in a first aspect, the present invention provides a gate-all-around transistor, which includes: a semiconductor substrate, an active structure, a gate stack structure, gate sidewalls, and a semiconductor liner layer. The active structure is disposed on the semiconductor substrate. The active structure includes a source region, a drain region, and at least one layer of nanostructure located between the source region and the drain region. Both ends of each layer of nanostructure are electrically connected to the source region and the drain region respectively. The gate stack structure is disposed on the semiconductor substrate and surrounds the outer periphery of each layer of nanostructure. The gate sidewalls span across the at least one layer of nanostructure and are located on both sides of the gate stack structure along the length direction. The semiconductor liner layer is disposed between the gate stack structure and the source region and the drain region respectively, and between each layer of nanostructure and the source region and the drain region respectively. The conductivity type of the semiconductor liner layer is the same as that of the source region and the drain region.

[0006] In the case of adopting the above technical solution, in the gate-all-around transistor provided by the present invention, the part of the semiconductor liner layer disposed between the gate stack structure and the source region and the drain region respectively can not only limit the length of the gate stack structure, but also prevent the etchant for etching the sacrificial layer from affecting the source region and the drain region during the process of releasing the nanostructure, thereby improving the yield of the gate-all-around transistor.

[0007] In addition, a semiconductor buffer layer is also disposed between each layer of nanostructure and the source region and the drain region respectively. At this time, both the source region and the drain region are separated from the nanostructure and the gate stack structure through the semiconductor buffer layer respectively. Moreover, the material of the semiconductor buffer layer is a semiconductor material. Therefore, after the semiconductor buffer layer is formed, at least the semiconductor buffer layer (or the semiconductor buffer layer and the semiconductor substrate) can be used as a seed layer to form the source region and the drain region, thereby solving the problem that the inner sidewall made of an insulating material in the prior art limits the gate length, resulting in the inability to use the sacrificial layer covered by the inner sidewall as a seed layer when forming the source region and the drain region subsequently, and thus there are a large number of defects in the source region and the drain region. This improves the formation quality of the source region and the drain region, which is conducive to effectively providing stress to the channel layer used to manufacture the nanostructure through the source region and the drain region, thereby facilitating the improvement of the carrier mobility in the nanostructure and enhancing the working performance of the gate-all-around transistor. Secondly, along the thickness direction of the semiconductor substrate, the semiconductor buffer layer with conductive characteristics is located below the corresponding layer of nanostructure and is electrically connected to the adjacent layer of nanostructure. In this case, when the gate-all-around transistor is in the working state, the channel portion (the part of the nanostructure surrounded by the gate stack structure) included in each layer of nanostructure can not only be conducted with the source region and the drain region respectively through the connection portion (the part of the nanostructure located below the gate sidewall), but also be conducted with the source region and the drain region respectively through the connection portion and the semiconductor buffer layer, improving the driving performance of the gate-all-around transistor.

[0008] Furthermore, a semiconductor buffer layer is also disposed between each layer of nanostructure and the source region and the drain region respectively. At this time, after forming the semiconductor buffer material that entirely covers both sides of the remaining channel layer and the remaining sacrificial layer used to manufacture the nanostructure by using processes such as epitaxy, the semiconductor buffer layer can be obtained without using the part of the semiconductor buffer material that covers both sides of the remaining channel layer, thereby simplifying the manufacturing process of the gate-all-around transistor and improving the manufacturing efficiency of the gate-all-around transistor.

[0009] In one example, the material of the semiconductor buffer layer is the same as that of at least one layer of nanostructure.

[0010] In one example, the material of at least one layer of nanostructure includes Si 1-x Ge x , and the material of the semiconductor buffer layer includes Si 1-y Ge y ; where x is greater than or equal to 0 and less than or equal to 1; y is greater than or equal to 0 and less than or equal to 1; the absolute value of the difference between x and y is less than or equal to 15%.

[0011] In one example, the semiconductor buffer layer located between the gate stack structure and the source region, and between each layer of nanostructures and the source region, is integrally continuous with the source region; and / or, the semiconductor buffer layer located between the gate stack structure and the drain region, and between each layer of nanostructures and the drain region, is integrally continuous with the drain region.

[0012] In one example, the doping concentration of the semiconductor buffer layer is less than or equal to the doping concentrations of the source region and the drain region.

[0013] In one example, the doping concentration of the semiconductor buffer layer is greater than or equal to 5E18 cm -3 and less than or equal to 1E20 cm -3 .

[0014] In one example, along the length direction of the gate stack structure, the sidewalls of the semiconductor buffer layer located between the gate stack structure and the source region and the drain region respectively are flush with the sidewalls of the nanostructures; or, along the length direction of the gate stack structure, the sidewalls of the semiconductor buffer layer located between the gate stack structure and the source region and the drain region respectively are recessed inward relative to the sidewalls of the nanostructures.

[0015] In one example, along the length direction of the gate stack structure, the thickness of the semiconductor buffer layer located between the gate stack structure and the source region and the drain region respectively is greater than or equal to 1 nm and less than or equal to 8 nm.

[0016] In a second aspect, the present invention provides a method for manufacturing a gate-all-around transistor. The method for manufacturing the gate-all-around transistor includes: First, providing a semiconductor substrate. Next, forming an active structure, gate sidewalls, and a semiconductor buffer layer on the semiconductor substrate; the active structure includes a source region, a drain region, and at least one layer of nanostructures located between the source region and the drain region; both ends of each layer of nanostructures are electrically connected to the source region and the drain region respectively; the gate sidewalls straddle at least one layer of nanostructures. Next, forming a gate stack structure surrounding the outer periphery of each layer of nanostructures on the semiconductor substrate; the gate sidewalls are located on both sides of the gate stack structure along the length direction; the semiconductor buffer layer is disposed between the gate stack structure and the source region and the drain region respectively, and between each layer of nanostructures and the source region and the drain region respectively; the conductivity type of the semiconductor buffer layer is the same as the conductivity types of the source region and the drain region.

[0017] In one example, forming an active structure, gate sidewalls, and a semiconductor liner layer on a semiconductor substrate includes: forming a fin structure on the semiconductor substrate and a mask structure spanning the fin structure; along the thickness direction of the semiconductor substrate, the fin structure includes sacrificial layers and channel layers alternately stacked; among the alternately stacked sacrificial layers and channel layers, the bottommost layer is a sacrificial layer; the mask structure includes a sacrificial gate and gate sidewalls located on both sides of the sacrificial gate along the length direction. Next, selectively remove the portions of the fin structure exposed outside the mask structure. Next, remove the two side edge portions of each remaining sacrificial layer along the length direction. Next, along the length direction of the sacrificial gate, form a semiconductor liner layer covering both sides of the remaining fin structure; the material of the semiconductor liner layer is different from that of the sacrificial layer. Next, form source and drain regions on the semiconductor substrate.

[0018] In one example, an in-situ doped epitaxial process is used to form the semiconductor liner layer.

[0019] In one example, an in-situ epitaxial process is used to form source and / or drain regions on the side of the semiconductor liner layer facing away from the remaining fin structure.

[0020] For the beneficial effects of the second aspect and its various implementation manners in the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present invention and form a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0022] Figure 1 A longitudinal cross-sectional schematic view of a partial structure of a gate-all-around transistor provided for the related art;

[0023] Figure 2 A schematic structural view of a gate-all-around transistor during manufacturing provided by an embodiment of the present invention Figure 1 ;

[0024] Figure 3 A schematic structural view of a gate-all-around transistor during manufacturing provided by an embodiment of the present invention Figure 2 ;

[0025] Figure 4 A schematic structural view of a gate-all-around transistor during manufacturing provided by an embodiment of the present invention Figure 3 ;

[0026] Figure 5 A schematic structural view of a gate-all-around transistor during manufacturing provided by an embodiment of the present invention Figure 4 ;

[0027] Figure 6 Schematic diagram of the structure of the gate-all-around transistor provided by the embodiment of the present invention during the manufacturing process Figure 5 ;

[0028] Figure 7 Schematic diagram of the structure of the gate-all-around transistor provided by the embodiment of the present invention during the manufacturing process Figure 6 ;

[0029] Figure 8 Schematic diagram of the structure of the gate-all-around transistor provided by the embodiment of the present invention during the manufacturing process Figure 7 ;

[0030] Figure 9 Schematic diagram of the structure of the gate-all-around transistor provided by the embodiment of the present invention during the manufacturing process Figure 8 ;

[0031] Figure 10 Schematic diagram of the structure of the gate-all-around transistor provided by the embodiment of the present invention during the manufacturing process Figure 9 ;

[0032] Figure 11 Schematic diagram of the structure of the gate-all-around transistor provided by the embodiment of the present invention during the manufacturing process Figure 10 ;

[0033] Figure 12 Schematic diagram of the structure of the gate-all-around transistor provided by the embodiment of the present invention during the manufacturing process Figure 10 One;

[0034] Figure 13 Schematic diagram of the structure of the gate-all-around transistor provided by the embodiment of the present invention during the manufacturing process Figure 10 Two;

[0035] Figure 14 Schematic diagram of the structure of the gate-all-around transistor provided by the embodiment of the present invention during the manufacturing process Figure 10 Three;

[0036] Figure 15 Schematic diagram of the structure of the gate-all-around transistor provided by the embodiment of the present invention during the manufacturing process Figure 10 Four;

[0037] Figure 16 Schematic diagram of the structure of the gate-all-around transistor provided by the embodiment of the present invention during the manufacturing process Figure 10 Five;

[0038] Figure 17 Schematic diagram of the structure of the gate-all-around transistor provided by the embodiment of the present invention during the manufacturing process Figure 10 Six.

[0039] Reference numerals: 11 is a semiconductor substrate, 12 is a source region, 13 is a drain region, 14 is a nanostructure, 15 is a gate stack structure, 16 is a gate sidewall, 17 is a semiconductor liner layer, 18 is a shallow trench isolation structure, 19 is an interlayer dielectric layer, 20 is a fin structure, 21 is a mask structure, 22 is a sacrificial layer, 23 is a channel layer, 24 is a sacrificial gate, and 25 is an inner sidewall. Detailed implementation manners

[0040] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0041] Schematic diagrams of various structures according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, where some details are enlarged for clearer expression, and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0042] In the context of the present invention, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component. To make the technical problems, technical solutions, and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely used to explain the present invention and are not used to limit the present invention.

[0043] Furthermore, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0044] In the description of the present invention, it should be noted that, unless otherwise clearly defined and limited, the terms "mounted", "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0045] The gate stack structure included in the gate-all-around transistor is formed not only on the top and sidewalls of at least one layer of nanostructures, but also on the bottom of at least one layer of nanostructures. Therefore, compared with planar transistors and fin field-effect transistors, the gate-all-around transistor has advantages such as higher gate control ability. Based on this, when the transistors included in a semiconductor device adopt gate-all-around transistors, the working performance of the semiconductor device can be improved.

[0046] In addition, during the actual application process, inner sidewalls can be provided between the gate stack structure and the source region, and between the gate stack structure and the drain region, to prevent the etchant for etching the sacrificial layer from damaging the source region and the drain region during the process of releasing at least one layer of nanostructures, which is beneficial to controlling the length of the gate stack structure.

[0047] However, there are many defects in the source region and the drain region of the gate-all-around transistor formed by the existing manufacturing methods, which is not conducive to improving the working performance of the gate-all-around transistor. Specifically, the above-mentioned inner sidewalls are usually made of insulating materials such as silicon nitride or silicon oxynitride. At this time, as Figure 1 shown, during the process of forming the source region 12 and the drain region 13 by using an epitaxial process, only the remaining part of the channel layer 23 (or only the remaining part of the channel layer 23 and the semiconductor substrate 11) can be used as the seed layer, and due to the existence of the inner sidewall 25, the remaining part of the sacrificial layer 22 cannot be used as the seed layer, resulting in a large number of defects in the formed source region 12 and drain region 13, making it difficult for the source region 12 and the drain region 13 to provide stress to the remaining part of the channel layer 23 (this part is used to manufacture at least one layer of nanostructures 14), and further not being conducive to improving the carrier mobility in at least one layer of nanostructures 14, resulting in poor working performance of the gate-all-around transistor.

[0048] To solve the above technical problems, an embodiment of the present invention provides a gate-all-around transistor and a manufacturing method thereof. Among them, the gate-all-around transistor provided in the embodiment of the present invention includes a semiconductor buffer layer disposed between the gate stack structure and the source region and the drain region respectively, and between each layer of nanostructure and the source region and the drain region respectively. Moreover, the conductivity type of the semiconductor buffer layer is the same as that of the source region and the drain region, so as to improve the formation quality of the source region and the drain region in the gate-all-around transistor, reduce the number of defects in the source region and the drain region, facilitate the source region and the drain region to provide effective stress for the nanostructure, and facilitate improving the yield and working performance of the gate-all-around transistor.

[0049] In a first aspect, an embodiment of the present invention provides a gate-all-around transistor. As Figure 16 shown, the gate-all-around transistor includes: a semiconductor substrate 11, an active structure, a gate stack structure 15, gate sidewalls 16, and a semiconductor buffer layer 17. The active structure is disposed on the semiconductor substrate 11. The active structure includes a source region 12, a drain region 13, and at least one layer of nanostructure 14 located between the source region 12 and the drain region 13. Both ends of each layer of nanostructure 14 are electrically connected to the source region 12 and the drain region 13 respectively. The gate stack structure 15 is disposed on the semiconductor substrate 11 and surrounds the outer periphery of each layer of nanostructure 14. The gate sidewalls 16 straddle the at least one layer of nanostructure 14 and are located on both sides of the gate stack structure 15 along the length direction. The semiconductor buffer layer 17 is disposed between the gate stack structure 15 and the source region 12 and the drain region respectively, and between each layer of nanostructure 14 and the source region 12 and the drain region respectively. The conductivity type of the semiconductor buffer layer 17 is the same as that of the source region 12 and the drain region 13.

[0050] In the case of adopting the above technical solution, as Figure 16 shown, in the gate-all-around transistor provided in the embodiment of the present invention, the part of the semiconductor buffer layer 17 disposed between the gate stack structure 15 and the source region 12 and the drain region respectively can not only limit the length of the gate stack structure 15, but also prevent the etchant for etching the sacrificial layer 22 from affecting the source region 12 and the drain region during the process of releasing the nanostructure 14, thereby improving the yield of the gate-all-around transistor. In addition, as Figure 16 shown, the semiconductor buffer layer 17 is also disposed between each layer of nanostructure 14 and the source region 12 and the drain region respectively. At this time, both the source region 12 and the drain region 13 are separated from the nanostructure 14 and the gate stack structure 15 through the semiconductor buffer layer 17 respectively. Moreover, the material of the semiconductor buffer layer 17 is a semiconductor material. Therefore, after the semiconductor buffer layer 17 is formed, as Figures 2 to 16As shown, at least the semiconductor cushion layer 17 (or the semiconductor cushion layer 17 and the semiconductor substrate 11) can be used as a seed layer to form the source region 12 and the drain region 13, thereby solving the problem that in the prior art, the inner sidewall made of an insulating material limits the gate length, resulting in the inability to use the sacrificial layer 22 covered by the inner sidewall as a seed layer when forming the source region 12 and the drain region 13 subsequently, leading to a large number of defects in the source region 12 and the drain region 13, improving the formation quality of the source region 12 and the drain region 13, facilitating the effective provision of stress from the source region 12 and the drain region 13 into the channel layer 23 for manufacturing the nanostructure 14, and thus facilitating the improvement of the carrier mobility in the nanostructure 14 and enhancing the working performance of the gate-all-around transistor. Secondly, along the thickness direction of the semiconductor substrate 11, the semiconductor cushion layer 17 with conductive characteristics is located below the corresponding layer of the nanostructure 14 and is electrically connected to the adjacent layer of the nanostructure 14. In this case, when the gate-all-around transistor is in the working state, the channel portion (the portion of the nanostructure 14 surrounded by the gate stack structure 15) included in each layer of the nanostructure 14 can not only be conducted with the source region 12 and the drain region 13 respectively through the connection portion (the portion of the nanostructure 14 located below the gate sidewall 16), but also be conducted with the source region 12 and the drain region 13 respectively through the connection portion and the semiconductor cushion layer 17, improving the driving performance of the gate-all-around transistor. Furthermore, the semiconductor cushion layer 17 is also disposed between each layer of the nanostructure 14 and the source region 12 and the drain region 13 respectively. At this time, after forming the semiconductor cushion material covering both sides of the remaining channel layer 23 and the remaining sacrificial layer 22 for manufacturing the nanostructure 14 as a whole layer by means of epitaxy and other processes, the semiconductor cushion layer 17 can be obtained without covering the portions on both sides of the remaining channel layer 23 with the semiconductor cushion material, thereby simplifying the manufacturing process of the gate-all-around transistor and improving the manufacturing efficiency of the gate-all-around transistor.

[0051] In the actual application process, the above-mentioned semiconductor substrate can be a semiconductor substrate such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a silicon-on-insulator substrate on which no structure is formed.

[0052] Exemplarily, the above-mentioned semiconductor substrate can also be a semiconductor substrate on which some structures are formed. For example: in the case of applying the gate-all-around transistor provided in the embodiment of the present invention to the gate-all-around transistor in the second layer or higher layer in an integrated circuit, the above-mentioned semiconductor substrate can include a semiconductor substrate, a lower-layer device formed on the semiconductor substrate, and an interlayer dielectric layer for isolating the lower-layer device, etc.

[0053] For an active structure, in terms of materials, the source region, drain region, and at least one layer of nanostructured material included in the active structure are all semiconductor materials. Among them, the materials of the source region and drain region can be the same as or different from the material of the nanostructure. The materials of the source region, drain region, and nanostructure can be determined according to the conduction type of the gate-all-around transistor and actual requirements, and no specific limitations are made here. For example: when the gate-all-around transistor is an N-type gate-all-around transistor, the material of the nanostructure can be silicon, and the materials of the source region and drain region can be silicon or germanium silicide with a low germanium content, so as to provide tensile stress to the nanostructure and facilitate further improving the carrier mobility in the nanostructure included in the N-type gate-all-around transistor. Another example: when the gate-all-around transistor is a P-type gate-all-around transistor, the material of the nanostructure can be germanium silicide or germanium, and the materials of the source region and drain region can be germanium or germanium silicide with a high germanium content, so as to provide compressive stress to the nanostructure and facilitate further improving the carrier mobility in the nanostructure included in the P-type gate-all-around transistor.

[0054] In terms of structure, the active structure can include only one layer of nanostructure. Or, as Figure 16 shown, the active structure can also include at least two layers of nanostructures 14 spaced apart along the thickness direction of the semiconductor substrate 11. In addition, the nanostructure 14 can be a nanowire with a small width or a nanosheet with a large width. The embodiments of the present invention do not make specific limitations on the number of layers and morphology of the nanostructures 14 included in the active structure.

[0055] In addition, it should be noted that, as Figure 16 shown, it can be defined that each layer of nanostructure 14 includes an integrally continuous channel portion and a connection portion. Among them, there is no obvious physical demarcation line between the channel portion and the connection portion of each layer of nanostructure 14. The regional division of the channel portion and the connection portion included in each layer of nanostructure 14 is determined according to the gate stack structure 15. The portion of the gate stack structure 15 surrounding each layer of nanostructure 14 is the channel portion of the nanostructure 14, and the portion of each layer of nanostructure 14 outside the gate stack structure 15 is the connection portion of the nanostructure 14.

[0056] For the gate stack structure, as Figure 16 shown, the gate stack structure 15 can include a gate dielectric layer and a gate electrode located on the gate dielectric layer. Among them, the gate dielectric layer surrounds the outer periphery of the channel portion of each layer of nanostructure 14 and is formed on the part of the semiconductor substrate 11 corresponding to the gate electrode formation region. Specifically, the material of the gate dielectric layer can be an insulating material such as HfO2, ZrO2, TiO2, or Al2O3. The material of the above-mentioned gate electrode can be a conductive material such as TiN, TaN, or TiSiN.

[0057] For the gate sidewall, as Figure 16As shown, the gate sidewall 16 can be located only on both sides of the gate stack structure 15 along the length direction. Alternatively, the gate sidewall 16 can also surround the outer sidewall of the gate stack structure 15. The material of the gate sidewall 16 can include any one of insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0058] For the semiconductor buffer layer, in terms of material, the material of the semiconductor buffer layer can be any semiconductor material different from the sacrificial layer, as long as it can be applied to the gate-all-around transistor provided in the embodiments of the present invention.

[0059] Exemplarily, as Figure 16 shown, the material of the semiconductor buffer layer 17 can be the same as that of at least one layer of nanostructure 14. In this case, there is no lattice difference between the semiconductor buffer layer 17 and the nanostructure 14, which is beneficial to reducing the limitation of the epitaxial critical thickness of the semiconductor buffer layer 17, and is beneficial to the semiconductor buffer layer 17 having a relatively large thickness, so that the semiconductor buffer layer 17 has a high corrosion resistance to the etchant for etching the sacrificial layer, ensuring that the etchant for etching the sacrificial layer will not affect the source region 12 and the drain region 13. In addition, it is also beneficial to improve the formation quality of the semiconductor buffer layer 17, improve its own conductivity, and further improve the driving performance of the gate-all-around transistor.

[0060] As for the specific material of the semiconductor buffer layer, it can be set according to actual needs. Exemplarily, the material of at least one layer of nanostructure can include Si 1-x Ge x , and the material of the semiconductor buffer layer can include Si 1-y Ge y ; where x is greater than or equal to 0 and less than or equal to 1; y is greater than or equal to 0 and less than or equal to 1; the absolute value of the difference between x and y is less than or equal to 15%.

[0061] For example: when the material of at least one layer of nanostructure includes Si 0.9 Ge 0.1 , the material of the semiconductor buffer layer can include Si 0.95 Ge 0.05 , Si 0.96 Ge 0.04 , Si 0.97 Ge 0.03 or Si 0.98 Ge 0.02 etc.

[0062] In terms of doping, the doping concentration of the semiconductor buffer layer can be set according to actual needs, and no specific limitation is made here. Specifically, the doping concentration of the semiconductor buffer layer can be less than or equal to the doping concentrations of the source region and the drain region.

[0063] Exemplarily, the doping concentration of the semiconductor cushion layer can be greater than or equal to 5E18 cm -3 and less than or equal to 1E20 cm -3 . For example: the doping concentration of the semiconductor cushion layer can be 5E18 cm -3 , 6E18 cm -3 , 7E18 cm -3 , 8E18 cm -3 , 1E19 cm -3 , 3E19 cm -3 , 5E19 cm -3 , 8E19 cm -3 or 1E20 cm -3 etc.

[0064] Of course, the doping concentration of the semiconductor cushion layer can also be greater than the doping concentrations of the source region and the drain region.

[0065] In terms of the formation thickness, as Figure 16 shown, along the length direction of the gate stack structure 15, the sidewalls of the semiconductor cushion layer 17 located between the gate stack structure 15 and the source region 12 and the drain region 13 respectively can be flush with the sidewalls of the nanostructure 14. Or, as Figure 17 shown, along the length direction of the gate stack structure 15, the sidewalls of the semiconductor cushion layer 17 located between the gate stack structure 15 and the source region 12 and the drain region 13 respectively can also be recessed inward relative to the sidewalls of the nanostructure 14. To ensure that the source region 12 and the drain region 13 have a relatively large formation range, which is conducive to the source region 12 and the drain region 13 being able to provide sufficient stress to the nanostructure 14, further improving the driving performance of the gate-all-around transistor.

[0066] As for the specific thickness of the semiconductor cushion layer, it can be determined according to the thicknesses of the semiconductor cushion layer and the sacrificial layer, as well as the type of the etchant for etching the sacrificial layer in the actual manufacturing process, and no specific limitation is made here.

[0067] Exemplarily, along the length direction of the gate stack structure, the thickness of the semiconductor cushion layer located between the gate stack structure and the source region and the drain region respectively is greater than or equal to 1 nm and less than or equal to 8 nm.

[0068] In addition, along the length direction of the gate stack structure, the thicknesses of the various parts of the semiconductor cushion layer can be the same or different. Among them, when the thicknesses of the various parts of the semiconductor cushion layer are different, the thickness of the semiconductor cushion layer located between the nanostructure and the source region and the drain region respectively can be less than the thickness of the semiconductor cushion layer located between the gate stack structure and the source region and the drain region respectively, so as to further improve the driving performance of the gate-all-around transistor.

[0069] In one example, as Figure 12As shown, the semiconductor buffer layer 17 located between the gate stack structure and the source region 12, and between each layer of nanostructures 14 and the source region 12, may be integrally continuous with the source region 12; and / or, the semiconductor buffer layer 17 located between the gate stack structure and the drain region 13, and between each layer of nanostructures 14 and the drain region 13, may be integrally continuous with the drain region 13. In this case, the manufacturing process of the gate-all-around transistor can be further simplified, and the manufacturing efficiency of the gate-all-around transistor can be improved.

[0070] Of course, as Figure 16 and Figure 17 shown, the semiconductor buffer layer 17 located between the gate stack structure 15 and the source region 12, and between each layer of nanostructures 14 and the source region 12, may also be non-integrally continuous with the source region 12 (the materials of the two may also be different); and / or, the semiconductor buffer layer 17 located between the gate stack structure 15 and the drain region 13, and between each layer of nanostructures 14 and the drain region 13, may also be non-integrally continuous with the drain region 13 (the materials of the two may also be different), so as to meet the usage requirements in different application scenarios.

[0071] In some cases, as Figure 7 、 Figure 16 and Figure 17 shown, the gate-all-around transistor provided by the embodiment of the present invention may further include at least one of a shallow trench isolation structure 18 and an interlayer dielectric layer 19. Among them, the shallow trench isolation structure 18 is formed on the semiconductor substrate 11, and is used to define the active region of the semiconductor substrate 11, reduce the leakage risk, and further improve the yield and working performance of the gate-all-around transistor. The above-mentioned interlayer dielectric layer 19 covers the semiconductor substrate 11, and the top of the interlayer dielectric layer 19 is flush with the top of the gate stack structure 15, so as to protect the source region 12 and the drain region 13 from the etching and cleaning operations for removing the sacrificial gate 24 and the sacrificial layer 22, and improve the yield of the gate-all-around transistor.

[0072] As for the materials of the shallow trench isolation structure and the interlayer dielectric layer, it may include any insulating material such as silicon oxide, silicon oxynitride or silicon nitride oxide, and specific limitations are not made here.

[0073] In a second aspect, an embodiment of the present invention provides a method for manufacturing a gate-all-around transistor. The manufacturing process will be described below according to Figures 2 to 17 the perspective view or cross-sectional view of the operations shown. Specifically, the method for manufacturing the gate-all-around transistor includes the following steps:

[0074] First, a semiconductor substrate is provided. The type of the semiconductor substrate may refer to the foregoing, and will not be elaborated here.

[0075] Next, as Figures 2 to 12As shown, an active structure, a gate sidewall 16, and a semiconductor buffer layer 17 are formed on a semiconductor substrate 11; the active structure includes a source region 12, a drain region 13, and at least one layer of nanostructure 14 located between the source region 12 and the drain region 13; both ends of each layer of nanostructure 14 are electrically connected to the source region 12 and the drain region 13 respectively; the gate sidewall 16 straddles at least one layer of nanostructure 14.

[0076] Among them, for the specific structure of the above active structure, the materials of the active structure, the gate sidewall, and the semiconductor buffer layer, as well as information such as the thickness and doping of the semiconductor buffer layer, reference can be made to the previous text and will not be elaborated here.

[0077] Exemplarily, forming the active structure, the gate sidewall, and the semiconductor buffer layer on the semiconductor substrate may include the steps:

[0078] As Figures 2 to 6 shown, a fin structure 20 and a mask structure 21 straddling the fin structure 20 are formed on the semiconductor substrate 11; along the thickness direction of the semiconductor substrate 11, the fin structure 20 includes sacrificial layers 22 and channel layers 23 that are alternately stacked; among the alternately stacked sacrificial layers 22 and channel layers 23, the bottommost layer is the sacrificial layer 22; the mask structure 21 includes a sacrificial gate 24 and gate sidewalls 16 located on both sides of the sacrificial gate 24 along the length direction.

[0079] Specifically, the channel layers included in the above fin structure are used to fabricate the nanostructures included in the active structure. Therefore, the number of channel layers included in the fin structure is equal to the number of nanostructures included in the active structure, and the material of the channel layers is the same as the material of the nanostructures included in the active structure.

[0080] Regarding the sacrificial layer, the channel part included in the nanostructure will be released by removing part of the sacrificial layer later. Therefore, the thickness of the sacrificial layer can be determined according to the spacing between different layers of nanostructures in the active structure and the spacing between the nanostructures and the semiconductor substrate in the actual application scenario. Regarding the material of the sacrificial layer, the material of the sacrificial layer can be any semiconductor material different from the semiconductor buffer layer and the channel layer.

[0081] Exemplarily, the material of at least one layer of channel layer may include Si 1-x Ge x , the material of the semiconductor buffer layer may include Si 1-y Ge y , the material of the sacrificial layer may include Si 1-z Ge z ; where x is greater than or equal to 0 and less than or equal to 1; y is greater than or equal to 0 and less than or equal to 1; z is greater than or equal to 0 and less than or equal to 1; the absolute value of the difference between x and y is less than or equal to 15%; the absolute value of the difference between z and x and y respectively is greater than or equal to 20%.

[0082] In addition, in the sacrificial layer and the channel layer arranged alternately in a stacked manner, the film layer at the bottom layer is the sacrificial layer. The film layer at the top layer can be the sacrificial layer or the channel layer.

[0083] Regarding the above-mentioned mask structure, the material of the mask structure can be set according to actual needs, as long as it can play a mask protection role in the subsequent process.

[0084] Exemplarily, the mask structure may only include a sacrificial gate and gate sidewalls, and the gate sidewalls are located on both sides of the sacrificial gate along the length direction. The material of the sacrificial gate may include materials such as polysilicon that are easy to remove. The material of the gate sidewalls can refer to the previous text.

[0085] Alternatively, the above-mentioned mask structure may also include a gate oxide layer, a sacrificial gate located on the gate oxide layer, and gate sidewalls located on both sides of the sacrificial gate along the length direction. The material of the gate oxide layer may include materials such as silicon oxide.

[0086] In the actual manufacturing process, as Figure 2 shown, processes such as epitaxy can be used to form a sacrificial layer 22 and a channel layer 23 arranged alternately in a stacked manner along the thickness direction of the semiconductor substrate 11. Then, as Figure 3 shown, processes such as photolithography and etching are used to pattern the sacrificial layer 22 and the channel layer 23, as well as part of the semiconductor substrate 11, to form fins. Next, as Figure 4 shown, processes such as deposition and etching can be used to form a shallow trench isolation structure 18 for defining an active region between adjacent fins. The top height of the shallow trench isolation structure 18 is less than or equal to the bottom height of the sacrificial layer 22 at the bottom layer. Among them, the part of the fin exposed outside the shallow trench isolation structure 18 is a fin structure 20. Next, a deposition process can be used to form a mask material covering the semiconductor substrate 11. Then, as Figure 5 and Figure 6 shown, processes such as photolithography and etching are used to selectively etch the mask material to form the above-mentioned mask structure 21.

[0087] It should be noted that when the gate-all-around transistor does not include the above-mentioned shallow trench isolation structure, only the sacrificial layer and the channel layer can be patterned. And a fin structure can be directly obtained after the patterning process.

[0088] Next, as Figure 7 and Figure 8 shown, processes such as dry etching or wet etching can be used to selectively remove the part of the fin structure exposed outside the mask structure 21. At this time, the sidewalls of the remaining channel layer 23 and the sacrificial layer 22 are self-aligned with the sidewalls of the mask structure 21.

[0089] Next, asFigure 9 As shown, processes such as dry etching or wet etching can be used to remove the two side edge portions along the length direction of each remaining sacrificial layer 22. Specifically, along the length direction of the sacrificial gate 24, the length of the removed portion of the sacrificial layer 22 (i.e., the length of the formed notch) can be determined according to the thickness of the semiconductor substrate layer 17 and the length requirement for the gate stack structure 15, and no specific limitation is made here.

[0090] Next, as Figure 10 shown, along the length direction of the sacrificial gate 24, a semiconductor substrate layer 17 covering both sides of the remaining fin structure is formed; the material of the semiconductor substrate layer 17 is different from that of the sacrificial layer 22.

[0091] Among them, information such as the doping situation, material, and thickness of the semiconductor substrate layer can refer to the previous text. Specifically, in the actual manufacturing process, an in-situ doped epitaxial process can be used to form the semiconductor substrate layer to reduce the impact of the process of doping the semiconductor substrate layer on the nanostructure and further improve the yield of the gate-all-around transistor.

[0092] Next, as Figure 11 and Figure 12 shown, processes such as epitaxy can be used to form a source region 12 and a drain region 13 on the semiconductor substrate 11.

[0093] In the actual application process, an in-situ epitaxial process can be used to form a source region and / or a drain region on the side of the semiconductor substrate layer facing away from the remaining fin structure. Of course, other deposition or epitaxial equipment can also be used to additionally form a source region and / or a drain region. The specific manufacturing method of the source region and the drain region can be set according to the materials of the source region and the drain region, the material of the semiconductor substrate layer, and the actual requirements, and no specific limitation is made here.

[0094] Next, as Figure 13 shown, processes such as deposition and planarization can be used to form an interlayer dielectric layer 19 covering the semiconductor substrate 11. The top of this interlayer dielectric layer is flush with the top of the mask structure 21. The material of the interlayer dielectric layer 19 can refer to the previous text and will not be elaborated here.

[0095] Next, as Figure 13 and Figure 14 shown, processes such as dry etching or wet etching can be used to sequentially remove the sacrificial gate and the remaining sacrificial layer.

[0096] Next, as Figure 16 and Figure 17As shown, processes such as atomic layer deposition can be used to form a gate stack structure 15 surrounding the outer periphery of each layer of nanostructures 14 on the semiconductor substrate 11; the gate sidewalls 16 are located on both sides of the gate stack structure 15 along the length direction; the semiconductor liner layer 17 is disposed between the gate stack structure 15 and the source region 12 and the drain region 13 respectively, and between each layer of nanostructures 14 and the source region 12 and the drain region 13 respectively; the conductivity type of the semiconductor liner layer 17 is the same as that of the source region 12 and the drain region 13.

[0097] Among them, the specific structure and materials of the gate stack structure can refer to the foregoing, and will not be elaborated here.

[0098] For the beneficial effects of the second aspect and its various implementation manners in the embodiments of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, and will not be elaborated here.

[0099] In the above description, technical details such as the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shape. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used in combination advantageously.

[0100] The embodiments of the present invention have been described above. However, these embodiments are only for more clearly explaining, rather than limiting the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present invention.

Claims

1. A gate-all-around transistor, characterized in that Comprising: A semiconductor substrate, An active structure disposed on the semiconductor substrate; the active structure includes a source region, a drain region, and at least one layer of nanostructure located between the source region and the drain region; both ends of each layer of the nanostructure are electrically connected to the source region and the drain region respectively; A gate stack structure disposed on the semiconductor substrate and surrounding the outer periphery of each layer of the nanostructure; Gate sidewalls spanning across the at least one layer of nanostructure and located on both sides of the gate stack structure in the length direction; A semiconductor liner layer disposed between the gate stack structure and the source region and the drain region respectively, and between each layer of the nanostructure and the source region and the drain region respectively; the conductivity type of the semiconductor liner layer is the same as that of the source region and the drain region.

2. The gate-all-around transistor according to claim 1, wherein The material of the semiconductor liner layer is the same as that of at least one layer of the nanostructure.

3. The gate-all-around transistor according to claim 1, wherein At least one layer of the nanostructured material includes Si 1-x Ge x , and the semiconductor buffer layer material includes Si 1-y Ge y ; Wherein, x is greater than or equal to 0 and less than or equal to 1; y is greater than or equal to 0 and less than or equal to 1; the absolute value of the difference between x and y is less than or equal to 15%.

4. The gate-all-around transistor according to claim 1, wherein The semiconductor liner layer located between the gate stack structure and the source region and between each layer of the nanostructure and the source region is integrally continuous with the source region; And / or, the semiconductor liner layer located between the gate stack structure and the drain region and between each layer of the nanostructure and the drain region is integrally continuous with the drain region.

5. The gate-all-around transistor according to claim 1, wherein The doping concentration of the semiconductor liner layer is less than or equal to the doping concentrations of the source region and the drain region; and / or, the doping concentration of the semiconductor buffer layer is greater than or equal to 5E18 cm -3 and less than or equal to 1E20 cm -3 .

6. The gate-all-around transistor according to claim 1, wherein Along the length direction of the gate stack structure, the sidewalls of the semiconductor liner layer located between the gate stack structure and the source region and the drain region are flush with the sidewalls of the nanostructure; Or, along the length direction of the gate stack structure, the sidewalls of the semiconductor liner layer located between the gate stack structure and the source region and the drain region are recessed inward relative to the sidewalls of the nanostructure.

7. The gate-all-around transistor according to claim 6, wherein Along the length direction of the gate stack structure, the thickness of the semiconductor liner layer located between the gate stack structure and the source region and the drain region is greater than or equal to 1 nm and less than or equal to 8 nm.

8. A manufacturing method of a gate-all-around transistor, characterized in that Comprising: Providing a semiconductor substrate; Forming an active structure, gate sidewalls, and a semiconductor liner layer on the semiconductor substrate; the active structure includes a source region, a drain region, and at least one layer of nanostructure located between the source region and the drain region; both ends of each layer of the nanostructure are electrically connected to the source region and the drain region respectively; the gate sidewalls span across the at least one layer of nanostructure; Forming a gate stack structure surrounding the outer periphery of each layer of the nanostructure on the semiconductor substrate; The gate sidewalls are located on both sides of the gate stack structure in the length direction; the semiconductor liner layer is disposed between the gate stack structure and the source region and the drain region respectively, and between each layer of the nanostructure and the source region and the drain region respectively; the conductivity type of the semiconductor liner layer is the same as that of the source region and the drain region.

9. The manufacturing method of the gate-all-around transistor according to claim 8, wherein, Forming an active structure, gate sidewalls, and a semiconductor liner layer on the semiconductor substrate includes: Form a fin structure on the semiconductor substrate, and a mask structure spanning across the fin structure; along the thickness direction of the semiconductor substrate, the fin structure includes sacrificial layers and channel layers alternately stacked; among the alternately stacked sacrificial layers and channel layers, the bottommost layer is a sacrificial layer; the mask structure includes a sacrificial gate and gate sidewalls located on both sides of the sacrificial gate along the length direction; Selectively remove the portions of the fin structure exposed outside the mask structure; Remove the two side edge portions along the length direction of each remaining sacrificial layer; Form a semiconductor liner layer covering both sides of the remaining fin structure along the length direction of the sacrificial gate; the material of the semiconductor liner layer is different from the material of the sacrificial layer; Form the source region and the drain region on the semiconductor substrate.

10. The manufacturing method of the gate-all-around transistor according to claim 9, wherein, Form the semiconductor liner layer by using an in-situ doped epitaxial process; And / or, form the source region and / or the drain region on the side of the semiconductor liner layer facing away from the remaining fin structure by using an in-situ epitaxial process.

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