Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors, a JFET region of the semiconductor device is arranged on a first surface of a semiconductor body, and a first gate insulating layer is arranged on the first surface and covers the JFET region. The second gate insulating layer is arranged on the side, away from the semiconductor body, of the first gate insulating layer, the orthographic projection of the second gate insulating layer on the first surface is overlapped with the JFET region, and the second gate insulating layer further comprises a third surface away from the side of the semiconductor body. The gate structure is at least partially disposed on the third surface. The source electrode is arranged on the first surface of the semiconductor body, and the drain electrode is arranged on the second surface of the semiconductor body. The thickness of the insulating layer corresponding to the overlapping area of the JFET area and the drain electrode is increased through the arrangement of the second gate insulating layer, the gate-drain capacitance can be effectively reduced through the increase of the thickness of the insulating layer, and therefore the dynamic loss of the device can be reduced.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] In a depletion-mode planar silicon carbide semiconductor device, the region where the JFET region overlaps with the drain affects the gate-drain capacitance of the device, and a large gate-drain capacitance will result in a large dynamic loss of the device. How to effectively reduce the gate-drain capacitance is a problem that needs to be focused on in this field. Summary of the Invention

[0003] Embodiments of this application provide a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle, aiming to reduce the gate-drain capacitance of the semiconductor device, thereby reducing the loss.

[0004] To achieve the above object, the embodiments of this application provide the following technical solutions:

[0005] In a first aspect, an embodiment of this application provides a semiconductor device, including a semiconductor body, a first gate insulating layer, a second gate insulating layer, a gate structure, a source electrode, and a drain electrode. The semiconductor body is set to a first conductivity type. The semiconductor body includes a first surface and a second surface arranged opposite to each other. The semiconductor body further includes a well region set to a second conductivity type and a JFET region set to a first conductivity type. Both the well region and the JFET region are disposed on the first surface. The first gate insulating layer is disposed on the first surface and covers the JFET region. The second gate insulating layer is disposed on a side of the first gate insulating layer away from the semiconductor body. The orthographic projection of the second gate insulating layer on the first surface overlaps with the JFET region. The second gate insulating layer further includes a third surface on a side away from the semiconductor body. The gate structure is at least partially disposed on the third surface. The source electrode is disposed on the first surface, and the drain electrode is disposed on the second surface.

[0006] In some embodiments, the orthographic projection of the second gate insulating layer on the first surface is located within the orthographic projection of the first gate insulating layer on the first surface, and the outer contour of the orthographic projection of the second gate insulating layer on the first surface does not coincide with the outer contour of the orthographic projection of the first gate insulating layer on the first surface.

[0007] In some embodiments, the first gate insulating layer includes a fourth surface on a side away from the semiconductor body. The second gate insulating layer is disposed on the fourth surface and exposes a part of the fourth surface. A part of the gate structure is disposed on the third surface, and another part is disposed on the fourth surface.

[0008] In some embodiments, the thickness range of the first gate insulating layer is 300 angstroms to 800 angstroms, and the thickness range of the second gate insulating layer is 3000 angstroms to 8000 angstroms.

[0009] In a second aspect, the present application further provides a method for manufacturing a semiconductor device, including the following steps S10 to step S50:

[0010] Step S10: Form a well region and a JFET region on a semiconductor body. The semiconductor body is set to a first conduction type. The semiconductor body includes a first surface and a second surface arranged opposite to each other. The well region is set to a second conduction type and is formed on the first surface. The JFET region is set to the first conduction type and is formed on the first surface.

[0011] Step S20: Form a stacked first gate insulating layer and second gate insulating layer on the first surface. The first gate insulating layer covers the JFET region. The second gate insulating layer is located on the side of the first gate insulating layer away from the semiconductor body. The positive projection of the second gate insulating layer on the first surface overlaps with the JFET region. The second gate insulating layer includes a third surface on the side away from the semiconductor body.

[0012] Step S30: Form a gate structure, and at least a part of the gate structure is located on the third surface.

[0013] Step S40: Form a source electrode on the first surface.

[0014] Step S50: Form a drain electrode on the second surface.

[0015] In some embodiments, forming the first gate insulating layer and the second gate insulating layer includes the following steps S21 to step S22:

[0016] Step S21: Form a stacked third gate insulating layer and fourth gate insulating layer on the first surface. The outer contour of the positive projection of the fourth gate insulating layer on the first surface coincides with the outer contour of the positive projection of the third gate insulating layer on the first surface. The positive projections of the third gate insulating layer and the fourth gate insulating layer on the first surface both overlap with the JFET region.

[0017] Step S22: Form a fifth gate insulating layer on the first surface.

[0018] Among them, the third gate insulating layer and the fifth gate insulating layer together form the first gate insulating layer, and the fourth gate insulating layer serves as the second gate insulating layer.

[0019] In some embodiments, forming the third gate insulating layer and the fourth gate insulating layer includes the following steps S211 to step S213:

[0020] Step S211: Form a third gate insulating film on the first surface by using a thermal oxidation process.

[0021] Step S212: Form a fourth gate insulating film on the side of the third gate insulating film away from the semiconductor body by using a thin film deposition process.

[0022] Step S213: Etch the third gate insulating film and the fourth gate insulating film by using a photolithography process to form a third gate insulating layer and a fourth gate insulating layer.

[0023] The step of forming the fifth gate insulating layer includes: forming the fifth gate insulating layer on the first surface by using a thermal oxidation process.

[0024] In the embodiment provided by the present application, the semiconductor device includes a semiconductor body, a first gate insulating layer, a second gate insulating layer, a gate structure, a source electrode, and a drain electrode. Compared with the related art, the semiconductor device in the embodiment of the present application is equivalent to adding a second gate insulating layer. Since the second gate insulating layer is disposed on the side of the first gate insulating layer away from the semiconductor body, the orthographic projection of the second gate insulating layer on the first surface overlaps with the JFET region, and the second gate insulating layer further includes a third surface on the side away from the semiconductor body, and at least a part of the gate structure is disposed on the third surface. It can be understood that the setting of the second gate insulating layer increases the thickness of the insulating layer corresponding to the overlapping region between the JFET region and the drain electrode, and the increase in the thickness of the insulating layer can effectively reduce the gate-drain capacitance, thereby reducing the dynamic loss of the device. Moreover, in the embodiment of the present application, only by adding the second gate insulating layer, the thickness of the insulating layer is increased, and the thickness of the JFET region of the device remains unchanged, so the on-resistance of the device will not be affected, that is, the related performance of the device will not be damaged.

[0025] In addition, for preparing the semiconductor device, the present application also provides a preparation method. The preparation method has a simple process and is easy to operate, can be prepared by using existing relatively mature processes, and has little impact on the production cost. That is, the preparation method provided by the embodiment of the present application is simple and feasible, which is beneficial to large-scale preparation of semiconductor devices with low dynamic loss.

[0026] On the other hand, the embodiment of the present application also provides a power module, which includes a substrate and the semiconductor device according to any one of the above embodiments, and the substrate is used to carry the semiconductor device.

[0027] On yet another hand, the embodiment of the present application also provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and the semiconductor device according to any one of the above embodiments, and the semiconductor device is electrically connected to the circuit board.

[0028] In another aspect, an embodiment of the present application further provides a vehicle, which includes a load and a power conversion circuit as described in the above embodiment. The power conversion circuit is configured to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current, and then input the converted current into the load.

[0029] The above power module, power conversion circuit, and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above embodiments, and will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description of the embodiments in conjunction with the accompanying drawings, where:

[0031] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

[0032] Figure 2 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0033] Figures 3 to 14 are diagrams of each step for manufacturing a semiconductor device provided by an embodiment of the present application;

[0034] Figure 15 is a schematic structural diagram of a power module provided by an embodiment of the present application;

[0035] Figure 16 is a schematic structural diagram of a power conversion circuit provided by an embodiment of the present application;

[0036] Figure 17 is a schematic structural diagram of a vehicle provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The technical solutions in some embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of them. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art shall fall within the scope of protection of the present application.

[0038] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, that is, "including, but not limited to".

[0039] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0040] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral one; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other.

[0041] In addition, the use of "based on" implies openness and inclusiveness, because a process, step, calculation, or other action "based on" one or more of the said conditions or values may, in practice, be based on additional conditions or values beyond the said ones.

[0042] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0043] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of the regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations caused by, for example, manufacturing. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0044] Examples of the embodiments are shown in the drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only for explaining the present application and should not be construed as limiting the present application.

[0045] As mentioned in the background art, in a depletion-mode planar silicon carbide semiconductor device, the region where the JFET region overlaps with the drain affects the gate-drain capacitance of the device, and a larger gate-drain capacitance results in a larger dynamic loss of the device. Through relevant research, increasing the thickness of the gate insulating layer in this overlapping region can effectively reduce the gate-drain capacitance, thereby reducing the dynamic loss of the device.

[0046] Based on this, an embodiment of the present application provides a semiconductor device 10, as Figure 1 shown, Figure 1 which is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application.

[0047] The semiconductor device 10 includes a semiconductor body 11, a first gate insulating layer 12, a second gate insulating layer 13, a gate structure 14, a source electrode 15, and a drain electrode 16. The semiconductor body 11 is set to a first conduction type. The semiconductor body 10 includes a first surface P1 and a second surface P2 that are oppositely arranged. The semiconductor body 10 further includes a well region 17 set to a second conduction type and a JFET region set to a first conduction type. The well region 17 and the JFET region are both disposed on the first surface P1. The first gate insulating layer 12 is disposed on the first surface P1 and covers the JFET region. The second gate insulating layer 13 is disposed on a side of the first gate insulating layer 12 away from the semiconductor body 11. A positive projection of the second gate insulating layer 12 on the first surface P1 overlaps with the JFET region. The second gate insulating layer 13 further includes a third surface P3 on a side away from the semiconductor body 11. The gate structure 14 is at least partially disposed on the third surface P3. The source electrode 15 is disposed on the first surface P1, and the drain electrode 16 is disposed on the second surface P2.

[0048] Exemplarily, as Figure 1 shown, the semiconductor device 10 further includes a first region 18 and a second region 19. The first region 18 and the well region 17 have the same conduction type, both being the second conduction type, and the second region 19 is of the first conduction type. By inputting a turn-on voltage to the gate structure 14, when the semiconductor device 10 conducts forward and the working current is small, the working current flows from the source electrode 15 through the second region 19, the well region 17, and the JFET region to the drain electrode 16.

[0049] The first gate insulating layer 12 and the second gate insulating layer 13 are located between the gate structure 14 and the first surface P1 of the semiconductor, and can isolate the gate structure 14 from the semiconductor body 11 to prevent the semiconductor device 10 from short-circuiting.

[0050] Compared with the related art, the semiconductor device 10 in the embodiment of the present application is equivalent to adding a second gate insulating layer 13. Based on the set position of the second gate insulating layer 13, within the overlapping region between the JFET region and the drain 16, the insulating layer corresponding between the gate structure 14 and the drain 16 includes the first gate insulating layer 12 and the second gate insulating layer 13. That is, compared with the related art, it is equivalent to increasing the thickness of the insulating layer corresponding to this overlapping region. The increase in the thickness of this insulating layer can effectively reduce the gate-drain capacitance, thereby reducing the dynamic loss of the device. Moreover, in the embodiment of the present application, only by adding the second gate insulating layer 13, the thickness of this insulating layer is increased, and the thickness of the JFET region of the device remains unchanged, so it will not affect the on-resistance of the device, that is, the related performance of the device will not be damaged.

[0051] In some embodiments, as Figure 1 shown, the orthographic projection of the second gate insulating layer 13 on the first surface P1 is located within the orthographic projection of the first gate insulating layer 12 on the first surface P1, and the outer contour of the orthographic projection of the second gate insulating layer 13 on the first surface P1 does not coincide with the outer contour of the orthographic projection of the first gate insulating layer 12 on the first surface P1.

[0052] That is, the projected area of the second gate insulating layer 13 is smaller than the projected area of the first gate insulating layer 12, and the projected area of the second gate insulating layer 13 is located inside the projected area of the first gate insulating layer 12. Preferably, the projected area of the second gate insulating layer 13 can be located at the center of the projected area of the first gate insulating layer 12.

[0053] For example, as Figure 1 shown, the orthographic projection of the first gate insulating layer 12 on the first surface P1 overlaps with the orthographic projection of the well region 17 on the first surface P1, while the orthographic projection of the second gate insulating layer 13 on the first surface P1 has no overlap with the orthographic projection of the well region 17 on the first surface P1.

[0054] By reasonably designing the position of the second gate insulating layer 13, the magnetic field distribution inside the device can be optimized, and then the equivalent capacitance value of the gate-drain capacitance can be optimized, achieving the goal of reducing the gate-drain capacitance and the dynamic loss of the device with the optimal solution.

[0055] In some embodiments, as Figure 1 shown, the first gate insulating layer 12 includes a fourth surface P4 on the side away from the semiconductor body 11. The second gate insulating layer 13 is disposed on the fourth surface P4 and exposes a part of the fourth surface P4. A part of the gate structure 14 is disposed on the third surface P3, and another part is disposed on the fourth surface P4.

[0056] It can be understood that the thickness of the insulating layer between the gate structure 14 and the first surface P1 affects the control effect of the gate structure 14 on the device conduction. In the embodiments of the present application, the gate structure 14 has a convex platform morphology. The insulating layer between a part of the gate structure 14 and the first surface P1 is the first gate insulating layer 12, and the insulating layer between another part of the gate structure 14 and the first surface P1 is the first gate insulating layer 12 and the second gate insulating layer 13. Based on this, the control effect of the gate structure 14 on the device conduction can be ensured, and the gate-drain capacitance can be effectively reduced, thereby reducing the dynamic loss of the device.

[0057] In some embodiments, as Figure 1 shown, the thickness range of the first gate insulating layer 12 is 300 Å to 800 Å, such as 300 Å, 400 Å, 500 Å, 600 Å, 700 Å or 800 Å, etc. The thickness range of the second gate insulating layer 13 is 3000 Å to 8000 Å, such as 3000 Å, 4000 Å, 5000 Å, 6000 Å, 7000 Å or 8000 Å, etc. Based on this, in the overlapping region between the JFET region and the drain 16, the thickness range of the insulating layer corresponding to between the gate structure 14 and the drain 16 is 3300 Å to 8800 Å. Compared with the related art where only the first gate insulating layer 12 is included, the thickness of this insulating layer increases by an order of magnitude, and the effect of reducing the gate-drain capacitance is significant, which can greatly reduce the dynamic loss of the device.

[0058] Second, the present application also provides a method for manufacturing a semiconductor device, as Figure 2 shown, Figure 2 is a flowchart of the method for manufacturing a semiconductor device provided by the embodiments of the present application, Figures 3 to 14 are the diagrams of each step for manufacturing a semiconductor device provided by the embodiments of the present application.

[0059] This manufacturing method includes the following steps S10 to step S50:

[0060] Step S10: As Figures 3 to 7 shown, a well region 17 and a JFET region are formed on the semiconductor body 11. The semiconductor body 11 is set to the first conduction type. The semiconductor body 11 includes a relatively arranged first surface P1 and a second surface P2. The well region 17 is set to the second conduction type and is formed on the first surface P1. The JFET region is set to the first conduction type and is formed on the first surface P1.

[0061] Exemplarily, as Figure 3As shown, a mask template 31 is formed on the first surface P1 of the semiconductor body 11 by using a plasma enhanced chemical vapor deposition process. The material of the mask template 31 may include silicon dioxide or photoresist, and the mask template 31 exposes a part of the first surface P1. Then, ion implantation is performed under the action of the mask template 31 to form a first region 18, and the first region 18 is set to the second conductivity type. For example, the first conductivity type is N-type, the second conductivity type is P-type, and the ions implanted into the first region 18 include aluminum ions.

[0062] After that, as Figure 4 shown, a mask template 32 is formed and a second ion implantation is performed under the action of the mask template 32 to form a well region 17, and the well region 17 is set to the second conductivity type. It can be understood that under the operation as Figures 3 to 4 shown, the first region 18 has undergone two ion implantations.

[0063] Next, as Figure 5 shown, a mask template 33 is formed by using a high temperature oxidation (HTO) deposition process. The HTO deposition process has better coverage and can ensure that the mask template 33 covers the semiconductor body 11.

[0064] After that, as Figure 6 shown, the mask template 33 is etched so that the mask template 33 exposes a part of the first surface P1, and ion implantation is performed on the exposed part to form a second region 19, and the second region 19 is set to the first conductivity type.

[0065] Next, as Figure 7 shown, the mask template is removed to expose the complete first surface P1.

[0066] Thus, the process of forming a JFET region on the semiconductor body 11 is realized. The JFET region here refers to the region between two adjacent well regions 17.

[0067] In some embodiments, a carbon film is further deposited on the first surface P1 and subjected to high temperature annealing activation, and the carbon film is removed after the annealing activation is completed. This process helps to activate the doped ions and repair the lattice defects caused by processes such as ion implantation, which is beneficial to improving the yield and reliability of the device.

[0068] Step S20: After the high temperature annealing, as Figures 8 to 10As shown, a stacked first gate insulating layer 12 and a second gate insulating layer 13 are formed on the first surface P1. The first gate insulating layer 12 covers the JFET region. The second gate insulating layer 13 is located on the side of the first gate insulating layer 12 away from the semiconductor body 11. The orthographic projection of the second gate insulating layer 13 on the first surface P1 overlaps with the JFET region. The second gate insulating layer 13 includes a third surface P3 on the side away from the semiconductor body 11.

[0069] Exemplarily, in some embodiments, forming the first gate insulating layer 12 and the second gate insulating layer 13 includes the following steps S21 to step S22:

[0070] Step S21: As Figures 8 to 9 shown, a stacked third gate insulating layer 21 and a fourth gate insulating layer 22 are formed on the first surface P1. The outer contour of the orthographic projection of the fourth gate insulating layer 22 on the first surface P1 coincides with the outer contour of the orthographic projection of the third gate insulating layer 21 on the first surface P1. The orthographic projections of the third gate insulating layer 21 and the fourth gate insulating layer 22 on the first surface P1 both overlap with the JFET region.

[0071] Exemplarily, as Figure 8 shown, in some embodiments, forming the third gate insulating layer 21 and the fourth gate insulating layer 22 includes the following steps S211 to step S213:

[0072] Step S211: Using a thermal oxidation process, a third gate insulating thin film 210 is formed on the first surface P1.

[0073] Exemplarily, the thickness range of the third gate insulating thin film 210 is 300 Å to 800 Å.

[0074] Step S212: Using a thin film deposition process, a fourth gate insulating thin film 220 is formed on the side of the third gate insulating thin film 210 away from the semiconductor body 11.

[0075] Exemplarily, the thickness range of the fourth gate insulating thin film 220 is 3000 Å to 8000 Å, and the material includes silicon dioxide.

[0076] Since the process of directly preparing the fourth gate insulating thin film 220 on the first surface P1 using a thin film deposition process will damage the first surface P1, which will in turn affect the device function, therefore, on the basis of forming the third gate insulating thin film 210 by a thermal oxidation process, then using a thin film deposition process to prepare the fourth gate insulating thin film 220 can effectively improve the yield and device reliability.

[0077] Step S213: As Figure 9As shown, by using a photolithography process, the third gate insulating film 210 and the fourth gate insulating film 220 are etched to form the third gate insulating layer 21 and the fourth gate insulating layer 22.

[0078] Step S22: As Figure 10 shown, a fifth gate insulating layer 23 is formed on the first surface P1.

[0079] Among them, the third gate insulating layer 21 and the fifth gate insulating layer 23 together form the first gate insulating layer 12, and the fourth gate insulating layer 22 serves as the second gate insulating layer 13. As Figure 10 shown, the first gate insulating layer 12 includes a fourth surface P4 on the side away from the semiconductor body 11, the second gate insulating layer 13 includes a third surface P3 on the side away from the semiconductor body 11, the second gate insulating layer 13 is disposed on the fourth surface P4, and a part of the fourth surface P4 is exposed.

[0080] The preparation process of the fifth gate insulating layer 23 can be the same as the preparation process of the third gate insulating film 210 in step S211, that is, in some embodiments, the step of forming the fifth gate insulating layer 23 includes: using a thermal oxidation process to form the fifth gate insulating layer 23 on the first surface P1.

[0081] Thus, the stacked first gate insulating layer 12 and the second gate insulating layer 13 are formed on the first surface P1.

[0082] Step S30: As Figures 11 to 12 shown, a gate structure 14 is formed, and at least a part of the gate structure 14 is located on the third surface P3.

[0083] Exemplarily, as Figure 11 shown, a polysilicon material is deposited in a whole layer.

[0084] Then as Figure 12 shown, the polysilicon material is etched to form the required morphology of the gate structure 14.

[0085] For example, a part of the gate structure 14 is disposed on the third surface P3, and another part is disposed on the fourth surface P4.

[0086] Step S40: As Figures 13 to 14 shown, a source electrode 15 is formed on the first surface P1.

[0087] Exemplarily, as Figure 13 shown, an interlayer dielectric layer 20 is formed, and the interlayer dielectric layer 20 covers the gate structure 14. Then, the interlayer dielectric layer 20 and the first gate insulating layer 12 are etched to obtain the required morphology.

[0088] After that, as Figure 14As shown, the interlayer dielectric layer 20 is etched to form a via that exposes the gate structure 14, and then a metal layer is deposited on the first surface P1 and the metal layer is patterned. The portion of the metal layer that is electrically connected to the gate structure 14 through the via serves as an external pad of the gate structure 14, and the other portion of the metal layer is the source 15.

[0089] Step S50: Figure 14 As shown, a drain 16 is formed on the second surface P2.

[0090] At this point, the semiconductor device 10 is completed.

[0091] The above preparation method is simple in process and easy to operate. It can be prepared using existing relatively mature processes, and has little impact on production costs. For example, the third gate insulating layer 21, the fourth gate insulating layer 22 and the fifth gate insulating layer 23 can be formed by two thermal oxidation processes and one thin film deposition process. Among them, the third gate insulating layer 21 and the fifth gate insulating layer 23 together form the first gate insulating layer 12, and the fourth gate insulating layer 22 serves as the second gate insulating layer 13. Based on this, in the overlapping area between the JFET region and the drain 16, the insulating layer corresponding to the gate structure 14 and the drain 16 includes the first gate insulating layer 12 and the second gate insulating layer 13, that is, compared with the related art, it is equivalent to increasing the thickness of the insulating layer corresponding to the overlapping area, and the increase in the thickness of the insulating layer can effectively reduce the gate-drain capacitance, thereby reducing the dynamic loss of the device. Moreover, in the embodiment of the present application, the thickness of the insulating layer is increased only by adding the second gate insulating layer 13, and the thickness of the JFET region of the device remains unchanged, so it will not affect the on-resistance of the device, that is, the relevant performance of the device will not be damaged.

[0092] That is, the preparation method provided in the embodiment of the present application is simple and feasible, and is conducive to the large-scale preparation of semiconductor devices 10 with low dynamic losses.

[0093] On the other hand, an embodiment of the present application further provides a power module, Figure 15 A schematic diagram of the structure of a power module provided in an embodiment of the present application.

[0094] like Figure 15 As shown, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments, and the substrate 201 is used to carry the semiconductor device 10 .

[0095] Exemplarily, the power module 200 can be used as one of a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is a device used to control the power flow. The power management module is used to manage the power supply to ensure stable and efficient distribution of power to different parts of an electronic device. The power regulator is used to regulate the power output to meet the requirements of a specific application.

[0096] On the other hand, an embodiment of the present application also provides a power conversion circuit. Figure 16 It is a schematic structural diagram of the power conversion circuit provided by the embodiment of the present application.

[0097] As Figure 16 shown, the power conversion circuit 300 includes a circuit board 301 and the semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 301. The power conversion circuit 300 can be used for current conversion, voltage conversion, or power factor correction.

[0098] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter, or a power factor correction (PFC) circuit. Among them, the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce harmonic pollution of the power grid.

[0099] On the other hand, an embodiment of the present application also provides a vehicle. Figure 17 It is a schematic structural diagram of the vehicle provided by the embodiment of the present application.

[0100] As Figure 17 shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment. The power conversion circuit 300 is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input it to the load 401 to supply power to the load 401.

[0101] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application, who thinks of changes or substitutions, should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims described above.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor body, which is set to a first conductivity type and includes a first surface and a second surface that are oppositely arranged; the semiconductor body further includes a well region that is set to a second conductivity type and a JFET region that is set to a first conductivity type, and both the well region and the JFET region are disposed on the first surface; A first gate insulating layer, which is disposed on the first surface and covers the JFET region; A second gate insulating layer, which is disposed on a side of the first gate insulating layer away from the semiconductor body; a positive projection of the second gate insulating layer on the first surface overlaps with the JFET region; the second gate insulating layer includes a third surface on a side away from the semiconductor body; A gate structure, at least a part of which is disposed on the third surface; A source electrode, which is disposed on the first surface; A drain electrode, which is disposed on the second surface.

2. The semiconductor device according to claim 1, wherein, A positive projection of the second gate insulating layer on the first surface is located within a range of a positive projection of the first gate insulating layer on the first surface; And, an outer contour of the positive projection of the second gate insulating layer on the first surface does not coincide with an outer contour of the positive projection of the first gate insulating layer on the first surface.

3. The semiconductor device according to claim 2, wherein The first gate insulating layer includes a fourth surface on a side away from the semiconductor body, the second gate insulating layer is disposed on the fourth surface and exposes a part of the fourth surface; A part of the gate structure is disposed on the third surface, and another part is disposed on the fourth surface.

4. The semiconductor device according to claim 1, wherein The thickness range of the first gate insulating layer is 300 Å to 800 Å; The thickness range of the second gate insulating layer is 3000 Å to 8000 Å.

5. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a well region and a JFET region on a semiconductor body, the semiconductor body being set to a first conductivity type and including a first surface and a second surface that are oppositely arranged; the well region is set to a second conductivity type and is formed on the first surface; the JFET region is set to a first conductivity type and is formed on the first surface; Forming a stacked first gate insulating layer and a second gate insulating layer on the first surface, the first gate insulating layer covering the JFET region; the second gate insulating layer is located on a side of the first gate insulating layer away from the semiconductor body, a positive projection of the second gate insulating layer on the first surface overlaps with the JFET region; the second gate insulating layer includes a third surface on a side away from the semiconductor body; Forming a gate structure, at least a part of the gate structure being located on the third surface; Forming a source electrode on the first surface; Forming a drain electrode on the second surface.

6. The preparation method according to claim 5, characterized in that, Forming the first gate insulating layer and the second gate insulating layer includes: Forming a stacked third gate insulating layer and a fourth gate insulating layer on the first surface, an outer contour of a positive projection of the fourth gate insulating layer on the first surface coincides with an outer contour of a positive projection of the third gate insulating layer on the first surface; positive projections of the third gate insulating layer and the fourth gate insulating layer on the first surface both overlap with the JFET region; Form a fifth gate insulating layer on the first surface; Among them, the third gate insulating layer and the fifth gate insulating layer together form the first gate insulating layer, and the fourth gate insulating layer serves as the second gate insulating layer.

7. The preparation method according to claim 6, wherein Forming the third gate insulating layer and the fourth gate insulating layer includes: Adopt a thermal oxidation process to form a third gate insulating film on the first surface; Adopt a thin film deposition process to form a fourth gate insulating film on the side of the third gate insulating film away from the semiconductor body; Adopt a photolithography process to etch the third gate insulating film and the fourth gate insulating film to form the third gate insulating layer and the fourth gate insulating layer; Forming the fifth gate insulating layer includes: Adopt a thermal oxidation process to form the fifth gate insulating layer on the first surface.

8. A power module, characterized in that, Including: At least one semiconductor device as described in any one of claims 1 to 4; A substrate for carrying the semiconductor device.

9. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1 to 4, and the semiconductor device is electrically connected to the circuit board.

10. A vehicle, characterized in that, Including: A load and the power conversion circuit as described in claim 9, and the power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

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